WO2020206796A1 - Circuit goa et panneau d'affichage - Google Patents

Circuit goa et panneau d'affichage Download PDF

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Publication number
WO2020206796A1
WO2020206796A1 PCT/CN2019/086401 CN2019086401W WO2020206796A1 WO 2020206796 A1 WO2020206796 A1 WO 2020206796A1 CN 2019086401 W CN2019086401 W CN 2019086401W WO 2020206796 A1 WO2020206796 A1 WO 2020206796A1
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WO
WIPO (PCT)
Prior art keywords
transistor
node
electrically connected
level
signal
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Application number
PCT/CN2019/086401
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English (en)
Chinese (zh)
Inventor
张留旗
韩佰祥
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Publication of WO2020206796A1 publication Critical patent/WO2020206796A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • This application relates to the field of display technology, in particular to a GOA circuit and a display panel.
  • OA full English name: Gate Driver on Array, full Chinese name: integrated gate drive circuit
  • the signal output by the GOA circuit requires two pulse waveforms: one is a positive pulse waveform, which can be generated by a conventional GOA circuit; the other is a negative pulse waveform.
  • the existing GOA circuit generates a negative pulse waveform signal, and its circuit design is relatively complicated.
  • the purpose of the embodiments of the present application is to provide a GOA circuit and a display panel, which can solve the technical problem that the existing GOA circuit generates a negative pulse waveform signal and its circuit design is relatively complicated.
  • the embodiment of the present application provides a GOA circuit, including: multi-stage cascaded GOA units, each level of GOA unit includes: an input module, an inverter module, a sustain module, a first output module, a second output module, and an output Control module
  • the input module is connected to the current level clock signal and the upper level transmission signal, and is electrically connected to the first node, for outputting the upper level transmission signal to under the control of the current level clock signal The first node;
  • the inverter module is electrically connected to the second node and the first node, and is used to control the potential of the second node under the control of the potential of the first node;
  • the maintaining module receives a low-level signal, and is electrically connected to the second node and the first node, for maintaining the potential of the first node under the control of the potential of the second node The potential of the low-level signal;
  • the first output module is connected to the clock signal of the current level, and is electrically connected to the second node, for outputting a transmission signal of the current level under the control of the potential of the second node;
  • the second output module is connected to the clock signal of the current level and is electrically connected to the second node for outputting the scan signal of the current level under the control of the potential of the second node;
  • the output control module is connected to a high-level signal, and is electrically connected to the first node, the current-level scanning signal, and the current-level transmission signal, and is used to control the potential of the first node , Pulling up the transmission signal of the current level to the potential of the high level signal, and pulling up the scan signal of the current level to the potential of the high level signal;
  • the GOA circuit further includes an eleventh transistor; the gate and source of the eleventh transistor are electrically connected to a reset signal, and the drain of the eleventh transistor is electrically connected to the first node;
  • the first-level GOA unit is started by the start signal, and the remaining GOA units are started by the corresponding upper-level GOA unit.
  • the input module includes a first transistor
  • the gate of the first transistor is electrically connected to the clock signal of the current stage, the source of the first transistor is electrically connected to the upper stage signal, and the drain of the first transistor is electrically connected Connected to the first node.
  • the inverter module includes a second transistor, a third transistor, a fourth transistor, and a fifth transistor;
  • the gate of the second transistor and the gate of the third transistor are both electrically connected to the first node, and the source of the second transistor and the source of the third transistor are both electrically connected to The low-level signal; the drain of the second transistor, the drain of the fourth transistor, and the gate of the fifth transistor are electrically connected, the gate of the fourth transistor, the fourth transistor.
  • the source of the transistor and the source of the fifth transistor are both electrically connected to the high-level signal; the drain of the third transistor and the drain of the fifth transistor are both electrically connected to the second node Sexual connection.
  • the sustain module includes a sixth transistor
  • the gate of the sixth transistor is electrically connected to the second node, the source of the sixth transistor is electrically connected to the low-level signal, and the drain of the sixth transistor is electrically connected to the The first node.
  • the first output module includes a seventh transistor
  • the gate of the seventh transistor is electrically connected to the second node, the source of the seventh transistor is electrically connected to the local clock signal, and the drain of the seventh transistor is electrically connected to the Describe the transmission signal at this level.
  • the second output module includes an eighth transistor
  • the gate of the eighth transistor is electrically connected to the second node, the source of the eighth transistor is electrically connected to the local clock signal, and the drain of the eighth transistor is electrically connected to the Describe the scan signal at this level.
  • the output control module includes a ninth transistor and a tenth transistor
  • the gate of the ninth transistor and the gate of the tenth transistor are both electrically connected to the first node, and the source of the ninth transistor and the source of the tenth transistor are both electrically connected to
  • the drain of the ninth transistor is electrically connected to the current-level transmission signal
  • the drain of the tenth transistor is electrically connected to the current-level scanning signal.
  • the embodiment of the present application provides a GOA circuit, including: multi-stage cascaded GOA units, each level of GOA unit includes: an input module, an inverter module, a sustain module, a first output module, a second output module, and an output Control module
  • the input module is connected to the current level clock signal and the upper level transmission signal, and is electrically connected to the first node, for outputting the upper level transmission signal to under the control of the current level clock signal The first node;
  • the inverter module is electrically connected to the second node and the first node, and is used to control the potential of the second node under the control of the potential of the first node;
  • the maintaining module receives a low-level signal, and is electrically connected to the second node and the first node, for maintaining the potential of the first node under the control of the potential of the second node The potential of the low-level signal;
  • the first output module is connected to the clock signal of the current level, and is electrically connected to the second node, for outputting a transmission signal of the current level under the control of the potential of the second node;
  • the second output module is connected to the clock signal of the current level and is electrically connected to the second node for outputting the scan signal of the current level under the control of the potential of the second node;
  • the output control module is connected to a high-level signal, and is electrically connected to the first node, the current-level scanning signal, and the current-level transmission signal, and is used to control the potential of the first node , Pulling up the transmission signal of the current level to the potential of the high level signal, and pulling up the scan signal of the current level to the potential of the high level signal.
  • the input module includes a first transistor
  • the gate of the first transistor is electrically connected to the clock signal of the current stage, the source of the first transistor is electrically connected to the upper stage signal, and the drain of the first transistor is electrically connected Connected to the first node.
  • the inverter module includes a second transistor, a third transistor, a fourth transistor, and a fifth transistor;
  • the gate of the second transistor and the gate of the third transistor are both electrically connected to the first node, and the source of the second transistor and the source of the third transistor are both electrically connected to The low-level signal; the drain of the second transistor, the drain of the fourth transistor, and the gate of the fifth transistor are electrically connected, the gate of the fourth transistor, the fourth transistor.
  • the source of the transistor and the source of the fifth transistor are both electrically connected to the high-level signal; the drain of the third transistor and the drain of the fifth transistor are both electrically connected to the second node Sexual connection.
  • the sustain module includes a sixth transistor
  • the gate of the sixth transistor is electrically connected to the second node, the source of the sixth transistor is electrically connected to the low-level signal, and the drain of the sixth transistor is electrically connected to the The first node.
  • the first output module includes a seventh transistor
  • the gate of the seventh transistor is electrically connected to the second node, the source of the seventh transistor is electrically connected to the local clock signal, and the drain of the seventh transistor is electrically connected to the Describe the transmission signal at this level.
  • the second output module includes an eighth transistor
  • the gate of the eighth transistor is electrically connected to the second node, the source of the eighth transistor is electrically connected to the local clock signal, and the drain of the eighth transistor is electrically connected to the Describe the scan signal at this level.
  • the output control module includes a ninth transistor and a tenth transistor
  • the gate of the ninth transistor and the gate of the tenth transistor are both electrically connected to the first node, and the source of the ninth transistor and the source of the tenth transistor are both electrically connected to
  • the drain of the ninth transistor is electrically connected to the current-level transmission signal
  • the drain of the tenth transistor is electrically connected to the current-level scanning signal.
  • the GOA circuit further includes an eleventh transistor; the gate and source of the eleventh transistor are electrically connected to a reset signal, and the drain of the eleventh transistor It is electrically connected to the first node.
  • the first-level GOA unit is started by the start signal, and the remaining GOA units are started by the corresponding upper-level GOA unit.
  • An embodiment of the present application also provides a display panel, which includes a GOA circuit, the GOA circuit includes: multi-level cascaded GOA units, each level of GOA unit includes: input module, inverting module, sustaining module, second An output module, a second output module, and an output control module;
  • the input module is connected to the current level clock signal and the upper level transmission signal, and is electrically connected to the first node, for outputting the upper level transmission signal to under the control of the current level clock signal The first node;
  • the inverter module is electrically connected to the second node and the first node, and is used to control the potential of the second node under the control of the potential of the first node;
  • the maintaining module receives a low-level signal, and is electrically connected to the second node and the first node, for maintaining the potential of the first node under the control of the potential of the second node The potential of the low-level signal;
  • the first output module is connected to the clock signal of the current level, and is electrically connected to the second node, for outputting a transmission signal of the current level under the control of the potential of the second node;
  • the second output module is connected to the clock signal of the current level and is electrically connected to the second node for outputting the scan signal of the current level under the control of the potential of the second node;
  • the output control module is connected to a high-level signal, and is electrically connected to the first node, the current-level scanning signal, and the current-level transmission signal, and is used to control the potential of the first node , Pulling up the transmission signal of the current level to the potential of the high level signal, and pulling up the scan signal of the current level to the potential of the high level signal.
  • the input module includes a first transistor
  • the gate of the first transistor is electrically connected to the clock signal of the current stage, the source of the first transistor is electrically connected to the upper stage signal, and the drain of the first transistor is electrically connected Connected to the first node.
  • the inverter module includes a second transistor, a third transistor, a fourth transistor, and a fifth transistor;
  • the gate of the second transistor and the gate of the third transistor are both electrically connected to the first node, and the source of the second transistor and the source of the third transistor are both electrically connected to The low-level signal; the drain of the second transistor, the drain of the fourth transistor, and the gate of the fifth transistor are electrically connected, the gate of the fourth transistor, the fourth transistor.
  • the source of the transistor and the source of the fifth transistor are both electrically connected to the high-level signal; the drain of the third transistor and the drain of the fifth transistor are both electrically connected to the second node Sexual connection.
  • the sustain module includes a sixth transistor
  • the gate of the sixth transistor is electrically connected to the second node, the source of the sixth transistor is electrically connected to the low-level signal, and the drain of the sixth transistor is electrically connected to the The first node.
  • the GOA circuit and display panel provided by the embodiments of the present application adopt a relatively simple circuit design to output a negative pulse waveform signal.
  • FIG. 1 is a schematic structural diagram of a GOA circuit provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of the first circuit of a GOA unit in the GOA circuit provided by the embodiment of the application;
  • FIG. 3 is a signal timing diagram of a GOA unit in the GOA circuit provided by an embodiment of the application;
  • FIG. 4 is a schematic diagram of a second circuit of a GOA unit in the GOA circuit provided by the embodiment of the application.
  • FIG. 5 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • the transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one of the poles is called the source and the other is called the drain. According to the form in the figure, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the source, and the output end is the drain. In addition, the transistors used in the embodiments of the present application are all N-type transistors, where the N-type transistor is turned on when the gate is at a high level, and turned off when the gate is at a low level.
  • FIG. 1 is a schematic structural diagram of a GOA circuit provided by an embodiment of the application.
  • the GOA circuit 10 provided by the embodiment of the present application includes multi-stage cascaded GOA units 20.
  • Each GOA unit 20 is used to output a negative pulse waveform scanning signal and a negative pulse waveform grade transmission signal.
  • the first-level GOA unit 20 is connected to the start signal STV, and then the second-level GOA unit 20, the third-level GOA unit 20, ..., the last-level GOA unit 20 are sequentially Pass start.
  • the n-1 level GOA unit When the n-1 level GOA unit is working, the n-1 level GOA unit outputs a negative pulse waveform scanning signal and a negative pulse waveform grade transmission signal, which are used to control the light-emitting diodes in the light-emitting diode display panel. Subsequently, the stage transmission signal of the n-1th stage GOA unit activates the nth stage GOA unit, and the nth stage GOA unit outputs a scanning signal with a negative pulse waveform and a stage transmission signal with a negative pulse waveform. Finally, the stage transmission signal of the nth stage GOA unit activates the n+1 stage GOA unit, and the n+1 stage GOA unit outputs a scanning signal with a negative pulse waveform and a stage transmission signal with a negative pulse waveform.
  • FIG. 2 is a schematic diagram of a first circuit of a GOA unit in the GOA circuit provided by an embodiment of the application.
  • the GOA unit 20 includes: an input module 101, an inversion module 102, a maintenance module 103, a first output module 104, a second output module 105, and an output control module 106.
  • the input module 101 is connected to the clock signal CK(n) of the current level and the upper level transmission signal Cout(n-1), and is electrically connected to the first node a for the clock signal CK(n) of the current level Under the control of, the upper level transmission signal Cout(n-1) is output to the first node a.
  • the inverter module 102 is electrically connected to the second node b and the first node a for controlling the potential of the second node b under the control of the potential of the first node a.
  • the maintaining module 103 is connected to the low-level signal VGL, and is electrically connected to the second node b and the first node a, and is used to maintain the potential of the first node a at a low level under the control of the potential of the second node b.
  • Level signal VGL potential is connected to the low-level signal VGL, and is electrically connected to the second node b and the first node a, and is used to maintain the potential of the first node a at a low level under the control of the potential of the second node b.
  • Level signal VGL potential is connected to the low-level signal VGL, and is electrically connected to the second node b and the first node a, and is used to maintain the potential of the first node a at a low level under the control of the potential of the second node b.
  • Level signal VGL potential is connected to the low-level signal VGL, and is electrically connected to the second node b and the first node a, and is used to maintain
  • the first output module 104 is connected to the clock signal CK(n) of the current stage, and is electrically connected to the second node b, for outputting the transmission signal Cout(n) of the current stage under the control of the potential of the second node b .
  • the second output module 105 is connected to the clock signal CK(n) of the current level and is electrically connected to the second node b for outputting the scan signal G(n) of the current level under the control of the potential of the second node b.
  • the output control module 106 is connected to the high-level signal VGH, and is electrically connected to the first node a, the current-level scanning signal G(n), and the current-level transmission signal Cout(n), which is used to connect to the first node a Under the control of the potential of, the current level transmission signal Cout(n) is pulled up to the potential of the high level signal VGH, and the current level scanning signal G(n) is pulled up to the potential of the high level signal VGH.
  • the input module 101 includes a first transistor T1; the gate of the first transistor T1 is electrically connected to the clock signal CK(n) of the current stage, and the source of the first transistor T1 is electrically connected to the upper stage By transmitting the signal Cout(n-1), the drain of the first transistor T1 is electrically connected to the first node a.
  • the inverter module 102 includes a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5; the gate of the second transistor T2 and the gate of the third transistor T3 are both electrically connected At the first node a, the source of the second transistor T2 and the source of the third transistor T3 are electrically connected to the low-level signal VGL; the drain of the second transistor T2, the drain of the fourth transistor T4, and the fifth The gate of the transistor T5 is electrically connected, the gate of the fourth transistor T4, the source of the fourth transistor T4, and the source of the fifth transistor T5 are all electrically connected to the high-level signal VGH; the drain of the third transistor T3 And the drain of the fifth transistor T5 is electrically connected to the second node b.
  • the maintenance module 103 includes a sixth transistor T6; the gate of the sixth transistor T6 is electrically connected to the second node b, the source of the sixth transistor T6 is electrically connected to the low-level signal VGL, and the sixth transistor T6 is electrically connected to the low-level signal VGL.
  • the drain of the transistor T6 is electrically connected to the first node a.
  • the first output module 104 includes a seventh transistor T7; the gate of the seventh transistor T7 is electrically connected to the second node b, and the source of the seventh transistor T7 is electrically connected to the clock signal CK ( n), the drain of the seventh transistor T7 is electrically connected to the current level transmission signal Cout(n).
  • the second output module 105 includes an eighth transistor T8; the gate of the eighth transistor T8 is electrically connected to the second node b, and the source of the eighth transistor T8 is electrically connected to the clock signal CK ( n), the drain of the eighth transistor T8 is electrically connected to the scan signal G(n) of the current stage.
  • the output control module 106 includes a ninth transistor T9 and a tenth transistor T10; the gate of the ninth transistor T9 and the gate of the tenth transistor T10 are both electrically connected to the first node a, and the ninth transistor T9
  • the source of the tenth transistor T10 and the source of the tenth transistor T10 are electrically connected to the high-level signal VGH, the drain of the ninth transistor T9 is electrically connected to the current level transmission signal Cout(n), and the drain of the tenth transistor T10 It is electrically connected to the scanning signal G(n) of this level.
  • the existing GOA circuit generates positive pulse waveform signals
  • the transistors used are generally N-type transistors
  • the existing GOA circuits generate negative pulse waveform signals
  • the transistors used are generally P-type transistors.
  • the P-type transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level. That is, the existing light emitting diode display panel simultaneously generates a positive pulse waveform signal and a negative pulse waveform signal, which requires the use of two different types of transistors.
  • the difference between the GOA circuit 10 provided by the embodiment of this application and the existing GOA circuit is that the GOA circuit 10 provided by the embodiment of this application generates a signal of a negative pulse waveform, and the transistors used are all N-type transistors, which can be used in light-emitting diodes.
  • the same type of transistors are used in, the process is simplified, and the circuit design is relatively simple.
  • FIG. 3 is a signal timing diagram of a GOA unit in the GOA circuit provided by the embodiment of the application.
  • the working sequence of the GOA unit 20 includes: a first time period t1, a second time period t2, and a third time period t3.
  • the clock signal CK(n) of the current stage is at a high potential, so that the first transistor T1 is turned on, and the upper stage transmission signal Cout(n-1) is output to the first node a, so that The potential of a node a is low. Since the potential of the first node a is high, the second transistor T2 and the third transistor T3 are turned off, so that the potential of the second node b is high. Since the potential of the second node b is a high potential, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned on.
  • the potential of the transmission signal Cout(n) of this stage is high, and the scanning signal G(n ) Is a high potential, and the low-level signal VGL is output to the first node a through the sixth transistor T6 to maintain the potential of the first node a at the potential of the low-level signal VGL. Since the potential of the first node a is low, the ninth transistor T9 and the tenth transistor T10 are turned off.
  • the clock signal CK(n) of the current stage is at a low potential, so that the first transistor T1 is turned off, and the potential of the first node a is at a low potential. Since the potential of the first node a is a low potential, the second transistor T2 and the third transistor T3 are turned off, and the potential of the second node b is a high potential. Since the potential of the second node b is a high potential, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned on.
  • the potential of the transmission signal Cout(n) of the current stage is a low potential, and the scan signal G(n ) Is a low potential, and the low-level signal VGL is output to the first node a through the sixth transistor T6 to maintain the potential of the first node a at the potential of the low-level signal VGL. Since the potential of the first node a is low, the ninth transistor T9 and the tenth transistor T10 are turned off.
  • the clock signal CK(n) of the current stage is at a high level, so that the first transistor T1 is turned on, and the upper-stage transmission signal Cout(n-1) is output to the first node a, so that the first node a
  • the potential is high. Since the potential of the first node a is high, the second transistor T2 and the third transistor T3 are turned on, so that the potential of the second node b is low. Since the potential of the second node b is low, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.
  • the ninth transistor T9 and the tenth transistor T10 are turned on, the potential of the transmission signal Cout(n) of this stage is high, and the potential of the scanning signal G(n) of this stage is high Potential.
  • the first transistor T1 is continuously turned on by the clock signal CK(n) of the current stage, and the upper-level transmission signal Cout(n-1) is continuously output to the first node a to maintain the potential of the first node a at a high potential. So as to ensure that the transmission signal Cout(n) of this level and the scanning signal G(n) of this level output high potential for a long time.
  • FIG. 4 is a schematic diagram of a second type of circuit of a GOA unit in the GOA circuit provided by an embodiment of the application.
  • the difference between the circuit shown in FIG. 4 and the circuit shown in FIG. 2 is that the GOA circuit shown in FIG. 4 also includes: an eleventh transistor T11; the gate and source of the eleventh transistor T11 are electrically connected At the reset signal R, the drain of the eleventh transistor T11 is electrically connected to the first node a.
  • each level of GOA unit is reset through the eleventh transistor T11 in each level of GOA unit 20, thereby Improve the stability of GOA circuit.
  • the potential of the reset signal R is high, and the eleventh transistor T11 is turned on, so that the potential of the first node a is high. Since the potential of the first node a is high, the second transistor T2 and the third transistor T3 are turned on, so that the potential of the second node b is low. Since the potential of the second node b is low, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.
  • the ninth transistor T9 and the tenth transistor T10 are turned on, the potential of the transmission signal Cout(n) of this stage is high, and the potential of the scanning signal G(n) of this stage is high Potential.
  • FIG. 5 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • the display panel includes a display area 100 and a GOA circuit 200 integratedly arranged on the edge of the display area 100; wherein the structure and principle of the GOA circuit 200 are similar to the GOA circuit 10 described above, and will not be repeated here.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

L'invention concerne un circuit GOA (10) et un panneau d'affichage. Un signal de forme d'onde d'impulsion négative est délivré au moyen d'une conception de circuit relativement simple.
PCT/CN2019/086401 2019-04-08 2019-05-10 Circuit goa et panneau d'affichage WO2020206796A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910276192.1 2019-04-08
CN201910276192.1A CN110070828B (zh) 2019-04-08 2019-04-08 Goa电路及显示面板

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WO2020206796A1 true WO2020206796A1 (fr) 2020-10-15

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Publication number Priority date Publication date Assignee Title
CN110503913B (zh) * 2019-08-27 2023-02-28 上海中航光电子有限公司 一种扫描电路、显示面板和显示面板的驱动方法
CN111261108A (zh) * 2020-02-11 2020-06-09 深圳市华星光电半导体显示技术有限公司 栅极驱动电路
CN113593460A (zh) * 2021-07-19 2021-11-02 Tcl华星光电技术有限公司 Goa电路

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