WO2020206793A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2020206793A1
WO2020206793A1 PCT/CN2019/086308 CN2019086308W WO2020206793A1 WO 2020206793 A1 WO2020206793 A1 WO 2020206793A1 CN 2019086308 W CN2019086308 W CN 2019086308W WO 2020206793 A1 WO2020206793 A1 WO 2020206793A1
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WIPO (PCT)
Prior art keywords
electrode
display panel
layer
insulating layer
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/086308
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English (en)
French (fr)
Inventor
江志雄
蒙艳红
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US16/618,928 priority Critical patent/US20210356515A1/en
Publication of WO2020206793A1 publication Critical patent/WO2020206793A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • This application relates to the field of display technology, and in particular to a display panel.
  • the display panel includes a substrate 100, a first metal layer 110, a gate insulating layer 120, and a second metal layer 130.
  • Two electrodes (not shown) of the electrostatic test electrode are connected to the first metal layer 110 and The second metal layer 130 is electrically connected.
  • the gate insulating layer 120 is deposited, the thickness of the film in the slope angle area 111 is usually smaller than the thickness of the film in the middle area, so static electricity is likely to occur in the slope angle area 111.
  • the measured thickness is often the slope angle area 111. In this way, it is impossible to characterize the electrostatic breakdown characteristics of the middle region where the thickness of the gate insulating layer 120 is normal.
  • the existing display panel has the technical problem of inaccurate electrostatic testing of the gate insulating layer, which needs to be improved.
  • the present application provides a display panel to alleviate the technical problem of inaccurate electrostatic testing of the gate insulating layer in the existing display panel.
  • the present application provides a display panel to alleviate the technical problem of inaccurate electrostatic testing of the gate insulating layer in the existing display panel.
  • This application provides a display panel, including:
  • the first metal layer is patterned with a first electrode
  • the second metal layer is patterned with a second electrode, and the projections of the second electrode and the first electrode on the substrate overlap;
  • the test circuit layer is electrically connected to the second electrode, and the connection area is located in the projection area of the second electrode on the substrate;
  • the electrostatic test electrode includes a first test electrode and a second test electrode, the first test electrode is electrically connected to the first electrode, and the second test electrode is electrically connected to the test circuit layer.
  • the first metal layer is formed on the substrate, the gate insulating layer is formed on a side of the first metal layer away from the substrate, and the second metal layer is formed on The gate insulating layer is formed on a side away from the first metal layer, the insulating layer is formed on the side of the second metal layer away from the gate insulating layer, and the test circuit layer is formed on the insulating layer away from One side of the second metal layer.
  • the display panel includes a low temperature polysilicon thin film transistor, and the first metal layer is also patterned to form a gate of the low temperature polysilicon thin film transistor.
  • the display panel includes an oxide thin film transistor, and the second metal layer is also patterned to form the gate of the oxide thin film transistor.
  • the display panel includes a storage capacitor, the first metal layer is patterned to form the first metal plate of the storage capacitor, and the second metal layer is patterned to form the storage capacitor.
  • the second metal plate is patterned to form the storage capacitor.
  • the insulating layer is a passivation layer.
  • the insulating layer is a stacked structure of a passivation layer and an interlayer insulating layer.
  • the display panel is a liquid crystal display panel
  • the test circuit layer is a pixel electrode of the liquid crystal display panel.
  • the display panel is an OLED display panel
  • the test circuit layer is a common electrode of the OLED display panel.
  • the test circuit layer is formed on the substrate, the second metal layer is formed on a side of the test circuit layer away from the substrate, and the gate insulating layer is formed on the substrate.
  • the second metal layer is formed on the side away from the test circuit layer, the first metal layer is formed on the side of the gate insulating layer away from the second metal layer, and the insulating layer is formed on the first metal layer A side away from the gate insulating layer.
  • the display panel includes a low temperature polysilicon thin film transistor, and the second metal layer is also patterned to form the gate of the low temperature polysilicon thin film transistor.
  • the display panel includes an oxide thin film transistor, and the first metal layer is also patterned to form the gate of the oxide thin film transistor.
  • the display panel includes a storage capacitor, the first metal layer is patterned to form the first metal plate of the storage capacitor, and the second metal layer is patterned to form the storage capacitor.
  • the second metal plate is patterned to form the storage capacitor.
  • the insulating layer is a passivation layer.
  • the insulating layer is an interlayer insulating layer.
  • the insulating layer is a stacked structure of a passivation layer and an interlayer insulating layer.
  • the first electrode is formed with a first via hole
  • the test circuit layer is formed with a second via hole
  • the first test electrode passes through the first via hole and the first via hole.
  • the electrodes are electrically connected
  • the second test electrode is electrically connected to the test circuit layer through the second via hole.
  • the first electrode is formed with a first connection terminal
  • the test circuit layer is formed with a second connection terminal
  • the first test electrode is connected to the first connection terminal through the first connection terminal.
  • the electrodes are electrically connected
  • the second test electrode is electrically connected to the test circuit layer through the second connection terminal.
  • the first test electrode is formed with a third connection terminal
  • the second test electrode is formed with a fourth connection terminal
  • the first test electrode is connected to the third connection terminal through the third connection terminal.
  • the first electrode is electrically connected
  • the second test electrode is electrically connected to the test circuit layer through the fourth connection terminal.
  • the first electrode is formed with a first connection terminal
  • the test circuit layer is formed with a second connection terminal
  • the first test electrode is formed with a third connection terminal
  • the second test The electrode is formed with a fourth connection terminal
  • the first connection terminal is electrically connected to the third connection terminal
  • the second connection terminal is electrically connected to the fourth connection terminal.
  • the present application provides a display panel, including a substrate, a first metal layer, a second metal layer, a gate insulating layer, an insulating layer, a test circuit layer, and an electrostatic test electrode.
  • the first metal layer is patterned with a first electrode;
  • the second metal layer is patterned with a second electrode, and the projections of the second electrode and the first electrode on the substrate overlap;
  • the gate insulating layer is formed on the first metal layer and the Between the second metal layers;
  • the test circuit layer is electrically connected to the second electrode, and the connection area is located in the projection area of the second electrode on the substrate;
  • the electrostatic test electrode includes a first test electrode And a second test electrode, the first test electrode is electrically connected with the first electrode, and the second test electrode is electrically connected with the test circuit layer.
  • the first test electrode is electrically connected to the first electrode
  • the second test electrode is electrically connected to the test circuit layer. Since an insulating layer is also provided between the first metal layer and the test circuit layer, the gradient angle of the gate insulating layer is The zone film layer is thick and is not easy to generate static electricity, so the static test electrode can test the anti-static ability of the middle area of the gate insulating layer.
  • FIG. 1 is a schematic diagram of the structure of an existing display panel
  • FIG. 2 is a schematic diagram of the first structure of a display panel provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of a second structure of a display panel provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of a third structure of a display panel provided by an embodiment of the application.
  • FIG. 5 is a schematic diagram of a fourth structure of a display panel provided by an embodiment of the application.
  • the present application provides a display panel to alleviate the technical problem of inaccurate electrostatic testing of the gate insulating layer in the existing display panel.
  • FIG. 2 it is a schematic diagram of the first structure of the display panel provided by the embodiment of this application.
  • the display panel includes a substrate 10, a first metal layer, a gate insulating layer 30, a second metal layer, an insulating layer 50, a test circuit layer 60, and an electrostatic test electrode.
  • the substrate 10 may be a flexible substrate, and its material may include at least one of polyimide, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyarylate, and polyethersulfone. One kind.
  • the substrate 10 may also be a rigid substrate, and specifically may be a glass substrate or other rigid substrates. The embodiments of the present application do not limit the type and material of the substrate.
  • the first metal layer is formed on the substrate 10, and the first electrode 20 is patterned and formed.
  • the material of the first metal layer may include at least one of titanium, aluminum and copper.
  • the embodiment of the present application does not compare the material of the first metal layer. To limit, only the test signal can be conducted normally.
  • the gate insulating layer 30 is formed on the side of the first metal layer away from the substrate 10.
  • the material of the gate insulating layer 30 is generally silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or an interlayer of the three. Structure etc.
  • the gate insulating layer 30 is formed on the first metal layer by a chemical vapor deposition method.
  • the second metal layer is formed on the side of the gate insulating layer 30 away from the first electrode 20, and is patterned to form the second electrode 40.
  • the second metal layer is made of aluminum, titanium, copper or other metal materials.
  • the projections of the second electrode 40 and the first electrode 20 on the substrate 10 coincide.
  • the projection range of the second electrode 40 on the substrate 10 is equal to the projection of the first electrode 20 on the substrate 10, and the overlapping area corresponds to the middle area where the thickness of the gate insulating layer 30 is normal.
  • the second electrode 40 Since the projection range of the second electrode 40 on the substrate 10 is equal to the projection of the first electrode 20 on the substrate 10, the second electrode 40 does not cover the gate insulating layer 30 in the slope angle area 200, so that when the first electrode 20 and the second electrode 20 When there is current on the electrode 40, the gate insulating layer 30 located in the slope angle area 200 will not have current accumulation, that is, the current will only act on the gate insulating layer 30 located in the middle area, increasing the test of the gate insulating layer 30 Accuracy.
  • the display panel includes a low-temperature polysilicon thin film transistor, and the first metal layer is also patterned to form a gate of the low-temperature polysilicon thin film transistor.
  • Low-temperature polysilicon thin-film transistors have outstanding advantages such as low preparation temperature, high carrier mobility, and small device size, and are widely used in display panels.
  • the low-temperature polysilicon thin film transistor has a bottom gate structure, and the first metal layer is patterned to form the gate of the low-temperature polysilicon thin film transistor, which is arranged in the same layer as the first electrode 20.
  • the display panel includes an oxide thin film transistor, and the second metal layer is further patterned to form the gate of the oxide thin film transistor.
  • the oxide thin film transistor has a top gate structure, and the second metal layer is patterned to form the gate of the oxide thin film transistor, which is arranged in the same layer as the second electrode 40.
  • the display panel includes a storage capacitor, and the first metal layer and the second metal layer are the first metal plate and the second metal plate of the storage capacitor.
  • the insulating layer 50 is formed on the side of the second metal layer away from the gate insulating layer 30.
  • the insulating layer 50 is a passivation layer, and the material of the insulating layer 50 can be silicon oxide (SiOx), silicon nitride (SiNx), or a sandwich structure of the two, etc., for opposing the second electrode 40 Protect the second electrode 40 from being corroded by water vapor or oxygen, causing corrosion or oxidation.
  • the insulating layer 50 is a stacked structure of a passivation layer and an interlayer insulating layer.
  • the interlayer insulating layer is formed on the side of the second metal layer away from the gate insulating layer 30, and the passivation layer is formed on the The side of the interlayer insulating layer away from the second metal layer.
  • the material of the interlayer insulating layer is organic photoresist, and the material of the passivation layer can be silicon oxide (SiOx), silicon nitride (SiNx), or a sandwich structure of the two.
  • the test circuit layer 60 is formed on the insulating layer 50 away from the second metal layer, and is electrically connected to the second electrode 40, and the connection area is located in the projection area of the second electrode 40 on the substrate 10.
  • connection area where the test circuit layer 60 is electrically connected to the second electrode 40 is located in the projection area of the second electrode 40 on the substrate 10, that is, the connection area is only located in the middle area where the thickness of the gate insulating layer 30 is normal.
  • the gate insulating layer 30 located in the slope angle area 200 will not have current accumulation, that is, the current will only act on the gate insulating layer 30 located in the middle area, which further increases the gate insulation. Level 30 test accuracy.
  • a via hole (not shown in the figure) is formed on the insulating layer 50, and the via hole completely penetrates the insulating layer 50 so that the second electrode 40 can be exposed through the via hole, and the test circuit layer 60 and the second electrode 40 pass through the via hole. In this way, when the test is performed, it can be ensured that the second electrode 40 is in good contact with the test circuit layer 60, and the signal of the second electrode 40 can be well transmitted to the test circuit layer 60.
  • the via is formed by etching the insulating layer 50, and the specific etching method may be dry etching or wet etching.
  • the via can also be formed by other methods, and the embodiment of the present application does not limit how to form the via.
  • the display panel is a liquid crystal display panel
  • the test circuit layer 60 is a pixel electrode of the liquid crystal display panel.
  • the display panel is an OLED display panel
  • the test circuit layer 60 is a common electrode of the OLED display panel
  • the common electrode is a transparent conductive layer made of indium tin metal oxide (ITO) material.
  • the electrostatic test electrode is used to test the antistatic ability of the gate insulating layer 40.
  • the electrostatic test electrode includes a first test electrode (not shown in the figure) and a second test electrode (not shown in the figure), the first test electrode and the first electrode 20 The second test electrode is electrically connected to the test circuit layer 60.
  • the first test electrode of the electrostatic test electrode is electrically connected with the first metal layer
  • the second test electrode is electrically connected with the second metal layer.
  • the gate insulating layer is located between the first metal layer and the second metal layer. Because the gate insulating layer is non-conductive under normal conditions, when the current provided by the electrostatic test electrode is small, the gate insulating layer is not broken down and the first metal There is no conduction between the layer and the second metal layer, that is, there is no conduction between the first electrode and the second electrode of the electrostatic test electrode, and no current can be tested. When the current provided by the electrostatic test electrode gradually increases and reaches a critical value, the gate insulating layer is broken down. At this time, the first metal layer and the second metal layer are connected at the breakdown point, and the first electrode of the electrostatic test electrode and There is conduction between the second electrodes, and current is detected.
  • the electrostatic test electrode electrically connects the first electrode and the first metal layer, and the second electrode and the second metal layer are electrically connected to form an increased current. By detecting the current or not, the electrostatic breakdown characteristics of the gate insulating layer are obtained. The current value at the moment when the first electrode and the second electrode are turned on reflects the antistatic ability of the gate insulating layer.
  • the gate insulating layer when the gate insulating layer is formed, a slope angle area is formed. In the slope angle area at the edge, the thickness of the gate insulation layer is small, and in the middle area, the thickness of the gate insulation layer is large. Normally, what the electrostatic test electrode needs to test is whether the middle area of the gate insulating layer is broken down by static electricity, and in the slope corner area of the edge, the thickness of the gate insulating layer is small, so when the electrostatic test electrode is applied with current, This area is often broken down first. At this time, the first electrode and the second electrode are connected, and the electrostatic test electrode obtains an electrostatic value.
  • the static electricity value at this time reflects the antistatic ability of the gate insulating layer in the slope corner area of the edge, but cannot reflect the antistatic ability of the gate insulating layer in the middle area. Therefore, the result of the electrostatic test electrode test is not accurate.
  • the value of is smaller than the actual value, and it is difficult to characterize the electrostatic breakdown characteristics of the middle region where the thickness of the gate insulating layer is normal.
  • This application conducts the signal of the second electrode 40 to the test circuit layer 60.
  • the first test electrode is electrically connected to the first electrode 20, and the second test electrode is electrically connected to the test circuit layer 60. Since an insulating layer 50 is also formed on the gate insulating layer 30 between the test circuit layer 60 and the first electrode 20, the thickness of the insulating film in the slope angle region 200 increases, and the thickness is not less than that of the gate insulating layer 30 The thickness of the middle area.
  • the test circuit layer 60 is electrically connected to the second electrode 40, and the connection area is located in the projection area of the second electrode 40 on the substrate 10.
  • the gate insulating layer 30 located in the slope angle area 200 will not have current accumulation, that is, the current will only act on the gate insulating layer 30 located in the middle area.
  • the gate insulating layer 30 in the gradient angle region 200 will not be broken down first, and the gate insulating layer 30 in the middle area will be broken down first, so the electrostatic test electrode
  • the measured current value at the moment when the first test electrode and the second test electrode are turned on correctly reflects the electrostatic breakdown characteristics of the middle region where the thickness of the gate insulating layer is normal.
  • the first electrode 20 is formed with a first via hole (not shown), and the test circuit layer 60 is formed with a second via hole (not shown in the figure). (Shown), the first test electrode is electrically connected to the first electrode 20 through the first via hole, and the second test electrode is electrically connected to the test circuit layer 60 through the second via hole.
  • the first electrode 20 is formed with a first connection terminal (not shown)
  • the test circuit layer 60 is formed with a second connection terminal (not shown)
  • the first test electrode passes through the first connection terminal. It is electrically connected to the first electrode 20, and the second test electrode is electrically connected to the test circuit layer 60 through the second connection terminal.
  • the first test electrode is formed with a third connection terminal (not shown in the figure)
  • the second test electrode is formed with a fourth connection terminal (not shown in the figure)
  • the first test electrode passes through the third connection terminal. It is electrically connected to the first electrode 20, and the second test electrode is electrically connected to the test circuit layer 60 through the fourth connection terminal.
  • the first electrode 20 is formed with a first connection terminal (not shown), the test circuit layer 60 is formed with a second connection terminal (not shown), and the first test electrode is formed with a third connection.
  • the second test electrode is formed with a fourth connection terminal (not shown in the figure)
  • the first connection terminal is electrically connected to the third connection terminal
  • the second connection terminal is electrically connected to the fourth connection terminal.
  • FIG. 3 it is a schematic diagram of the second structure of the display panel provided by the embodiment of this application.
  • the display panel includes a substrate 10, a first metal layer, a gate insulating layer 30, a second metal layer, an insulating layer 50, a test circuit layer 60, and an electrostatic test electrode.
  • the display panel in this embodiment further includes a color resist layer 80.
  • the color resist layer 80 is formed on the side of the insulating layer 50 away from the second metal layer.
  • the test circuit layer 60 is formed on the color resist layer. 80 away from the side of the insulating layer 50.
  • the display panel is a COA (Color Filter on Array) type liquid crystal display panel.
  • the COA type display panel refers to a liquid crystal display panel prepared by using COA technology.
  • COA technology is a color filter in the field of liquid crystal display technology.
  • COA(Color Filter on Array) technology can reduce parasitic capacitance, increase aperture ratio and relieve MM Mura's technical advantages have gradually surpassed traditional non-COA technologies in the market and have played an increasingly important position.
  • the thickness of the insulating film in the slope angle region 200 is further increased, and the thickness It is not less than the thickness of the middle region of the gate insulating layer 30, so the gate insulating layer 30 in the gradient angle region 200 is less likely to be broken down, and the accuracy of the electrostatic test is further improved.
  • FIG. 4 it is a schematic diagram of the third structure of the display panel provided by the embodiment of this application.
  • the display panel includes a substrate 10, a first metal layer, a gate insulating layer 30, a second metal layer, an insulating layer 50, a test circuit layer 60, and an electrostatic test electrode.
  • the test circuit layer 60 is formed on the substrate 10, the second metal layer is formed on the side of the test circuit layer 60 away from the substrate 10, and the gate insulating layer 30 is formed on the side of the second metal layer away from the test circuit layer 60.
  • the first metal layer It is formed on the side of the gate insulating layer 30 away from the second metal layer, and the insulating layer 50 is formed on the side of the first metal layer away from the gate insulating layer 30.
  • the second metal layer is patterned to form a second electrode 40
  • the first metal layer is patterned to form a first electrode 20.
  • the projection of the second electrode 40 and the first electrode 20 on the substrate 10 overlaps, and the overlap area corresponds to the gate insulating layer 30 The middle area with normal film thickness. In this way, when both the first electrode 20 and the second electrode 40 have current, the gate insulating layer 30 located in the slope angle area 200 will not have current accumulation, that is, the current will only act on the gate insulating layer 30 located in the middle area. , Which increases the accuracy of the test of the gate insulating layer 30.
  • the test circuit layer 60 is electrically connected to the second electrode 40, and the connection area is located in the projection area of the second electrode 40 on the substrate 10.
  • connection area where the test circuit layer 60 is electrically connected to the second electrode 40 is located in the projection area of the second electrode 40 on the substrate 10, that is, the connection area is only located in the middle area where the thickness of the gate insulating layer 30 is normal.
  • the gate insulating layer 30 located in the slope angle area 200 will not have current accumulation, that is, the current will only act on the gate insulating layer 30 located in the middle area, which further increases the gate insulation. Level 30 test accuracy.
  • the material of the gate insulating layer 30 is generally silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or a sandwich structure of the three, and is formed on the second metal layer by chemical vapor deposition.
  • the insulating layer 50 is formed on the side of the first metal layer away from the gate insulating layer 30.
  • the insulating layer 50 is a passivation layer, and the material of the insulating layer 50 can be silicon oxide (SiOx), silicon nitride (SiNx), or a sandwich structure of the two, etc., for the first electrode 20 Protect the first electrode 20 from being corroded by water vapor or oxygen, causing corrosion or oxidation.
  • the insulating layer 50 is an interlayer insulating layer, and the material of the interlayer insulating layer is an organic photoresist.
  • the insulating layer 50 is a stacked structure of a passivation layer and an interlayer insulating layer.
  • the interlayer insulating layer is formed on the side of the second metal layer away from the gate insulating layer 30, and the passivation layer is formed on the The side of the interlayer insulating layer away from the second metal layer.
  • the material of the interlayer insulating layer is organic photoresist, and the material of the passivation layer can be silicon oxide (SiOx), silicon nitride (SiNx), or a sandwich structure of the two.
  • the display panel further includes a conductive layer 70, the insulating layer 50 is formed with a via hole (not shown), and the via hole completely penetrates the insulating layer 50, so that the second electrode 40 can be exposed through the opening of the via hole. , The conductive layer 70 and the first electrode 20 are electrically connected through the opening.
  • the via is formed by etching the insulating layer 50, and the specific etching method may be dry etching or wet etching.
  • the via can also be formed by other methods, and the embodiment of the present application does not limit how to form the via.
  • the display panel is a liquid crystal display panel
  • the conductive layer 70 is a pixel electrode of the liquid crystal display panel.
  • the display panel is an OLED display panel
  • the conductive layer 70 is a common electrode of the OLED display panel
  • the common electrode is a transparent conductive layer made of indium tin metal oxide (ITO) material.
  • the display panel includes a low temperature polysilicon thin film transistor, and the second metal layer is patterned to form a gate of the low temperature polysilicon thin film transistor.
  • Low-temperature polysilicon thin-film transistors have outstanding advantages such as low preparation temperature, high carrier mobility, and small device size, and are widely used in display panels.
  • the low-temperature polysilicon thin film transistor has a bottom gate structure, and the second metal layer is patterned to form the gate of the low-temperature polysilicon thin film transistor, which is arranged in the same layer as the second electrode 40.
  • the display panel includes an oxide thin film transistor, and the first metal layer is patterned to form the gate of the oxide thin film transistor.
  • the oxide thin film transistor has a top gate structure, and the first metal layer is patterned to form the gate of the oxide thin film transistor, which is arranged in the same layer as the first electrode 20.
  • the display panel includes a storage capacitor, and the first metal layer and the second metal layer are the first metal plate and the second metal plate of the storage capacitor.
  • This application conducts the signal of the second electrode 40 to the test circuit layer 60.
  • the first test electrode is electrically connected to the first electrode 20, and the second test electrode is electrically connected to the test circuit layer 60. Since an insulating layer 50 is also formed on the gate insulating layer 30 between the test circuit layer 60 and the first electrode 20, the thickness of the insulating film in the slope angle region 200 increases, and the thickness is not less than that of the gate insulating layer 30 The thickness of the middle area.
  • the test circuit layer 60 is electrically connected to the second electrode 40, and the connection area is located in the projection area of the second electrode 40 on the substrate 10.
  • the gate insulating layer 30 located in the slope angle area 200 will not have current accumulation, that is, the current will only act on the gate insulating layer 30 located in the middle area.
  • the gate insulating layer 30 in the gradient angle region 200 will not be broken down first, and the gate insulating layer 30 in the middle area will be broken down first, so the electrostatic test electrode
  • the measured current value at the moment when the first test electrode and the second test electrode are turned on correctly reflects the electrostatic breakdown characteristics of the middle region where the thickness of the gate insulating layer is normal.
  • the first electrode 20 is formed with a first via hole (not shown), and the test circuit layer 60 is formed with a second via hole (not shown in the figure). (Shown), the first test electrode is electrically connected to the first electrode 20 through the first via hole, and the second test electrode is electrically connected to the test circuit layer 60 through the second via hole.
  • the first electrode 20 is formed with a first connection terminal (not shown)
  • the test circuit layer 60 is formed with a second connection terminal (not shown)
  • the first test electrode passes through the first connection terminal. It is electrically connected to the first electrode 20, and the second test electrode is electrically connected to the test circuit layer 60 through the second connection terminal.
  • the first test electrode is formed with a third connection terminal (not shown in the figure)
  • the second test electrode is formed with a fourth connection terminal (not shown in the figure)
  • the first test electrode passes through the third connection terminal. It is electrically connected to the first electrode 20, and the second test electrode is electrically connected to the test circuit layer 60 through the fourth connection terminal.
  • the first electrode 20 is formed with a first connection terminal (not shown), the test circuit layer 60 is formed with a second connection terminal (not shown), and the first test electrode is formed with a third connection.
  • the second test electrode is formed with a fourth connection terminal (not shown in the figure)
  • the first connection terminal is electrically connected to the third connection terminal
  • the second connection terminal is electrically connected to the fourth connection terminal.
  • FIG. 5 it is a schematic diagram of the fourth structure of the display panel provided by the embodiment of this application.
  • the display panel includes a substrate 10, a first metal layer, a gate insulating layer 30, a second metal layer, an insulating layer 50, a test circuit layer 60, and an electrostatic test electrode.
  • the display panel in this embodiment further includes a color resist layer 80.
  • the color resist layer 80 is formed on the side of the insulating layer 50 away from the second metal layer.
  • the test circuit layer 60 is formed on the color resist layer. 80 away from the side of the insulating layer 50.
  • the display panel is a COA (Color Filter on Array) type liquid crystal display panel.
  • the COA type display panel refers to a liquid crystal display panel prepared by using COA technology.
  • COA technology is a color filter in the field of liquid crystal display technology.
  • COA(Color Filter on Array) technology can reduce parasitic capacitance, increase aperture ratio and relieve MM Mura's technical advantages have gradually surpassed traditional non-COA technologies in the market and have played an increasingly important position.
  • the thickness of the insulating film in the slope angle region 200 is further increased, and the thickness It is not less than the thickness of the middle region of the gate insulating layer 30, so the gate insulating layer 30 in the gradient angle region 200 is less likely to be broken down, and the accuracy of the electrostatic test is further improved.
  • the application provides a display panel, including a substrate, a first metal layer, a second metal layer, a gate insulating layer, an insulating layer, a test circuit layer, and an electrostatic test electrode.
  • the first metal layer is patterned with a first electrode;
  • the metal layer is patterned to form a second electrode, and the projections of the second electrode and the first electrode on the substrate overlap;
  • the gate insulating layer is formed between the first metal layer and the second metal layer;
  • the test circuit layer is electrically connected to the second electrode , And the connection area is located in the projection area of the second electrode on the substrate;
  • the electrostatic test electrode includes a first test electrode and a second test electrode, the first test electrode is electrically connected to the first electrode, and the second test electrode is electrically connected to the test circuit layer.
  • the electrostatic test electrode can test the anti-static properties of the middle area of the gate insulating layer. Electrostatic ability.

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Abstract

一种显示面板，其包括第二金属层和第一金属层；第二金属层形成的第二电极（40）和第一金属层形成的第一电极（20）在基板（10）上的投影重合；栅绝缘层（30）形成于第一金属层和第二金属层之间；测试电路层（60）与第二电极（40）电连接；静电测试电极的第一测试电极与第一电极（20）电连接，第二测试电极与测试电路层（60）电连接，可以测试栅绝缘层（30）中间区域的防静电能力。

Description

显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板。
 背景技术
现有的显示面板制备过程中，通常需要测试栅绝缘层的抵抗静电击穿的能力。如图1所示，显示面板包括基板100、第一金属层110、栅绝缘层120、第二金属层130，静电测试电极的两个电极（图未示出）分别与第一金属层110和第二金属层130电连接。由于栅绝缘层120沉积时，在坡度角区111的膜层厚度通常比中间区域膜层厚度小，因此容易在坡度角区111发生静电，静电测试时，测试到的往往是坡度角区111被击穿，这样就无法表征栅绝缘层120膜厚正常的中间区域的静电击穿特性。
因此，现有的显示面板存在栅绝缘层静电测试不准确的技术问题，需要改进。
 技术问题
本申请提供一种显示面板，以缓解现有的显示面板中栅绝缘层静电测试不准确的技术问题。
 技术解决方案
本申请提供一种显示面板，以缓解现有的显示面板中栅绝缘层静电测试不准确的技术问题。
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种显示面板，包括：
基板；
第一金属层，图案化形成有第一电极；
第二金属层，图案化形成有第二电极，所述第二电极和所述第一电极在所述基板上的投影重合；
栅绝缘层，形成于所述第一金属层和所述第二金属层之间；
绝缘层；
测试电路层，与所述第二电极电连接，且连接区域位于所述第二电极在所述基板上的投影区域内；
静电测试电极，包括第一测试电极和第二测试电极，所述第一测试电极与所述第一电极电连接，所述第二测试电极与所述测试电路层电连接。
在本申请的显示面板中，所述第一金属层形成在所述基板上，所述栅绝缘层形成在所述第一金属层远离所述基板的一侧，所述第二金属层形成在所述栅绝缘层远离所述第一金属层的一侧，所述绝缘层形成在所述第二金属层远离所述栅绝缘层的一侧，所述测试电路层形成在所述绝缘层远离所述第二金属层的一侧。
在本申请的显示面板中，所述显示面板包括低温多晶硅薄膜晶体管，所述第一金属层还图案化形成所述低温多晶硅薄膜晶体管的栅极。
在本申请的显示面板中，所述显示面板包括氧化物薄膜晶体管，所述第二金属层还图案化形成所述氧化物薄膜晶体管的栅极。
在本申请的显示面板中，所述显示面板包括存储电容，所述第一金属层图案化形成所述存储电容的第一金属极板，所述第二金属层图案化形成所述存储电容的第二金属极板。
在本申请的显示面板中，所述绝缘层为钝化层。
在本申请的显示面板中，所述绝缘层为钝化层和层间绝缘层的叠层结构。
在本申请的显示面板中，所述显示面板为液晶显示面板，所述测试电路层为所述液晶显示面板的像素电极。
在本申请的显示面板中，所述显示面板为OLED显示面板，所述测试电路层为所述OLED显示面板的公共电极。
在本申请的显示面板中，所述测试电路层形成在所述基板上，所述第二金属层形成在所述测试电路层远离所述基板的一侧，所述栅绝缘层形成在所述第二金属层远离所述测试电路层的一侧，所述第一金属层形成在所述栅绝缘层远离所述第二金属层的一侧，所述绝缘层形成在所述第一金属层远离所述栅绝缘层的一侧。
在本申请的显示面板中，所述显示面板包括低温多晶硅薄膜晶体管，所述第二金属层还图案化形成所述低温多晶硅薄膜晶体管的栅极。
在本申请的显示面板中，所述显示面板包括氧化物薄膜晶体管，所述第一金属层还图案化形成所述氧化物薄膜晶体管的栅极。
在本申请的显示面板中，所述显示面板包括存储电容，所述第一金属层图案化形成所述存储电容的第一金属极板，所述第二金属层图案化形成所述存储电容的第二金属极板。
在本申请的显示面板中，所述绝缘层为钝化层。
在本申请的显示面板中，所述绝缘层为层间绝缘层。
在本申请的显示面板中，所述绝缘层为钝化层和层间绝缘层的叠层结构。
在本申请的显示面板中，所述第一电极形成有第一过孔，所述测试电路层形成有第二过孔，所述第一测试电极通过所述第一过孔与所述第一电极电连接，所述第二测试电极通过所述第二过孔与所述测试电路层电连接。
在本申请的显示面板中，所述第一电极形成有第一连接端子，所述测试电路层形成有第二连接端子，所述第一测试电极通过所述第一连接端子与所述第一电极电连接，所述第二测试电极通过所述第二连接端子与所述测试电路层电连接。
在本申请的显示面板中，所述第一测试电极形成有第三连接端子，所述第二测试电极形成有第四连接端子，所述第一测试电极通过所述第三连接端子与所述第一电极电连接，所述第二测试电极通过所述第四连接端子与所述测试电路层电连接。
在本申请的显示面板中，所述第一电极形成有第一连接端子，所述测试电路层形成有第二连接端子，所述第一测试电极形成有第三连接端子，所述第二测试电极形成有第四连接端子，所述第一连接端子与所述第三连接端子电连接，所述第二连接端子与所述第四连接端子电连接。
 有益效果
本申请提供一种显示面板，包括基板、第一金属层、第二金属层、栅绝缘层、绝缘层、测试电路层和静电测试电极，所述第一金属层图案化形成有第一电极；所述第二金属层图案化形成有第二电极，所述第二电极和所述第一电极在所述基板上的投影重合；所述栅绝缘层形成于所述第一金属层和所述第二金属层之间；所述测试电路层与所述第二电极电连接，且连接区域位于所述第二电极在所述基板上的投影区域内；所述静电测试电极包括第一测试电极和第二测试电极，所述第一测试电极与所述第一电极电连接，所述第二测试电极与所述测试电路层电连接。本申请将第一测试电极与第一电极电连接，将第二测试电极与测试电路层电连接，由于第一金属层与测试电路层之间还设置有绝缘层，在栅绝缘层的坡度角区膜层较厚，不易发生静电，因此静电测试电极可以测试栅绝缘层中间区域的防静电能力。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有的显示面板的结构示意图；
图2为本申请实施例提供的显示面板的第一种结构示意图；
图3为本申请实施例提供的显示面板的第二种结构示意图；
图4为本申请实施例提供的显示面板的第三种结构示意图；
图5为本申请实施例提供的显示面板的第四种结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请提供一种显示面板，以缓解现有的显示面板中栅绝缘层静电测试不准确的技术问题。
如图2所示，为本申请实施例提供的显示面板的第一种结构示意图。显示面板包括基板10、第一金属层、栅绝缘层30、第二金属层、绝缘层50、测试电路层60和静电测试电极。
基板10可以为柔性衬底，其材料可以包括聚酰亚胺、聚对苯二甲酸乙 二醇酯、聚萘二甲酸乙二醇酯、聚碳酸酯、聚芳酯以及聚醚砜中的至少一种。基板10也可以为刚性衬底，具体可以为玻璃衬底或者其他刚性衬底。本申请实施例不对衬底的种类以及材料进行限定。
第一金属层形成于基板10上，并图案化形成有第一电极20，第一金属层的材料可以包括钛、铝以及铜中的至少一种，本申请实施例不对第一金属层的材料进行限定，只需可以正常传导测试信号即可。
栅绝缘层30形成于第一金属层远离基板10的一侧，栅绝缘层30的材料一般为氧化硅(SiOx)、氮化硅(SiNx)、氮氧化硅(SiON)、或者三者的夹层结构等。
在一种实施例中，栅绝缘层30通过化学气相沉积的方法，形成在第一金属层上。
第二金属层形成于栅绝缘层30远离第一电极20的一侧，并图案化形成有第二电极40，第二金属层为铝层、钛层、铜层或其他金属材料制成，第二电极40与第一电极20在基板10上的投影重合。在本实施例中，第二电极40在基板10上的投影范围等于第一电极20在基板10上的投影，重合区域对应栅绝缘层30膜厚正常的中间区域。
由于第二电极40在基板10上的投影范围等于第一电极20在基板10上的投影，第二电极40没有覆盖坡度角区200内的栅绝缘层30，这样当第一电极20和第二电极40上均有电流时，位于坡度角区200内的栅绝缘层30不会有电流聚集，即电流只会作用在位于中间区域内的栅绝缘层30上，增大了栅绝缘层30测试的准确性。
在一种实施例中，显示面板包括低温多晶硅薄膜晶体管，第一金属层还图案化形成低温多晶硅薄膜晶体管的栅极。
低温多晶硅薄膜晶体管具有制备温度低，载流子迁移率高，器件尺寸小等突出优点，在显示面板中普遍应用。在本实施例中，低温多晶硅薄膜晶体管为底栅结构，第一金属层图案化形成低温多晶硅薄膜晶体管的栅极，与第一电极20同层设置。
在一种实施例中，显示面板包括氧化物薄膜晶体管，第二金属层还图案化形成氧化物薄膜晶体管的栅极。
氧化物薄膜晶体管的生产工艺简单，光刻书面较少，且均匀性很好，广泛应用与高代线、大尺寸显示面板上。在本实施例中，氧化物薄膜晶体管为顶栅结构，第二金属层图案化形成氧化物薄膜晶体管的栅极，与第二电极40同层设置。
在一种实施例中，显示面板包括存储电容，第一金属层和第二金属层为存储电容的第一金属极板和第二金属极板。
绝缘层50形成于第二金属层远离栅绝缘层30的一侧。
在一种实施例中，绝缘层50为钝化层，绝缘层50的材质可以为氧化硅(SiOx)、氮化硅(SiNx)、或者二者的夹层结构等，用于对第二电极40进行保护，避免第二电极40受到水汽或者氧气侵蚀，发生腐蚀或者氧化现象。
在一种实施例中，绝缘层50为钝化层和层间绝缘层的叠层结构，层间绝缘层形成在第二金属层远离栅绝缘层30的一侧，钝化层形成在所述层间绝缘层远离第二金属层的一侧。层间绝缘层的材料为有机光阻，钝化层的材质可以为氧化硅(SiOx)、氮化硅(SiNx)、或者二者的夹层结构等。
测试电路层60形成于绝缘层50远离第二金属层的方向上，与第二电极40电连接，且连接区域位于第二电极40在基板10上的投影区域内。
由于测试电路层60与第二电极40电连接的连接区域位于第二电极40在基板10上的投影区域内，即连接区域仅位于栅绝缘层30膜厚正常的中间区域，当测试电路层60与第一电极20都有电流时，位于坡度角区200内的栅绝缘层30不会有电流聚集，即电流只会作用在位于中间区域内的栅绝缘层30上，进一步增大了栅绝缘层30测试的准确性。
绝缘层50上形成有过孔（图未示出），且过孔完全贯穿绝缘层50，以便通过过孔可以露出第二电极40，测试电路层60与第二电极40通过该过孔电性连接，这样在进行测试时，可以保证第二电极40与测试电路层60良好接触，保证第二电极40的信号良好传输至测试电路层60中。
在一种实施例中，过孔是通过刻蚀绝缘层50的方式形成，具体的刻蚀方式可以是干法刻蚀或者湿法刻蚀。当然，还可以通过其他方法形成过孔，本申请实施例对如何形成过孔不进行限定。
在一种实施例中，显示面板为液晶显示面板，测试电路层60为液晶显示面板的像素电极。
在一种实施例中，显示面板为OLED显示面板，测试电路层60为OLED显示面板的公共电极，公共电极是由铟锡金属氧化物(ITO)材料制成的透明导电层。
静电测试电极用于测试栅绝缘层40的防静电能力，静电测试电极包括第一测试电极（图未示出）和第二测试电极（图未示出），第一测试电极与第一电极20电连接，第二测试电极与测试电路层60电连接。
在现有的显示面板中，静电测试电极的第一测试电极与第一金属层电连接，第二测试电极与第二金属层电连接。静电测试电极在测试栅绝缘层的静电击穿特性时，需对第一电极和第二电极通电，并逐渐加大电流。
栅绝缘层位于第一金属层与第二金属层之间，由于栅绝缘层在正常情况下是不导电的，因此静电测试电极提供的电流较小时，栅绝缘层未被击穿，第一金属层和第二金属层之间不导通，也即静电测试电极的第一电极和第二电极之间不导通，测试不到有电流。当静电测试电极提供的电流逐渐增大，达到一临界值时，栅绝缘层被击穿，此时第一金属层与第二金属层在击穿点导通，静电测试电极的第一电极和第二电极之间导通，测试到有电流。静电测试电极通过将第一电极与第一金属层电连接，第二电极与第二金属层电连接，并组建增大电流，通过检测到电流与否，得到栅绝缘层的静电击穿特性。第一电极和第二电极导通时刻的电流值反映了栅绝缘层的抗静电能力。
然而，栅绝缘层在形成时，会形成坡度角区，在边缘的坡度角区内，栅绝缘层的膜层厚度较小，在中间区域，栅绝缘层的膜层厚度较大。通常情况下，静电测试电极需要测试的是栅绝缘层的中间区域是否被静电击穿，而在边缘的坡度角区内，栅绝缘层的膜层厚度较小，因此静电测试电极施加电流时，该区域往往先被击穿，此时第一电极和第二电极导通，静电测试电极得到一个静电值。但此时的静电值反映的是栅绝缘层在边缘的坡度角区内的抗静电能力，而不能反映栅绝缘层在中间区域的抗静电能力，因此静电测试电极测试的结果不准确，测得的值比实际偏小，难以表征栅绝缘层膜厚正常的中间区域的静电击穿特性。
本申请通过将第二电极40的信号传导至测试电路层60，在静电测试电极工作时，第一测试电极与第一电极20电连接，第二测试电极与测试电路层60电连接。由于在测试电路层60与第一电极20之间，栅绝缘层30上还形成有绝缘层50，在坡度角区200内，起绝缘作用的膜层厚度增加，且厚度不小于栅绝缘层30的中间区域的厚度。同时，由于第二电极40和第一电极20在基板10上的投影重合，测试电路层60与第二电极40电连接，且连接区域位于第二电极40在基板10上的投影区域内，因此当静电测试电极通电时，位于坡度角区200内的栅绝缘层30不会有电流聚集，即电流只会作用在位于中间区域内的栅绝缘层30上。
因此，静电测试电极的测试电流逐渐增大时，在坡度角区200内的栅绝缘层30不会首先被击穿，首先被击穿的是中间区域内的栅绝缘层30，这样静电测试电极测试到的让第一测试电极和第二测试电极导通时刻的电流值，正确反映了栅绝缘层膜厚正常的中间区域的静电击穿特性。
静电测试电极与显示面板的连接方式有多种，在一种实施例中，第一电极20形成有第一过孔（图未示出），测试电路层60形成有第二过孔（图未示出），第一测试电极通过第一过孔与第一电极20电连接，第二测试电极通过第二过孔与测试电路层60电连接。
在一种实施例中，第一电极20形成有第一连接端子（图未示出），测试电路层60形成有第二连接端子（图未示出），第一测试电极通过第一连接端子与第一电极20电连接，第二测试电极通过第二连接端子与测试电路层60电连接。
在一种实施例中，第一测试电极形成有第三连接端子（图未示出），第二测试电极形成有第四连接端子（图未示出），第一测试电极通过第三连接端子与第一电极20电连接，第二测试电极通过第四连接端子与测试电路层60电连接。
在一种实施例中，第一电极20形成有第一连接端子（图未示出），测试电路层60形成有第二连接端子（图未示出），第一测试电极形成有第三连接端子（图未示出），第二测试电极形成有第四连接端子（图未示出），第一连接端子与第三连接端子电连接，第二连接端子与第四连接端子电连接。
如图3所示，为本申请实施例提供的显示面板的第二种结构示意图。显示面板包括基板10、第一金属层、栅绝缘层30、第二金属层、绝缘层50、测试电路层60和静电测试电极。
与图2中结构不同之处在于，本实施例中显示面板还包括色阻层80，色阻层80形成于绝缘层50远离第二金属层的一侧，测试电路层60形成于色阻层80远离绝缘层50的一侧。
在本实施例中，显示面板为COA(Color Filter on Array)型液晶显示面板，COA型显示面板是指采用COA技术制备而成的液晶显示面板，COA技术是液晶显示技术领域中将彩色滤光片和阵列基板集成在一起的集成技术，即将彩色色阻涂布于已制备完成的阵列基板上以形成彩色滤光层的技术。由于COA(Color Filter on Array)技术可以降低寄生电容、提高开口率与缓解MM mura的技术优势，在市场上已经逐渐超越传统非COA技术，发挥越来越重要的地位。
由于在测试电路层60与第一电极20之间，栅绝缘层30上还形成有绝缘层50和色阻层80，在坡度角区200内，起绝缘作用的膜层厚度进一步增加，且厚度不小于栅绝缘层30的中间区域的厚度，因此在坡度角区域200内的栅绝缘层30更不易被击穿，静电测试的准确性进一步提高。
如图4所示，为本申请实施例提供的显示面板的第三种结构示意图。显示面板包括基板10、第一金属层、栅绝缘层30、第二金属层、绝缘层50、测试电路层60和静电测试电极。
测试电路层60形成在基板10上，第二金属层形成在测试电路层60远离基板10的一侧，栅绝缘层30形成在第二金属层远离测试电路层60的一侧，第一金属层形成在栅绝缘层30远离第二金属层的一侧，绝缘层50形成在第一金属层远离栅绝缘层30的一侧。
第二金属层图案化形成有第二电极40，第一金属层图案化形成有第一电极20，第二电极40与第一电极20在基板10上的投影重合，重合区域对应栅绝缘层30膜厚正常的中间区域。这样当第一电极20和第二电极40上均有电流时，位于坡度角区200内的栅绝缘层30不会有电流聚集，即电流只会作用在位于中间区域内的栅绝缘层30上，增大了栅绝缘层30测试的准确性。
测试电路层60与第二电极40电连接，且连接区域位于第二电极40在基板10上的投影区域内。
由于测试电路层60与第二电极40电连接的连接区域位于第二电极40在基板10上的投影区域内，即连接区域仅位于栅绝缘层30膜厚正常的中间区域，当测试电路层60与第一电极20都有电流时，位于坡度角区200内的栅绝缘层30不会有电流聚集，即电流只会作用在位于中间区域内的栅绝缘层30上，进一步增大了栅绝缘层30测试的准确性。
栅绝缘层30的材料一般为氧化硅(SiOx)、氮化硅(SiNx)、氮氧化硅(SiON)、或者三者的夹层结构等，通过化学气相沉积法形成在第二金属层上。
绝缘层50形成于第一金属层远离栅绝缘层30的一侧。
在一种实施例中，绝缘层50为钝化层，绝缘层50的材质可以为氧化硅(SiOx)、氮化硅(SiNx)、或者二者的夹层结构等，用于对第一电极20进行保护，避免第一电极20受到水汽或者氧气侵蚀，发生腐蚀或者氧化现象。
在一种实施例中，绝缘层50为层间绝缘层，层间绝缘层的材料为有机光阻。
在一种实施例中，绝缘层50为钝化层和层间绝缘层的叠层结构，层间绝缘层形成在第二金属层远离栅绝缘层30的一侧，钝化层形成在所述层间绝缘层远离第二金属层的一侧。层间绝缘层的材料为有机光阻，钝化层的材质可以为氧化硅(SiOx)、氮化硅(SiNx)、或者二者的夹层结构等。
在本实施中，显示面板还包括一导电层70，绝缘层50上形成有过孔（图未示出），且过孔完全贯穿绝缘层50，以便通过过孔的开口可以露出第二电极40，导电层70与第一电极20通过该开口电性连接。
在一种实施例中，过孔是通过刻蚀绝缘层50的方式形成，具体的刻蚀方式可以是干法刻蚀或者湿法刻蚀。当然，还可以通过其他方法形成过孔，本申请实施例对如何形成过孔不进行限定。
在一种实施例中，显示面板为液晶显示面板，导电层70为液晶显示面板的像素电极。
在一种实施例中，显示面板为OLED显示面板，导电层70为OLED显示面板的公共电极，公共电极是由铟锡金属氧化物(ITO)材料制成的透明导电层。
在一种实施例中，显示面板包括低温多晶硅薄膜晶体管，第二金属层图案化形成低温多晶硅薄膜晶体管的栅极。
低温多晶硅薄膜晶体管具有制备温度低，载流子迁移率高，器件尺寸小等突出优点，在显示面板中普遍应用。在本实施例中，低温多晶硅薄膜晶体管为底栅结构，第二金属层图案化形成低温多晶硅薄膜晶体管的栅极，与第二电极40同层设置。
在一种实施例中，显示面板包括氧化物薄膜晶体管，第一金属层图案化形成氧化物薄膜晶体管的栅极。
氧化物薄膜晶体管的生产工艺简单，光刻书面较少，且均匀性很好，广泛应用与高代线、大尺寸显示面板上。在本实施例中，氧化物薄膜晶体管为顶栅结构，第一金属层图案化形成氧化物薄膜晶体管的栅极，与第一电极20同层设置。
在一种实施例中，显示面板包括存储电容，第一金属层和第二金属层为存储电容的第一金属极板和第二金属极板。
本申请通过将第二电极40的信号传导至测试电路层60，在静电测试电极工作时，第一测试电极与第一电极20电连接，第二测试电极与测试电路层60电连接。由于在测试电路层60与第一电极20之间，栅绝缘层30上还形成有绝缘层50，在坡度角区200内，起绝缘作用的膜层厚度增加，且厚度不小于栅绝缘层30的中间区域的厚度。同时，由于第二电极40和第一电极20在基板10上的投影重合，测试电路层60与第二电极40电连接，且连接区域位于第二电极40在基板10上的投影区域内，因此当静电测试电极通电时，位于坡度角区200内的栅绝缘层30不会有电流聚集，即电流只会作用在位于中间区域内的栅绝缘层30上。
因此，静电测试电极的测试电流逐渐增大时，在坡度角区200内的栅绝缘层30不会首先被击穿，首先被击穿的是中间区域内的栅绝缘层30，这样静电测试电极测试到的让第一测试电极和第二测试电极导通时刻的电流值，正确反映了栅绝缘层膜厚正常的中间区域的静电击穿特性。
静电测试电极与显示面板的连接方式有多种，在一种实施例中，第一电极20形成有第一过孔（图未示出），测试电路层60形成有第二过孔（图未示出），第一测试电极通过第一过孔与第一电极20电连接，第二测试电极通过第二过孔与测试电路层60电连接。
在一种实施例中，第一电极20形成有第一连接端子（图未示出），测试电路层60形成有第二连接端子（图未示出），第一测试电极通过第一连接端子与第一电极20电连接，第二测试电极通过第二连接端子与测试电路层60电连接。
在一种实施例中，第一测试电极形成有第三连接端子（图未示出），第二测试电极形成有第四连接端子（图未示出），第一测试电极通过第三连接端子与第一电极20电连接，第二测试电极通过第四连接端子与测试电路层60电连接。
在一种实施例中，第一电极20形成有第一连接端子（图未示出），测试电路层60形成有第二连接端子（图未示出），第一测试电极形成有第三连接端子（图未示出），第二测试电极形成有第四连接端子（图未示出），第一连接端子与第三连接端子电连接，第二连接端子与第四连接端子电连接。
如图5所示，为本申请实施例提供的显示面板的第四种结构示意图。显示面板包括基板10、第一金属层、栅绝缘层30、第二金属层、绝缘层50、测试电路层60和静电测试电极。
与图4中结构不同之处在于，本实施例中显示面板还包括色阻层80，色阻层80形成于绝缘层50远离第二金属层的一侧，测试电路层60形成于色阻层80远离绝缘层50的一侧。
在本实施例中，显示面板为COA(Color Filter on Array)型液晶显示面板，COA型显示面板是指采用COA技术制备而成的液晶显示面板，COA技术是液晶显示技术领域中将彩色滤光片和阵列基板集成在一起的集成技术，即将彩色色阻涂布于已制备完成的阵列基板上以形成彩色滤光层的技术。由于COA(Color Filter on Array)技术可以降低寄生电容、提高开口率与缓解MM mura的技术优势，在市场上已经逐渐超越传统非COA技术，发挥越来越重要的地位。
由于在测试电路层60与第一电极20之间，栅绝缘层30上还形成有绝缘层50和色阻层80，在坡度角区200内，起绝缘作用的膜层厚度进一步增加，且厚度不小于栅绝缘层30的中间区域的厚度，因此在坡度角区域200内的栅绝缘层30更不易被击穿，静电测试的准确性进一步提高。
根据上述实施例可知：
本申请提供一种显示面板，包括基板、第一金属层、第二金属层、栅绝缘层、绝缘层、测试电路层和静电测试电极，第一金属层图案化形成有第一电极；第二金属层图案化形成有第二电极，第二电极和第一电极在基板上的投影重合；栅绝缘层形成于第一金属层和第二金属层之间；测试电路层与第二电极电连接，且连接区域位于第二电极在基板上的投影区域内；静电测试电极包括第一测试电极和第二测试电极，第一测试电极与第一电极电连接，第二测试电极与测试电路层电连接。本申请中由于第一金属层与测试电路层之间还设置有绝缘层，在栅绝缘层的坡度角区膜层较厚，不易发生静电，因此静电测试电极可以测试栅绝缘层中间区域的防静电能力。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其包括：
    基板；
    第一金属层，图案化形成有第一电极；
    第二金属层，图案化形成有第二电极，所述第二电极和所述第一电极在所述基板上的投影重合；
    栅绝缘层，形成于所述第一金属层和所述第二金属层之间；
    绝缘层；
    测试电路层，与所述第二电极电连接，且连接区域位于所述第二电极在所述基板上的投影区域内；
    静电测试电极，包括第一测试电极和第二测试电极，所述第一测试电极与所述第一电极电连接，所述第二测试电极与所述测试电路层电连接。
  2. 如权利要求1所述的显示面板，其中，所述第一金属层形成在所述基板上，所述栅绝缘层形成在所述第一金属层远离所述基板的一侧，所述第二金属层形成在所述栅绝缘层远离所述第一金属层的一侧，所述绝缘层形成在所述第二金属层远离所述栅绝缘层的一侧，所述测试电路层形成在所述绝缘层远离所述第二金属层的一侧。
  3. 如权利要求2所述的显示面板，其中，所述显示面板包括低温多晶硅薄膜晶体管，所述第一金属层还图案化形成所述低温多晶硅薄膜晶体管的栅极。
  4. 如权利要求2所述的显示面板，其中，所述显示面板包括氧化物薄膜晶体管，所述第二金属层还图案化形成所述氧化物薄膜晶体管的栅极。
  5. 如权利要求2所述的显示装置，其中，所述显示面板包括存储电容，所述第一金属层图案化形成所述存储电容的第一金属极板，所述第二金属层图案化形成所述存储电容的第二金属极板。
  6. 如权利要求2所述的显示面板，其中，所述绝缘层为钝化层。
  7. 如权利要求2所述的显示面板，其中，所述绝缘层为钝化层和层间绝缘层的叠层结构。
  8. 如权利要求2所述的显示面板，其中，所述显示面板为液晶显示面板，所述测试电路层为所述液晶显示面板的像素电极。
  9. 如权利要求2所述的显示面板，其中，所述显示面板为OLED显示面板，所述测试电路层为所述OLED显示面板的公共电极。
  10. 如权利要求1所述的显示面板，其中，所述测试电路层形成在所述基板上，所述第二金属层形成在所述测试电路层远离所述基板的一侧，所述栅绝缘层形成在所述第二金属层远离所述测试电路层的一侧，所述第一金属层形成在所述栅绝缘层远离所述第二金属层的一侧，所述绝缘层形成在所述第一金属层远离所述栅绝缘层的一侧。
  11. 如权利要求10所述的显示面板，其中，所述显示面板包括低温多晶硅薄膜晶体管，所述第二金属层还图案化形成所述低温多晶硅薄膜晶体管的栅极。
  12. 如权利要求10所述的显示面板，其中，所述显示面板包括氧化物薄膜晶体管，所述第一金属层还图案化形成所述氧化物薄膜晶体管的栅极。
  13. 如权利要求10所述的显示面板，其中，所述显示面板包括存储电容，所述第一金属层图案化形成所述存储电容的第一金属极板，所述第二金属层图案化形成所述存储电容的第二金属极板。
  14. 如权利要求10所述的显示面板，其中，所述绝缘层为钝化层。
  15. 如权利要求10所述的显示面板，其中，所述绝缘层为层间绝缘层。
  16. 如权利要求10所述的显示面板，其中，所述绝缘层为钝化层和层间绝缘层的叠层结构。
  17. 如权利要求1所述的显示面板，其中，所述第一电极形成有第一过孔，所述测试电路层形成有第二过孔，所述第一测试电极通过所述第一过孔与所述第一电极电连接，所述第二测试电极通过所述第二过孔与所述测试电路层电连接。
  18. 如权利要求1所述的显示面板，其中，所述第一电极形成有第一连接端子，所述测试电路层形成有第二连接端子，所述第一测试电极通过所述第一连接端子与所述第一电极电连接，所述第二测试电极通过所述第二连接端子与所述测试电路层电连接。
  19. 如权利要求1所述的显示面板，其中，所述第一测试电极形成有第三连接端子，所述第二测试电极形成有第四连接端子，所述第一测试电极通过所述第三连接端子与所述第一电极电连接，所述第二测试电极通过所述第四连接端子与所述测试电路层电连接。
  20. 如权利要求1所述的显示面板，其中，所述第一电极形成有第一连接端子，所述测试电路层形成有第二连接端子，所述第一测试电极形成有第三连接端子，所述第二测试电极形成有第四连接端子，所述第一连接端子与所述第三连接端子电连接，所述第二连接端子与所述第四连接端子电连接。
PCT/CN2019/086308 2019-04-11 2019-05-10 显示面板 Ceased WO2020206793A1 (zh)

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