WO2020199242A1 - 存储器和其电子装置及其测试系统、测试方法和应用方法 - Google Patents

存储器和其电子装置及其测试系统、测试方法和应用方法 Download PDF

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WO2020199242A1
WO2020199242A1 PCT/CN2019/082581 CN2019082581W WO2020199242A1 WO 2020199242 A1 WO2020199242 A1 WO 2020199242A1 CN 2019082581 W CN2019082581 W CN 2019082581W WO 2020199242 A1 WO2020199242 A1 WO 2020199242A1
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memory
data exchange
test
parameter information
characteristic parameter
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PCT/CN2019/082581
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English (en)
French (fr)
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王树锋
刘纪文
曲虹亮
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前海晶云(深圳)存储技术有限公司
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Priority to CN201990000295.9U priority Critical patent/CN213691455U/zh
Publication of WO2020199242A1 publication Critical patent/WO2020199242A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Definitions

  • the present invention relates to the technical field of integrated circuit design, packaging and testing of DRAM (Dynamic Random Access Memory), that is, dynamic random access memory, in particular to a dynamic random access memory with built-in characteristic parameter information, an electronic device containing the memory, and memory testing System, memory test method and memory application method.
  • DRAM Dynamic Random Access Memory
  • DRAM chip dynamic random access memory, or DRAM chip
  • various CPUs have different requirements for the matching memory DRAM chip, so higher requirements are put forward for the adaptability of DRAM chips.
  • each DRAM storage unit in a dynamic random access memory has its own optimal setting range of related circuit parameters.
  • the traditional method is to select a circuit parameter range for the CPU platform as the test standard, which conforms to the dynamics of the standard. Random access memory is supplied to customers as standard components.
  • the characteristic parameter information of the DRAM chip is usually not left in the DRAM chip.
  • the CPU needs to obtain the characteristic parameter information of the DRAM in advance and judge whether the characteristic parameter information is matched or not; therefore, the cooperation between the CPU and the DRAM is relatively rigid, and not flexible.
  • the entire chip may not be able to continue to be used.
  • the dynamic random access memory designed in the present invention stores the characteristic parameter information of the memory through a built-in non-volatile memory, and shares the stored characteristic parameter information with the external CPU or other external devices, so that the external CPU or other external devices can interact with
  • the memory coordination is better and more flexible. Even if some memory cells fail, the dynamic random access memory can continue to be used.
  • DDR SDRAM is the abbreviation of Double Data Rate Synchronous Dynamic Random Access Memory in English, and the Chinese meaning is double-rate synchronous dynamic random access memory.
  • LPDDR SDRAM is the abbreviation of English Low Power Double Data Rate Synchronous Dynamic Random Access Memory.
  • the Chinese meaning is low-power double-rate synchronous dynamic random access memory.
  • EEPROM is the abbreviation of Electrically erasable programmable read only memory in English, and the Chinese meaning is electrically erasable programmable read-only memory.
  • NOR FLASH NOR non-volatile flash memory
  • the Chinese meaning of NAND FLASH is non-volatile flash memory.
  • eMCP is the abbreviation of Embedded Multi-Chip Package in English.
  • the Chinese meaning is: Embedded Multi-Chip Package; it is a form of chip packaging; for example: eMCP254b, where 254b represents 254 solder balls as the signal interface.
  • LPDDR is the abbreviation of Low Power Double Data Rate in English.
  • the Chinese meaning is: Low Power Double Rate; short for LPDDR SDRM; is a form of chip packaging; in LPDDR2 168b, LPDDR3 178b, LPDDR4 200b, LPDDR4 366b, the number The meaning of adding b is to use different numbers of solder balls as the signal interface; LPDDR2, LPDDR3, LPDDR4 and LPDDR5 refer to the second, third, fourth, and fifth generation LPDDR SDRAM chip packaging forms respectively.
  • MCP is the abbreviation of English Multi-Chip Package, the Chinese meaning is: multi-chip package; is a form of chip packaging; MCP162b, where 162b means 162 solder balls as the signal interface.
  • DDR is the abbreviation of English Double Data Rate.
  • the Chinese meaning is: double rate; short for DDR SDRAM; DDR is also a form of chip packaging; in DDR3 78b, DDR4 78b, DDR5 170b, DDR3, DDR4 and DDR5 are respectively Refers to the third, fourth, and fifth generations of DDR SDRAM chip packaging.
  • the number followed by b means that different numbers of solder balls are used as signal interfaces.
  • CPU is the abbreviation of English Central Processing Unit, and the Chinese meaning is: central processing unit.
  • CAS Latency is the abbreviation of English column address strobe Latency, Chinese meaning: column address strobe time delay.
  • CAS is the abbreviation of column address strobe in English, which means that the column address is valid or the column address is strobe.
  • RCD in tRCD is the abbreviation of RAS to CAS Delay in English, and is also described as: tRCD, RAS to CAS Delay, Active to CMD; the Chinese meaning of tRCD is the row addressing to column addressing delay time; the smaller the value, the better the performance it is good.
  • tRCD RAS to CAS Delay
  • Active to CMD the Chinese meaning of tRCD is the row addressing to column addressing delay time; the smaller the value, the better the performance it is good.
  • RAS in tRAS is the abbreviation of English Min RAS Active Time, and is also described as: tRAS, Active to Precharge Delay, Row Active Time, Precharge Wait State, Row Active Delay, Row Precharge Delay, RAS Active Time; the Chinese meaning of tRAS: The shortest period from which the memory line is valid to precharge. Adjusting this parameter needs to be determined according to the specific situation. This parameter should be determined according to the actual situation. It does not mean that the larger or the smaller the better. If the tRAS cycle is too long, the system will degrade performance due to unnecessary waiting. Reducing the tRAS cycle will cause the activated row address to enter the inactive state earlier.
  • tRAS If the period of tRAS is too short, the burst transmission of data may not be completed due to lack of sufficient time, which may cause data loss or damage.
  • This value is generally set to CAS latency+tRCD+2 clock cycles. If the value of CAS latency is 2 and the value of tRCD is 3, the optimal tRAS value should be set to 7 clock cycles. To improve system performance, the value of tRAS should be reduced as much as possible, but if a memory error or crash occurs, the value of tRAS should be increased.
  • tRP Row Precharge Time in English, and is also described as: tRP, RAS Precharge, Precharge to active; the Chinese meaning of tRP: memory row address controller precharge time".
  • tRP is used to set the charging time required by the RAS before another row can be activated. Too long tRP parameter setting will cause all rows to activate too long. Setting it to 2 can reduce the precharge time, thereby making it more Activate the next line quickly.
  • AC in tAC is the abbreviation of English Access time from CLK, and the Chinese meaning of tAC is the maximum number of input clocks at the time of the maximum CAS delay.
  • CL in tCL is the abbreviation of English CAS Latency Control, and is also described as tCL, CL, CAS Latency Time, CAS Time Delay; tCL Chinese meaning: the latency of the front address controller for memory read and write operations; it refers to memory access
  • the delay time required for data is simply the response speed of the memory after receiving instructions from the CPU; the smaller the number, the shorter the response time.
  • the RC in tRC should be the abbreviation of Row Cycle Time.
  • the Chinese meaning means "SDRAM row cycle time", which is the minimum number of clock cycles required for the entire process including row cell precharging to activation.
  • CPC is the abbreviation of Command Per Clock in English.
  • the Chinese means the number of executed instructions per clock cycle. It is also called the command rate. It also translates as: first command delay. It is generally described as DRAM Command Rate, CMD Rate, etc.
  • DRAM Command Rate CMD Rate
  • ROM is the abbreviation of read only memory in English, and the Chinese meaning is: read only memory.
  • RAM is the abbreviation of ramdom access memory in English, and the Chinese meaning is: random access memory.
  • IROM is the abbreviation of internal read only memory in English. The Chinese meaning is: internal ROM, which refers to the ROM integrated into the system on chip.
  • IRAM is the abbreviation of internal ramdom access memory in English.
  • the Chinese meaning is: internal RAM, which refers to the RAM integrated into the system on chip.
  • SoC is the abbreviation of system on chip in English.
  • the Chinese meaning is: system-on-chip, also called system-on-chip, which means that it is a product, an integrated circuit with a dedicated target, which contains a complete system and all the contents of embedded software.
  • BL0 is the abbreviation of BootLoader0 in English.
  • the Chinese meaning refers to the startup code solidified in IROM; the startup code is used to initialize the system clock, set the watchdog, initialize the heap and stack, and load BL1.
  • BL1 is the abbreviation of BootLoader1 in English.
  • the Chinese meaning refers to the maximum 16K code in the header of the uboot binary file that is automatically copied from the external expansion memory or ROM in IRAM. This code is used to initialize RAM, close the Cache, set the stack, and load BL2.
  • BL2 is the abbreviation of BootLoader2 in English.
  • the Chinese meaning refers to the complete code of uboot executed in memory after code redirection. This code is used to initialize other peripherals and load the OS (operation system) kernel.
  • BootLoader is a combination of Booter and Loader: the former means to initialize the embedded system hardware to make it run, at least partly running, similar to the BIOS (Basic Input Output System) in the PC; the latter means to embed The operating system image is loaded into memory and jumps to run.
  • BIOS Basic Input Output System
  • BIOS In embedded systems, there is usually no firmware program like BIOS, so the loading and starting tasks of the entire system are completely completed by BootLoader.
  • BIOS firmware program
  • the system In an embedded system based on the ARM7TDMI kernel, the system usually starts execution at address 0x00000000 when it is powered on or reset, and the BootLoader program of the system is usually arranged at this address.
  • BootLoader is a small program that runs before the operating system kernel runs. Through this small program, hardware devices can be initialized and a map of memory space can be established to bring the system's software and hardware environment to a proper state, so as to prepare the correct environment for the final call of the operating system kernel.
  • the present invention designs a memory with a built-in non-volatile memory, which is a dynamic random access memory; in the non-volatile memory, the characteristic parameter information of the memory is stored, These stored characteristic parameter information can be shared with external devices, so that the external devices can cooperate with the memory, and the memory can continue to be used even if some storage units fail.
  • the technical solution for the above technical problems to be solved by the present invention is a memory, which is a dynamic random access memory, including a DRAM memory, and a DRAM data exchange interface for data exchange between the DRAM memory and the outside; it is characterized by:
  • non-volatile memory which is used to store the characteristic parameter information of DRAM memory
  • It also includes a non-volatile memory data exchange interface for data exchange between the non-volatile memory and the outside.
  • the characteristic parameter information stored in the non-volatile memory includes CAS Latency parameters, tRCD parameters, tRP parameters, and tRAS parameters.
  • the characteristic parameter information stored in the non-volatile memory also includes Fast RAS To CAS Delay parameters, tAC parameters, and tCL parameters.
  • the characteristic parameter information stored in the non-volatile memory further includes address index information of the defective storage unit, and the address index information is used to locate the address partition where the defective storage unit is located.
  • the DRAM memory includes DDR SDRAM memory used in computers and servers.
  • the DDR SDRAM memory includes the third generation DDR SDRAM memory, namely DDR3 SDRAM memory, the fourth generation DDR SDRAM memory, namely DDR4 SDRAM, and the fifth generation DDR SDRAM memory, namely DDR5 SDRAM.
  • the DRAM memory includes LPDDR SDRAM memory for mobile terminals.
  • the LPDDR SDRAM memory includes second-generation LPDDR SDRAM memory, namely LPDDR2 SDRAM memory, third-generation LPDDR SDRAM memory, namely LPDDR3 SDRAM, fourth-generation LPDDR SDRAM memory, namely LPDDR4 SDRAM, and fifth-generation LPDDR SDRAM memory, namely LPDDR5 SDRAM.
  • second-generation LPDDR SDRAM memory namely LPDDR2 SDRAM memory
  • third-generation LPDDR SDRAM memory namely LPDDR3 SDRAM
  • fourth-generation LPDDR SDRAM memory namely LPDDR4 SDRAM
  • fifth-generation LPDDR SDRAM memory namely LPDDR5 SDRAM.
  • the non-volatile memory includes any one or more of EEPROM memory, NOR FLASH memory and NAND FLASH memory.
  • the non-volatile memory data exchange interface includes an I 2 C interface.
  • the package specifications of the memory include LPDDR2 168b, LPDDR3 178b, LPDDR4 200b, LPDDR4 366b, eMCP 221b, eMCP 254b, MCP 162b, DDR3 78b, DDR4 78b and DDR5 170b; the idle pins in the above packages are used for volatility Memory data exchange interface.
  • the technical solution to the above technical problem to be solved by the present invention may also be a memory test system, including a test host for test control and a test interface board for providing memory test interfaces; the interfaces on the test interface board include Test board DRAM data exchange interface, test board non-volatile memory data exchange interface; the test board DRAM data exchange interface on the test interface board is used for docking with the DRAM data exchange interface of the memory to be tested; the test interface board The test board non-volatile memory data exchange interface is used for docking with the non-volatile memory data exchange interface of the memory to be tested; the test host controls the connection of the DRAM data exchange interface of the test board and the DRAM data exchange interface of the memory to be tested, and Obtain the characteristic parameter information of the memory to be tested; the test host writes the characteristic parameter information into the non-volatile memory of the memory through the non-volatile memory data exchange interface of the test board, so that the memory has its own characteristic parameter information.
  • the interface on the test interface board also includes a test control data exchange interface; the test control data exchange interface is simultaneously connected with the test board DRAM data exchange interface and the test board non-volatile memory data exchange interface; the test host controls the data exchange interface through the test , Control the connection between the DRAM data exchange interface of the test board and the DRAM data exchange interface of the memory to be tested, and obtain the characteristic parameter information of the memory to be tested; the test host controls the data exchange interface through the test, so that the characteristic parameter information is non-volatile through the test board
  • the memory data exchange interface writes into the non-volatile memory of the memory to enable the characteristic parameter information inside the memory.
  • the technical solution to the above technical problem to be solved by the present invention can also be a memory testing method, including step 11: putting the memory to be tested into the test interface board of the memory testing system; step 12: the test host sends to the memory to be tested Test instruction, start the test; Step 13: The test host scans the memory to be tested to obtain the characteristic parameter information of the memory; Step 14: The test host writes the acquired characteristic parameter information of the memory into the memory through the non-volatile memory data exchange interface Non-volatile memory.
  • the memory testing method further includes step 141: the test host classifies the memory according to the acquired characteristic parameter information of the memory, and writes the classification data and characteristic parameter information of the memory into the memory through the non-volatile memory data exchange interface.
  • the test host classifies the memory according to the acquired characteristic parameter information of the memory, and writes the classification data and characteristic parameter information of the memory into the memory through the non-volatile memory data exchange interface.
  • Non-volatile memory Non-volatile memory.
  • a memory test method further includes step A5: the test host sets the characteristic parameter information that needs to be obtained according to the external command, and the test host writes the specified characteristic parameter information into the non-volatile memory according to the requirement of the external command.
  • the technical solution to the above-mentioned technical problem to be solved by the present invention may also be an electronic device equipped with the above-mentioned memory.
  • the electronic device includes a CPU in a main control system, and the CPU includes a CPU-DRAM data exchange interface and a CPU non- Volatile memory data exchange interface; CPU-DRAM data exchange interface is used to interface with the DRAM data exchange interface of the memory to realize data exchange between CPU and memory; CPU non-volatile memory data exchange interface is used for non-volatile memory Volatile memory data exchange interface docking; CPU obtains the characteristic parameter information of each unit of the memory connected to the CPU through the CPU non-volatile memory data exchange interface, and the CPU controls the drive of the memory according to the memory characteristic parameter information.
  • the technical solution to the above technical problem to be solved by the present invention may also be a memory testing method based on the electronic device, including: Step 21: CPU sends a test instruction to the memory to be tested to start the test; Step 22: CPU controls scanning The memory to be tested obtains the new characteristic parameter information; Step 23: The CPU writes the acquired new characteristic parameter information into the non-volatile memory in the memory through the non-volatile memory data exchange interface, overwriting the original stored in the non-volatile memory Characteristic parameter information.
  • the above-mentioned memory test method further includes step 231: The CPU classifies the memory according to the acquired new characteristic parameter information, and writes the classification data of the memory and the characteristic parameter information into the non-volatile memory through the non-volatile memory data exchange interface. Lost memory.
  • the foregoing memory test method further includes step 24: the CPU reconfigures the drive parameters of the memory according to the acquired new characteristic parameter information.
  • the technical solution to the above technical problem to be solved by the present invention may also be a memory application method including step 31: setting the memory to be a dynamic random access memory, including DRAM memory and non-volatile memory.
  • the memory is used to store the characteristic parameter information of the DRAM memory;
  • Step 34 The application terminal CPU performs drive control of the memory according to all the characteristic parameter information of the acquired memory.
  • the beneficial effect of the present invention is: through the characteristic parameter information stored in the non-volatile memory, according to the requirements of different devices for DRAM, the memory that meets their needs can be customized; for some storage units The faulty memory can also be used in this way.
  • Figure 1 is a schematic diagram of the memory architecture
  • Figure 2 is a schematic diagram of the architecture of the memory test system
  • Figure 3 is a schematic diagram of the connection architecture of the memory and its test system
  • Figure 4 is a schematic diagram of the test flow of the memory
  • FIG. 5 is a schematic diagram of a flow of memory application in an electronic device
  • FIG. 6 is a schematic diagram of a flow of online testing of a memory in an electronic device
  • Figure 7 is one of the application scenarios of the memory, which is a schematic diagram of the memory architecture of the mobile phone terminal; the CPU in the figure is the CPU of the mobile phone terminal, and it can be seen that there are IRAM, IROM, RAM and ROM set therein; the RAM part of which is designed by the present invention Memory
  • FIG. 8 is a schematic flow chart of a mobile phone startup process in the prior art
  • Figure 9 is a flow diagram of the mobile phone startup process after applying the memory designed in the present invention.
  • Figure 9 adds a step relative to Figure 8, that is, before running the kernel to start the system, there is a step in which it will be loaded and saved in the non- The memory characteristic parameter data in the volatile storage medium and the RAM drive are configured accordingly.
  • the memory is a dynamic random access memory, including a DRAM memory, and a DRAM data exchange interface for data exchange between the DRAM memory and the outside; it also includes a non-volatile memory, It is used to store the characteristic parameter information of the DRAM memory; it also includes a non-volatile memory data exchange interface for data exchange between the non-volatile memory and the outside.
  • the characteristic parameter information stored in the non-volatile memory includes CAS Latency parameters, tRCD parameters, tRP parameters, and tRAS parameters.
  • the characteristic parameter information stored in the non-volatile memory also includes Fast RAS To CAS Delay parameters, tAC parameters, and tCL parameters.
  • the characteristic parameter information stored in the non-volatile memory further includes address index information of the defective storage unit, and the address index information is used to locate the address partition where the defective storage unit is located.
  • the purpose of setting the address index information is to facilitate the feature parameter information in the non-volatile memory to be released to the external device to accurately specify the address partition of the defective storage unit.
  • the DRAM memory has A memory cells, that is, there are A memory addresses.
  • the B value of the address partition size can be dynamically adjusted according to the EEPROM storage capacity.
  • the address partition can be as small as possible, which can be more detailed to correspond to each small address partition; when the EEPROM storage capacity is small, the address partition can be as large as possible, and the record can be recorded as much as possible within a reasonable amount. More characteristic parameter information. A balance is obtained between the space utilization of DRAM memory and the storage capacity of EEPROM.
  • the DRAM memory is divided into 8 banks by two chip selection signals (CS0, CS1), and each bank is composed of several rows and columns of capacitor units; the address index information can be performed in units of banks Index, address index information is the bank corresponding to each parameter.
  • the DRAM memory includes DDR SDRAM memory used in computers and servers.
  • the DDR SDRAM memory includes the third generation DDR SDRAM memory, namely DDR3 SDRAM memory, the fourth generation DDR SDRAM memory, namely DDR4 SDRAM, and the fifth generation DDR SDRAM memory, namely DDR5 SDRAM.
  • the DRAM memory includes LPDDR SDRAM memory for mobile terminals.
  • the LPDDR SDRAM memory includes second-generation LPDDR SDRAM memory, namely LPDDR2SDRAM memory, third-generation LPDDR SDRAM memory, namely LPDDR3 SDRAM, fourth-generation LPDDR SDRAM memory, namely LPDDR4 SDRAM, and fifth-generation LPDDR SDRAM memory, namely LPDDR5SDRAM.
  • the non-volatile memory includes any one or more of EEPROM memory, NOR FLASH memory, and NAND FLASH memory.
  • the non-volatile memory data exchange interface includes an I 2 C interface.
  • the packaging specifications of the memory include LPDDR2 168b, LPDDR3 178b, LPDDR4 200b, LPDDR4 366b, eMCP 221b, eMCP 254b, MCP 162b, DDR3 78b, DDR4 78b, and DDR5 170b;
  • the idle pins in the package are used as a volatile memory data exchange interface.
  • a memory test system as shown in FIGS. 2 and 3, it includes a test host for test control and a test interface board for providing memory test interfaces;
  • the interface on the test interface board includes a test board DRAM Data exchange interface, test board non-volatile memory data exchange interface;
  • the test board DRAM data exchange interface on the test interface board is used to interface with the DRAM data exchange interface of the memory to be tested;
  • the test board on the test interface board The non-volatile memory data exchange interface is used to interface with the non-volatile memory data exchange interface of the memory to be tested;
  • the test host controls the connection between the DRAM data exchange interface of the test board and the DRAM data exchange interface of the memory to be tested, and obtains the test The characteristic parameter information of the memory; when testing the host, the characteristic parameter information is written into the non-volatile memory of the memory through the non-volatile memory data exchange interface of the test board, so that the memory has its own characteristic parameter information.
  • the interface on the test interface board also includes a test control data exchange interface; the test control data exchange interface is simultaneously with the test board DRAM data exchange interface and the test board Non-volatile memory data exchange interface connection; the test host passes the test control data exchange interface, controls the connection between the test board DRAM data exchange interface and the DRAM data exchange interface of the memory to be tested, and obtains the characteristic parameter information of the memory to be tested; the test host passes The test control data exchange interface allows the characteristic parameter information to be written into the non-volatile memory of the memory through the non-volatile memory data exchange interface of the test board, so that the characteristic parameter information inside the memory is carried.
  • the embodiment of a memory testing method shown in FIG. 4 includes: Step 11: Put the memory to be tested into the test interface board of the memory testing system; Step 12: The test host sends a test instruction to the memory to be tested to start the test Step 13: The test host scans the memory to be tested to obtain the characteristic parameter information of the memory; Step 14: The test host writes the acquired characteristic parameter information of the memory to the non-volatile memory in the memory through the non-volatile memory data exchange interface Step 141: The test host classifies the memory according to the acquired characteristic parameter information of the memory, and writes the classification data and characteristic parameter information of the memory to the non-volatile memory in the memory through the non-volatile memory data exchange interface.
  • Step A5 The test host sets the characteristic parameter information that needs to be obtained according to the external command, and writes the specified characteristic parameter information into the non-volatile memory according to the requirement of the external command.
  • the characteristic parameters can include the voltage range applicable to the memory and set Memory write and read information.
  • Step A5 may be before step 12 or step 13, or after step 12 or step 13, as long as the test host and the memory under test have established an electrical connection, it can start.
  • the embodiment of the electronic device equipped with the above-mentioned memory includes a CPU in the main control system, and the CPU includes a CPU-DRAM data exchange interface and a CPU non-volatile memory data exchange interface;
  • CPU -DRAM data exchange interface is used to interface with the DRAM data exchange interface of the memory to realize data exchange between the CPU and the memory;
  • the CPU non-volatile memory data exchange interface is used to interface with the non-volatile memory data exchange interface of the memory;
  • the CPU obtains the characteristic parameter information of each unit of the memory connected to the CPU through the CPU non-volatile memory data exchange interface, and the CPU controls the drive of the memory according to the characteristic parameter information of the memory.
  • a memory testing method based on the above electronic device includes: Step 21: CPU sends a test instruction to the memory to be tested to start the test; Step 22: CPU controls to scan the memory to be tested to obtain new characteristic parameter information Step 23: The CPU writes the acquired new feature parameter information into the nonvolatile memory in the memory through the nonvolatile memory data exchange interface, and overwrites the feature parameter information originally stored in the nonvolatile memory.
  • a memory testing method based on the above electronic device further includes step 231: the CPU classifies the memory according to the acquired new feature parameter information, and passes the memory classification data and the feature parameter information together
  • the non-volatile memory data exchange interface writes into the non-volatile memory in the memory;
  • Step 24 The CPU reconfigures the drive parameters of the memory according to the acquired new characteristic parameter information.
  • an embodiment of a memory application method includes step 31: setting a memory, which is a dynamic random access memory, including a DRAM memory and a non-volatile memory, and the non-volatile memory is used To store the characteristic parameter information of the DRAM memory; Step 32: Set a terminal that uses the memory, and the terminal includes an application terminal CPU.
  • an embodiment of a memory application method further includes step 33: the application terminal CPU sends an instruction to the memory to obtain characteristic parameter information stored in the nonvolatile memory of the memory; step 34: the application terminal CPU obtains All the characteristic parameter information of the memory, the drive control of the memory. The CPU drives the data exchange between the memory and the CPU.
  • the startup code BL0 is stored in the IROM of the CPU of the terminal. After the CPU is powered on, it will go to the IROM to run BL0. To initialize the system clock, set the watchdog, initialize the heap and stack, and finally load the BL1 stored in the ROM to IRAM for execution. At this time, you can initialize the RAM, close the Cache, set the stack, and then load the stored in the ROM BL2 and BL2 are responsible for initializing other peripherals, and finally loading the OS kernel code stored in ROM into RAM, and then running the kernel program to start the system.
  • the reason for distinguishing between BL1 and BL2, instead of combining the two to execute, is that IRAM is very small, only tens of K in size, and cannot fit the complete uboot code, so it is divided into two parts. Move the larger part to RAM to run.
  • BL1 initializes the memory (RAM) and tells BL2 the basic information of the memory (several chip selections, total memory size), BL2 assembles this information in a device called a device tree (device tree) result body, and finally pass the device tree to the kernel, and start the kernel.
  • the device tree information is parsed to perform various specific settings.
  • the memory information including the available area and area size information is obtained from the device tree, and these available areas are told to the system for use by the system.
  • the step of the CPU reading the characteristic parameter information in the non-volatile memory and configuring the corresponding memory driver can be completed at any link after the step of running BL0 and before the running kernel is started. That is, the step of reading the characteristic parameter information in the non-volatile memory and configuring the corresponding memory driver can be completed before step BL1 or in step BL1, or can be completed in or after step BL2. As long as the system boots up, the above steps of reading the characteristic parameter information and configuring the corresponding memory driver are completed before the kernel program starts.
  • a memory is used in the application embodiment of the mobile phone terminal.
  • the RAM is initialized, which is the dynamic random access memory designed by the present invention, that is, it will be stored in
  • the characteristic parameter information in the non-volatile memory is transferred to the CPU, so that the CPU builds a new memory driver based on the characteristic parameter information.
  • the chip testing mode (Patten) is mainly to set the highest and lowest voltage values, and then perform several tests on each access address.
  • Write and read scans are sequential scans and random scans; chip levels are classified according to the set voltage range and read and write times, and are used as standard storage IC components for application terminals, such as mobile phones; the higher the chip level, the voltage is applicable
  • the range is small and the number of read and write scans is large. The better the compatibility with application platforms, that is, various CPUs, but the test yield is low and the cost is high.
  • DRAM memory chip When designing and developing the application terminal, select the corresponding level of dynamic random access memory memory chip, namely DRAM memory chip, and adjust the system software and hardware to adapt to the DRAM memory chip.
  • the price of DRAM memory chips can be balanced by extending the development time.
  • the intensification of market competition the increase of platforms, the shortening of the cycle of launching new models on each platform, and the personalized customer needs, the development cycle of new models of application terminals has been greatly compressed.
  • the existing standardized supply methods of DRAM memory chips are increasingly incompatible with the compatibility and customization requirements of the current market, and new DRAM memory chip solutions are urgently needed.
  • the characteristic parameter information of the DRAM memory is recorded in the non-volatile memory integrated with the DRAM memory in the same chip for the CPU to call and adjust the drive parameter value of the CPU to the optimal parameter, so that the CPU and the DRAM memory
  • the matching range between the two is greatly expanded and becomes more flexible; the usability of DRAM memory can be increased from 70% to more than 90%.
  • this approach greatly improves the overall efficiency of such electronic devices, and can achieve a better balance between cost efficiency.

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Abstract

一种存储器，是动态随机存取存储器，包括DRAM存储器和非易失性存储器；其中的DRAM存储器通过DRAM数据交换接口和外部进行数据交换；非易失性存储器通过非易失性存储器数据交换接口和外部进行数据交换；非易失性存储器用于存储DRAM存储器的特征参数信息，可根据不同设备对DRAM存储器的要求，针对性的定制符合各自需求的存储器；对一些部分存储单元故障的存储器，也能通过该方法继续使用。

Description

存储器和其电子装置及其测试系统、测试方法和应用方法 技术领域
本发明涉及DRAM(Dynamic Random Access Memory)即动态随机存取存储器的集成电路设计、封装及测试技术领域，具体涉及内置有特征参数信息的动态随机存取存储器，包含该存储器的电子装置，存储器测试系统，存储器测试方法和存储器应用方法。
背景技术
现有技术中，动态随机存取存储器即DRAM芯片应用范围十分广泛，各种不同的CPU对与之配合的内存DRAM芯片的要求也不相同，因此对DRAM芯片的适应性提出了更高的要求。
现有技术中，每一个动态随机存取存储器中的DRAM存储单元有自己最优的相关电路参数设置范围，传统的做法是针对CPU平台来选择一个电路参数范围做为测试标准，符合标准的动态随机存取存储器做为标准元器件供应客户。
现有技术中，DRAM芯片中通常不会留有该芯片的特征参数信息，CPU需要事先获取DRAM的特征参数信息，并判断这些特征参数信息是否匹配使用；因此CPU和DRAM的配合相对僵化，并不灵活。且DRAM芯片中若出现了部分存储单元的损坏，可能导致整个芯片不能继续使用。
本发明设计的动态随机存取存储器通过内置一个非易失性存储器，存储存储器的特征参数信息，并将存储的特征参数信息与外部CPU或其他外部设备共享，使得外部CPU或其他外部设备能和存储器协同的更好，更灵活，即使是存在部分存储单元失效，也可以继续使用动态随机存取存储器。
以下为名字解释。
DDR SDRAM是英文Double Data Rate Synchronous Dynamic Random Access Memory的缩写，中文含义是双倍速率同步动态随机存取存储器。
LPDDR SDRAM是英文Low Power Double Data Rate Synchronous Dynamic Random Access Memory的缩写，中文含义是低功耗双倍速率同步动态随机存取存储器。
EEPROM是英文Electrically erasable programmable read only memory的缩写，中文含义是电可擦可编程只读存储器。
NOR FLASH的中文含义是或非型非易失闪存。
NAND FLASH的中文含义是与非型非易失闪存。
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eMCP是英文Embedded Multi-Chip Package的缩写，中文含义是：嵌入式多芯片封装；是一种芯片封装形式；如：eMCP254b其中254b代表是以254颗锡球做为信号接口。
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LPDDR是英文Low Power Double Data Rate的缩写，中文含义是：低功耗双倍速率；是LPDDR SDRM的简称；是一种芯片封装形式；在LPDDR2 168b、LPDDR3 178b、LPDDR4 200b、LPDDR4 366b中，数字加b的含义是，以不同数量锡球做为信号接口；其中LPDDR2，LPDDR3、LPDDR4和LPDDR5分别是指第二、三、四、五代的LPDDR SDRAM芯片封装形式。
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MCP是英文Multi-Chip Package的缩写，中文含义是：多芯片封装；是一种芯片封装形式；MCP162b其中162b的含义是，以 162颗锡球做为信号接口。
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DDR是英文Double Data Rate的缩写，中文含义是：双倍速率；是DDR SDRAM的简称；DDR也是一种芯片封装形式；在DDR3 78b、DDR4 78b、 DDR5 170b中，其中DDR3，DDR4和 DDR5分别是指第三、四、五代的DDR SDRAM芯片封装形式，其后数字加b的含义是，以不同数量锡球做为信号接口。
CPU是英文Central Processing Unit的缩写，中文含义是：中央处理器。
CAS Latency是英文column address strobe Latency的缩写，中文含义：列地址选通脉冲时间延迟。其中CAS是英文column address strobe的缩写，表示的是列地址有效或列地址选通。
tRCD中的RCD是英文RAS to CAS Delay的缩写，也被描述为：tRCD、RAS to CAS Delay、Active to CMD；tRCD的中文含义是行寻址到列寻址延迟时间；数值越小，性能越好。对内存进行读、写或刷新操作时，需要在这两种脉冲信号之间插入延迟时钟周期。在JEDEC规范中，它是排在第二的参数，降低此延时，可以提高性能。但如果该值设置太低、太高，同样会导致系统不稳定，如果超频性能不佳，则可将此值设为内存的默认值或尝试提高tRCD值。
tRAS中的RAS是英文Min RAS Active Time的缩写，也被描述为：tRAS、Active to Precharge Delay、Row Active Time、Precharge Wait State、Row Active Delay、Row Precharge Delay、RAS Active Time；tRAS的中文含义：内存行有效至预充电的最短周期。调整这个参数需要结合具体情况而定，这个参数要根据实际情况而定，并不是说越大或越小就越好。如果tRAS的周期太长，系统会因为无谓的等待而降低性能。降低tRAS周期，则会导致已被激活的行地址会更早的进入非激活状态。如果tRAS的周期太短，则可能因缺乏足够的时间而无法完成数据的突发传输，这样会引发丢失数据或损坏数据。该值一般设定为CAS latency+tRCD+2个时钟周期。如果CAS latency的值为2，tRCD的值为3，则最佳的tRAS值应该设置为7个时钟周期。为提高系统性能，应尽可能降低tRAS的值，但如果发生内存错误或死机，则应该增大tRAS的值。
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tRP中的RP是英文Row Precharge Time的缩写，也被描述为：tRP、RAS Precharge、 Precharge to active；tRP的中文含义：内存行地址控制器预充电时间”。预充电参数越小则内存读写速度就越快。tRP用来设定在另一行能被激活之前，RAS需要的充电时间。tRP参数设置太长会导致所有的行激活延迟过长，设为2可以减少预充电时间，从而更快地激活下一行。然而，想要把tRP设为2对大多数内存都是个很高的要求，可能会造成行激活之前的数据丢失，内存控制器不能顺利地完成读写操作。对于桌面计算机来说，推荐预充电参数的值设定为2个时钟周期，这是最佳的设置。如果比此值低，则会因为每次激活相邻紧接着的bank将需要1个时钟周期，这将影响DDR内存的读写性能，从而降低性能。只有在tRP值为2而出现系统不稳定的情况下，将此值设定为3个时钟周期。一般说来，tRP值建议 2-5之间的值。值为2将获取最高的性能，该值为4将在超频时获取最佳的稳定性，同样的而该值为5则太保守。大部分内存都无法使用2的值，需要超频才可以达到该参数。
Fast RAS To CAS Delay的中文含义：行地址触发信号到列地址触发信号之间的延迟时间；通常是RAS下降到CAS下降之间的时间。
tAC中的AC是英文Access time from CLK的缩写，tAC的中文含义是最大CAS延迟时的最大数输入时钟。
tCL中的CL是英文CAS Latency Control的缩写，也被描述为tCL、CL、CAS Latency Time、CAS Time Delay；tCL中文含义：内存读写操作前列地址控制器的潜伏时间；指的是内存存取数据所需的延迟时间，简单的说，就是内存接到CPU的指令后的反应速度；数字越小，代表反应所需的时间越短。
tRC中的RC是应为Row Cycle Time的缩写，中文含义表示“SDRAM行周期时间”，它是包括行单元预充电到激活在内的整个过程所需要的最小的时钟周期数。其计算公式是：row cycle time(tRC)＝minimum row active time(tRAS)+row precharge time(tRP)。因此，设置该参数之前，需要知道tRAS值和tRP值是多少。如果tRC的时间过长，会因在完成整个时钟周期后激活新的地址而等待无谓的延时，而降低性能。然后一旦该值设置过小，在被激活的行单元被充分充电之前，新的周期就可以被初始化。在这种情况下，仍会导致数据丢失和损坏。因此，最好根据tRC＝tRAS+tRP进行设置，如果你的内存模块的tRAS值是7个时钟周期，而tRP的值为4个时钟周期，则理想的tRC的值应当设置为11个时钟周期。
CPC是英文Command Per Clock的缩写，中文含义每时钟周期的执行指令数，也叫指令比率，也有翻译为：首命令延迟。一般还被描述为DRAM Command Rate、CMD Rate等。由于目前的DDR内存的寻址，先要进行P-Bank的选择(通过CS片选信号进行)，然后才是L-Bank/行激活与列地址的选择。这个参数的含义就是指在P-Bank选择完之后多少时间可以发出具体 的寻址的L-Bank/行激活命令，单位是时钟周期。显然，CPC越短越好。
ROM是英文read only memory的缩写，中文含义是：只读存储器。
RAM是英文ramdom access memory的缩写，中文含义是：随机访问存储器。
IROM是英文internal read only memory的缩写，中文含义是：内部ROM，指的是集成到片上系统内部的ROM。
IRAM是英文internal ramdom access memory的缩写，中文含义是：内部RAM，指的是集成到片上系统内部的RAM。
SoC是英文system on chip缩写，中文含义是：系统级芯片，也有称片上系统，意指它是一个产品，是一个有专用目标的集成电路，其中包含完整系统并有嵌入软件的全部内容。
BL0是英文BootLoader0的缩写，中文含义是指IROM中固化的启动代码；启动代码用于初始化系统时钟，设置看门狗，初始化堆和栈，加载BL1。
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BL1是英文BootLoader1的缩写，中文含义是指在IRAM自动从外扩存储器即ROM中拷贝的uboot二进制文件的头最大16K代码，该段代码用作初始化RAM，关闭Cache，设置栈，加载BL2。
BL2是英文BootLoader2的缩写，中文含义是指在代码重定向后在内存中执行的uboot的完整代码，该段代码用作初始化其它外设，加载OS(operation system操作系统)内核。
BootLoader是Booter和Loader的合写：前者意味着要初始化嵌入式系统硬件使之运行起来，至少是部分运行起来，与PC机中的BIOS(Basic Input Output System)作用相似；后者意味着将嵌入式操作系统映像加载到内存中，并跳转过去运行。
而在嵌入式系统中，通常并没有像BIOS那样的固件程序，因此整个系统的加载启动任务就完全由BootLoader来完成。比如在一个基于ARM7TDMI内核的嵌入式系统中，系统在上电或复位时通常都从地址0x00000000处开始执行，而在这个地址处安排的通常就是系统的BootLoader程序。
简单地说，BootLoader就是在操作系统内核运行之前运行的一段小程序。通过这段小程序，可以初始化硬件设备、建立内存空间的映射图，从而将系统的软硬件环境带到一个合适的状态，以便为最终调用操作系统内核准备好正确的环境。
发明内容
为了避免上述现有技术的不足，本发明设计了一种内置有非易失性存储器的存储器，该存储器是动态随机存取存储器；在非易失性存储器中，存有存储器的特征参数信息，这些存储的特征参数信息可与外部设备共享，使得外部设备能和存储器协同，即使是存在部分存储单元失效，也可以继续使用存储器。
本发明要解决的上述技术问题的技术方案是，一种存储器，是动态随机存取存储器，包括DRAM存储器，以及用于DRAM存储器和外部进行数据交换的DRAM数据交换接口；其特征在于：
还包括非易失性存储器，用于存储DRAM存储器的特征参数信息；
还包括非易失性存储器数据交换接口，用于非易失性存储器和外部进行数据交换。
所述非易失性存储器中存储的特征参数信息包括CAS Latency参数、tRCD参数、tRP参数和tRAS参数。
所述非易失性存储器中存储的特征参数信息还包括Fast RAS To CAS Delay参数、tAC参数和tCL参数。
所述非易失性存储器中存储的特征参数信息还包括缺陷存储单元的地址索引信息，所述地址索引信息用于定位缺陷存储单元所在的地址分区。
所述DRAM存储器，包括用于电脑和服务器的DDR SDRAM存储器。
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所述DDR SDRAM存储器，包括第三代DDR SDRAM存储器即DDR3 SDRAM存储器、第四代DDR SDRAM存储器即DDR4 SDRAM、第五代DDR SDRAM存储器即DDR5 SDRAM。
所述DRAM存储器，包括用于用于移动终端的LPDDR SDRAM存储器。
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所述LPDDR SDRAM存储器，包括第二代LPDDR SDRAM存储器即LPDDR2 SDRAM存储器、第三代LPDDR SDRAM存储器即LPDDR3 SDRAM、第四代LPDDR SDRAM存储器即LPDDR4 SDRAM和第五代LPDDR SDRAM存储器即LPDDR5 SDRAM。
所述非易失性存储器包括EEPROM存储器、NOR FLASH存储器和NAND FLASH存储器中的任意一种或多种。
所述非易失性存储器数据交换接口包括I 2C接口。
[根据细则26改正13.05.2019]　
所述存储器的封装规格包括LPDDR2 168b、LPDDR3 178b、LPDDR4 200b、LPDDR4 366b、eMCP 221b、eMCP 254b、MCP 162b、DDR3 78b、DDR4 78b和 DDR5 170b；利用上述封装中的闲置管脚用作易失性存储器数据交换接口。
本发明要解决的上述技术问题的技术方案还可以是，一种存储器测试系统，包括用于测试控制的测试主机和用于提供存储器测试接口的测试接口板；所述测试接口板上的接口包括测试板DRAM数据交换接口、测试板非易失性存储器数据交换接口；所述测试接口板上的测试板DRAM数据交换接口用于和待测试存储器的DRAM数据交换接口对接；所述测试接口板上的测试板非易失性存储器数据交换接口用于和待测试存储器的非易失性存储器数据交换接口对接；测试主机，控制测试板DRAM数据交换接口和待测试存储器的DRAM数据交换接口连接，并获取待测试存储器的特征参数信息；测试主机，通过测试板非易失性存储器数据交换接口 将特征参数信息写入存储器的非易失性存储器，使存储器内部自带特征参数信息。
所述测试接口板上的接口还包括测试控制数据交换接口；测试控制数据交换接口同时和测试板DRAM数据交换接口和测试板非易失性存储器数据交换接口连接；测试主机通过测试控制数据交换接口，控制测试板DRAM数据交换接口和待测试存储器的DRAM数据交换接口连接，并获取待测试存储器的特征参数信息；测试主机通过测试控制数据交换接口，让特征参数信息，通过测试板非易失性存储器数据交换接口写入存储器的非易失性存储器，使存储器内部自带的特征参数信息。
本发明要解决的上述技术问题的技术方案还可以是，一种存储器测试方法，包括步骤11：将待测存储器放入存储器测试系统中的测试接口板；步骤12：测试主机向待测存储器发送测试指令，启动测试；步骤13：测试主机扫描待测存储器，获取存储器的特征参数信息；步骤14：测试主机将获取的存储器的特征参数信息通过非易失性存储器数据交换接口写入存储器中的非易失性存储器。
所述存储器测试方法，还包括步骤141：测试主机根据获取的存储器的特征参数信息进行存储器的分类，并将存储器的分类数据和特征参数信息一起通过非易失性存储器数据交换接口写入存储器中的非易失性存储器。
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一种存储器测试方法，还包括步骤A5:测试主机根据外部指令对需要获取的特征参数信息进行设定，测试主机根据外部指令的要求将指定的特征参数信息写入非易失性存储器。
本发明要解决的上述技术问题的技术方案还可以是，一种装备有上述存储器的电子装置，所述电子装置包括主控制系统中的CPU，所述CPU包括CPU-DRAM数据交换接口和CPU非易失性存储器数据交换接口；CPU-DRAM数据交换接口用于和存储器的DRAM数据交换接口对接，实现CPU和存储器之间的数据交换；CPU非易失性存储器数据交换接口用于和存储器的非易失性存储器数据交换接口对接；CPU通过CPU非易失性存储器数据交换接口获取与CPU连接的存储器各单元特征参数信息，CPU根据存储器特征参数信息进行存储器的驱动控制。
本发明要解决的上述技术问题的技术方案还可以是，一种基于所述电子装置的存储器测试方法，包括，步骤21：CPU向待测存储器发送测试指令，启动测试；步骤22：CPU控制扫描待测存储器，获取新特征参数信息；步骤23：CPU将获取的新特征参数信息通过非易失性存储器数据交换接口写入存储器中的非易失性存储器，覆盖非易失性存储器原先存储的特征参数信息。
上述存储器测试方法，还包括步骤231：CPU根据获取的新特征参数信息进行存储器的分类，并将存储器的分类数据和特征参数信息一起通过非易失性存储器数据交换接口写入存储 器中的非易失性存储器。
上述存储器测试方法，还包括步骤24：CPU根据获取的新特征参数信息重新配置存储器的驱动参数。
本发明要解决的上述技术问题的技术方案还可以是，一种存储器应用方法，包括步骤31：设置存储器，是动态随机存取存储器，包括DRAM存储器和非易失性存储器，所述非易失性存储器，用于存储DRAM存储器的特征参数信息；步骤32：设置应用所述存储器的终端，所述终端包括应用终端CPU；步骤33：应用终端CPU向存储器发送指令，获取存储器的非易失性存储器中存储的特征参数信息；步骤34：应用终端CPU根据获取的存储器的所有特征参数信息，进行存储器的驱动控制。
同现有技术相比较，本发明的有益效果是：通过非易失性存储器存储的特征参数信息，可以根据不同设备对DRAM的要求，针对性的定制符合各自需求的存储器；对一些部分存储单元故障的存储器，也能通过该方法继续使用。
附图说明
图1是存储器的架构示意图；
图2是存储器测试系统的架构示意图；
图3是存储器及其测试系统组成的连接架构示意图；
图4是存储器的测试流程示意图；
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图5是存储器在电子装置中应用的流程示意图；
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图6是存储器在电子装置中进行在线测试的流程示意图；
图7是存储器的应用场景之一，是手机终端的存储器架构示意图；图中的CPU为手机终端的CPU，可见其内设置有IRAM、IROM、RAM和ROM；其中的RAM部分应用了本发明设计的存储器；
图8是现有技术中手机启动过程的流程示意图；
图9是应用了本发明设计的存储器之后，手机启动过程的流程示意图；图9相对图8增加了一个步骤，就是在运行内核启动系统之前，有一个步骤，该步骤中，会加载保存在非易失性存储介质中的内存特征参数数据并据此配置RAM的驱动。
具体实施方式
以下结合各附图对本发明的实施方式做进一步详述。
如图1所示的一种存储器的实施例中，存储器是动态随机存取存储器，包括DRAM存储器，以及用于DRAM存储器和外部进行数据交换的DRAM数据交换接口；还包括非易失性存储器，用 于存储DRAM存储器的特征参数信息；还包括非易失性存储器数据交换接口，用于非易失性存储器和外部进行数据交换。
所述非易失性存储器中存储的特征参数信息包括CAS Latency参数、tRCD参数、tRP参数和tRAS参数。所述非易失性存储器中存储的特征参数信息还包括Fast RAS To CAS Delay参数、tAC参数和tCL参数。
所述非易失性存储器中存储的特征参数信息还包括缺陷存储单元的地址索引信息，所述地址索引信息用于定位缺陷存储单元所在的地址分区。
设置地址索引信息的目的是方便将非易失性存储器中的特征参数信息在释放给外部设备使用时，能准确指明缺陷存储单元的地址分区。
需要指出的是，由于DRAM存储器和EEPROM存储容量大小不一，尤其是EEPROM存储容量有限，因此需要做有效区域放缩。地址索引信息所用的地址分区的策略会根据实际应用端的需求做区分。
常用的地址索引信息对应策略包括以下几种：
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例如在一个实施例中，假设DRAM存储器有A个存储单元即有A个存储地址，设定 B（B>6）个存储单元为一个地址分区，若第6个存储单元有暇疵，为缺陷存储单元，则标记第一个区为坏，地址索引信息中就会记录下第一区为缺陷存储单元所在的位置；若第n个存储单元有暇疵，就标记第C区有瑕疵，其中C＝取整(n/B)+1；地址索引信息中就会记录下第C区为缺陷存储单元所在的位置。其中设定地址分区大小的B数值，是可以根据EEPROM存储容量大小进行动态调节的。也就是说，当EEPROM存储容量大时，地址分区可以尽量取小，能更细化对应每个小的地址分区；当EEPROM存储容量小时，地址分区可以尽量大，在合理数量的范围能记录尽量多的特征参数信息。在DRAM存储器的空间利用率和EEPROM存储容量之间获得平衡。
又例如在另一个实施例中，假设DRAM存储器以两个片选信号(CS0、CS1)分为8个bank，每个bank由若干行和列的电容单元组成；地址索引信息可以bank为单位进行索引，地址索引信息就是各参数对应的bank。
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在一些附图未显示的实施例中，所述DRAM存储器，包括用于电脑和服务器的DDR SDRAM存储器。所述DDR SDRAM存储器，包括第三代DDR SDRAM存储器即DDR3 SDRAM存储器、第四代DDR SDRAM存储器即DDR4 SDRAM、第五代DDR SDRAM存储器即DDR5 SDRAM。
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在一些附图未显示的实施例中，所述DRAM存储器，包括用于用于移动终端的LPDDR SDRAM存储器。所述LPDDR SDRAM存储器，包括第二代LPDDR SDRAM存储器即LPDDR2SDRAM存储器、 第三代LPDDR SDRAM存储器即LPDDR3 SDRAM、第四代LPDDR SDRAM存储器即LPDDR4 SDRAM和第五代LPDDR SDRAM存储器即LPDDR5SDRAM。
在一些附图未显示的实施例中，所述非易失性存储器包括EEPROM存储器、NOR FLASH存储器和NAND FLASH存储器中的任意一种或多种。所述非易失性存储器数据交换接口包括I 2C接口。
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在一些附图未显示的实施例中，所述存储器的封装规格包括LPDDR2 168b、LPDDR3 178b、LPDDR4 200b、LPDDR4 366b、eMCP 221b、eMCP 254b、MCP 162b、DDR3 78b、DDR4 78b和DDR5 170b；利用上述封装中的闲置管脚用作易失性存储器数据交换接口。
如图2和3所示的一种存储器测试系统的实施例中，包括用于测试控制的测试主机和用于提供存储器测试接口的测试接口板；所述测试接口板上的接口包括测试板DRAM数据交换接口、测试板非易失性存储器数据交换接口；所述测试接口板上的测试板DRAM数据交换接口用于和待测试存储器的DRAM数据交换接口对接；所述测试接口板上的测试板非易失性存储器数据交换接口用于和待测试存储器的非易失性存储器数据交换接口对接；测试主机，控制测试板DRAM数据交换接口和待测试存储器的DRAM数据交换接口连接，并获取待测试存储器的特征参数信息；测试主机，通过测试板非易失性存储器数据交换接口将特征参数信息写入存储器的非易失性存储器，使存储器内部自带特征参数信息。
如图2和3所示的一种存储器测试系统的实施例中，所述测试接口板上的接口还包括测试控制数据交换接口；测试控制数据交换接口同时和测试板DRAM数据交换接口和测试板非易失性存储器数据交换接口连接；测试主机通过测试控制数据交换接口，控制测试板DRAM数据交换接口和待测试存储器的DRAM数据交换接口连接，并获取待测试存储器的特征参数信息；测试主机通过测试控制数据交换接口，让特征参数信息，通过测试板非易失性存储器数据交换接口写入存储器的非易失性存储器，使存储器内部自带的特征参数信息。
如图4所示的一种存储器测试方法的实施例中包括，步骤11：将待测存储器放入存储器测试系统中的测试接口板；步骤12：测试主机向待测存储器发送测试指令，启动测试；步骤13：测试主机扫描待测存储器，获取存储器的特征参数信息；步骤14：测试主机将获取的存储器的特征参数信息通过非易失性存储器数据交换接口写入存储器中的非易失性存储器；步骤141：测试主机根据获取的存储器的特征参数信息进行存储器的分类，并将存储器的分类数据和特征参数信息一起通过非易失性存储器数据交换接口写入存储器中的非易失性存储器。
在一些附图中没有显示的一种存储器测试方法的实施例中包括，
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步骤 A5：测试主机根据外部指令对需要获取的特征参数信息进行设定，根据外部指令的要求将指定的特征参数信息写入非易失性存储器。也就是说，在测试中，可以根据客户的定制化需求，在测试程序中灵活的配置想要存储在非易失性存储器中的特征参数，这些特征参数可以包括存储器适用的电压范围，设定存储器的写入和读取信息。步骤A5可以在上述步骤12或步骤13之前，也可以在步骤12或步骤13之后，只要测试主机和待测存储器已经建立了电连接之后，就可以开始。
在附图中没有显示的，装备有上述存储器的电子装置的实施例中，包括主控制系统中的CPU，所述CPU包括CPU-DRAM数据交换接口和CPU非易失性存储器数据交换接口；CPU-DRAM数据交换接口用于和存储器的DRAM数据交换接口对接，实现CPU和存储器之间的数据交换；CPU非易失性存储器数据交换接口用于和存储器的非易失性存储器数据交换接口对接；CPU通过CPU非易失性存储器数据交换接口获取与CPU连接的存储器各单元特征参数信息，CPU根据存储器特征参数信息进行存储器的驱动控制。
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如图6所示，一种基于上述电子装置的存储器测试方法中，包括，步骤21：CPU向待测存储器发送测试指令，启动测试；步骤22：CPU控制扫描待测存储器，获取新特征参数信息；步骤23：CPU将获取的新特征参数信息通过非易失性存储器数据交换接口写入存储器中的非易失性存储器，覆盖非易失性存储器原先存储的特征参数信息。
在附图中没有显示的，一种基于上述电子装置的存储器测试方法中，还包括步骤231：CPU根据获取的新特征参数信息进行存储器的分类，并将存储器的分类数据和特征参数信息一起通过非易失性存储器数据交换接口写入存储器中的非易失性存储器；步骤24：CPU根据获取的新特征参数信息重新配置存储器的驱动参数。
在附图中没有显示的，一种存储器应用方法的实施例中包括步骤31：设置存储器，是动态随机存取存储器，包括DRAM存储器和非易失性存储器，所述非易失性存储器，用于存储DRAM存储器的特征参数信息；步骤32：设置应用所述存储器的终端，所述终端包括应用终端CPU。
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图5所示，一种存储器应用方法的实施例中还包括步骤33：应用终端CPU向存储器发送指令，获取存储器的非易失性存储器中存储的特征参数信息；步骤34：应用终端CPU根据获取的存储器的所有特征参数信息，进行存储器的驱动控制。CPU驱动存储器和CPU之间的数据交换。
如图7和图8所示，在没有装备有本发明设计的应用手机终端的启动过程中，终端的CPU的IROM中存储了启动代码BL0，CPU上电之后就会去IROM中运行BL0，用来初始化系统时 钟，设置看门狗，初始化堆和栈，最后加载存储在ROM中的BL1到IRAM中去执行，在这时可以进行初始化RAM，关闭Cache，设置栈，然后加载保存在ROM中的BL2，BL2负责初始化其它外设，并最终加载存储在ROM中的OS内核代码到RAM中，之后运行内核程序启动系统。
如图7所示，之所以要区分BL1和BL2，而不是两者合并到一起去执行，原因在于IRAM很小，只有几十K大小，装不下uboot完全的代码，所以才会分成两部分，把大的那部分移到RAM中去运行，BL1中初始化了内存(RAM)并告诉BL2内存的基本信息(几个片选，总内存大小)，BL2中把这些信息组装在一种叫设备树(device tree)的结果体中，并最终把设备树传递给内核，并启动内核。内核启动之后，解析设备树信息进行各种具体的设置，其中从设备树中拿到内存信息包括可用区域和区域大小信息，并把这些可用的区域告诉系统，让系统去使用。
具体地，CPU读取非易失性存储器中的特征参数信息并配置相应存储器驱动的步骤可以在运行BL0的步骤之后和运行内核启动之前的任意环节完成。即读取非易失性存储器中的特征参数信息并配置相应存储器驱动的步骤可以在步骤BL1之前或步骤BL1中完成，也可以在步骤BL2中或之后完成。只要系统引导起来后，在内核程序启动之前完成上述读取特征参数信息并配置相应存储器驱动的步骤就可以。
如图9所示，一个存储器在应用手机终端的应用实施例中，系统在启动过程中，是在在步骤BL2之后，初始化RAM即本发明所设计的动态随机存取存储器，也就是将存储在非易失性存储器中的特征参数信息传递给CPU，让CPU以特征参数信息为依据建立新的存储器驱动。
现有技术中的动态随机存取存储器内存芯片(DRAM内存芯片)的测试方法和应用中，芯片测试模式(Patten)最主要是设定最高、最低电压值后，对每个存取地址进行若干次写入、读取扫描即顺序扫描和随机扫描；芯片等级是按照设定电压范围以及读写次数来分级，作为标准存储IC元器件供给应用终端，如手机；芯片等级越高，其电压适用范围小、读写扫描次数多，对应用平台即各种CPU的兼容性越好，但测试良率低、成本高。
应用终端设计开发时选择对应等级的动态随机存取存储器内存芯片即DRAM内存芯片，通过调整系统的软硬件来适应DRAM内存芯片，芯片等级越高，适应性约好，成本越高，延长了开发周期、增加了开发成本。在开发平台少、竞争不激烈时期，可通过延长开发时间来平衡DRAM内存芯片的价格。随着市场竞争的加剧、平台的增加、各平台推出新型号周期的缩短以及个性化的客户需求，极大的压缩了应用终端新机型的开发周期。现有DRAM内存芯片的标准化供应方式越来越不适应当前市场的兼容性和客制化需求，迫切需要新的DRAM内存芯片解决方案。
在本发明中，将DRAM存储器的特征参数信息记录在与DRAM存储器集成在同一芯片中的非易失存储器中，供CPU调用并调整CPU的驱动参数值到最优参数，使得CPU和DRAM存储器之间的匹配范围大大拓展，也变得更为灵活；可以将DRAM存储器的可用率从70％提升至90％以上。在CPU的功能和性能日益强大的背景下，这样的方式大大提高了该类电子装置的综合效率，能在成本效率之间取得更好的平衡。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (21)

  1. 一种存储器，是动态随机存取存储器，包括DRAM存储器，以及用于DRAM存储器和外部进行数据交换的DRAM数据交换接口；其特征在于：
    还包括非易失性存储器，用于存储DRAM存储器的特征参数信息；
    还包括非易失性存储器数据交换接口，用于非易失性存储器和外部进行数据交换。
  2. 根据权利要求1所述的存储器，其特征在于：
    所述非易失性存储器中存储的特征参数信息包括CAS Latency参数、tRCD参数、tRP参数和tRAS参数。
  3. 根据权利要求2所述的存储器，其特征在于：
    所述非易失性存储器中存储的特征参数信息还包括Fast RAS To CAS Delay参数、tAC参数和tCL参数。
  4. 根据权利要求2所述的存储器，其特征在于：
    所述非易失性存储器中存储的特征参数信息还包括缺陷存储单元的地址索引信息，所述地址索引信息用于定位缺陷存储单元所在的地址分区。
  5. 根据权利要求1所述的存储器，其特征在于：
    所述DRAM存储器，包括用于电脑和服务器的DDR SDRAM存储器。
  6. 根据权利要求5所述的存储器，其特征在于：
    所述DDR SDRAM存储器，包括第三代DDR SDRAM存储器即DDR3 SDRAM存储器、第四代DDR SDRAM存储器即DDR4 SDRAM、第五代DDR SDRAM存储器即DDR5 SDRAM。
  7. 根据权利要求1所述的存储器，其特征在于：
    所述DRAM存储器，包括用于移动终端的LPDDR SDRAM存储器。
  8. 根据权利要求7所述的存储器，其特征在于：
    所述LPDDR SDRAM存储器，包括第二代LPDDR SDRAM存储器即LPDDR2 SDRAM存储器、第三代LPDDR SDRAM存储器即LPDDR3 SDRAM、第四代LPDDR SDRAM存储器即LPDDR4 SDRAM和第五代LPDDR SDRAM存储器即LPDDR5SDRAM。
  9. 根据权利要求1所述的存储器，其特征在于：
    所述非易失性存储器包括EEPROM存储器、NOR FLASH存储器和NAND FLASH存储器中的任意一种或多种。
  10. 根据权利要求1所述的存储器，其特征在于：
    所述非易失性存储器数据交换接口包括I 2C接口。
  11. 根据权利要求1所述的存储器，其特征在于：
    所述存储器的封装规格包括LPDDR2 168b、LPDDR3 178b、LPDDR4 200b、LPDDR4 366b、eMCP 221b、eMCP 254b、MCP 162b、DDR3 78b、DDR4 78b和DDR5 170b；利用上述封装中的闲置管脚用作易失性存储器数据交换接口。
  12. 一种存储器测试系统，其特征在于：
    包括用于测试控制的测试主机和用于提供存储器测试接口的测试接口板；
    所述测试接口板上的接口包括测试板DRAM数据交换接口、测试板非易失性存储器数据交换接口；
    所述测试接口板上的测试板DRAM数据交换接口用于和待测试存储器的DRAM数据交换接口对接；
    所述测试接口板上的测试板非易失性存储器数据交换接口用于和待测试存储器的非易失性存储器数据交换接口对接；
    测试主机，控制测试板DRAM数据交换接口和待测试存储器的DRAM数据交换接口连接，并获取待测试存储器的特征参数信息；测试主机，通过测试板非易失性存储器数据交换接口将特征参数信息写入存储器的非易失性存储器，使存储器内部自带特征参数信息。
  13. 根据权利要求12所述存储器测试系统，其特征在于：
    所述测试接口板上的接口还包括测试控制数据交换接口；测试控制数据交换接口同时和测试板DRAM数据交换接口和测试板非易失性存储器数据交换接口连接；
    测试主机通过测试控制数据交换接口，控制测试板DRAM数据交换接口和待测试存储器的DRAM数据交换接口连接，并获取待测试存储器的特征参数信息；
    测试主机通过测试控制数据交换接口，让特征参数信息，通过测试板非易失性存储器数据交换接口写入存储器的非易失性存储器，使存储器内部自带的特征参数信息。
  14. 一种存储器测试方法，其特征在于，包括，
    步骤11：将待测存储器放入存储器测试系统中的测试接口板；
    步骤12：测试主机向待测存储器发送测试指令，启动测试；
    步骤13：测试主机扫描待测存储器，获取存储器的特征参数信息；
    步骤14：测试主机将获取的存储器的特征参数信息通过非易失性存储器数据交换接口写入存储器中的非易失性存储器。
  15. 根据权利要求14所述的存储器测试方法，其特征在于，还包括
    步骤141：测试主机根据获取的存储器的特征参数信息进行存储器的分类，并将存储器的 分类数据和特征参数信息一起通过非易失性存储器数据交换接口写入存储器中的非易失性存储器。
  16. 根据权利要求14所述的存储器测试方法，其特征在于，还包括
    步骤A5：测试主机根据外部指令对需要获取的特征参数信息进行设定，测试主机根据外部指令的要求将指定的特征参数信息写入非易失性存储器。
  17. 一种装备有权利要求1至11中任意一项存储器的电子装置，其特征在于：
    所述电子装置包括主控制系统中的CPU，所述CPU包括CPU-DRAM数据交换接口和CPU非易失性存储器数据交换接口；
    CPU-DRAM数据交换接口用于和存储器的DRAM数据交换接口对接，实现CPU和存储器之间的数据交换；
    CPU非易失性存储器数据交换接口用于和存储器的非易失性存储器数据交换接口对接；
    CPU通过CPU非易失性存储器数据交换接口获取与CPU连接的存储器各单元特征参数信息，CPU根据存储器特征参数信息进行存储器的驱动控制。
  18. 一种基于权利要求17所述电子装置的存储器测试方法，其特征在于，包括，
    步骤21：CPU向待测存储器发送测试指令，启动测试；
    步骤22：CPU控制扫描待测存储器，获取新特征参数信息；
    步骤23：CPU将获取的新特征参数信息通过非易失性存储器数据交换接口写入存储器中的非易失性存储器，覆盖非易失性存储器原先存储的特征参数信息。
  19. 根据权利要求18所述的存储器测试方法，其特征在于，还包括
    步骤231：CPU根据获取的新特征参数信息进行存储器的分类，并将存储器的分类数据和特征参数信息一起通过非易失性存储器数据交换接口写入存储器中的非易失性存储器。
  20. 根据权利要求18所述的存储器测试方法，其特征在于，还包括
    步骤24：CPU根据获取的新特征参数信息重新配置存储器的驱动参数。
  21. 一种存储器应用方法，其特征在于，
    步骤31：设置存储器，是动态随机存取存储器，包括DRAM存储器和非易失性存储器，所述非易失性存储器，用于存储DRAM存储器的特征参数信息；
    步骤32：设置应用所述存储器的终端，所述终端包括应用终端CPU；
    步骤33：应用终端CPU向存储器发送指令，获取存储器的非易失性存储器中存储的特征参数信息；
    步骤34：应用终端CPU根据获取的存储器的所有特征参数信息，进行存储器的驱动控制。
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