WO2020198996A1 - 一种信号处理装置及信号处理方法 - Google Patents

一种信号处理装置及信号处理方法 Download PDF

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Publication number
WO2020198996A1
WO2020198996A1 PCT/CN2019/080582 CN2019080582W WO2020198996A1 WO 2020198996 A1 WO2020198996 A1 WO 2020198996A1 CN 2019080582 W CN2019080582 W CN 2019080582W WO 2020198996 A1 WO2020198996 A1 WO 2020198996A1
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Prior art keywords
local oscillator
oscillator signal
signal
controller
link
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PCT/CN2019/080582
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English (en)
French (fr)
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杜皎
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华为技术有限公司
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Priority to CN201980094599.0A priority Critical patent/CN113632395B/zh
Priority to PCT/CN2019/080582 priority patent/WO2020198996A1/zh
Publication of WO2020198996A1 publication Critical patent/WO2020198996A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • This application relates to the field of communications, and in particular to a signal processing device and signal processing method.
  • the local oscillator signal chain (LO Buffer Chain) with a frequency divider is generally open, which will cause the RF transceiver chip to consume additional power consumption.
  • the frequency divider in the local oscillator signal link has the problem of random phase after each power-up. For example, if the local oscillator signal link is always on, then The phase of the output signal of the local oscillator signal link is continuous, and if the local oscillator signal link is turned on from closed to open, that is, it is re-powered, the phase of the output signal of the local oscillator signal link may be relative to the signal with continuous phase. A large phase reversal occurred.
  • the phase of the output signal is unstable during the switching of the local oscillator signal link.
  • the embodiments of the present application provide a signal processing device and a signal processing method, which can make the phase of the output signal of the signal processing device more stable during the switch state switching process.
  • a signal processing device which may include:
  • PLL Phase Locked Loop
  • the output end of the PLL is connected to the first input end of the local oscillator signal link and the input end of the controller.
  • the output end of the controller Connected to the second input of the local oscillator signal link; PLL is used to output the first local oscillator signal to the local oscillator signal link and the controller, and the local oscillator signal link is used to divide the first local oscillator signal to generate
  • the second local oscillator signal is used by the controller to output a control signal to the local oscillator signal link according to the first local oscillator signal, and the control signal is used to control the local oscillator signal link to open or close.
  • the number of local oscillator signal links supported in the signal processing device may be one or more, and the control signal output by the controller may control the opening or closing of multiple local oscillator signal links.
  • the PLL can be directly connected to the local oscillator signal link and controller, or it can be connected to the local oscillator signal link and controller through other circuits or modules.
  • the controller can be connected to the local oscillator signal The link is directly connected, or it may be connected to the local oscillator signal link through other circuits or modules, which is not specifically limited here.
  • the signal processing device in this application may specifically be a radio frequency transceiver chip, in addition to this, it may also be a terminal device or a base station.
  • the controller can also obtain the first local oscillator signal from the PLL according to The first local oscillator signal controls the opening or closing of the local oscillator signal link. Therefore, in this application, the first local oscillator signal is combined with the first local oscillator signal to control the opening or closing of the local oscillator signal link, so that the local oscillator signal link can be powered on again. At this time, the phase of the second local oscillator signal output is controllable, so that the phase of the second local oscillator signal output by the local oscillator signal link during the switch state switching process is more stable.
  • the controller includes a counting unit and a control unit, wherein the input of the counting unit is connected to the output of the PLL, the output of the counting unit is connected to the input of the control unit, and the output of the control unit is connected to the second part of the local oscillator signal link.
  • the input terminal is connected; the counting unit is used to obtain the first local oscillator signal and output a trigger signal to the control unit according to the first local oscillator signal.
  • the period of the trigger signal is an integer multiple of the clock period of the second local oscillator signal, and the control unit is used for Output the control signal to the local oscillator signal link according to the trigger signal.
  • the internal structure and processing logic of a controller are provided, that is, the controller includes a counting unit and a control unit, and the first local oscillator signal is combined to control the local oscillator signal through the cooperation of the counting unit and the control unit.
  • the structure and processing logic of the controller are simple and easy to implement, which improves the feasibility of the solution.
  • the counting unit includes a first frequency divider, and the control unit includes a first flip-flop DFF.
  • the frequency division ratio of the first frequency divider is an integer multiple of the frequency division ratio of the local oscillator signal link.
  • an electronic device for specifically realizing the above counting unit and control unit that is, the first frequency divider and the first DFF, is listed, which improves the practicability of the solution.
  • the counting unit includes a cycle counter, and the control unit includes a second DFF.
  • the cycle counter starts the cycle counting according to the first local oscillator signal, and outputs a trigger signal to the second DFF at the end of each cycle counting cycle.
  • the cycle counting cycle is the second DFF. An integer multiple of the clock period of the local oscillator signal.
  • another electronic device for specifically realizing the above-mentioned counting unit and control unit is listed, that is, a cycle counter and a second DFF, which improves the scalability of the solution.
  • the clock period of the second local oscillator signal is 2*N times the clock period of the first local oscillator signal, and N is an integer greater than or equal to 1.
  • the local oscillator signal link can specifically divide the first local oscillator signal by an even number to obtain the second local oscillator signal, which is easier to implement.
  • the local oscillator signal link can also be the first local oscillator signal.
  • the oscillator signal is divided by odd numbers to obtain the second local oscillator signal, which is not specifically limited here.
  • the local oscillator signal link includes at least one buffer and a second frequency divider.
  • the first input end of the buffer is connected to the output end of the PLL, and the output end of the buffer is connected to the first input end of the second frequency divider.
  • the output end of the device is connected to the second input end of the buffer and/or the second input end of the second frequency divider; the buffer is used to obtain the first local oscillator signal and the control signal, if the control signal is used to control the local oscillator signal chain
  • the buffer transmits the first local oscillator signal to the second frequency divider. If the control signal is used to control the local oscillator signal link to close, the buffer locks the first local oscillator signal and locks the first local oscillator signal.
  • the vibration signal is transmitted to the second frequency divider; the second frequency divider is used to perform frequency division processing on the first local oscillator signal to generate a second local oscillator signal.
  • composition structure and processing logic of the local oscillator signal link are provided, which completes the circuit structure of the solution, and further improves the feasibility of the solution.
  • the controller is also used to obtain a time division duplex TDD signal.
  • the controller is used to output a control signal to the local oscillator according to the first local oscillator signal.
  • the signal link includes: the controller outputs a TDD control signal to the local oscillator according to the first local oscillator signal and the TDD signal.
  • Signal link, the TDD control signal is used to control the opening or closing of the local oscillator signal link, and every two adjacent TDD control signals output by the controller are separated by an integer multiple of the clock period of the second local oscillator signal.
  • a specific application scenario is provided, that is, when the local oscillator signal link is switched with the TDD signal, the TDD control signal can be used to control the local oscillator signal link to open or close. After the routing is switched to the off state, the phase state of the second local oscillator signal will be locked.
  • the high and low levels of the TDD control signal correspond to the on and off of the local oscillator signal link, and the phase continuous controller outputs the same for every two adjacent ones.
  • the TDD control signals are separated by integer multiples of the clock period of the second local oscillator signal.
  • the phase state of each timing corresponds to one clock cycle, and every two second local oscillator signals If the phase of the second local oscillator signal is the same as the clock cycle, then the local oscillator signal link has passed an integer multiple of the second local oscillator signal’s clock cycle from closed to open.
  • the phase of the local oscillator signal link in the on state is continuous of.
  • the second aspect of the present application provides a signal processing method, which may include:
  • the controller obtains the first local oscillator signal from the PLL;
  • the controller outputs a control signal to the local oscillator signal link according to the first local oscillator signal, and controls the local oscillator signal link to turn on or off through the control signal.
  • the local oscillator signal link is used to obtain the first local oscillator signal from the PLL and The first local oscillator signal is subjected to frequency division processing to generate a second local oscillator signal.
  • the controller outputting a control signal to the local oscillator signal link according to the first local oscillator signal includes:
  • the controller generates a trigger signal according to the first local oscillator signal, and the period of the trigger signal is an integer multiple of the clock period of the second local oscillator signal;
  • the controller outputs a control signal to the local oscillator signal link according to the trigger signal.
  • the controller generating the trigger signal according to the first local oscillator signal includes:
  • the controller performs frequency division processing on the first local oscillator signal to generate a trigger signal, and the frequency division ratio of the controller is an integer multiple of the frequency division ratio of the local oscillator signal link.
  • the controller generating the trigger signal according to the first local oscillator signal includes:
  • the controller starts the cycle counting according to the first local oscillator signal, and generates a trigger signal at the end of each cycle counting cycle, and the cycle counting cycle is an integer multiple of the clock cycle of the second local oscillator signal.
  • the clock period of the second local oscillator signal is 2*N times the clock period of the first local oscillator signal, and N is an integer greater than or equal to 1.
  • the method further includes:
  • the controller obtains the time division duplex TDD signal
  • the controller outputting a control signal to the local oscillator signal link according to the first local oscillator signal includes:
  • the controller outputs the TDD control signal to the local oscillator signal link according to the first local oscillator signal and the TDD signal, and controls the local oscillator signal link to turn on or off through the TDD control signal.
  • the controller outputs every two adjacent TDD control signals. The signals are separated by an integer multiple of the clock period of the second local oscillator signal.
  • the controller can also obtain the first local oscillator signal from the PLL. Signal and control the opening or closing of the local oscillator signal link according to the first local oscillator signal. Therefore, in this application, the first local oscillator signal is combined with the first local oscillator signal to control the opening or closing of the local oscillator signal link.
  • the phase of the second local oscillator signal output by the circuit is controllable when the circuit is re-powered, so that the phase of the second local oscillator signal output by the local oscillator signal link during the switch state switching process is more stable.
  • Figure 1 is a schematic diagram of a system scenario applied by this application.
  • FIG. 1 Schematic diagram of the time sequence of the local oscillator signal
  • FIG. 3 is a schematic diagram of a structure of the signal processing device in this application.
  • FIG. 4 is a schematic diagram of another structure of the signal processing device in this application.
  • FIG. 5 is a schematic diagram of signal timing related to the signal processing device in the present application.
  • FIG. 6 is a schematic diagram of another structure of the signal processing device in this application.
  • FIG. 7 is a schematic diagram of another structure of the signal processing device in this application.
  • FIG. 8 is a schematic diagram of another structure of the signal processing device in this application.
  • FIG. 9 is a schematic structural diagram when the signal processing device in this application is a terminal or a base station.
  • FIG. 10 is a schematic diagram of another structure when the signal processing device in this application is a terminal or a base station;
  • FIG. 11 is a schematic diagram of an embodiment of the signal processing method in this application.
  • FIG. 1 The system architecture or scenario of the main application of this application is shown in Figure 1, including access network equipment and terminal equipment. Both access network equipment and terminal equipment can work in licensed frequency bands or unlicensed frequency bands in base stations and terminal equipment. Regardless of whether it is a licensed frequency band or an unlicensed frequency band, in this application, one or more carriers can be included. Carrier aggregation for licensed frequency bands and unlicensed frequency bands can include one or more carriers included in licensed frequency bands and unlicensed frequency bands including Carrier aggregation is performed on one or more of the carriers.
  • the access network equipment can be a long-term evolution (LTE) system or an authorized auxiliary access long-term evolution (LAA-LTE) system in an evolved base station (evolutional Node B, which may be referred to as eNB or e-NodeB), macro base station, micro base station (also called “small base station”), pico base station, access point (AP), transmission point (TP), or new radio (new radio, NR)
  • LTE long-term evolution
  • LAA-LTE authorized auxiliary access long-term evolution
  • eNB evolved base station
  • macro base station macro base station
  • micro base station also called “small base station”
  • pico base station access point
  • AP access point
  • TP transmission point
  • new radio new radio
  • Terminal equipment can be referred to as user equipment (UE), mobile station (MS), mobile terminal (mobile terminal), smart terminal, etc.
  • the terminal equipment can be accessed through a radio access network (RAN).
  • RAN radio access network
  • the terminal device can be a mobile phone (or called a "cellular" phone), a computer with a mobile terminal, etc.
  • the terminal device can also be a portable, pocket-sized, handheld, computer built-in or vehicle-mounted mobile device, and the future NR network They exchange voice or data with the wireless access network.
  • Description of terminal equipment In this application, all devices that can communicate with the base station can be regarded as terminal equipment. In this application, the UE and the base station in a general sense will be introduced.
  • the local oscillator signal link in the radio frequency transceiver chip applied to the base station or UE is generally open, which will cause the radio frequency transceiver chip to consume additional power consumption.
  • the frequency divider in the local oscillator signal link has the problem of random phase after each power-on.
  • the sequence of the local oscillator signal processed by the local oscillator signal link can be as shown in Figure 2, that is, the sequence of the local oscillator signal is "1010", for example, if the local oscillator signal link is always on, then the local oscillator
  • the phase of the output signal of the oscillator signal link is continuous, and if the local oscillator signal link is turned on from closed to open, that is, re-powered, the phase of the output signal of the local oscillator signal link may be larger than the signal with continuous phase.
  • phase of the local oscillator signal is "1" before the local oscillator signal link is closed, and the phase of the local oscillator signal is "0" after the local oscillator signal link is opened next time, so there is There may be a problem that the phase of the local oscillator signal output by the local oscillator signal link is unstable during the process of the local oscillator signal link from opening to closing to opening.
  • an embodiment of the present application provides a signal processing device, which will be described below.
  • the signal processing device in the embodiment of the present application may be specifically applied to a radio frequency transceiver chip, and the radio frequency transceiver chip may be applied to a base station or a terminal.
  • FIG. 3 is a schematic diagram of an embodiment of the signal processing device in this application.
  • the signal processing device includes a phase locked loop (PLL) 301, a local oscillator signal link 302, and a controller 303.
  • PLL phase locked loop
  • the output terminal of the phase-locked loop 301 is respectively connected to the first input terminal of the local oscillator signal link 302 and the input terminal of the controller 303, and the output terminal of the controller 303 is connected to the second input terminal of the local oscillator signal link 302. Connected.
  • the phase locked loop 301 is used to output the first local oscillator signal to the local oscillator signal link 302 and the controller 303;
  • the local oscillator signal link 302 is used to perform frequency division processing on the first local oscillator signal to generate a second local oscillator signal;
  • the controller 303 is configured to output a control signal to the local oscillator signal link 302 according to the first local oscillator signal, and the control signal is used to control the local oscillator signal link 302 to open or close.
  • the local oscillator signal link 302 when the control signal is at a high level, the local oscillator signal link 302 is turned on and works normally. When the control signal is low, the local oscillator signal link 302 is closed. Specifically, the local oscillator signal link 302 locks the first local oscillator signal currently input, for example, pulls the first local oscillator signal high or low, Then the second local oscillator signal output by the local oscillator signal link 302 maintains the state before the local oscillator signal link 302 is closed, and there is no dynamic power consumption when the local oscillator signal link 302 is closed, which can effectively reduce the signal processing device The overall power consumption.
  • the controller can also obtain the first local oscillator signal from the PLL. Signal and control the opening or closing of the local oscillator signal link according to the first local oscillator signal. Therefore, in this application, the first local oscillator signal is combined with the first local oscillator signal to control the opening or closing of the local oscillator signal link.
  • the phase of the second local oscillator signal output by the circuit is controllable when the circuit is re-powered, so that the phase of the second local oscillator signal output by the local oscillator signal link during the switch state switching process is more stable.
  • the local oscillator signal link needs to be switched with the TDD signal. For example, when the TDD signal is pulled high, the local oscillator signal link is opened, and the TDD signal is pulled low, then the local oscillator signal link is closed. And it is necessary to ensure that the phase of the output signal of the local oscillator signal link is continuous during the switching process of the local oscillator signal link with the TDD signal. It can be seen that with the introduction of the TDD signal, it is no longer to control the opening or closing of the local oscillator signal link only according to the control signal generated by the first local oscillator signal, which will be described in detail below.
  • the controller 303 can obtain a time-division duplex (TDD) signal in addition to the first local oscillator signal, and output the TDD control signal to the local oscillator signal according to the first local oscillator signal and the TDD signal Link 302, the TDD control signal is used to control the opening or closing of the local oscillator signal link 302.
  • the TDD control signal in this embodiment is equivalent to the control signal in the embodiment shown in FIG. 3.
  • each phase output by the controller 303 Two adjacent TDD control signals are separated by an integer multiple of the clock period of the second local oscillator signal.
  • the local oscillator signal link 302 may include at least one buffer 3021 and a frequency divider 3022.
  • the first input end of the buffer 3021 is connected to the output end of the phase-locked loop 301, and the output end of the buffer 3021 is connected to the frequency divider 3022.
  • the first input terminal is connected, the output terminal of the controller 303 may be connected to the second input terminal of the buffer 3021, or may be connected to the second input terminal of the frequency divider 3022, or at the same time to the second input terminal of the buffer 3021 Terminal is connected to the second input terminal of the frequency divider 3022;
  • the buffer 3021 can obtain the TDD control signal in addition to the first local oscillator signal. If the TDD control signal is used to control the local oscillator signal chain When the circuit 302 is closed, the buffer 3021 locks the first local oscillator signal, and transmits the locked first local oscillator signal to the frequency divider 3022.
  • the buffer 3021 restores the first local oscillator signal, and transmits the restored first local oscillator signal to the frequency divider 3022; if the output terminal of the controller 303 is not connected to the second input terminal of the buffer 3021, it is connected to the frequency divider The second input terminal of 3022 is connected, then the TDD control signal directly controls the opening or closing of the frequency divider.
  • the frequency divider 3022 is used to generate the second local oscillator signal according to the first local oscillator signal. Specifically, the frequency divider 3022 performs frequency division processing on the first local oscillator signal. Normally, the frequency division ratio of the frequency divider 3022 is 2 or a multiple of 2, that is, the frequency of the second local oscillator signal can be 1/2*N of the frequency of the first local oscillator signal, where N is an integer greater than or equal to 1, and the clock period of the second local oscillator signal is 2*N times the clock period of the first local oscillator signal.
  • the frequency division ratio of the frequency divider 3022 may also be other values, for example, the frequency division ratio is 3, 5, 7, etc., which are not specifically limited here.
  • the clock period of the second local oscillator signal is twice the clock period of the first local oscillator signal.
  • continuous first local oscillator signal means that the state of the first local oscillator signal continuously does not change with the TDD control signal being pulled up or down, and the same is true for “continuous second local oscillator signal”;
  • changing first local oscillator signal means that the state of the first local oscillator signal is continuous when the TDD control signal is pulled high, and the state of the first local oscillator signal is locked when the TDD control signal is pulled low. The same applies to the "changing second local oscillator signal”.
  • the changed second local oscillator signal changes with the change of the TDD control signal, and when the TDD control signal changes is determined by the change of the TDD signal, that is, although the TDD signal is pulled down
  • the state of the second local oscillator signal will not be locked immediately, but the state of the second local oscillator signal will be locked when the TDD control signal is pulled low. This is due to the rising edge (or falling edge) of the TDD signal and the second local oscillator signal.
  • the rising edge (or falling edge) of the vibration signal may not be aligned, so the rising edge (or falling edge) of the TDD control signal needs to be aligned with the rising edge (or falling edge) of the second local oscillator signal to ensure the second local oscillator
  • the signal enters the locked state at the time of the rising edge (or falling edge), and then recovers from the locked state at the time of another rising edge (or falling edge), so that the phase of the second local oscillator signal after the recovery from the locked state is the same as The phase of the second local oscillator signal before locking is the same.
  • the clock period of the second local oscillator signal to realize that the phase of the second local oscillator signal after recovery from the locked state is the same as the phase before the second local oscillator signal is locked.
  • the controller 303 needs to change the TDD control signal (pull it high) at a time point that matches the clock period of the second local oscillator signal after detecting a change in the TDD signal (pull it high or pull it low). Or pull down).
  • This application specifically provides a variety of controller implementation methods, which are introduced below:
  • the controller 303 includes a first frequency divider 3031 and a first flip-flop (delay flip-flop, DFF) 3032, wherein the input end of the first frequency divider 3031 and the output end of the phase locked loop 301
  • the output terminal of the first frequency divider 3031 is connected to the input terminal of the first flip-flop 3032, and the output terminal of the first flip-flop 3032 is connected to the input terminal of the local oscillator signal link 302.
  • the first frequency divider 3031 can obtain the first local oscillator signal and output a trigger signal to the first trigger 3032 according to the first local oscillator signal.
  • the first frequency divider 3031 and the local oscillator signal link 302 divide The function of the frequency converter 3022 is similar, and the clock period of the trigger signal is an integer multiple of the clock period of the second local oscillator signal.
  • the timing of the trigger signal is aligned with that of the second local oscillator signal. For example, if the trigger signal is The clock cycle is the same as the clock cycle of the second local oscillator signal.
  • the timing diagram of the trigger signal refer to the timing diagram of the “continuous second local oscillator signal” in FIG. 5.
  • the first trigger 3032 can acquire the TDD signal and output the TDD control signal to the local oscillator signal link 302 according to the change of the TDD signal and the trigger signal. Specifically, the first trigger 3032 detects the acquired TDD signal, if detected The TDD signal changes (for example, pulled low), and further outputs a low-level TDD control signal to the local oscillator signal link 302 at the time of the next rising edge (or falling edge) of the trigger signal to control the local oscillator signal link 302 to close Similarly, if the first flip-flop 3032 detects that the TDD signal is pulled high, it further outputs a high-level TDD control signal to the local oscillator signal link 302 at the time of the next rising edge (or falling edge) of the trigger signal to control The local oscillator signal link 302 is turned on.
  • the TDD control signals are separated by integer multiples of the clock period of the second local oscillator signal.
  • the controller 303 includes a loop counter 3033 and a second flip-flop 3034.
  • the input terminal of the loop counter 3033 is connected to the output terminal of the phase-locked loop 301, and the output terminal of the loop counter 3033 is connected to the second flip-flop 3034.
  • the input terminal of the second flip-flop 3034 is connected to the input terminal of the local oscillator signal link 302. It should be noted that both the cycle counter 3033 and the second flip-flop 3034 can acquire the TDD signal.
  • the cycle counter 3033 If the cycle counter 3033 detects that the TDD signal is pulled low, it will start cycle counting on the rising edge (or falling edge) of the next clock cycle of the first local oscillator signal, and send a trigger signal to the second flip-flop 3034. After receiving the trigger signal, output the pulled-down TDD control signal to the local oscillator signal link 302; the cycle counter 3033 keeps counting until the TDD signal is detected to be pulled high, and then it needs to complete a complete cycle of cycle counting and then trigger the second trigger The second trigger 3034 receives the trigger signal and outputs the pulled high TDD control signal to the local oscillator signal link 302 after receiving the trigger signal.
  • the trigger signal is output to the second flip-flop 3034 at the end of each cycle counting period, where the cycle counting period is an integer multiple of the clock period of the second local oscillator signal .
  • the cycle counter adds 1 to the original count. If the clock period of the second local oscillator signal is T, then the phase of the second local oscillator signal changes once every T/2. That is, the loop counter counts once every T/2 duration, so every two counts of the loop counter corresponds to one clock cycle of the second local oscillator signal. For example, if the cycle counting cycle is set to 2, the cycle counter will cycle counting according to the count value of "121212", if the cycle counting cycle is set to 4, the cycle counter will cycle counting according to the count value of "12341234!.
  • the second flip-flop 3034 After the cycle counter 3033 starts counting, and before the second flip-flop 3034 detects that the TDD signal is pulled high, the second flip-flop 3034 does not output the TDD control signal according to the trigger signal. Until the second trigger 3034 detects that the TDD signal is pulled high, the second trigger 3034 outputs the TDD control signal to the local oscillator signal link 302 after receiving the next trigger signal. Since the preset cycle count cycle is an integer multiple of the clock cycle of the second local oscillator signal, it can be achieved between two adjacent TDD control signals output by the second flip-flop 3034 with the same state (both pulled high). Separate by integer multiples of the clock period of the second local oscillator signal.
  • the cycle counter 3033 replaces the first frequency divider 3031, and the first frequency divider in the first implementation
  • the device 3031 needs to keep working at all times, while the cycle counter 3033 in the second implementation mode only works during the TDD signal pull-down period. To a certain extent, the second implementation mode consumes more power than the first implementation mode. low.
  • first divider 3031 and the loop counter 3033 are replaced by other counting units with counting functions, and other control logics are used.
  • the control unit replaces the aforementioned first trigger 3032 and second trigger 3034.
  • the local oscillator signal link may generate the second local oscillator signal according to the first local oscillator signal from the PLL, where the clock period of the second local oscillator signal is the clock of the first local oscillator signal The period is 2*N times, and N is an integer greater than or equal to 1.
  • the local oscillator signal link is switched with the TDD signal, the local oscillator signal link can be controlled to open or close through the TDD control signal. After the link is switched from on to off, the phase state of the second local oscillator signal will be locked.
  • the high and low levels of the TDD control signal correspond to the on and off of the local oscillator signal link, and the controller outputs every two adjacent ones that are the same
  • the TDD control signals are separated by integer multiples of the clock period of the second local oscillator signal. Since the timing of the second local oscillator signal is 1010, the phase state of each timing corresponds to one clock period, and every two second local oscillator signals If the phase of the second local oscillator signal is the same in the clock cycle, then the local oscillator signal link has passed an integer multiple of the second local oscillator signal’s clock cycle from off to on.
  • the phase of the local oscillator signal link in the on state is continuous Therefore, it only needs to increase the controller to realize the phase continuity during the switching process of the local oscillator signal link with the TDD signal, the circuit complexity is low, and the cost and power consumption are effectively saved.
  • the signal processing device in this application can be applied to other scenarios in addition to the above-mentioned scenario where the local oscillator signal link is switched with the TDD signal.
  • One of the extended scenarios is listed below.
  • the signal output by the phase-locked loop 301 can also be a clock signal (the first clock signal as shown in Fig. 8);
  • the signal processing device only includes a local oscillator signal link ( Of course, it can also include multiple).
  • the signal processing device in this embodiment can also support multiple signal links (the first signal link and the second signal link as shown in FIG.
  • the controller 303 obtains the TDD signal and outputs the TDD control signal.
  • the controller 303 can also obtain the switch signal and output the switch control signal.
  • the switch control signal can also control multiple signal link switches. And the phase of the output clock signal of each signal link is continuous during the switching process with the switch control signal.
  • the processing logic of the first frequency divider 3031 and the first flip-flop 3032 in the controller 303 is similar to the processing logic of the controller 303 in the embodiment shown in FIG. 6, and will not be repeated here.
  • the frequency division ratio of the frequency divider in each signal link may be the same or different.
  • the frequency division ratio of the first frequency divider in the controller 303 is an integer multiple of the frequency division ratio of the frequency divider in each signal link; if The frequency division ratio of the frequency divider in each signal link is different, the frequency division ratio of the first frequency divider 3031 in the controller 303 may be the least common multiple of the frequency division ratio of the frequency divider in each signal link For example, if the frequency division ratio of the frequency divider in the first signal link is 2 and the frequency division ratio in the second signal link is 3, then the frequency division ratio of the first frequency divider 3031 in the controller 303 can be 6 or multiples of 6.
  • the embodiments of the present application also provide a signal processing device.
  • the signal processing device may be a terminal or a base station, and the signal processing device is configured to perform operations performed by the signal processing device in the foregoing embodiment.
  • FIG. 9 shows a simplified schematic diagram of the structure of the terminal or the base station.
  • the terminal or base station includes a processor, a memory, a radio frequency circuit, an antenna, and an input and output device.
  • the processor is mainly used to process the communication protocol and communication data, control the terminal or base station, execute the software program, and process the data of the software program.
  • the memory is mainly used to store software programs and data.
  • the radio frequency circuit is mainly used for the conversion of baseband signal and radio frequency signal and the processing of radio frequency signal.
  • the antenna is mainly used to send and receive radio frequency signals in the form of electromagnetic waves.
  • Input and output devices such as touch screens, display screens, and keyboards, are mainly used to receive data input by users and output data to users. It should be noted that some types of terminal devices may not have input and output devices.
  • the processor When a terminal or a base station needs to send data, the processor performs baseband processing on the data to be sent and outputs the baseband signal to the radio frequency circuit.
  • the radio frequency circuit performs radio frequency processing on the baseband signal and then sends the radio frequency signal out in the form of electromagnetic waves through the antenna.
  • the radio frequency circuit receives the radio frequency signal through the antenna, converts the radio frequency signal into a baseband signal, and outputs the baseband signal to the processor, and the processor converts the baseband signal into data and processes the data .
  • only one memory and processor are shown in FIG. 9. In actual terminal equipment products, there may be one or more processors and one or more memories.
  • the memory may also be referred to as a storage medium or storage device.
  • the memory may be set independently of the processor, or may be integrated with the processor, which is not limited in the embodiment of the present application.
  • the antenna and radio frequency circuit with the transceiver function can be regarded as the transceiver unit of the terminal device, and the processor with the processing function can be regarded as the processing unit of the terminal device.
  • the terminal device includes a transceiver unit 910 and a processing unit 920.
  • the transceiver unit may also be referred to as a transceiver, a transceiver, a transceiver, and so on.
  • the processing unit may also be called a processor, a processing board, a processing module, a processing device, and so on.
  • the device for implementing the receiving function in the transceiver unit 910 can be regarded as the receiving unit, and the device for implementing the sending function in the transceiver unit 910 can be regarded as the sending unit, that is, the transceiver unit 910 includes a receiving unit and a sending unit.
  • the transceiver unit may sometimes be called a transceiver, a transceiver, or a transceiver circuit.
  • the receiving unit may sometimes be called a receiver, receiver, or receiving circuit.
  • the transmitting unit may sometimes be called a transmitter, a transmitter, or a transmitting circuit.
  • transceiver unit 910 is configured to perform operations performed by the signal processing apparatus in the foregoing embodiment, and details are not described herein again.
  • the equipment shown in FIG. 10 can also be referred to.
  • the device includes a processor 1010, a data sending processor 1020, and a data receiving processor 1030.
  • the signal processing device in the foregoing embodiment may be the sending data processor 1020 and/or the receiving data processor 1030 in FIG. 10, and complete corresponding functions.
  • the signal processing device when the signal processing device is a radio frequency transceiver chip, the chip includes at least one processor, a memory, and a transceiver.
  • the memory stores instructions, and the processor is used to execute the signal processing device in the foregoing embodiment. The specific operations performed will not be repeated here.
  • the signal processing method of the present application can be applied to the signal processing device in any of the above-mentioned embodiments of FIG. 3, FIG. 4, FIG. 6 and FIG. 7, and the signal processing method is specifically executed by the controller.
  • an embodiment of the signal processing method in this application includes:
  • the controller obtains a first local oscillator signal.
  • the controller can obtain the first local oscillator signal from the phase-locked loop.
  • the first local oscillator signal refer to the related description in the embodiment shown in FIG. 3, which will not be repeated here.
  • the controller outputs a control signal to the local oscillator signal link according to the first local oscillator signal, and controls the local oscillator signal link to be turned on or off through the control signal.
  • the local oscillator signal link is used to obtain the first local oscillator signal and perform frequency division processing on the first local oscillator signal to generate the second local oscillator signal.
  • the specific method for the controller to output the control signal can be referred to the above-mentioned Figure 3 The relevant description in the illustrated embodiment will not be repeated here.
  • the controller can also obtain the first local oscillator signal from the PLL. Signal and control the opening or closing of the local oscillator signal link according to the first local oscillator signal. Therefore, in this application, the first local oscillator signal is combined with the first local oscillator signal to control the opening or closing of the local oscillator signal link.
  • the phase of the second local oscillator signal output by the circuit is controllable when the circuit is re-powered, so that the phase of the second local oscillator signal output by the local oscillator signal link during the switch state switching process is more stable.
  • the controller outputting the control signal to the local oscillator signal link according to the first local oscillator signal includes:
  • the controller generates a trigger signal according to the first local oscillator signal, and the period of the trigger signal is an integer multiple of the clock period of the second local oscillator signal;
  • the controller outputs a control signal to the local oscillator signal link according to the trigger signal.
  • the controller generating the trigger signal according to the first local oscillator signal includes:
  • the controller performs frequency division processing on the first local oscillator signal to generate a trigger signal, and the frequency division ratio of the controller is an integer multiple of the frequency division ratio of the local oscillator signal link.
  • the controller generating the trigger signal according to the first local oscillator signal includes:
  • the controller starts the cycle counting according to the first local oscillator signal, and generates a trigger signal at the end of each cycle counting cycle, and the cycle counting cycle is an integer multiple of the clock cycle of the second local oscillator signal.
  • the clock period of the second local oscillator signal is 2*N times the clock period of the first local oscillator signal, and N is an integer greater than or equal to 1.
  • the signal processing method further includes:
  • the controller obtains the time division duplex TDD signal
  • the controller outputting a control signal to the local oscillator signal link according to the first local oscillator signal includes:
  • the controller outputs the TDD control signal to the local oscillator signal link according to the first local oscillator signal and the TDD signal, and controls the local oscillator signal link to turn on or off through the TDD control signal.
  • the controller outputs every two adjacent TDD control signals. The signals are separated by an integer multiple of the clock period of the second local oscillator signal.
  • the processor mentioned in the embodiment of the present invention may be a central processing unit (Central Processing Unit, CPU), or may also be other general-purpose processors, digital signal processors (Digital Signal Processors, DSPs), and application-specific integrated circuits ( Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.
  • the general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like.
  • the memory mentioned in the embodiments of the present invention may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), and electrically available Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory.
  • the volatile memory may be a random access memory (Random Access Memory, RAM), which is used as an external cache.
  • RAM random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous dynamic random access memory
  • DDR SDRAM double data rate synchronous dynamic random access memory
  • Enhanced SDRAM, ESDRAM enhanced synchronous dynamic random access memory
  • Synchlink DRAM, SLDRAM synchronous connection dynamic random access memory
  • DR RAM Direct Rambus RAM
  • the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component
  • the memory storage module
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • each unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of this application essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , Including several instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, read-only memory), random access memory (RAM, random access memory), magnetic disk or optical disk and other media that can store program code .

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Abstract

本申请实施例提供了一种信号处理装置及信号处理方法，可以使得信号处理装置在开关状态切换的过程中其输出信号的相位更稳定。本申请中的信号处理装置包括：锁相环路、本振信号链路以及控制器，锁相环路的输出端分别与本振信号链路的第一输入端以及控制器的输入端相连，控制器的输出端与本振信号链路的第二输入端相连；锁相环路用于输出第一本振信号至本振信号链路以及控制器，本振信号链路用于对第一本振信号进行分频处理生成第二本振信号，控制器用于根据第一本振信号输出控制信号至本振信号链路，控制信号用于控制本振信号链路开启或关闭。

Description

一种信号处理装置及信号处理方法 技术领域
本申请涉及通信领域，尤其涉及一种信号处理装置及信号处理方法。
背景技术
在目前的射频收发芯片设计中带分频器的本振信号链路(LO Buffer Chain)一般是常开的，这会导致射频收发芯片消耗额外的功耗。
为此需要为本振信号链路设置开关切换，然而本振信号链路中的分频器每次上电启动后存在相位随机的问题，例如，若本振信号链路一直处于开启状态，那么该本振信号链路输出信号的相位是连续的，而若本振信号链路由关闭到打开，即重新上电，那么该本振信号链路输出信号的相位相对于相位连续的信号有可能出现大幅度的相位翻转。
因此本振信号链路在开关状态切换的过程中存在输出信号的相位不稳定的问题。
发明内容
本申请实施例提供了一种信号处理装置及信号处理方法，可以使得信号处理装置在开关状态切换的过程中其输出信号的相位更稳定。
有鉴于此，本申请第一方面提供一种信号处理装置，可以包括：
锁相环路(Phase Locked Loop，PLL)、本振信号链路以及控制器，PLL的输出端分别与本振信号链路的第一输入端以及控制器的输入端相连，控制器的输出端与本振信号链路的第二输入端相连；PLL用于输出第一本振信号至本振信号链路以及控制器，本振信号链路用于对第一本振信号进行分频处理生成第二本振信号，控制器用于根据第一本振信号输出控制信号至本振信号链路，控制信号用于控制本振信号链路开启或关闭。
需要说明的是，信号处理装置中支持的本振信号链路的数量可以是一个也可以是多个，控制器输出的控制信号可以控制多个本振信号链路开启或关闭。
需要说明的是，PLL可以与本振信号链路以及控制器可以是直接相连，也可以是通过其他电路或模块与本振信号链路以及控制器相连，同理，控制器可以与本振信号链路直接相连，也可以是通过其他电路或模块与本振信号链路相连，具体此处不做限定。
需要说明的是，本申请中的信号处理装置具体可以是射频收发芯片，除此之外，也可以是终端设备或者基站。
在本实施方式中，由于本振信号链路用于对来自PLL的第一本振信号做分频处理得到第二本振信号，而控制器也可以获取来自PLL的第一本振信号并根据该第一本振信号控制本振信号链路的开启或关闭，因此本申请中结合第一本振信号来控制本振信号链路的开启或关闭，可以使得在本振信号链路重新上电时其输出的第二本振信号的相位是可控的，那么也就使得该本振信号链路在开关状态切换的过程中输出的第二本振信号的相位更稳定。
可选的，在一些可能的实施方式中，
控制器包括计数单元和控制单元，其中，计数单元的输入端与PLL的输出端相连，计 数单元的输出端与控制单元的输入端相连，控制单元的输出端与本振信号链路的第二输入端相连；计数单元用于获取第一本振信号，并根据第一本振信号输出触发信号至控制单元，触发信号的周期是第二本振信号的时钟周期的整数倍，控制单元用于根据触发信号输出控制信号至本振信号链路。
在本实施方式中，提供了一种控制器的内部结构组成以及处理逻辑，即控制器包括计数单元和控制单元，通过计数单元和控制单元的配合实现结合第一本振信号来控制本振信号链路的开启或关闭，该控制器的结构和处理逻辑简单易行，提高了本方案的可实现性。
可选的，在一些可能的实施方式中，
计数单元包括第一分频器，控制单元包括第一触发器DFF，第一分频器的分频比是本振信号链路的分频比的整数倍。
在本实施方式中，列举了一种用于具体实现上述计数单元和控制单元的电子器件，即第一分频器和第一DFF，提高了本方案的实用性。
可选的，在一些可能的实施方式中，
计数单元包括循环计数器，控制单元包括第二DFF，循环计数器根据第一本振信号开启循环计数，并在每个循环计数的周期结束时输出触发信号至第二DFF，循环计数的周期为第二本振信号的时钟周期的整数倍。
在本实施方式中，列举了另一种用于具体实现上述计数单元和控制单元的电子器件，即循环计数器和第二DFF，提高了本方案的扩展性。
可选的，在一些可能的实施方式中，
第二本振信号的时钟周期为第一本振信号的时钟周期的2*N倍，N为大于或等于1的整数。
在本实施方式中，本振信号链路具体可以是对第一本振信号进行偶数分频以得到第二本振信号，实现方式更容易，当然本振信号链路也可以是对第一本振信号进行奇数分频以得到第二本振信号，具体此处不做限定。
可选的，在一些可能的实施方式中，
本振信号链路包括至少一个缓冲器和第二分频器，缓冲器的第一输入端与PLL的输出端相连，缓冲器的输出端与第二分频器的第一输入端相连，控制器的输出端与缓冲器的第二输入端和/或第二分频器的第二输入端相连；缓冲器用于获取第一本振信号以及控制信号，若控制信号用于控制本振信号链路开启，则缓冲器传输第一本振信号至第二分频器，若控制信号用于控制本振信号链路关闭，则缓冲器锁定第一本振信号，并将锁定后的第一本振信号传输至第二分频器；第二分频器用于对第一本振信号进行分频处理生成第二本振信号。
在本实施方式中，提供了本振信号链路的组成结构以及处理逻辑，完善了本方案的电路结构，进一步提高了本方案的可实现性。
可选的，在一些可能的实施方式中，
控制器还用于获取时分双工TDD信号，控制器用于根据第一本振信号输出控制信号至本振信号链路包括：控制器根据第一本振信号以及TDD信号输出TDD控制信号至本振信号链路，TDD控制信号用于控制本振信号链路开启或关闭，控制器输出的每相邻两个相同的 TDD控制信号之间相隔整数倍个第二本振信号的时钟周期。
在本实施方式中，提供了一种具体的应用场景，即本振信号链路随TDD信号切换的过程中，可以通过TDD控制信号来控制本振信号链路开启或关闭，在本振信号链路由开启切换到关闭状态后会锁定第二本振信号的相位状态，TDD控制信号的高低电平分别对应本振信号链路开启和关闭，并且相位连续控制器输出的每相邻两个相同的TDD控制信号之间相隔整数倍个第二本振信号的时钟周期，由于第二本振信号的时序为1010，每个时序的相位状态对应一个时钟周期，每隔两个第二本振信号的时钟周期该第二本振信号的的相位相同，那么本振信号链路由关闭到开启经过了整数倍个第二本振信号的时钟周期，本振信号链路在开启状态的相位是连续的。
本申请第二方面提供了一种信号处理方法，可以包括：
控制器获取来自PLL的第一本振信号；
控制器根据第一本振信号输出控制信号至本振信号链路，并通过控制信号控制本振信号链路开启或关闭，本振信号链路用于获取来自PLL的第一本振信号并对第一本振信号进行分频处理生成第二本振信号。
可选的，在一些可能的实施方式中，
控制器根据第一本振信号输出控制信号至本振信号链路包括：
控制器根据第一本振信号生成触发信号，触发信号的周期为第二本振信号的时钟周期的整数倍；
控制器根据触发信号输出控制信号至本振信号链路。
可选的，在一些可能的实施方式中，
控制器根据第一本振信号生成触发信号包括：
控制器对第一本振信号进行分频处理生成触发信号，控制器的分频比是本振信号链路的分频比的整数倍。
控制器根据第一本振信号生成触发信号包括：
控制器根据第一本振信号开启循环计数，并在每个循环计数的周期结束时生成触发信号，循环计数的周期为第二本振信号的时钟周期的整数倍。
可选的，在一些可能的实施方式中，
第二本振信号的时钟周期为第一本振信号的时钟周期的2*N倍，N为大于或等于1的整数。
可选的，在一些可能的实施方式中，方法还包括：
控制器获取时分双工TDD信号；
控制器根据第一本振信号输出控制信号至本振信号链路包括：
控制器根据第一本振信号以及TDD信号输出TDD控制信号至本振信号链路，并通过TDD控制信号控制本振信号链路开启或关闭，控制器输出的每相邻两个相同的TDD控制信号之间相隔整数倍个第二本振信号的时钟周期。
本申请实施例提供的技术方案中，由于本振信号链路用于对来自PLL的第一本振信号做分频处理得到第二本振信号，而控制器也可以获取来自PLL的第一本振信号并根据该第 一本振信号控制本振信号链路的开启或关闭，因此本申请中结合第一本振信号来控制本振信号链路的开启或关闭，可以使得在本振信号链路重新上电时其输出的第二本振信号的相位是可控的，那么也就使得该本振信号链路在开关状态切换的过程中输出的第二本振信号的相位更稳定。
附图说明
图1为本申请所应用的系统场景示意图；
图2为本振信号的时序示意图；
图3为本申请中信号处理装置的一种结构示意图；
图4为本申请中信号处理装置的另一种结构示意图；
图5为与本申请中信号处理装置相关的信号时序示意图；
图6为本申请中信号处理装置的另一种结构示意图；
图7为本申请中信号处理装置的另一种结构示意图；
图8为本申请中信号处理装置的另一种结构示意图；
图9为本申请中信号处理装置为终端或基站时的一种结构示意图；
图10为本申请中信号处理装置为终端或基站时的另一种结构示意图；
图11为本申请中信号处理方法的一个实施例示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例例如能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
本申请主要应用的系统架构或者场景如图1所示，包括接入网设备和终端设备。接入网设备和终端设备均可以工作在许可频段或免许可频段上的基站和终端设备。无论是许可频段，还是免许可频段，在本申请中，都可以包括一个或多个载波，许可频段和非许可频段进行载波聚合，可以包括许可频段包括的一个或多个载波与非许可频段包括的一个或多个载波进行载波聚合。
接入网设备可以是长期演进(long term evolution，LTE)系统或者授权辅助接入长期演进(authorized auxiliary access long-term evolution，LAA-LTE)系统中的演进 型基站(evolutional Node B，简称可以为eNB或e-NodeB)、宏基站、微基站(也称为“小基站”)、微微基站、接入站点(access point，AP)、传输站点(transmission point，TP)或新空口(new radio，NR)系统中的基站，例如，新一代基站(new generation Node B，gNodeB)等。
终端设备可称之为用户设备(user equipment，UE)、移动台(mobile station，MS)、移动终端(mobile terminal)、智能终端等，该终端设备可以经无线接入网(radio access network，RAN)与一个或多个核心网进行通信。例如，终端设备可以是移动电话(或称为“蜂窝”电话)、具有移动终端的计算机等，终端设备还可以是便携式、袖珍式、手持式、计算机内置的或者车载的移动装置以及未来NR网络中的终端设备，它们与无线接入网交换语音或数据。对终端设备的说明：本申请中，和基站可以进行数据通信的都可以看为终端设备，本申请中将以一般意义上的UE和基站来介绍。
目前应用于基站或UE的射频收发芯片中的本振信号链路一般是常开的，这会导致射频收发芯片消耗额外的功耗。
为了降低射频收发芯片的功耗，为此需要为本振信号链路设置开关切换，然而本振信号链路中的分频器每次上电启动后存在相位随机的问题。经本振信号链路处理后的本振信号的时序可以如图2所示，即该本振信号的时序为“1010…”，例如，若本振信号链路一直处于开启状态，那么该本振信号链路输出信号的相位是连续的，而若本振信号链路由关闭到打开，即重新上电，那么该本振信号链路输出信号的相位相对于相位连续的信号有可能出现大幅度的相位翻转，可能会出现本振信号链路关闭之前该本振信号的相位是“1”，而下一次本振信号链路开启后该本振信号的相位是“0”，也就有可能出现本振信号链路由开启到关闭再到在开启的过程中，本振信号链路输出的本振信号的相位不稳定的问题。
为了解决上述问题，本申请实施例提供了一种信号处理装置，下面进行介绍。
需要说明的是，本申请实施例中的信号处理装置具体可以应用于射频收发芯片中，该射频收发芯片可以应用于基站也可以应用于终端。
请参阅图3，图3为本申请中信号处理装置的一个实施例示意图，该信号处理装置包括锁相环路(phase locked loop，PLL)301，本振信号链路302以及控制器303，其中，锁相环路301的输出端分别与本振信号链路302的第一输入端以及控制器303的输入端相连，控制器303的的输出端与本振信号链路302的第二输入端相连。
下面对上述信号处理装置中各部件的功能进行描述：
锁相环路301用于输出第一本振信号至本振信号链路302以及控制器303；
本振信号链路302用于对第一本振信号进行分频处理生成第二本振信号；
控制器303用于根据第一本振信号输出控制信号至本振信号链路302，控制信号用于控制本振信号链路302开启或关闭。
需要说明的是，当控制信号为高电平时，本振信号链路302开启并正常工作。当控制信号为低电平时，本振信号链路302关闭，具体地，本振信号链路302锁死当前输入的第一本振信号，例如将该第一本振信号拉高或拉低，那么本振信号链路302输出的第二本振信号维持本振信号链路302关闭前的状态，在本振信号链路302关闭时是没有动态功耗的， 可以有效的降低该信号处理装置的整体功耗。
本申请实施例提供的技术方案中，由于本振信号链路用于对来自PLL的第一本振信号做分频处理得到第二本振信号，而控制器也可以获取来自PLL的第一本振信号并根据该第一本振信号控制本振信号链路的开启或关闭，因此本申请中结合第一本振信号来控制本振信号链路的开启或关闭，可以使得在本振信号链路重新上电时其输出的第二本振信号的相位是可控的，那么也就使得该本振信号链路在开关状态切换的过程中输出的第二本振信号的相位更稳定。
下面结合一种具体的应用场景对本申请中的信号处理装置进行进一步的介绍：
在该应用场景中，需要使得本振信号链路随TDD信号切换，例如TDD信号拉高，则本振信号链路开启，TDD信号拉低，则本振信号链路关闭。并且需要保证本振信号链路随TDD信号切换的过程中，本振信号链路输出信号的相位连续。可以看出，随着TDD信号的引入不再是只根据第一本振信号生成的控制信号来控制本振信号链路的开启或关闭，下面进行详细说明。
请参阅图4，控制器303除了获取第一本振信号外还可以获取时分双工(time-division duplex，TDD)信号，并根据第一本振信号以及TDD信号输出TDD控制信号至本振信号链路302，TDD控制信号用于控制本振信号链路302开启或关闭，本实施例中的TDD控制信号相当于图3所示实施例中的控制信号，此外，控制器303输出的每相邻两个相同的TDD控制信号之间相隔整数倍个第二本振信号的时钟周期。
本振信号链路302可以包括至少一个缓冲器3021以及分频器3022，缓冲器3021的第一输入端与锁相环路301的输出端相连，缓冲器3021的输出端与分频器3022的第一输入端相连，控制器303的输出端即可以与缓冲器3021的第二输入端相连，也可以与分频器3022的第二输入端相连，又或者同时与缓冲器3021的第二输入端及分频器3022的第二输入端相连；
如果控制器303的输出端与缓冲器3021的第二输入端相连，那么缓冲器3021除了用于获取第一本振信号外还可以获取TDD控制信号，若TDD控制信号用于控制本振信号链路302关闭，则缓冲器3021锁定第一本振信号，并将锁定后的第一本振信号传输至分频器3022，若TDD控制信号用于控制本振信号链路302开启，则缓冲器3021恢复第一本振信号，并将恢复后的第一本振信号传输至分频器3022；如果控制器303的输出端没有与缓冲器3021的第二输入端相连，而是与分频器3022的第二输入端相连，那么TDD控制信号直接控制分频器的开启或关闭。
分频器3022用于根据第一本振信号生成第二本振信号，具体地，分频器3022对第一本振信号做分频处理，通常情况下，该分频器3022的分频比为2或者2的倍数，即可以使得第二本振信号的频率为第一本振信号的频率的1/2*N，N为大于或等于1的整数，第二本振信号的时钟周期为第一本振信号的时钟周期的2*N倍。当然在一些应用场景中，该分频器3022的分频比也可以是其他数值，例如分频比为3、5、7等，具体此处不做限定。
基于上述描述，下面结合以上各信号的时序图对本申请的原理进行介绍：
请参阅图5，以第二本振信号的时钟周期为第一本振信号的时钟周期的2倍为例。其 中，“连续的第一本振信号”表示第一本振信号的状态连续不随TDD控制信号拉高或拉低而改变，“连续的第二本振信号”同理；“变化的第一本振信号”表示当TDD控制信号拉高时第一本振信号的状态连续，当TDD控制信号拉低时第一本振信号的状态锁定，“变化的第二本振信号”同理。从图中可以看出，变化的第二本振信号是随着TDD控制信号的变化而变化的，并且TDD控制信号何时变化是由TDD信号的变化决定的，也就是说虽然TDD信号拉低了，但是不会立即锁定第二本振信号的状态，而是当TDD控制信号拉低时锁定第二本振信号的状态，这是由于TDD信号的上升沿(或下降沿)与第二本振信号的上升沿(或下降沿)可能没有对齐，因此需要使得TDD控制信号的上升沿(或下降沿)与第二本振信号的上升沿(或下降沿)对齐，即保证第二本振信号在上升沿(或下降沿)的时刻进入锁定状态，随后在另一个上升沿(或下降沿)的时刻从锁定状态中恢复，这样一来第二本振信号从锁定状态恢复后的相位与第二本振信号锁定前的相位相同。由于第二本振信号的时序为“1010…”,即每隔两个时钟周期相位相同，那么就需要相邻的两个状态相同(同为拉高)的TDD控制信号之间相隔整数倍个第二本振信号的时钟周期，以实现第二本振信号从锁定状态恢复后的相位与第二本振信号锁定前的相位相同，通过对比“连续的第二本振信号”和“变化的第二本振信号”可以看出在本振信号链路关闭的时段是经过了整数倍个第二本振信号的时钟周期。
可以理解的是，为了实现上述效果，控制器303需要在检测到TDD信号变化(拉高或拉低)后，在与第二本振信号的时钟周期匹配的时间点改变TDD控制信号(拉高或拉低)。本申请具体提供了多种控制器的实现方式，下面分别进行介绍：
第一种实现方式：
请参阅图6，控制器303包括第一分频器3031和第一触发器(delay flip-flop，DFF)3032，其中，第一分频器3031的输入端与锁相环路301的输出端相连，第一分频器3031的输出端与第一触发器3032的输入端相连，第一触发器3032的输出端与本振信号链路302的输入端相连。
第一分频器3031可以获取第一本振信号并根据第一本振信号输出触发信号至第一触发器3032，具体地，该第一分频器3031与本振信号链路302中的分频器3022的作用类似，并且该触发信号的时钟周期是第二本振信号的时钟周期的整数倍，另外该触发信号的时序与第二本振信号的时序对齐，例如，若该触发信号的时钟周期与第二本振信号的时钟周期相同，该触发信号的时序图可以参照图5中“连续的第二本振信号”的时序图。
第一触发器3032可以获取TDD信号并根据TDD信号的变化以及触发信号输出TDD控制信号至本振信号链路302，具体地，第一触发器3032对获取到的TDD信号进行检测，若检测到TDD信号变化(例如拉低)，进一步在触发信号的下一个上升沿(或下降沿)的时刻输出低电平的TDD控制信号至本振信号链路302，以控制本振信号链路302关闭，同理若第一触发器3032检测到TDD信号拉高，进一步在触发信号的下一个上升沿(或下降沿)的时刻输出高电平的TDD控制信号至本振信号链路302，以控制本振信号链路302开启，由于触发信号的时序与第二本振信号的时序对齐且时钟周期相同，因此可以实现第一触发器3032输出的相邻的两个状态相同(同为拉高)的TDD控制信号之间相隔整数倍个第二本振 信号的时钟周期。
第二种实现方式：
请参阅图7，控制器303包括循环计数器3033和第二触发器3034，其中，循环计数器3033的输入端与锁相环路301的输出端相连，循环计数器3033的输出端与第二触发器3034的输入端相连，第二触发器3034的输出端与本振信号链路302的输入端相连。需要说明的是，循环计数器3033和第二触发器3034都可以获取TDD信号。
若循环计数器3033检测到TDD信号拉低，则在第一本振信号下一个时钟周期的上升沿(或下降沿)开始循环计数，并向第二触发器3034发送触发信号，第二触发器3034收到该触发信号后输出拉低的TDD控制信号至本振信号链路302；循环计数器3033一直循环计数直到检测到TDD信号拉高，之后需要再完成一个完整周期的循环计数再向第二触发器3034发触发信号，第二触发器3034收到该触发信号后输出拉高的TDD控制信号至本振信号链路302。
需要说明的是，在循环计数器3033开始计数后，在每个循环计数的周期结束时输出触发信号至第二触发器3034，其中该循环计数的周期是第二本振信号的时钟周期的整数倍。第二本振信号的相位每改变一次循环计数器就在原计数的基础上加1，若第二本振信号的时钟周期为T，那么每T/2的时长第二本振信号的相位改变一次，也就是每T/2的时长循环计数器计数1次，因此循环计数器每计数2次对应第二本振信号的一个时钟周期。例如，若将循环计数的周期设为2，则循环计数器按照“121212…”的计数值循环计数，若将循环计数的周期设为4，则循环计数器按照“12341234…”的计数值循环计数。
在循环计数器3033开始计数后，且第二触发器3034未检测到TDD信号拉高之前，第二触发器3034并不根据触发信号输出TDD控制信号。直到若第二触发器3034检测到TDD信号拉高，第二触发器3034在收到下一个触发信号后输出TDD控制信号至本振信号链路302。由于预先设置的循环计数的周期是第二本振信号的时钟周期的整数倍，因此可以实现第二触发器3034输出的相邻的两个状态相同(同为拉高)的TDD控制信号之间相隔整数倍个第二本振信号的时钟周期。
从以上两种实现方式可以看出，第二种实现方式相对于第一种实现方式的主要区别在于用循环计数器3033代替了第一分频器3031，第一种实现方式中的第一分频器3031需要时刻保持工作，而第二种实现方式中的循环计数器3033只在TDD信号拉低期间工作，在一定程度上，第二种实现方式相对于第一种实现方式所消耗的功耗更低。
需要说明的是，基于以上两种实现方式的变形都在本方案的范围内，例如，用其他具有计数功能的计数单元代替上述的第一分频器3031和循环计数器3033，用其他具有控制逻辑的控制单元代替上述的第一触发器3032和第二触发器3034等。
本申请实施例提供的技术方案中，本振信号链路可以根据来自PLL的第一本振信号生成第二本振信号，其中，第二本振信号的时钟周期为第一本振信号的时钟周期的2*N倍，N为大于或等于1的整数，在本振信号链路随TDD信号切换的过程中，可以通过TDD控制信号来控制本振信号链路开启或关闭，在本振信号链路由开启切换到关闭状态后会锁定第二本振信号的相位状态，TDD控制信号的高低电平分别对应本振信号链路开启和关闭，并且 控制器输出的每相邻两个相同的TDD控制信号之间相隔整数倍个第二本振信号的时钟周期，由于第二本振信号的时序为1010，每个时序的相位状态对应一个时钟周期，每隔两个第二本振信号的时钟周期该第二本振信号的的相位相同，那么本振信号链路由关闭到开启经过了整数倍个第二本振信号的时钟周期，本振信号链路在开启状态的相位是连续的，因此只需要增加控制器即可实现在在本振信号链路随TDD信号切换的过程中相位连续，电路复杂度较低，有效地节省了成本和功耗。
需要说明的是，本申请中的信号处理装置除了可以应用于上述的本振信号链路随TDD信号切换的场景外，还可以应用于其他场景，下面列举其中一种扩展场景。
请参阅图8，图8所示的实施例与上述几个实施例的主要区别有如下几个方面：第一，不同于上述实施例中锁相环路301输出第一本振信号，本实施例中锁相环路301输出的信号也可以是时钟信号(如图8中所示的第一时钟信号)；第二，不同于上述实施例中信号处理装置只包括一个本振信号链路(当然也可以包括多个)，本实施例中信号处理装置也可以支持多条信号链路(如图8所示的第一信号链路和第二信号链路)；第三，不同于上述实施例中控制器303获取TDD信号输出TDD控制信号，本实施例中控制器303也可以获取开关信号并输出开关控制信号，通过该开关控制信号可以同样起到控制多条信号链路开关的作用，并且每条信号链路在随开关控制信号切换的过程中其输出的时钟信号相位连续。
需要说明的是，控制器303中的第一分频器3031和第一触发器3032的处理逻辑与上述图6所示实施例中控制器303的处理逻辑相似，此处不再赘述。此外，对于多个信号链路，每个信号链路中分频器的分频比可以相同也可以不同。如果每个信号链路中分频器的分频比相同，则控制器303中的第一分频器的分频比是每个信号链路中分频器的分频比的整数倍；如果每个信号链路中分频器的分频比不同，则控制器303中的第一分频器3031的分频比可以为每个信号链路中分频器的分频比的最小公倍数倍，例如，第一信号链路中分频器的分频比为2，第二信号链路中的分频比为3，那么控制器303中的第一分频器3031的分频比可以是6或者6的倍数。
本申请实施例还提供了一种信号处理装置，该信号处理装置可以是终端也可以是基站，该信号处理装置用于执行上述实施例中信号处理装置所执行的操作。
当信号处理装置为终端或基站时，图9示出了一种简化的终端或基站的结构示意图。如图9所示，终端或基站包括处理器、存储器、射频电路、天线以及输入输出装置。处理器主要用于对通信协议以及通信数据进行处理，以及对终端或基站进行控制，执行软件程序，处理软件程序的数据等。存储器主要用于存储软件程序和数据。射频电路主要用于基带信号与射频信号的转换以及对射频信号的处理。天线主要用于收发电磁波形式的射频信号。输入输出装置，例如触摸屏、显示屏，键盘等主要用于接收用户输入的数据以及对用户输出数据。需要说明的是，有些种类的终端设备可以不具有输入输出装置。
当终端或基站需要发送数据时，处理器对待发送的数据进行基带处理后，输出基带信号至射频电路，射频电路将基带信号进行射频处理后将射频信号通过天线以电磁波的形式向外发送。当有数据发送到终端或基站时，射频电路通过天线接收到射频信号，将射频信号转换为基带信号，并将基带信号输出至处理器，处理器将基带信号转换为数据并对该数 据进行处理。为便于说明，图9中仅示出了一个存储器和处理器。在实际的终端设备产品中，可以存在一个或多个处理器和一个或多个存储器。存储器也可以称为存储介质或者存储设备等。存储器可以是独立于处理器设置，也可以是与处理器集成在一起，本申请实施例对此不做限制。
在本申请实施例中，可以将具有收发功能的天线和射频电路视为终端设备的收发单元，将具有处理功能的处理器视为终端设备的处理单元。如图9所示，终端设备包括收发单元910和处理单元920。收发单元也可以称为收发器、收发机、收发装置等。处理单元也可以称为处理器，处理单板，处理模块、处理装置等。可选的，可以将收发单元910中用于实现接收功能的器件视为接收单元，将收发单元910中用于实现发送功能的器件视为发送单元，即收发单元910包括接收单元和发送单元。收发单元有时也可以称为收发机、收发器、或收发电路等。接收单元有时也可以称为接收机、接收器、或接收电路等。发送单元有时也可以称为发射机、发射器或者发射电路等。
应理解，收发单元910用于执行上述实施例中信号处理装置所执行的操作，具体此处不再赘述。
本实施例中的信号处理装置为终端或基站时，还可以参照图10所示的设备。在图10中，该设备包括处理器1010，发送数据处理器1020，接收数据处理器1030。上述实施例中的信号处理装置可以是图10中的发送数据处理器1020，和/或接收数据处理器1030，并完成相应的功能。
在另一种可能的设计中，当该信号处理装置为射频收发芯片时，该芯片包括至少一个处理器，存储器和收发器，存储器中存储有指令，处理器用于执上述实施例中信号处理装置所执行的操作，具体此处不再赘述。
上面对本申请中的信号处理装置进行了描述，此外，在上述信号处理装置的基础上本申请还提供了一种信号处理方法，下面进行介绍：
本申请的信号处理方法可应用于上述图3、图4、图6和图7任一实施例中的信号处理装置，该信号处理方法具体由控制器执行。
请参阅图11，本申请中信号处理方法的一个实施例包括：
1101、控制器获取第一本振信号。
本实施例中，控制器可以获取来自锁相环路的第一本振信号，关于第一本振信号的描述可以参照上述图3所示实施例中的相关描述，此处不再赘述。
1102、控制器根据第一本振信号输出控制信号至本振信号链路，并通过控制信号控制本振信号链路开启或关闭。
本实施例中，本振信号链路用于获取第一本振信号并对第一本振信号进行分频处理生成第二本振信号，控制器输出控制信号的具体方式可以参照上述图3所示实施例中的相关描述，此处不再赘述。
本申请实施例提供的技术方案中，由于本振信号链路用于对来自PLL的第一本振信号做分频处理得到第二本振信号，而控制器也可以获取来自PLL的第一本振信号并根据该第一本振信号控制本振信号链路的开启或关闭，因此本申请中结合第一本振信号来控制本振 信号链路的开启或关闭，可以使得在本振信号链路重新上电时其输出的第二本振信号的相位是可控的，那么也就使得该本振信号链路在开关状态切换的过程中输出的第二本振信号的相位更稳定。
可选地，控制器根据第一本振信号输出控制信号至本振信号链路包括：
控制器根据第一本振信号生成触发信号，触发信号的周期为第二本振信号的时钟周期的整数倍；
控制器根据触发信号输出控制信号至本振信号链路。
可选地，控制器根据第一本振信号生成触发信号包括：
控制器对第一本振信号进行分频处理生成触发信号，控制器的分频比是本振信号链路的分频比的整数倍。
可选地，控制器根据第一本振信号生成触发信号包括：
控制器根据第一本振信号开启循环计数，并在每个循环计数的周期结束时生成触发信号，循环计数的周期为第二本振信号的时钟周期的整数倍。
可选地，第二本振信号的时钟周期为第一本振信号的时钟周期的2*N倍，N为大于或等于1的整数。
可选地，该信号处理方法还包括：
控制器获取时分双工TDD信号；
控制器根据第一本振信号输出控制信号至本振信号链路包括：
控制器根据第一本振信号以及TDD信号输出TDD控制信号至本振信号链路，并通过TDD控制信号控制本振信号链路开启或关闭，控制器输出的每相邻两个相同的TDD控制信号之间相隔整数倍个第二本振信号的时钟周期。
应理解，本发明实施例中提及的处理器可以是中央处理单元(Central Processing Unit，CPU)，还可以是其他通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
还应理解，本发明实施例中提及的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synchlink DRAM，SLDRAM)和直接内存总线随机存取存储 器(Direct Rambus RAM，DR RAM)。
需要说明的是，当处理器为通用处理器、DSP、ASIC、FPGA或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件时，存储器(存储模块)集成在处理器中。
应注意，本文描述的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，read-only memory)、随机存取存储器(RAM，random access memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (13)

  1. 一种信号处理装置，其特征在于，包括：锁相环路PLL、本振信号链路以及控制器，所述PLL的输出端分别与所述本振信号链路的第一输入端以及所述控制器的输入端相连，所述控制器的输出端与所述本振信号链路的第二输入端相连；
    所述PLL用于输出第一本振信号至所述本振信号链路以及所述控制器；
    所述本振信号链路用于对所述第一本振信号进行分频处理生成第二本振信号；
    所述控制器用于根据所述第一本振信号输出控制信号至所述本振信号链路，所述控制信号用于控制所述本振信号链路开启或关闭。
  2. 根据权利要求1所述的信号处理装置，其特征在于，所述控制器包括计数单元和控制单元，其中，所述计数单元的输入端与所述PLL的输出端相连，所述计数单元的输出端与所述控制单元的输入端相连，所述控制单元的输出端与所述本振信号链路的第二输入端相连；
    所述计数单元用于获取所述第一本振信号，并根据所述第一本振信号输出触发信号至所述控制单元，所述触发信号的周期是所述第二本振信号的时钟周期的整数倍；
    所述控制单元用于根据所述触发信号输出所述控制信号至所述本振信号链路。
  3. 根据权利要求2所述的信号处理装置，其特征在于，所述计数单元包括第一分频器，所述控制单元包括第一触发器DFF，所述第一分频器的分频比是所述本振信号链路的分频比的整数倍。
  4. 根据权利要求2所述的信号处理装置，其特征在于，所述计数单元包括循环计数器，所述控制单元包括第二DFF，所述循环计数器根据所述第一本振信号开启循环计数，并在每个循环计数的周期结束时输出触发信号至所述第二DFF，所述循环计数的周期为所述第二本振信号的时钟周期的整数倍。
  5. 根据权利要求1所述的信号处理装置，其特征在于，所述第二本振信号的时钟周期为所述第一本振信号的时钟周期的2*N倍，所述N为大于或等于1的整数。
  6. 根据权利要求1所述的信号处理装置，其特征在于，所述本振信号链路包括至少一个缓冲器和第二分频器，所述缓冲器的第一输入端与所述PLL的输出端相连，所述缓冲器的输出端与所述第二分频器的第一输入端相连，所述控制器的输出端与所述缓冲器的第二输入端和/或所述第二分频器的第二输入端相连；
    所述缓冲器用于获取所述第一本振信号以及所述控制信号，若所述控制信号用于控制所述本振信号链路开启，则所述缓冲器传输所述第一本振信号至所述第二分频器，若所述控制信号用于控制所述本振信号链路关闭，则所述缓冲器锁定所述第一本振信号，并将锁定后的第一本振信号传输至所述第二分频器；
    所述第二分频器用于对所述第一本振信号进行分频处理生成第二本振信号。
  7. 根据权利要求1至6中任一项所述的信号处理装置，其特征在于，所述控制器还用于获取时分双工TDD信号，所述控制器用于根据所述第一本振信号输出控制信号至所述本振信号链路包括：
    所述控制器根据所述第一本振信号以及所述TDD信号输出TDD控制信号至所述本振信 号链路，所述TDD控制信号用于控制所述本振信号链路开启或关闭，所述控制器输出的每相邻两个相同的TDD控制信号之间相隔整数倍个所述第二本振信号的时钟周期。
  8. 一种信号处理方法，其特征在于，所述方法包括：
    控制器获取来自锁相环路PLL的第一本振信号；
    所述控制器根据所述第一本振信号输出控制信号至本振信号链路，并通过所述控制信号控制所述本振信号链路开启或关闭，所述本振信号链路用于获取来自所述PLL的所述第一本振信号并对所述第一本振信号进行分频处理生成第二本振信号。
  9. 根据权利要求8所述的方法，其特征在于，所述控制器根据所述第一本振信号输出控制信号至本振信号链路包括：
    所述控制器根据所述第一本振信号生成触发信号，所述触发信号的周期为所述第二本振信号的时钟周期的整数倍；
    所述控制器根据所述触发信号输出所述控制信号至所述本振信号链路。
  10. 根据权利要求9所述的方法，其特征在于，所述控制器根据所述第一本振信号生成触发信号包括：
    所述控制器对所述第一本振信号进行分频处理生成所述触发信号，所述控制器的分频比是所述本振信号链路的分频比的整数倍。
  11. 根据权利要求9所述的方法，其特征在于，所述控制器根据所述第一本振信号生成触发信号包括：
    所述控制器根据所述第一本振信号开启循环计数，并在每个循环计数的周期结束时生成触发信号，所述循环计数的周期为所述第二本振信号的时钟周期的整数倍。
  12. 根据权利要求8所述的方法，其特征在于，所述第二本振信号的时钟周期为所述第一本振信号的时钟周期的2*N倍，所述N为大于或等于1的整数。
  13. 根据权利要求8至12中任一项所述的方法，其特征在于，所述方法还包括：
    所述控制器获取时分双工TDD信号；
    所述控制器根据所述第一本振信号输出控制信号至本振信号链路包括：
    所述控制器根据所述第一本振信号以及所述TDD信号输出TDD控制信号至所述本振信号链路，并通过所述TDD控制信号控制所述本振信号链路开启或关闭，所述控制器输出的每相邻两个相同的TDD控制信号之间相隔整数倍个所述第二本振信号的时钟周期。
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