WO2020187043A1 - Unité de registre à décalage et son procédé d'attaque, circuit d'attaque de grille et dispositif d'affichage - Google Patents

Unité de registre à décalage et son procédé d'attaque, circuit d'attaque de grille et dispositif d'affichage Download PDF

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Publication number
WO2020187043A1
WO2020187043A1 PCT/CN2020/077995 CN2020077995W WO2020187043A1 WO 2020187043 A1 WO2020187043 A1 WO 2020187043A1 CN 2020077995 W CN2020077995 W CN 2020077995W WO 2020187043 A1 WO2020187043 A1 WO 2020187043A1
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WIPO (PCT)
Prior art keywords
node
transistor
noise reduction
circuit
control
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PCT/CN2020/077995
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English (en)
Chinese (zh)
Inventor
谷晓芳
马小叶
邵贤杰
马睿
张东徽
杜瑞芳
杨通
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Publication of WO2020187043A1 publication Critical patent/WO2020187043A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the embodiments of the present disclosure relate to a shift register unit and a driving method thereof, a gate driving circuit and a display device.
  • a pixel array of a liquid crystal display panel usually includes a plurality of rows of gate lines and a plurality of columns of data lines intersecting the plurality of rows of gate lines.
  • the gate line can be driven by a gate drive circuit.
  • the gate drive circuit can be implemented by a bonded integrated drive circuit.
  • the gate drive circuit can also be directly integrated on the thin film transistor array substrate to form GOA (Gate-driver On Array) to perform the gate line drive.
  • a GOA including multiple cascaded shift register units can be used to provide switching state voltage signals for multiple rows of gate lines of a pixel array, so as to control multiple rows of gate lines to turn on sequentially, and at the same time from the data lines to the pixel array
  • the pixel unit of the corresponding row provides a data signal to form the gray voltage required by each gray scale of the displayed image in each pixel unit, and then display a frame of image.
  • Current display panels increasingly use GOA technology to drive gate lines. GOA technology helps realize the narrow bezel design of the display panel and can reduce production costs.
  • At least one embodiment of the present disclosure provides a shift register unit including an input circuit, an output circuit, a first node noise reduction circuit, and a noise reduction reset circuit; wherein the input circuit is connected to the first node and is configured to respond to the input The control signal writes an input signal into the first node to control the level of the first node; the output circuit is connected to the first node and the output terminal, and is configured to receive a clock signal and output a clock signal to the first node.
  • the clock signal is output to the output terminal under the control of the level of the node;
  • the first node noise reduction circuit is respectively connected to the first node, the first noise reduction node, and the second noise reduction node, and is configured to The noise reduction is performed on the first node under the control of the level of the first noise reduction node or the level of the second noise reduction node;
  • the noise reduction reset circuit and the first noise reduction node It is connected to the second noise reduction node, and is configured to reset the first noise reduction node and the second noise reduction node in response to a first reset signal.
  • the shift register unit provided by at least one embodiment of the present disclosure further includes a first noise reduction circuit, a second noise reduction circuit, a first control circuit, and a second control circuit; wherein the first noise reduction circuit is connected to the The first node, the first noise reduction node, and the first control node are connected, and are configured to perform control on the first noise reduction node under the control of the level of the first node and the first control node.
  • the level of the node is controlled;
  • the second noise reduction circuit is respectively connected to the first node, the second noise reduction node and the second control node, and is configured to be at the level of the first node and the first node Under the control of the level of the second control node, the level of the second noise reduction node is controlled;
  • the first control circuit is connected to the first node and the first control node, and is configured to Under the control of the level of the first node, the level of the first control node is controlled;
  • the second control circuit is connected to the first node and the second control node, and is configured to Under the control of the level of a node, the level of the second control node is controlled.
  • the shift register unit provided by at least one embodiment of the present disclosure further includes an output reset circuit, wherein the output reset circuit is connected to the output terminal, and is configured to perform an operation on the output terminal in response to the first reset signal. Reset.
  • the output reset circuit is further connected to the first node, and is configured to reset the first node in response to the first reset signal.
  • the shift register unit provided by at least one embodiment of the present disclosure further includes a first node reset circuit, wherein the first node reset circuit is connected to the first node and is configured to respond to the second reset signal.
  • the first node is reset.
  • the shift register unit provided by at least one embodiment of the present disclosure further includes an output noise reduction circuit, wherein the output noise reduction circuit is respectively connected to the first noise reduction node, the second noise reduction node and the output noise reduction circuit. Terminal connection, configured to perform noise reduction on the output terminal under the control of the level of the first noise reduction node or the level of the second noise reduction node.
  • the noise reduction reset circuit includes a first transistor and a second transistor; the gate of the first transistor is connected to the first reset terminal to receive the For the first reset signal, the first electrode of the first transistor is connected to the first noise reduction node, the second electrode of the first transistor is connected to the first voltage terminal; the gate of the second transistor is connected to the The first reset terminal is connected to receive the first reset signal, the first electrode of the second transistor is connected to the second noise reduction node, and the second electrode of the second transistor is connected to the first voltage terminal connection.
  • the input circuit includes a third transistor; the gate and input terminal of the third transistor are connected to receive the input signal as the input control signal , The first pole of the third transistor is connected to the input terminal to receive the input signal, and the second pole of the third transistor is connected to the first node.
  • the output circuit includes a fourth transistor and a first capacitor; the gate of the fourth transistor is connected to the first node, and the fourth transistor The first pole of the transistor is connected to the clock signal terminal to receive the clock signal, the second pole of the fourth transistor is connected to the output terminal; the first pole of the first capacitor is connected to the first node, The second pole of the first capacitor is connected to the output terminal.
  • the first node noise reduction circuit includes a fifth transistor and a sixth transistor; the gate of the fifth transistor and the first noise reduction node Connected, the first electrode of the fifth transistor is connected to the first node, and the second electrode of the fifth transistor is connected to the first voltage terminal; the gate of the sixth transistor is connected to the second noise reduction The node is connected, the first electrode of the sixth transistor is connected to the first node, and the second electrode of the sixth transistor is connected to the first voltage terminal.
  • the first noise reduction circuit includes a seventh transistor and an eighth transistor, and the gate of the seventh transistor is connected to the first control node, The first electrode of the seventh transistor is connected to the second voltage terminal, the second electrode of the seventh transistor is connected to the first noise reduction node, and the gate of the eighth transistor is connected to the first node , The first pole of the eighth transistor is connected to the first noise reduction node, and the second pole of the eighth transistor is connected to the first voltage terminal;
  • the first control circuit includes a ninth transistor and a tenth transistor , The gate and the first electrode of the ninth transistor are connected to each other and the second voltage terminal, the second electrode of the ninth transistor is connected to the first control node, and the gate of the tenth transistor is The electrode is connected to the first node, the first electrode of the tenth transistor is connected to the first control node, and the second electrode of the tenth transistor is connected to the first voltage terminal.
  • the second noise reduction circuit includes an eleventh transistor and a twelfth transistor, and the gate of the eleventh transistor and the second control Node connection, the first electrode of the eleventh transistor is connected to the third voltage terminal, the second electrode of the eleventh transistor is connected to the second noise reduction node, and the gate of the twelfth transistor is connected to The first node is connected, the first electrode of the twelfth transistor is connected to the second noise reduction node, and the second electrode of the twelfth transistor is connected to the first voltage terminal; the second control circuit It includes a thirteenth transistor and a fourteenth transistor. The gate and the first electrode of the thirteenth transistor are connected to each other and to the third voltage terminal.
  • the second electrode of the thirteenth transistor is connected to the third voltage terminal.
  • Two control nodes are connected, the gate of the fourteenth transistor is connected to the first node, the first pole of the fourteenth transistor is connected to the second control node, and the second of the fourteenth transistor is connected The pole is connected to the first voltage terminal.
  • the output reset circuit includes a fifteenth transistor; the gate of the fifteenth transistor is connected to the first reset terminal to receive the first reset For signal, the first pole of the fifteenth transistor is connected to the output terminal, and the second pole of the fifteenth transistor is connected to the first voltage terminal.
  • the output reset circuit includes a sixteenth transistor; the gate of the sixteenth transistor is connected to the first reset terminal to receive the first reset Signal, the first pole of the sixteenth transistor is connected to the first node, and the second pole of the sixteenth transistor is connected to the first voltage terminal.
  • the first node reset circuit includes a seventeenth transistor; the gate of the seventeenth transistor is connected to the second reset terminal to receive the first node Two reset signals, the first pole of the seventeenth transistor is connected to the first node, and the second pole of the seventeenth transistor is connected to the first voltage terminal.
  • the output noise reduction circuit includes an eighteenth transistor and a nineteenth transistor; the gate of the eighteenth transistor and the first noise reduction circuit Node connection, the first pole of the eighteenth transistor is connected to the output terminal, the second pole of the eighteenth transistor is connected to the first voltage terminal; the gate of the nineteenth transistor is connected to the first voltage terminal; Two noise reduction nodes are connected, the first pole of the nineteenth transistor is connected to the output terminal, and the second pole of the nineteenth transistor is connected to the first voltage terminal.
  • At least one embodiment of the present disclosure further provides a method for driving a shift register unit according to any one of the embodiments of the present disclosure, including: in a noise reduction reset stage, making the noise reduction reset circuit respond to the first reset The signal resets the first noise reduction node and the second noise reduction node; in the input phase, causes the input circuit to write the input signal to the first node in response to the input control signal; and In the output phase, the output circuit is made to output the clock signal to the output terminal under the control of the level of the first node.
  • At least one embodiment of the present disclosure further provides a gate driving circuit including a plurality of cascaded shift register units according to any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure further provides a display device including the gate driving circuit described in any embodiment of the present disclosure.
  • FIG. 1 is a schematic block diagram of a shift register unit provided by some embodiments of the present disclosure
  • FIG. 2 is a schematic block diagram of another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 3 is a schematic block diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 4 is a schematic block diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 5 is a circuit diagram of a specific implementation example of the shift register unit shown in FIG. 3;
  • FIG. 6 is a circuit diagram of a specific implementation example of the shift register unit shown in FIG. 4;
  • 7 and 8 are signal timing diagrams of a shift register unit provided by some embodiments of the present disclosure.
  • FIG. 9 is a schematic block diagram of a gate driving circuit provided by some embodiments of the present disclosure.
  • FIG. 10 is a schematic block diagram of a display device provided by some embodiments of the present disclosure.
  • two sets of noise reduction control circuits can be used to alternately control the shift.
  • Each noise reduction circuit in the bit register unit reduces noise on each node (for example, a pull-up node) and an output terminal in the shift register unit.
  • two sets of noise reduction control circuits respectively receive alternating DC high-level signals and DC low-level signals, and the signals received by the two sets of noise reduction control circuits are mutually inverted signals.
  • the first group of noise reduction control circuits receives high-level signals
  • the second group of noise reduction control circuits receives low-level signals
  • the noise reduction circuits in the shift register unit control the noise reduction in the first group.
  • the second group of noise reduction control circuits receives high-level signals
  • the noise reduction circuits in the shift register unit are in the first Work under the control of two groups of noise reduction control circuits.
  • the switching period of the two sets of noise reduction control circuits is usually set to an integer multiple of the display screen refresh period, and the switching time point is set in the blanking stage of the display, that is, after the end of the previous frame or the next The frame shows the stage before the start of the picture.
  • the charge in the first group of noise reduction control circuits cannot be released directly and quickly through the transistors, but can only leak current through the transistors. The way is slowly released. Therefore, when the clock signal corresponding to the next frame of the display screen comes, the charge in the first group of noise reduction control circuits may not be completely discharged, which causes the first group of noise reduction control circuits to continue to reduce the noise in the shift register unit.
  • the noise circuit has an impact.
  • the noise reduction circuits in the shift register unit increase the discharge current of each node (for example, the pull-up node), thereby doubling the charge of each node.
  • the pull-up node cannot be fully charged when the clock signal comes due to the double discharge current of the pull-up node noise reduction circuit, resulting in the pull-up node.
  • the level of the pull node is low, and then under the control of the level of the pull node, the signal amplitude output by the output terminal is low, and the output signal is even further attenuated to no output, resulting in abnormal display or scan screen unpleasant sight.
  • At least one embodiment of the present disclosure provides a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • the shift register unit can switch to an invalid voltage during the switching process of two sets of noise reduction control circuits.
  • the charge in the level (for example, low level) noise reduction control circuit is released, thereby reducing or avoiding adverse effects on the amplitude of the output signal, ensuring the normal display of the picture, and improving the stability of the product including the shift register unit Sex and reliability.
  • At least one embodiment of the present disclosure provides a shift register unit.
  • a plurality of the shift register units can be cascaded to form a gate driving circuit to sequentially output a plurality of scanning signals.
  • the shift register unit includes an input circuit and an output circuit , The first node noise reduction circuit and noise reduction reset circuit.
  • the input circuit is connected to the first node and is configured to write the input signal to the first node in response to the input control signal to control the level of the first node.
  • the output circuit is connected to the first node and the output terminal, and is configured to receive the clock signal and output the clock signal to the output terminal under the control of the level of the first node.
  • the first node noise reduction circuit is respectively connected to the first node, the first noise reduction node and the second noise reduction node, and is configured to control the level of the first noise reduction node or the level of the second noise reduction node
  • the first node performs noise reduction.
  • the noise reduction reset circuit is connected to the first noise reduction node and the second noise reduction node, and is configured to reset the first noise reduction node and the second noise reduction node in response to the first reset signal.
  • FIG. 1 is a schematic block diagram of a shift register unit provided by some embodiments of the present disclosure.
  • the shift register unit 10 includes an input circuit 100, an output circuit 200, a first node noise reduction circuit 300, and a noise reduction reset circuit 400.
  • the input circuit 100 is connected to the first node PU and is configured to write an input signal to the first node PU in response to an input control signal to control the level of the first node PU.
  • the input control signal and the input signal are the same signal, that is, the input signal is multiplexed into the input control signal.
  • the input circuit 100 electrically connects the first node PU to the input terminal INT under the control of the input signal, so that the high level of the input signal can charge the first node PU, that is, the level of the first node PU can be increased. Pulling makes the level of the first node PU increase to control the output circuit 200 to turn on.
  • the embodiment of the present disclosure is not limited to this manner.
  • the input circuit 100 may also be connected to a high-voltage terminal provided separately and configured to connect the first node PU with the input signal under the control of the input signal provided by the input terminal INT.
  • the high-voltage terminal is electrically connected, so that the high-level signal output from the high-voltage terminal can charge the first node PU.
  • the low level of the input signal can also be discharged to the first node PU, so that the level of the first node PU is reduced to control the output circuit 200 to be turned on, and the way the level of the first node PU changes (That is, increase or decrease) can be determined according to the specific implementation of the output circuit 200.
  • the output circuit 200 is connected to the first node PU and the output terminal OP1, and is configured to receive a clock signal and output the clock signal to the output terminal OP1 under the control of the level of the first node PU.
  • the output circuit 200 is turned on under the control of the level of the first node PU, so that the clock signal terminal CLK that provides the clock signal is electrically connected to the output terminal OP1, so that the output circuit 200 can output the received clock signal to the output terminal OP1.
  • the output terminal OP1 may be a scan signal output terminal and used to provide a scan signal for a pixel circuit (such as a pixel row).
  • the scan signal may be transmitted to the pixel circuit through a gate line of a display panel connected to the scan signal output terminal.
  • the first node noise reduction circuit 300 is connected to the first node PU, the first noise reduction node PD1, and the second noise reduction node PD2, respectively, and is configured to be at the level of the first noise reduction node PD1 or the electrical level of the second noise reduction node PD2. Under the control of Ping, noise reduction is performed on the first node PU.
  • the first node noise reduction circuit 300 is respectively connected to the first node PU, the first noise reduction node PD1, the second noise reduction node PD2, and a separately provided first voltage terminal VSS (for example, a low voltage terminal), and is configured as Under the control of the level of the first noise reduction node PD1 or the level of the second noise reduction node PD2, the first node PU is electrically connected to the first voltage terminal VSS, thereby resetting the level of the first node PU
  • the voltage provided to the first voltage terminal VSS reduces or avoids noise caused by the level of the first node PU during the non-operation period, thereby reducing the noise of the first node PU (for example, pull-down).
  • the first noise reduction node PD1 and the second noise reduction node PD2 can be alternately at an effective level (for example, a high level),
  • the first node noise reduction circuit 300 alternately responds to the level of the first noise reduction node PD1 and the level of the second noise reduction node PD2 to reduce the noise of the first node PU.
  • the first node noise reduction circuit 300 when switching from a high level signal to a low level signal , because the charge at the noise reduction node cannot be quickly released, there is residual charge, which causes the level of the first noise reduction node PD1 and the level of the second noise reduction node PD2 to act on the first node noise reduction circuit 300 at the same time, so that the first node
  • the node noise reduction circuit 300 doubles the discharge current of the first node PU, so that the charge of the first node PU is reduced, so that the first node PU cannot be fully charged, thereby causing a bad effect on the amplitude of the scan signal output from the output terminal OP1, for example. influences.
  • the noise reduction reset circuit 400 is connected to the first noise reduction node PD1 and the second noise reduction node PD2, and is configured to respond to the first reset signal to the first noise reduction node PD1. And the second noise reduction node PD2 is reset.
  • the noise reduction reset circuit 400 is respectively connected to the first noise reduction node PD1, the second noise reduction node PD2, the first reset terminal RST1, and a separately provided first voltage terminal VSS (for example, a low voltage terminal), and is configured to In response to the first reset signal provided by the first reset terminal RST1, the first noise reduction node PD1 and the second noise reduction node PD2 are electrically connected to the first voltage terminal VSS, respectively, so that the first noise reduction node PD1 and the second noise reduction node PD1 are electrically connected to each other.
  • the noisy node PD2 is reset.
  • the charges at the first noise reduction node PD1 and the second noise reduction node PD2 may pass through the first voltage in the process of being reset by the noise reduction reset circuit 400
  • the terminal VSS is quickly released, so as to prevent the residual charge at the first noise reduction node PD1 or the second noise reduction node PD2 from having additional influence on the first node noise reduction circuit 300 during the switching process, thereby ensuring the first node noise reduction circuit 300 only performs noise reduction on the first node PU under the control of the level of any one of the first noise reduction node PD1 and the second noise reduction node PD2.
  • the first reset terminal RST1 may apply the first reset signal to the noise reduction reset circuit 400 before the input signal is written to the input terminal INT to reset the first noise reduction node PD1 and the second noise reduction node PD2, thereby avoiding the first noise reduction node PD1 and the second noise reduction node PD2.
  • the residual charge at the noise reduction node PD1 or the second noise reduction node PD2 has an adverse effect on the charging of the first node PU, and improves the stability of the amplitude of the scanning signal output by the output terminal OP1, for example, to include the shift register unit
  • the display device of 10 can perform normal screen display, thereby improving the stability and reliability of the display device.
  • FIG. 2 is a schematic block diagram of another shift register unit provided by some embodiments of the present disclosure.
  • the shift register unit 20 in this embodiment further includes a first noise reduction circuit 510, a second noise reduction circuit 520, a first control circuit 610, and a second control circuit 620.
  • Other structures are the same as those shown in FIG.
  • the shift register unit 10 shown is basically the same or similar, and will not be repeated here.
  • the first noise reduction circuit 510 is respectively connected to the first node PU, the first noise reduction node PD1, and the first control node PD_CN1, and is configured to control the level of the first node PU and the level of the first control node PD_CN1. The level of the first noise reduction node PD1 is controlled.
  • the first noise reduction circuit 510 is respectively connected to the first voltage terminal VSS, the second voltage terminal VDD1, the first node PU, the first control node PD_CN1, and the first noise reduction node PD1, and is configured to be connected to the first node PU
  • the first noise reduction node PD1 is electrically connected to the first voltage terminal VSS under the control of the level of the first noise reduction node PD1, thereby controlling the level of the first noise reduction node PD1 (for example, pull-down), so that the first noise reduction node PD1 is at a low level Level.
  • the first noise reduction circuit 510 can electrically connect the first noise reduction node PD1 and the second voltage terminal VDD1 under the control of the level of the first control node PD_CN1, so that when the second voltage terminal VDD1 provides a high level signal The first noise reduction node PD1 is charged so that the first noise reduction node PD1 is at a high level.
  • the second noise reduction circuit 520 is respectively connected to the first node PU, the second noise reduction node PD2, and the second control node PD_CN2, and is configured to control the level of the first node PU and the level of the second control node PD_CN2.
  • the level of the second noise reduction node PD2 is controlled.
  • the second noise reduction circuit 520 is respectively connected to the first voltage terminal VSS, the third voltage terminal VDD2, the first node PU, the second control node PD_CN2, and the second noise reduction node PD2, and is configured to be connected to the first node PU
  • the second noise reduction node PD2 is electrically connected to the first voltage terminal VSS under the control of the level of the second noise reduction node PD2, thereby controlling the level of the second noise reduction node PD2 (for example, pull-down), so that the second noise reduction node PD2 is at a low level Level.
  • the second noise reduction circuit 520 can electrically connect the second noise reduction node PD2 and the third voltage terminal VDD2 under the control of the level of the second control node PD_CN2, so that when the third voltage terminal VDD2 provides a high level signal The second noise reduction node PD2 is charged so that the second noise reduction node PD2 is at a high level.
  • the first control circuit 610 is connected to the first node PU and the first control node PD_CN1, and is configured to control the level of the first control node PD_CN1 under the control of the level of the first node PU.
  • the first control circuit 610 is respectively connected to the first voltage terminal VSS, the second voltage terminal VDD1, the first node PU, and the first control node PD_CN1, and is configured to enable the first node PU under the control of the level of the first node PU.
  • a control node PD_CN1 is electrically connected to the first voltage terminal VSS, so as to pull down the level of the first control node PD_CN1, so that the first control node PD_CN1 is at a low level.
  • the first control circuit 610 can make the first control node PD_CN1 at a high level when the second voltage terminal VDD1 provides a high level signal.
  • the second control circuit 620 is connected to the first node PU and the second control node PD_CN2, and is configured to control the level of the second control node PD_CN2 under the control of the level of the first node PU.
  • the second control circuit 620 is respectively connected to the first voltage terminal VSS, the third voltage terminal VDD2, the first node PU, and the second control node PD_CN2, and is configured to enable the first node PU under the control of the level of the first node PU.
  • the second control node PD_CN2 is electrically connected to the first voltage terminal VSS, so as to pull down the level of the second control node PD_CN2, so that the second control node PD_CN2 is at a low level.
  • the second control circuit 620 can make the second control node PD_CN2 at a high level when the third voltage terminal VDD2 provides a high level signal.
  • the second voltage terminal VDD1 and the third voltage terminal VDD2 are configured to alternately provide DC high-level signals, thereby passing through the first noise reduction circuit 510, the second noise reduction circuit 520, the first control circuit 610, and the second control circuit.
  • the function of 620 is to make the first noise reduction node PD1 and the second noise reduction node PD2 alternate to a high level, thereby controlling the first node noise reduction circuit 300 to reduce noise on the first node PU.
  • the third voltage terminal VDD2 provides a low-level signal.
  • the first noise reduction node PD1 Under the action of the first noise reduction circuit 510 and the first control circuit 610, the first noise reduction node PD1 is high level; when the third voltage terminal VDD2 provides a high level signal, the second voltage terminal VDD1 provides a low level signal. Under the action of the second noise reduction circuit 520 and the second control circuit 620, the first The second noise reduction node PD2 is high. In this way, the performance drift of the transistors in the shift register unit 20 due to long-term conduction can be reduced or avoided, thereby improving the performance of the shift register unit 20.
  • the noise reduction reset circuit 400 responds to the first reset signal to the first noise reduction node PD1 and the second noise reduction node PD2 is reset, so as to avoid that during the process of switching the level signal provided by the second voltage terminal VDD1 or the third voltage terminal VDD2 from high to low, the charge in the circuit cannot pass through, for example, the first control circuit 610 Or the second control circuit 620 is quickly released and remains in the first noise reduction node PD1 or the second noise reduction node PD2.
  • the first node noise reduction circuit 300 only controls the first node under the control of the level of the first noise reduction node PD1 or the level of the second noise reduction node PD2.
  • the PU performs noise reduction to avoid excessive discharge current of the first node PU during the charging process, thereby improving the stability of the output signal at the output end, for example, ensuring the normal output of the output end signal.
  • FIG. 3 is a schematic block diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • the shift register unit 30 in this embodiment further includes an output reset circuit 700, a first node reset circuit 800, and an output noise reduction circuit 900.
  • Other structures are basically the same as those of the shift register unit 20 shown in FIG. Identical or similar, so I won’t repeat them here.
  • the output reset circuit 700 is connected to the output terminal OP1 and is configured to reset the output terminal OP1 in response to the first reset signal.
  • the output reset circuit is respectively connected to the output terminal OP1, the first reset terminal RST1 and the first voltage terminal VSS, and is configured to enable the output terminal OP1 and the first voltage terminal VSS under the control of the first reset signal provided by the first reset terminal RST1.
  • the voltage terminal VSS is electrically connected to reset the output terminal OP1, for example, to make the voltage of the output terminal OP1 equal to the voltage of the first voltage terminal VSS.
  • the output reset circuit 700 may be further connected to the first node PU, and configured to reset the first node PU in response to the first reset signal.
  • the output reset circuit 700 may also be connected to the first node PU, and is configured to electrically connect the first node PU and the first voltage terminal VSS under the control of the first reset signal provided by the first reset terminal RST1, thereby
  • the node PU is reset, for example, to make the voltage of the first node PU equal to the voltage of the first voltage terminal VSS.
  • the output reset circuit 700 may reset the first node PU before and after scanning of one frame of image, or reset the first node PU only before or after scanning of one frame of image.
  • the first node reset circuit 800 is connected to the first node PU and is configured to reset the first node PU in response to the second reset signal.
  • the first node reset circuit 800 is respectively connected to the first node PU, the second reset terminal RST2, and the first voltage terminal VSS, and is configured to cause the first node PU, the second reset terminal RST2, and the first voltage terminal VSS to make the first
  • the node PU is electrically connected to the first voltage terminal VSS, thereby resetting the first node PU, for example, making the voltage of the first node PU equal to the voltage of the first voltage terminal VSS.
  • the first node reset circuit 800 resets the first node PU after the output of the shift register unit 30 ends.
  • the output noise reduction circuit 900 is respectively connected to the first noise reduction node PD1, the second noise reduction node PD2 and the output terminal OP1, and is configured to control the level of the first noise reduction node PD1 or the level of the second noise reduction node PD2 Next, perform noise reduction on the output OP1.
  • the output noise reduction circuit 900 is connected to the first voltage terminal VSS, the output terminal OP1, the first noise reduction node PD1, and the second noise reduction node PD2, respectively, and is configured to be at the level or the second noise reduction node PD1.
  • the output terminal OP1 is electrically connected to the first voltage terminal VSS, for example, the voltage of the output terminal OP1 is equal to the voltage of the first voltage terminal VSS, so that the output terminal OP1 is noise-reduced ( For example, pull down).
  • FIG. 4 is a schematic block diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • the output circuit 200 of the shift register unit 40 is not only connected to the output terminal OP1 (for example, the scan signal output terminal), but also to The second output terminal OP2 (for example, the shift signal output terminal) is connected to improve the driving capability of the shift register unit 40.
  • the scanning signal output terminal (such as the output terminal OP1) is used to provide scanning signals for the pixel circuit (such as pixel rows), and the shift signal output terminal (such as the second output terminal OP2) is used to provide other shift register units in the cascade. Provide input signal.
  • the output circuit 200 is also configured to receive a clock signal and output the clock signal to the second output terminal OP2 under the control of the level of the first node PU.
  • the output circuit 200 is turned on under the control of the level of the first node PU, so that the clock signal terminal CLK is electrically connected to the second output terminal OP2, so that the output circuit 200 can also output the received clock signal to the second output terminal OP2.
  • the output noise reduction circuit 900 may also be configured to reduce noise on the second output terminal OP2 under the control of the level of the first noise reduction node PD1 or the level of the second noise reduction node PD2.
  • the output noise reduction circuit 900 is also connected to the second output terminal OP2, and is configured to make the second output terminal OP2 and the second output terminal OP2 and the second output terminal OP2 under the control of the level of the first noise reduction node PD1 or the level of the second noise reduction node PD2
  • a voltage terminal VSS is electrically connected, for example, so that the voltage of the second output terminal OP2 is equal to the voltage of the first voltage terminal VSS, thereby reducing noise (for example, pull-down) on the second output terminal OP2.
  • FIG. 5 is a circuit diagram of a specific implementation example of the shift register unit shown in FIG. 3.
  • each transistor is an N-type transistor as an example, but this does not constitute a limitation to the embodiment of the present disclosure.
  • the shift register unit 30 includes first to nineteenth transistors M1-M19 and a first capacitor C1.
  • the noise reduction reset circuit 400 includes a first transistor M1 and a second transistor M2.
  • the gate of the first transistor M1 is configured to be connected to the first reset terminal RST1 to receive the first reset signal
  • the first electrode of the first transistor M1 is configured to be connected to the first noise reduction node PD1
  • the second electrode of the first transistor M1 It is configured to be connected to the first voltage terminal VSS.
  • the gate of the second transistor M2 is configured to be connected to the first reset terminal RST1 to receive the first reset signal
  • the first electrode of the second transistor M2 is configured to be connected to the second noise reduction node PD2, and the second electrode of the second transistor M2 It is configured to be connected to the first voltage terminal VSS.
  • the first transistor M1 and the second transistor M2 are turned on, connecting the first noise reduction node PD1 and the second noise reduction node PD2 to the first voltage terminal VSS. Are electrically connected to reset the first noise reduction node PD1 and the second noise reduction node PD2.
  • the input circuit 100 includes a third transistor M3.
  • the gate of the third transistor M3 is connected to the input terminal INT to receive the input signal as an input control signal.
  • the first pole of the third transistor M3 is connected to the input terminal INT to receive the input signal.
  • the second pole of the transistor M3 is configured to be connected to the first node PU.
  • the output circuit 200 includes a fourth transistor M4 and a first capacitor C1.
  • the gate of the fourth transistor M4 is configured to be connected to the first node PU, the first pole of the fourth transistor M4 is configured to be connected to the clock signal terminal CLK to receive the clock signal, and the second pole of the fourth transistor M4 is configured to be connected to the output terminal OP1 connection.
  • the first pole of the first capacitor C1 is configured to be connected to the first node PU, and the second pole of the first capacitor C1 is configured to be connected to the output terminal OP1.
  • the fourth transistor M4 is turned on, so that it can receive the clock signal of the clock signal terminal CLK, and output, for example, a scan signal through the output terminal OP1.
  • the first node noise reduction circuit 300 includes a fifth transistor M5 and a sixth transistor M6.
  • the gate of the fifth transistor M5 is configured to be connected to the first noise reduction node PD1
  • the first electrode of the fifth transistor M5 is configured to be connected to the first node PU
  • the second electrode of the fifth transistor M5 is configured to be connected to the first voltage terminal VSS connection.
  • the gate of the sixth transistor M6 is configured to be connected to the second noise reduction node PD2
  • the first electrode of the sixth transistor M6 is configured to be connected to the first node PU
  • the second electrode of the sixth transistor M6 is configured to be connected to the first voltage terminal VSS connection.
  • the fifth transistor M5 When the level of the first noise reduction node PD1 is high, the fifth transistor M5 is turned on; when the level of the second noise reduction node PD2 is high, the sixth transistor M6 is turned on.
  • the fifth transistor M5 or the sixth transistor M6 When any one of the first noise reduction node PD1 and the second noise reduction node PD2 is at a high level, the fifth transistor M5 or the sixth transistor M6 is turned on to electrically connect the first node PU and the first voltage terminal VSS, thereby The level of the first node PU can be pulled down to a low level to reduce noise.
  • the first noise reduction circuit 510 includes a seventh transistor M7 and an eighth transistor M8.
  • the gate of the seventh transistor M7 is configured to be connected to the first control node PD_CN1, the first pole of the seventh transistor M7 is configured to be connected to the second voltage terminal VDD1, and the second pole of the seventh transistor M7 is configured to be connected to the first noise reduction Node PD1 is connected.
  • the gate of the eighth transistor M8 is configured to be connected to the first node PU, the first pole of the eighth transistor M8 is configured to be connected to the first noise reduction node PD1, and the second pole of the eighth transistor M8 is configured to be connected to the first voltage terminal VSS connection.
  • the seventh transistor M7 is turned on, so that the first noise reduction node PD1 and the second voltage terminal VDD1 are electrically connected, so that when the second voltage terminal VDD1 provides a high level signal
  • the first noise reduction node PD1 is charged so that the first noise reduction node PD1 is at a high level.
  • the eighth transistor M8 is turned on to electrically connect the first noise reduction node PD1 and the first voltage terminal VSS, so that the level of the first noise reduction node PD1 can be pulled down to a low level .
  • the first noise reduction node PD1 when the first transistor M1 is turned on in response to the high level of the first reset signal to reset the first noise reduction node PD1, in order to ensure the voltage of the first voltage terminal VSS, the first noise reduction node PD1 To pull down the level to a low level, it is necessary to set the parameters of the first transistor M1 and the seventh transistor M7 (such as the on-resistance, that is, the resistance between the drain and the source of the transistor).
  • the first transistor M1 The on-resistance is set to be smaller than the on-resistance of the seventh transistor M7, so that even when the seventh transistor M7 is on, the first voltage terminal VSS can pull down the voltage of the first noise reduction node PD1 to approximately equal to the first voltage.
  • the voltage of the voltage terminal VSS can achieve the effect of resetting the first noise reduction node PD1.
  • the first control circuit 610 includes a ninth transistor M9 and a tenth transistor M10.
  • the gate and the first electrode of the ninth transistor M9 are connected to each other and configured to be connected to the second voltage terminal VDD1, and the second electrode of the ninth transistor M9 is configured to be connected to the first control node PD_CN1.
  • the gate of the tenth transistor M10 is configured to be connected to the first node PU, the first electrode of the tenth transistor M10 is configured to be connected to the first control node PD_CN1, and the second electrode of the tenth transistor M10 is configured to be connected to the first voltage terminal VSS. connection.
  • the ninth transistor M9 is turned on to electrically connect the first control node PD_CN1 and the second voltage terminal VDD1, thereby charging the first control node PD_CN1, so that the A control node PD_CN1 is at a high level.
  • the tenth transistor M10 is turned on to electrically connect the first control node PD_CN1 and the first voltage terminal VSS, so that the level of the first control node PD_CN1 can be pulled down to a low level.
  • the second noise reduction circuit 520 includes an eleventh transistor M11 and a twelfth transistor M12.
  • the gate of the eleventh transistor M11 is configured to be connected to the second control node PD_CN2, the first pole of the eleventh transistor M11 is configured to be connected to the third voltage terminal VDD2, and the second pole of the eleventh transistor M11 is configured to be connected to the Two noise reduction node PD2 is connected.
  • the gate of the twelfth transistor M12 is configured to be connected to the first node PU, the first electrode of the twelfth transistor M12 is configured to be connected to the second noise reduction node PD2, and the second electrode of the twelfth transistor M12 is configured to be connected to the A voltage terminal VSS is connected.
  • the eleventh transistor M11 is turned on to electrically connect the second noise reduction node PD2 and the third voltage terminal VDD2, thereby providing a high level signal at the third voltage terminal VDD2
  • the second noise reduction node PD2 is charged so that the second noise reduction node PD2 is at a high level.
  • the twelfth transistor M12 is turned on to electrically connect the second noise reduction node PD2 and the first voltage terminal VSS, so that the level of the second noise reduction node PD2 can be pulled down to a low level. level.
  • the second noise reduction node PD2 when the second transistor M2 is turned on in response to the high level of the first reset signal to reset the second noise reduction node PD2, in order to ensure the voltage of the first voltage terminal VSS, the second noise reduction node PD2 can be To pull down the level to a low level, it is necessary to set the parameters of the second transistor M2 and the eleventh transistor M11 (such as on-resistance, that is, the resistance between the drain and source of the transistor).
  • the second transistor M2 The on-resistance of the eleventh transistor M11 is set to be smaller than the on-resistance of the eleventh transistor M11, so that even when the eleventh transistor M11 is on, the first voltage terminal VSS can pull down the voltage of the second noise reduction node PD2 to approximately It is equal to the voltage of the first voltage terminal VSS to achieve the effect of resetting the second noise reduction node PD2.
  • the second control circuit 620 includes a thirteenth transistor M13 and a fourteenth transistor M14.
  • the gate and the first electrode of the thirteenth transistor M13 are connected to each other and configured to be connected to the third voltage terminal VDD2, and the second electrode of the thirteenth transistor M13 is configured to be connected to the second control node PD_CN2.
  • the gate of the fourteenth transistor M14 is configured to be connected to the first node PU, the first electrode of the fourteenth transistor M14 is configured to be connected to the second control node PD_CN2, and the second electrode of the fourteenth transistor M14 is configured to be connected to the first node.
  • the voltage terminal VSS is connected.
  • the thirteenth transistor M13 is turned on to electrically connect the second control node PD_CN2 and the third voltage terminal VDD2, thereby charging the second control node PD_CN2 to make The second control node PD_CN2 is at a high level.
  • the fourteenth transistor M14 is turned on, electrically connecting the second control node PD_CN2 and the first voltage terminal VSS, so that the level of the second control node PD_CN2 can be pulled down to a low level.
  • the output reset circuit 700 includes a fifteenth transistor M15.
  • the gate of the fifteenth transistor M15 is configured to be connected to the first reset terminal RST1 to receive the first reset signal
  • the first pole of the fifteenth transistor M15 is configured to be connected to the output terminal OP1
  • the second pole of the fifteenth transistor M15 It is configured to be connected to the first voltage terminal VSS.
  • the fifteenth transistor M15 is turned on to electrically connect the output terminal OP1 and the first voltage terminal VSS, thereby resetting the output terminal OP1.
  • the output reset circuit 700 may further include a sixteenth transistor M16.
  • the gate of the sixteenth transistor M16 is configured to be connected to the first reset terminal RST1 to receive the first reset signal
  • the first electrode of the sixteenth transistor M16 is configured to be connected to the first node PU
  • the second terminal of the sixteenth transistor M16 The pole is configured to be connected to the first voltage terminal VSS.
  • the sixteenth transistor M16 is turned on to electrically connect the first node PU and the first voltage terminal VSS, thereby resetting the first node PU.
  • the first node reset circuit 800 includes a seventeenth transistor M17.
  • the gate of the seventeenth transistor M17 is configured to be connected to the second reset terminal RST2 to receive the second reset signal
  • the first pole of the seventeenth transistor M17 is configured to be connected to the first node PU
  • the second terminal of the seventeenth transistor M17 The pole is configured to be connected to the first voltage terminal VSS.
  • the seventeenth transistor M17 is turned on to electrically connect the first node PU and the first voltage terminal VSS, thereby resetting the first node PU.
  • the output noise reduction circuit 900 includes an eighteenth transistor M18 and a nineteenth transistor M19.
  • the gate of the eighteenth transistor M18 is configured to be connected to the first noise reduction node PD1, the first pole of the eighteenth transistor M18 is configured to be connected to the output terminal OP1, and the second pole of the eighteenth transistor M18 is configured to be connected to the first The voltage terminal VSS is connected.
  • the gate of the nineteenth transistor M19 is configured to be connected to the second noise reduction node PD2, the first pole of the nineteenth transistor M19 is configured to be connected to the output terminal OP1, and the second pole of the nineteenth transistor M19 is configured to be connected to the first The voltage terminal VSS is connected.
  • the eighteenth transistor M18 When the level of the first noise reduction node PD1 is high, the eighteenth transistor M18 is turned on; when the level of the second noise reduction node PD2 is high, the nineteenth transistor M19 is turned on.
  • the eighteenth transistor M18 or the nineteenth transistor M19 When any one of the first noise reduction node PD1 and the second noise reduction node PD2 is at a high level, the eighteenth transistor M18 or the nineteenth transistor M19 is turned on to electrically connect the output terminal OP1 and the first voltage terminal VSS, Therefore, the level of the scanning signal output from the output terminal OP1 can be pulled down to a low level to reduce noise.
  • Fig. 6 is a circuit diagram of a specific implementation example of the shift register unit shown in Fig. 4.
  • the output circuit 200 when the output circuit 200 is connected to the second output terminal OP2, the output circuit 200 may further include a twentieth transistor M20.
  • the output noise reduction circuit 900 may further include a second Eleven transistor M21 and twenty-second transistor M22.
  • the gate of the twentieth transistor M20 is configured to be connected to the first node PU
  • the first pole of the twentieth transistor M20 is configured to be connected to the clock signal terminal CLK to receive the clock signal
  • the second pole of the twentieth transistor M20 is It is configured to be connected to the second output terminal OP2.
  • the twentieth transistor M20 is turned on, so that the clock signal of the clock signal terminal CLK can be transmitted to the second output terminal OP2 through the twentieth transistor M20, and output through the second output terminal OP2 .
  • the gate of the twenty-first transistor M21 is configured to be connected to the first noise reduction node PD1, the first electrode of the twenty-first transistor M21 is configured to be connected to the second output terminal OP2, and the second electrode of the twenty-first transistor M21 It is configured to be connected to the first voltage terminal VSS.
  • the gate of the twenty-second transistor M22 is configured to be connected to the second noise reduction node PD2, the first pole of the twenty-second transistor M22 is configured to be connected to the second output terminal OP2, and the second pole of the twenty-second transistor M22 It is configured to be connected to the first voltage terminal VSS.
  • the twenty-first transistor M21 When the first noise reduction node PD1 is at a high level, the twenty-first transistor M21 is turned on; when the second noise reduction node PD2 is at a high level, the twenty-second transistor M22 is turned on.
  • the twenty-first transistor M21 or the twenty-second transistor M22 When any one of the first noise reduction node PD1 and the second noise reduction node PD2 is at a high level, the twenty-first transistor M21 or the twenty-second transistor M22 is turned on, connecting the second output terminal OP2 and the first voltage terminal VSS is electrically connected, so that the level of the output signal of the second output terminal OP2 can be pulled down to a low level for noise reduction.
  • the first capacitor C1 may be a capacitive device manufactured by a process, for example, a capacitor device is realized by manufacturing a special capacitor electrode, and each electrode of the capacitor may be formed by a metal layer, a semiconductor Layer (for example, doped polysilicon), etc.; or, the first capacitor C1 may also be a parasitic capacitance between transistors, for example, it may be realized by the capacitance generated between the transistor itself and other devices or lines.
  • a capacitor device is realized by manufacturing a special capacitor electrode
  • each electrode of the capacitor may be formed by a metal layer, a semiconductor Layer (for example, doped polysilicon), etc.
  • the first capacitor C1 may also be a parasitic capacitance between transistors, for example, it may be realized by the capacitance generated between the transistor itself and other devices or lines.
  • the embodiments of the present disclosure This is not limited.
  • the first node PU, the first noise reduction node PD1, the second noise reduction node PD2, the first control node PD_CN1, and the second control node PD_CN2 do not indicate actual existence. Instead, it represents the junction of related electrical connections in the circuit diagram.
  • the transistors used in the embodiments of the present disclosure can be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description, but this is not It constitutes a limitation to the embodiment of the present disclosure.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • the transistors in the embodiments of the present disclosure are all described by taking an N-type transistor as an example.
  • the first electrode of the transistor is the drain and the second electrode is the source.
  • the present disclosure includes but is not limited to this.
  • one or more transistors in the shift register unit 10/20/30/40 provided by the embodiments of the present disclosure may also be P-type transistors.
  • the first electrode of the transistor is the source and the second electrode is For the drain, it is only necessary to connect the poles of the selected type of transistor with reference to the poles of the corresponding transistor in the embodiment of the present disclosure, and make the corresponding voltage terminal provide the corresponding high voltage or low voltage.
  • indium gallium zinc oxide Indium Gallium Zinc Oxide, IGZO
  • crystalline silicon can effectively reduce the size of the transistor and prevent leakage current.
  • pulse-up means charging a node or an electrode of a transistor so that the level of the node or the electrode is absolutely The value increases to achieve the operation of the corresponding transistor (for example, turn-on); “pull-down” means to discharge a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode is reduced, thereby achieving the corresponding Operation of the transistor (for example, turning off).
  • pulse-up means discharging a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode is reduced, thereby realizing the corresponding transistor Operation (for example, turn on);
  • pulse down means to charge a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode is increased, thereby realizing the operation of the corresponding transistor (for example, turning off) .
  • the second voltage terminal VDD1 and the third voltage terminal VDD2 are configured to alternately provide DC high-level signals.
  • the second voltage terminal VDD1 and the third voltage terminal VDD2 respectively provide alternate DC high-level signals.
  • the signal and the DC low-level signal, and the signals provided by the second voltage terminal VDD1 and the third voltage terminal VDD2 are mutually inverted signals.
  • each transistor is an N-type transistor as an example for description, but the embodiments of the present disclosure are not limited thereto.
  • RST1, VDD1, VDD2, PD1, PD2, CLK, INT, PU, OP1, etc. are used to indicate the corresponding signal terminals or nodes, and also used to indicate the corresponding The level of the signal or node.
  • the shift register unit 30 can perform the following operations respectively.
  • the second voltage signal VDD1 is switched from a DC low level signal to a DC high level signal
  • the third voltage signal VDD2 is switched from a DC high level signal to a DC low level signal
  • the ninth transistor M9 is turned on
  • the thirteenth transistor M13 is turned off.
  • the input terminal INT provides a low level signal
  • the third transistor M3 is turned off
  • the first node PU due to being reset
  • the eighth transistor M8 the tenth transistor M10, the twelfth transistor M12 and the fourteenth transistor M14 Deadline.
  • the level of the first control node PD_CN1 is pulled up to a high level through the ninth transistor M9, the seventh transistor M7 is turned on, and the level of the first noise reduction node PD1 is pulled up to a high level.
  • the fifth transistor M5 and the eighteenth transistor M18 are turned on, thereby respectively reducing the noise of the first node PU and the output terminal OP1.
  • the charge at the second noise reduction node PD2 can only be slowly leaked through the thirteenth transistor M13 and cannot be quickly released. Therefore, the level of the second noise reduction node PD2 is ignored due to the discharge of the charge. There is a drop, but it is still at a high level.
  • the first reset terminal RST1 provides a high-level signal
  • the first transistor M1 and the second transistor M2 are turned on, pulling down the level of the first noise reduction node PD1 and the level of the second noise reduction node PD2 respectively To a low level, so that the charge at the second noise reduction node PD2 leaks through the second transistor M2 and is quickly released.
  • the input terminal INT provides a high-level input signal in the subsequent stage
  • the residual charge at the second noise reduction node PD2 can be reduced or prevented from having an adverse effect on the charging of the first node PU, so that the first node PU is fully charged.
  • the stability of the amplitude of the scanning signal output by the output terminal OP1, for example, is improved, so that the display device including the shift register unit 30 can Perform normal screen display, thereby improving the stability and reliability of the display device.
  • the first reset terminal RST1 provides a low level signal, and the level of the first noise reduction node PD1 is pulled up to a high level again under the action of the high level second voltage signal VDD1. Therefore, under the control of the high level of the first noise reduction node PD1, the fifth transistor M5 and the eighteenth transistor M18 are turned on, so as to continue the noise reduction on the first node PU and the output terminal OP1, respectively.
  • the input terminal INT provides a high-level input signal
  • the third transistor M3 is turned on
  • the first node PU is charged to a high level
  • the fourth transistor M4 is turned on.
  • the fourth transistor M4 outputs the clock signal of the clock signal terminal CLK to the output terminal OP1; and the clock signal is still at a low level at this stage.
  • the eighth transistor M8 and the tenth transistor M10 are turned on under the control of the high level of the first node PU. Since the ninth transistor M9 and the tenth transistor M10 are serially divided, the level of the first control node PD_CN1 is pulled down to a low level.
  • the seventh transistor M7 is turned off, and the level of the first noise reduction node PD1 is pulled down to a low level by the turned-on eighth transistor M8.
  • the clock signal of the clock signal terminal CLK becomes a high level, and the potential of the first node PU is further increased due to the coupling effect (bootstrap effect) of the output terminal OP1 through the first capacitor C1.
  • the fourth transistor M4 is fully turned on, and the high-level clock signal is output to the output terminal OP1 as, for example, a scan signal.
  • the first noise reduction node PD1 and the second noise reduction node PD2 are kept at a low level, and the eighteenth transistor M18 and the nineteenth transistor M19 are kept off, which will not adversely affect the output.
  • the clock signal of the clock signal terminal CLK becomes low level, the potential of the first node PU is reduced due to the coupling effect, but it is still high level, the fourth transistor M4 remains on, and the power is low.
  • the flat clock signal is output to the output terminal OP1, so that the output terminal OP1 outputs a low-level scanning signal.
  • the second reset terminal RST2 provides a high-level signal (not shown in FIG. 8), and the seventeenth transistor M17 is turned on to pull the level of the first node PU to a low level.
  • the eighth transistor M8 and the tenth transistor M10 are turned off.
  • the level of the first control node PD_CN1 is pulled up to a high level by the ninth transistor M9, and the seventh transistor M7 is turned on to pull the level of the first noise reduction node PD1 to a high level.
  • the fifth transistor M5 and the eighteenth transistor M18 are turned on, thereby continuously reducing noise on the first node PU and the output terminal OP1, respectively.
  • At least one embodiment of the present disclosure further provides a gate drive circuit, which includes a plurality of cascaded shift register units according to any embodiment of the present disclosure.
  • FIG. 9 is a schematic block diagram of a gate driving circuit provided by some embodiments of the disclosure.
  • the gate driving circuit 50 includes a plurality of cascaded shift register units (SRn, SRn+1, SRn+2, SRn+3, etc.).
  • the number of multiple shift register units is not limited and can be determined according to actual needs.
  • the shift register unit may adopt the shift register unit 10/20/30/40 described in any embodiment of the present disclosure.
  • part or all of the shift register units may be the shift register units 10/20/30/40 described in any embodiment of the present disclosure.
  • the gate driving circuit 50 can be directly integrated on the array substrate of the display device using the same manufacturing process as the thin film transistor to realize the progressive scan driving function.
  • each of the plurality of shift register units has an input terminal INT, a first reset terminal RST1, a second reset terminal RST2, an output terminal OP1 (such as a scan signal output terminal), and a second output terminal OP2 (such as a shift signal output terminal). Output).
  • INT input terminal
  • RST1 reset terminal
  • RST2 reset terminal
  • OP1 output terminal
  • OP2 shift signal output terminal
  • Output output terminals that should be provided are not shown or marked in the figure.
  • the first reset terminal RST1 of each stage of shift register unit receives the provided first reset signal.
  • the second output terminal OP2 of each stage of shift register unit is connected to the second reset terminal RST2 of the previous stage of shift register unit.
  • the second output terminal OP2 of each stage of shift register unit is connected to the input terminal INT of the next stage of shift register unit.
  • the input terminal INT of the first stage shift register unit is configured to receive the trigger signal STV1; the second reset terminal RST2 of the last stage shift register unit is configured to receive an additional reset signal.
  • the above is the case of forward scanning.
  • the above-mentioned trigger signal STV1 for the first-stage shift register unit is replaced with the above-mentioned reset signal, and the above-mentioned reset signal for the last-stage shift register unit is replaced with the trigger signal STV1.
  • each stage of the shift register unit of the gate drive circuit does not include the second output terminal OP2, except for the first stage, the output terminal OP1 of each stage of the shift register unit and the previous stage shift register unit
  • the second reset terminal RST2 is connected.
  • the output terminal OP1 of each stage of shift register unit is connected to the input terminal INT of the next stage of shift register unit.
  • the input terminal INT of the first stage shift register unit is configured to receive the trigger signal STV1; the second reset terminal RST2 of the last stage shift register unit is configured to receive an additional reset signal.
  • the above is the case of forward scanning.
  • the above-mentioned trigger signal STV1 for the first-stage shift register unit is replaced with the above-mentioned reset signal, and the above-mentioned reset signal for the last-stage shift register unit is replaced with the trigger signal STV1.
  • the gate driving circuit 50 further includes a first system clock CLK1 and a second system clock CLK2, and the clock signals output by the first system clock CLK1 and the second system clock CLK2 are, for example, complementary to each other.
  • odd-numbered shift register units for example, SRn and SRn+2 are connected to the first system clock CLK1 to receive clock signals
  • even-numbered shift register units for example, SRn+1 and SRn+3 are connected to the second system clock CLK1.
  • the clock CLK2 is connected to receive the clock signal, thereby ensuring that the output signals of the output terminal OP1 and the second output terminal OP2 of each shift register unit are shifted.
  • the gate driving circuit 50 may further include a timing controller configured to provide a first system clock signal and a second system clock signal to the shift register units of each stage, and the timing controller may also be configured to provide Trigger signal STV1.
  • a timing controller configured to provide a first system clock signal and a second system clock signal to the shift register units of each stage, and the timing controller may also be configured to provide Trigger signal STV1.
  • more system clocks can be provided, such as 4, 6, etc.
  • the cascade mode of the shift register units of each stage in the gate drive circuit 50 and the connection mode with the system clock are not limited, and may be the above mode or other applicable modes.
  • the embodiment of the present disclosure does not limit the connection mode of the device.
  • the gate driving circuit 50 further includes a first voltage line LVSS, a second voltage line LVDD1, a third voltage line LVDD2, and other unshown voltage lines to provide the first and second voltage lines to each shift register unit. Voltage, third voltage and other required voltages.
  • the gate driving circuit 50 when used to drive a display panel, the gate driving circuit 50 can be arranged on one side of the display panel.
  • the display panel includes multiple rows of gate lines, and the output terminals OP1 of the shift register units of each stage in the gate driving circuit 50 may be configured to be connected to the multiple rows of gate lines in sequence to output scanning signals.
  • the gate driving circuit 50 can also be provided on both sides of the display panel to achieve bilateral driving.
  • the embodiment of the present disclosure does not limit the arrangement of the gate driving circuit 50.
  • the gate driving circuit 50 may be provided on one side of the display panel for driving odd-numbered gate lines, and the gate driving circuit 50 may be provided on the other side of the display panel for driving even-numbered gate lines.
  • At least one embodiment of the present disclosure also provides a display device.
  • the display device includes the gate driving circuit described in any embodiment of the present disclosure.
  • FIG. 10 is a schematic block diagram of a display device provided by some embodiments of the present disclosure.
  • the display device 60 includes a gate driving circuit 50, which is a gate driving circuit according to any embodiment of the disclosure.
  • the display device 60 can be any product or component with display function, such as a liquid crystal panel, a liquid crystal TV, an OLED panel, an OLED TV, a display, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc.
  • the disclosed embodiment does not limit this.
  • the display device 60 includes a display panel 6000, a gate driver 6010, a timing controller 6020, and a data driver 6030.
  • the display panel 6000 includes a plurality of pixel units P defined according to the intersection of a plurality of gate lines GL and a plurality of data lines DL; a gate driver 6010 is used to drive a plurality of gate lines GL; a data driver 6030 is used to drive a plurality of data lines DL;
  • the timing controller 6020 is used to process the image data RGB input from the outside of the display device 60, provide the processed image data RGB to the data driver 6030, and output the scan control signal GCS and the data control signal DCS to the gate driver 6010 and the data driver 6030, respectively, To control the gate driver 6010 and the data driver 6030.
  • the gate driver 6010 includes the gate driving circuit 50 provided in any of the above embodiments.
  • the output terminals OP1 of the multiple shift register units 10/20/30/40 in the gate driving circuit 50 are correspondingly connected to the multiple gate lines GL.
  • the multiple gate lines GL are correspondingly connected to the pixel units P arranged in multiple rows.
  • the output terminals OP1 of the shift register units 10/20/30/40 of each level in the gate driving circuit 50 sequentially output signals to the multiple gate lines GL, so that the multiple rows of pixel units P in the display panel 6000 are implemented row by row Scan function.
  • the gate driver 6010 may be implemented as a semiconductor chip, or integrated in the display panel 6000 to form a GOA circuit.
  • the data driver 6030 uses the reference gamma voltage to convert the digital image data RGB input from the timing controller 6020 into data signals according to a plurality of data control signals DCS from the timing controller 6020.
  • the data driver 6030 provides the converted data signals to the plurality of data lines DL.
  • the data driver 6030 may be implemented as a semiconductor chip.
  • the timing controller 6020 processes externally input image data RGB to match the size and resolution of the display panel 6000, and then provides the processed image data to the data driver 6030.
  • the timing controller 6020 uses a synchronization signal SYNC (such as a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) input from the outside of the display device 60 to generate a plurality of scan control signals GCS and a plurality of data control signals DCS.
  • the timing controller 6020 provides the generated scan control signal GCS and data control signal DCS to the gate driver 6010 and the data driver 6030, respectively, for controlling the gate driver 6010 and the data driver 6030.
  • the display device 60 may also include other components, such as a signal decoding circuit, a voltage conversion circuit, etc., for example, these components may use existing conventional components, which will not be described in detail here.
  • At least one embodiment of the present disclosure also provides a method for driving the shift register unit, which can be used to drive the shift register unit 10/20/30/40 according to any embodiment of the present disclosure.
  • the driving method of the shift register unit 10/20/30/40 includes the following operations.
  • the noise reduction reset circuit 400 resets the first noise reduction node PD1 and the second noise reduction node PD2 in response to the first reset signal.
  • the input circuit 100 writes the input signal to the first node PU in response to the input control signal.
  • the output circuit 200 In the output phase (that is, the fifth phase 5 described above), the output circuit 200 outputs the clock signal to the output terminal OP1 under the control of the level of the first node PU.

Abstract

L'invention concerne une unité (10) de registre à décalage et un procédé d'attaque de celle-ci, un circuit d'attaque de grille et un dispositif d'affichage, l'unité (10) de registre à décalage comportant un circuit (100) d'entrée, un circuit (200) de sortie, un circuit (300) de réduction du bruit de premier nœud et un circuit (400) de réinitialisation de réduction du bruit. Le circuit (100) d'entrée écrit le signal d'entrée dans un premier nœud (PU) en réponse au signal de commande d'entrée pour commander le niveau du premier nœud (PU). Le circuit (200) de sortie reçoit un signal d'horloge et délivre le signal d'horloge à une borne de sortie (OP1) sous le contrôle du niveau du premier nœud (PU). Le circuit (300) de réduction du bruit de premier nœud est relié au premier nœud (PU), à un premier nœud de réduction du bruit (PD1) et à un second nœud de réduction du bruit (PD2), et est configuré pour effectuer une réduction de bruit sur le premier nœud (PU) sous le contrôle du niveau du premier nœud de réduction du bruit (PD1) ou du niveau du second nœud de réduction du bruit (PD2). Le circuit (400) de réinitialisation de réduction du bruit est relié au premier nœud de réduction du bruit (PD1) et au second nœud de réduction du bruit (PD2), et est configuré pour réinitialiser le premier nœud de réduction du bruit (PD1) et le second nœud de réduction du bruit (PD2) en réponse au premier signal de réinitialisation. L'unité (10) de registre à décalage permet à la charge du premier nœud de réduction du bruit (PD1) et du second nœud de réduction du bruit (PD2) d'être libérée, réduisant l'interférence vis-à-vis de la sortie de signal de la borne de sortie (OP1).
PCT/CN2020/077995 2019-03-15 2020-03-05 Unité de registre à décalage et son procédé d'attaque, circuit d'attaque de grille et dispositif d'affichage WO2020187043A1 (fr)

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CN201910199588.0 2019-03-15
CN201910199588.0A CN111696490A (zh) 2019-03-15 2019-03-15 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置

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US20090040203A1 (en) * 2007-08-06 2009-02-12 Samsung Electronics Co., Ltd. Gate driving circuit and display device having the same
CN103258494A (zh) * 2013-04-16 2013-08-21 合肥京东方光电科技有限公司 一种移位寄存器、栅极驱动装置和液晶显示装置
CN205050536U (zh) * 2015-10-23 2016-02-24 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器和显示装置
CN106057152A (zh) * 2016-07-19 2016-10-26 深圳市华星光电技术有限公司 一种goa电路及液晶显示面板

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Publication number Priority date Publication date Assignee Title
US20070086558A1 (en) * 2005-10-18 2007-04-19 Au Optronics Corporation Gate line drivers for active matrix displays
CN101038792A (zh) * 2006-03-15 2007-09-19 三菱电机株式会社 移位寄存器电路和具备该电路的图像显示装置
US20090040203A1 (en) * 2007-08-06 2009-02-12 Samsung Electronics Co., Ltd. Gate driving circuit and display device having the same
CN103258494A (zh) * 2013-04-16 2013-08-21 合肥京东方光电科技有限公司 一种移位寄存器、栅极驱动装置和液晶显示装置
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