WO2020186383A1 - 校正电路以及相关信号处理电路及芯片 - Google Patents

校正电路以及相关信号处理电路及芯片 Download PDF

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Publication number
WO2020186383A1
WO2020186383A1 PCT/CN2019/078254 CN2019078254W WO2020186383A1 WO 2020186383 A1 WO2020186383 A1 WO 2020186383A1 CN 2019078254 W CN2019078254 W CN 2019078254W WO 2020186383 A1 WO2020186383 A1 WO 2020186383A1
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Prior art keywords
delay time
reference signal
corrected
delay
module
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PCT/CN2019/078254
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English (en)
French (fr)
Inventor
黄思衡
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2019/078254 priority Critical patent/WO2020186383A1/zh
Priority to EP19914208.4A priority patent/EP3751238A4/en
Priority to CN201980000372.5A priority patent/CN110073176B/zh
Priority to JP2020543988A priority patent/JP7002667B2/ja
Priority to US16/998,835 priority patent/US20200378813A1/en
Publication of WO2020186383A1 publication Critical patent/WO2020186383A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
    • G01F1/00—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow
    • G01F1/66—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by measuring frequency, phase shift or propagation time of electromagnetic or other waves, e.g. using ultrasonic flowmeters
    • G01F1/667—Arrangements of transducers for ultrasonic flowmeters; Circuits for operating ultrasonic flowmeters
    • G01F1/668—Compensating or correcting for variations in velocity of sound
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
    • G01F1/00—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow
    • G01F1/66—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by measuring frequency, phase shift or propagation time of electromagnetic or other waves, e.g. using ultrasonic flowmeters
    • G01F1/662—Constructional details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
    • G01F25/00—Testing or calibration of apparatus for measuring volume, volume flow or liquid level or for metering by volume
    • G01F25/10—Testing or calibration of apparatus for measuring volume, volume flow or liquid level or for metering by volume of flowmeters

Definitions

  • This application relates to a correction circuit, in particular to a correction circuit of a signal processing circuit, and related signal processing circuits and chips.
  • the flow rate needs to be measured by measuring the flow rate of the fluid, and the most important measurement parameter for measuring the flow rate is the delay time of the ultrasonic wave in the fluid.
  • the prior art has a relatively significant error in measuring the delay time, and therefore cannot generate a high-precision delay time. In view of this, further improvements and innovations are needed to improve the above situation.
  • One of the objectives of the present application is to disclose a correction circuit, in particular to a correction circuit of a signal processing circuit and related signal processing circuits and chips, to solve the above-mentioned problems.
  • An embodiment of the present application discloses a correction circuit for generating a gain coefficient by receiving a reference signal and a delayed reference signal, wherein the delayed reference signal is generated by the reference signal after a first delay time, and It is characterized in that the correction circuit includes: a delay module for adjusting the delay reference signal to a default delay reference signal based on a preset second delay time; a first window function module for adjusting the delay reference signal according to the window function Convert the reference signal into a first converted reference signal; a second window function module for converting the delayed reference signal into a first converted delayed reference signal according to the window function; a third window function module , Used to convert the preset delay reference signal into a converted preset delay reference signal according to the window function; a first delay time calculation module, by receiving the first converted reference signal and the first A first delay time to be corrected is generated by a converted delay reference signal, wherein there is a first delay error between the first delay time to be corrected and the first delay time; a second delay time calculation module , Generating a
  • An embodiment of the present application discloses a signal processing circuit, the signal processing circuit includes: the aforementioned correction circuit; and a delay time correction module, coupled to the correction circuit, and according to the first to-be-corrected delay Time and time and the gain coefficient to generate the first delay time.
  • An embodiment of the present application discloses a signal processing circuit, the signal processing circuit includes: a fourth window function module for converting the reference signal into a second converted reference signal according to the window function; fifth The window function module is used to convert the delay reference signal into a second converted delay reference signal according to the window function; a third delay time calculation module receives the second converted reference signal and the The second converted delay reference signal generates a third delay time to be corrected, wherein there is a third delay error between the third delay time to be corrected and the first delay time; the aforementioned correction circuit; and The delay time correction module is coupled to the third delay time calculation module, and generates the first delay time according to the third delay time to be corrected and the gain coefficient.
  • An embodiment of the application discloses a chip.
  • the chip includes the aforementioned correction circuit.
  • An embodiment of the application discloses a chip.
  • the chip includes the aforementioned signal processing circuit.
  • the signal processing circuit disclosed in this application includes the window function module. Due to the addition of the window function module, the first delay time to be corrected generated by the signal processing circuit has a ratio of the first delay error to the first delay time to be corrected, which is essentially a constant value Characteristics. Based on the characteristic that the ratio is essentially a constant value, the gain coefficient related to the ratio can be generated through the correction circuit, and then the first delay time to be corrected is corrected according to the gain coefficient to generate a correction After the delay time.
  • the delay error of the corrected delay time remains substantially zero or approaches zero when the corrected delay time changes. Accordingly, regardless of the degree of delay of the first delay time, the corrected delay time can relatively accurately reflect the first delay time. Therefore, the accuracy of the corrected delay time is relatively high.
  • the signal waveform diagram of FIG. 1 illustrates the case where the end points of the signal envelopes of the reference signal and the delayed signal are non-zero values.
  • the simulation diagram of FIG. 2 illustrates the relationship between the delay error and the delay time obtained by directly performing the cross-correlation operation on the reference signal and the delay signal of FIG. 1.
  • FIG. 3 is a block diagram of an embodiment of the signal processing circuit of this application.
  • the simulation schematic diagram of FIG. 4 illustrates the relationship between the third delay time to be corrected and the delay error of the third delay time to be corrected generated by the signal processing circuit of the present application.
  • FIG. 5 is a block diagram of an embodiment of the correction circuit of the signal processing circuit of the present application.
  • the simulation diagram of FIG. 6 illustrates the relationship between the delay error and the delay time obtained according to FIG. 2 and FIG. 4.
  • FIG. 7 is a block diagram of another embodiment of the signal processing circuit of this application.
  • first and second features are in direct contact with each other; and may also include
  • additional components are formed between the above-mentioned first and second features, so that the first and second features may not be in direct contact.
  • present disclosure may reuse component symbols and/or labels in multiple embodiments. Such repeated use is based on the purpose of brevity and clarity, and does not in itself represent the relationship between the different embodiments and/or configurations discussed.
  • spatially relative terms here such as “below”, “below”, “below”, “above”, “above” and similar, may be used to facilitate the description of the drawing
  • the relationship between one component or feature relative to another component or feature is shown.
  • these spatially relative terms also cover a variety of different orientations in which the device is in use or operation.
  • the device may be placed in other orientations (for example, rotated by 90 degrees or in other orientations), and these spatially-relative description words should be explained accordingly.
  • Cross-correlation (cross-correlation) technology is currently a common method for measuring the delay time between two signals.
  • the hardware implementing the cross-correlation technology includes, for example, a cross-correlation module, a peak search module, and a conversion module for converting tap delay to delay time.
  • the operation of the cross-correlation technology includes, for example, the cross-correlation module first performs a cross-correlation operation between a reference signal (reference signal) and a delayed signal (delayed signal), where the delayed reference signal is generated by the reference signal after a delay time.
  • the peak search module searches for the peak of the cross-correlation result.
  • the conversion module converts the index (index) corresponding to the peak value to the time according to the sampling frequency (sampling frequency), it becomes the aforementioned delay time.
  • the difference between the reference signal and the delayed signal is only the delay time between the two.
  • the waveform and amplitude of the two are approximately the same, the degree of mutual correlation between the two is relatively high.
  • the storage space of the memory (memory) used to store the reference signal and the delay signal is given and therefore limited. Therefore, the end-point of the signal envelope of the reference signal stored in the storage space and the end-point of the signal envelope of the delayed signal may both be non-zero in amplitude, or even both The difference between the end points of the signal may be close to the peak value of the reference signal or the peak value of the delayed signal, as shown in Figure 1.
  • the signal waveform diagram of FIG. 1 illustrates the case where the end points of the signal envelopes of the reference signal and the delayed signal are non-zero values.
  • the horizontal axis represents time, and the unit is seconds; and the vertical axis represents amplitude, and the unit can be any unit. 1, the amplitude of the end point Ep1 of the reference signal is a non-zero value, and the amplitude of the end point Ep2 of the delay signal is a non-zero value.
  • the simulation schematic diagram of FIG. 2 illustrates the relationship between the delay error and the delay time obtained by directly performing the cross-correlation operation on the reference signal and the delay signal of FIG. 1.
  • the vertical axis represents the delay time in seconds; and the horizontal axis represents the delay error in seconds.
  • the relationship between the delay error and the delay time is relatively complicated, because the delay error will vary with the amplitude of the end points Ep1 and Ep2 .
  • the accuracy of the delay time obtained by directly performing the cross-correlation operation on the reference signal whose end point amplitude is a non-zero value and the delay signal is relatively low.
  • the delay error is difficult to achieve a certain accuracy, such as about 100 picoseconds (ps).
  • Method one is to increase the storage space of the memory to store the complete reference signal and the complete delay signal.
  • the amplitudes of the start and end points of the complete reference signal and the complete delay signal approach zero. Therefore, the problem illustrated in Figure 2 does not occur.
  • the second method is to reduce the number of pulse waves generated by the excitation source of the ultrasonic transducer, thereby shortening the length of the reference signal and the length of the delay signal, so that the shortened reference signal and the shortened delay signal can be stored completely In the given storage space.
  • the method of increasing the storage space of the memory in the first method will not only increase the cost, but also increase the running time of the entire system, which in turn will increase the power consumption of the entire system.
  • the length of the reference signal and the length of the delayed signal are shortened, but the noise of the entire system remains unchanged. Therefore, the signal-to-noise ratio of the reference signal and the signal-to-noise ratio of the delayed signal are significantly reduced, resulting in an increase in the delay error.
  • FIG. 3 is a block diagram of an embodiment of the signal processing circuit 10 of this application.
  • the signal processing circuit 10 includes a fourth window function module 104, a fifth window function module 105, a third delay time calculation module 123, a correction circuit 140, and a delay time correction module 160.
  • the fourth window function module 104 is used to convert the reference signal S ref into a fourth converted reference signal S 4 according to the window function.
  • the window function includes triangular window, Hann Window, Hamming Window, Blackman Window, Blackman-Harris Window, Flat Window Top window (Flattopwin Window), cosine window or Gaussian window. Based on the principle of the window function, the amplitudes of the start point and the end point of the signal envelope of the fourth converted reference signal S 4 approach zero.
  • the fifth window function module 105 is used to convert the delayed reference signal S D1 into a fifth converted delayed reference signal S 5 according to the window function.
  • the delayed reference signal S D1 is generated by the reference signal S ref after a first delay time.
  • the first delay time is the time parameter desired by the circuit designer.
  • the amplitudes of the start point and the end point of the signal envelope of the fifth converted delayed reference signal S 5 approach zero.
  • two independent fourth window function modules 104 and fifth window function modules 105 are drawn, but the present application is not limited to this number.
  • two independent fourth window function modules 104 and fifth window function modules 105 can be replaced by a single window function module.
  • the two fourth window function modules 104 and the fifth window function module 105 can be implemented and replaced by more than two window function modules.
  • Third delay time calculating module 123 coupled to module 104, a fourth and a fifth window function window function module 105, by receiving a converted fourth reference signal S 4 and the fifth delay converted generating a third reference signal S 5
  • the third delay time calculation module 123 uses cross-correlation technology to operate.
  • the operation of the cross-correlation technique includes, for example, first performing a cross-correlation operation on the fourth converted reference signal S 4 and the fifth converted delayed reference signal S 5 . Next, search for the peak of the cross-correlation result. After the index (index) corresponding to the peak value is converted to the time according to the sampling frequency (sampling frequency), it is the third delay time T 3 to be corrected.
  • the linearity of the ratio of the third delay error to the third delay time T 3 to be corrected is related to the selected window function.
  • the basis window function related to the magnitude of the reference signal converted by the fourth end point S. 4 and related to the converted fifth delay end point of the amplitude of the reference signal S 5 is close to zero. Therefore, the degree of cross-correlation between the fourth converted reference signal S 4 and the fifth converted delayed reference signal S 5 is relatively high. Perform cross-correlation operation on such fourth converted reference signal S 4 and fifth converted delayed reference signal S 5 , and the delay error of the third to-be-corrected delay time T 3 can be better predicted, such as Shown in Figure 4.
  • FIG 4 is a schematic diagram illustrating an analog of the present application the third delay time of the signal processing circuit 10 calculates the relationship between the delay time to be corrected third block 123 generates the T 3 to be corrected with the third delay time T 3 of the third delay error .
  • the vertical axis represents the third delay time T 3 to be corrected, in seconds; and the horizontal axis represents the third delay error of the third delay time T 3 to be corrected, in seconds.
  • the relationship between the third delay error and the third delay time T 3 to be corrected is relatively simple, compared to the relationship between the delay error and the corrected delay time shown in FIG. 2.
  • the ratio of the delay error of the delay time to the delay time may be referred to as the error gain.
  • the ratio of the third delay error to the third delay time T 3 to be corrected remains substantially unchanged when the third delay time T 3 to be corrected changes, that is, it is related to the third delay time to be corrected.
  • the error gain of the delay time T 3 is close to linear.
  • the gain coefficient related to the third delay time T 3 to be corrected is generated, and then based on the third delay time to be corrected T 3 and its gain coefficient produce the corrected delay time T K. Remains substantially the corrected delay time T K delay after the delay error correction time T K is changed to zero, or close to zero, described in detail in FIG. Accordingly, regardless of the delay degree of the first delay time, the corrected delay time T K can relatively accurately reflect the first delay time. Therefore, the accuracy of the delay time T K after correction is relatively high.
  • the correction circuit 140 is used to generate the gain coefficient ⁇ related to the third delay time T 3 to be corrected by receiving the reference signal S ref and the delayed reference signal S D1 .
  • the delay time correction module 160 is coupled to the correction circuit 140 and the third delay time calculation module 123, and generates a corrected delay time T K based on the correction coefficient ⁇ and the third delay time T 3 to be corrected. Since the relationship between the third delay error and the third delay time T 3 to be corrected is relatively simple, regardless of the degree of delay of the first delay time, the corrected delay time T K can relatively accurately reflect the first delay time. Delay time.
  • FIG. 5 is a block diagram of an embodiment of the correction circuit 140 of the signal processing circuit 10 of this application.
  • the correction circuit 140 includes a first window function module 101, a second window function module 102, a third window function module 103, a first delay time calculation module 121, a second delay time calculation module 122, and a delay module 180 and calculation module 190.
  • the first window function module 101 is used to convert the reference signal S ref into the first converted reference signal S 1 according to the window function. Based on the principle of the window function, the amplitudes of the start point and the end point of the signal envelope of the first converted reference signal S 1 approach zero.
  • the second window function module 102 is used to convert the delayed reference signal SD1 into a second converted delayed reference signal S 2 according to the window function. Based on the principle of the window function, the amplitudes of the start point and the end point of the signal envelope of the second converted delayed reference signal S 2 approach zero.
  • the third window function module 103 is used to convert the preset delay reference signal S D2 into a third converted preset delay reference signal S 3 according to the window function, wherein the delay module 108 changes the preset delay time based on the preset second delay time
  • the delayed reference signal S D1 is adjusted to the preset delayed reference signal S D2 .
  • the second delay time is known and can be designed by the circuit designer. In some embodiments, the second delay time is one or more sampling periods.
  • the first delay time calculation module 121 generates a first delay time T 1 to be corrected by receiving the first converted reference signal S 1 and the second converted delayed reference signal S 2 , wherein the first delay time to be corrected T 1 There is a first delay error between and the first delay time.
  • the first delay error is substantially the same as the third delay error.
  • the operating principle of the first delay time calculation module 121 is the same as that of the third delay time calculation module 123, and will not be repeated here.
  • the linearity of the ratio of the first delay error to the first delay time T 1 to be corrected is related to the selected window function and the first waiting time
  • the time characteristic of the correction delay time T 1 relatively accurately reflects the time characteristic of the first delay time.
  • the second delay time calculation module 122 generates a second to-be-corrected delay time T 2 by receiving the first converted reference signal S 1 and the third converted preset delay reference signal S 3 , where the second delay time and the first There is a second delay error between the sum of a delay time and the second delay time T 2 to be corrected.
  • the operating principle of the second delay time calculation module 122 is the same as that of the third delay time calculation module 123, which will not be repeated here.
  • the linearity of the ratio of the second delay error to the second delay time T 2 to be corrected is related to the selected window function and the second delay time
  • the time characteristic of the correction delay time T 2 relatively accurately reflects the time characteristic of the sum of the first delay time and the second delay time.
  • the ratio of the second delay error to the second delay time T 2 to be corrected is substantially the same as the ratio of the first delay error to the first delay time T 1 to be corrected, and is substantially the same as the third delay error.
  • the ratio of the delay error to the third delay time T 3 to be corrected is substantially the same as the third delay error.
  • the calculation module 190 is coupled to the first delay time calculation module 121 and the second delay time calculation module 122, and is used to calculate the gain coefficient based on the first delay time T 1 to be corrected and the second delay time T 2 to be corrected ⁇ .
  • the calculation module 190 includes a plurality of logic operation circuits to implement the following equation (1) to calculate the gain coefficient ⁇ .
  • the gain coefficient ⁇ can be expressed as follows:
  • T 1 represents the first delay time to be corrected
  • T 2 represents the second delay time to be corrected
  • M represents the second delay time
  • the gain coefficient related to the first delay time T 1 to be corrected is substantially constant and the gain coefficient related to the second delay time T 2 to be corrected is substantially constant, the gain coefficient ⁇ can be regarded as a constant. Accordingly, the difference between the first delay time T 1 to be corrected and the second delay time T 2 to be corrected is proportional to the second delay time M. Furthermore, because the second delay time M is substantially constant, the difference between the first delay time T 1 to be corrected and the second delay time T 2 to be corrected is proportional to the gain coefficient ⁇ .
  • gain coefficient ⁇ can also be expressed as the following equation (2):
  • G represents the ratio of the first delay error to the first delay time to be corrected.
  • the delay time correction module 160 generates the corrected delay time T K based on the correction coefficient ⁇ and the third delay time to be corrected T 3 .
  • the delay time correction module 160 includes a plurality of logic operation circuits to implement the following equation (3) to calculate the corrected delay time T K.
  • the delay time T K after correction is expressed as follows:
  • T K represents the delay time after correction
  • the first delay time calculation module 121 and the second delay time calculation module 122 each include a cross-correlation module, a peak search module coupled to the cross-correlation module, and a conversion module coupled to the peak search module.
  • the cross-correlation module of the first delay time calculation module 121 performs a cross-correlation operation on the first converted reference signal S 1 and the second converted delayed reference signal S 2 .
  • the peak search module of the first delay time calculation module 121 searches for the peak value of the cross-correlation result provided by the cross-correlation module of the first delay time calculation module 121.
  • the conversion module of the first delay time calculation module 121 converts the peak value provided by the peak search module of the first delay time calculation module 121 into the first to-be-corrected delay time T 1 .
  • the cross-correlation module of the second delay time calculation module 122 performs a cross-correlation operation on the first converted reference signal S 1 and the third converted preset delay reference signal S 3 .
  • the peak searching module of the second delay time calculation module 122 searches for the peak value of the cross-correlation result provided by the cross-correlation module of the second delay time calculation module 122.
  • the conversion module of the second delay time calculation module 122 converts the peak value provided by the peak search module of the second delay time calculation module 122 into the second to-be-corrected delay time T 2 .
  • the simulation diagram of Fig. 6 illustrates the relationship between the delay error and the delay time obtained according to Fig. 2 and Fig. 4.
  • the simulation result 1 corresponds to the simulation result of Fig. 2, that is, the reference signal and the delay signal are directly cross-correlated Operation, the relationship between the delay error obtained by the window function conversion and the delay time;
  • the simulation result 2 is the corrected simulation result corresponding to Fig. 4, that is, the relationship between the delay error obtained by the window function conversion and the delay time.
  • the vertical axis represents the delay time, in seconds; and the horizontal axis represents the delay error of the delay time, in seconds.
  • the delay error of the corrected delay time T K of the simulation result 1 remains substantially unchanged or approaches zero when the corrected delay time T K changes. Accordingly, regardless of the delay degree of the first delay time, the corrected delay time T K can relatively accurately reflect the first delay time. Therefore, the accuracy of the delay time T K after correction is relatively high.
  • the delay time calculated by directly performing the cross-correlation operation on the reference signal and the delay signal because the delay error will vary with the magnitude of the end point. Therefore, the accuracy of the delay time obtained by directly performing the cross-correlation operation on the reference signal with such an end point and the delay signal is relatively low.
  • the delay error is difficult to achieve a certain accuracy, for example, about 100 picoseconds.
  • FIG. 7 is a block diagram of another embodiment of the signal processing circuit 20 of this application.
  • the signal processing circuit 20 is formed by integrating blocks and circuits with the same functions in the correction circuit 140 of Fig. 5 and the signal processing circuit 10 of Fig. 3.
  • the circuit structure of the signal processing circuit 20 is similar to the circuit structure of the correction circuit 140 in FIG. 5, the difference is that the signal processing circuit 20 includes a sixth delay time calculation module 221.
  • the function of the sixth delay time calculation module 221 is similar to that of the first delay time calculation module 121 of FIG. 5, except that the sixth delay time calculation module 221 provides the first delay time T 1 to the delay time
  • the time correction module 160 is also provided to the calculation module 190.
  • the above-mentioned signal processing circuit 10 may be implemented using a semiconductor process.
  • this application proposes another chip including the signal processing circuit 10, and the chip may be a semiconductor chip implemented by a different process.
  • the above-mentioned signal processing circuit 20 may be implemented using a semiconductor process.
  • this application proposes another chip including the signal processing circuit 20, and the chip may be a semiconductor chip implemented by a different process.
  • the above-mentioned correction circuit 140 may be implemented using a semiconductor process.
  • this application proposes another chip that includes the correction circuit 140, and the chip may be a semiconductor chip implemented by a different process.

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Abstract

一种校正电路(140)，所述校正电路(140)包括：延时模块(180)，用来产生预设延时参考信号(S D2)；第一窗函数模块(101)，用来将参考信号(S ref)转换为经转换参考信号(S 1)；第二窗函数模块(102)，用来将延时参考信号(S D1)转换为经转换延时参考信号(S 2)；第三窗函数模块(103)，用来将所述预设延时参考信号(S D2)转换为经转换预设延时参考信号(S 3)；第一延时时间计算模块(121)，通过接收所述经转换参考信号(S 1)及所述经转换延时参考信号(S 2)产生第一待校正延时时间(T 1)；第二延时时间计算模块(122)，通过接收所述经转换参考信号(S 1)及所述经转换预设延时参考信号(S 3)产生第二待校正延时时间(T 2)；以及计算模块(190)，用来基于所述第一待校正延时时间(T 1)及所述第二待校正延时时间(T 2)计算出增益系数(λ)。

Description

校正电路以及相关信号处理电路及芯片 技术领域
本申请涉及一种校正电路，尤其涉及一种信号处理电路的校正电路以及相关信号处理电路及芯片。
背景技术
在超声波流量计(ultrasonic flow meter)的应用中，需透过量测流体的流速推得流量，而量测流速最重要的量测参数是超声波在流体中的延时时间(delay time)。现有技术在量测延时时间上存在相对显着的误差，因此无法产生高准确度(high-precision)延时时间。有鉴于此，需要进一步改良及创新以改善上述情况。
发明内容
本申请的目的之一在于公开一种校正电路，尤其涉及一种信号处理电路的校正电路以及相关信号处理电路及芯片，来解决上述问题。
本申请的一实施例公开了一种校正电路，用来通过接收参考信号以及延时参考信号产生增益系数，其中所述延时参考信号为所述参考信号经过第一延时时间而产生，其特征在于，所述校正电路包括：延时模块，用来基于预设的第二延时时间将所述延时参考信号调整为默认延时参考信号；第一窗函数模块，用来依据窗函数将所述参考信号转换为第一经转换参考信号；第二窗函数模块，用来依据所述窗函数将所述延时参考信号转换为第一经转换延时参考信号；第三窗函数模块，用来依据所述窗函数将所述预设延时参考信号转 换为经转换预设延时参考信号；第一延时时间计算模块，通过接收所述第一经转换参考信号及所述第一经转换延时参考信号产生第一待校正延时时间，其中所述第一待校正延时时间和所述第一延时时间之间具有第一延时误差；第二延时时间计算模块，通过接收所述第一经转换参考信号及所述经转换预设延时参考信号产生第二待校正延时时间；以及计算模块，用来基于所述第一待校正延时时间及所述第二待校正延时时间计算出所述增益系数。
本申请的一实施例公开了一种信号处理电路，所述信号处理电路包括：前述的校正电路；以及延时时间校正模块，耦接于所述校正电路，并依据所述第一待校正延时时间以及所述增益系数来产生所述第一延时时间。
本申请的一实施例公开了一种信号处理电路，所述信号处理电路包括：第四窗函数模块，用来依据所述窗函数将所述参考信号转换为第二经转换参考信号；第五窗函数模块，用来依据所述窗函数将所述延时参考信号转换为第二经转换延时参考信号；第三延时时间计算模块，通过接收所述第二经转换参考信号及所述第二经转换延时参考信号产生第三待校正延时时间，其中所述第三待校正延时时间和所述第一延时时间之间具有第三延时误差；前述的校正电路；以及延时时间校正模块，耦接于所述第三延时时间计算模块，并依据所述第三待校正延时时间以及所述增益系数来产生所述第一延时时间。
本申请的一实施例公开了一种芯片。所述芯片包括前述的校正电路。
本申请的一实施例公开了一种芯片。所述芯片包括前述的信号处理电路。
本申请所公开的信号处理电路包括所述窗函数模块。由于所述窗函数模块的加入，所述信号处理电路产生的所述第一待校正延时时间具有所述第一延时误差和所述第一待校正延时时间的比值实质上为定值的特性。基于所述比值实质上为定值的特性，能透过所述 校正电路产生相关于所述比值的所述增益系数，再根据所述增益系数校正所述第一待校正延时时间以产生校正后延时时间。所述校正后延时时间的延时误差在所述校正后延时时间改变时实质上保持为零，或趋近于零。据此，无论所述第一延时时间的延时程度大小，所述校正后延时时间均能相对准确的反应出所述第一延时时间。因此，所述校正后延时时间的准确度相对较高。
附图说明
图1的信号波形图说明参考信号与延时信号的信号包络的结束点为非零数值的情况。
图2的模拟示意图说明对图1的参考信号与延时信号直接进行互相关运算得到的延时误差对延时时间的关系。
图3为本申请信号处理电路的实施例的方块示意图。
图4的模拟示意图说明本申请信号处理电路产生的第三待校正延时时间与第三待校正延时时间的延时误差的关系。
图5为本申请信号处理电路的校正电路的实施例的方块示意图。
图6的模拟示意图说明依据图2与图4得到的延时误差对延时时间的关系。
图7为本申请另一信号处理电路的实施例的方块示意图。
其中，附图标记说明如下：
10                       信号处理电路
101                      第一窗函数模块
102                      第二窗函数模块
103                      第三窗函数模块
104                      第四窗函数模块
105                      第五窗函数模块
121                      第一延时时间计算模块
122                      第二延时时间计算模块
123                      第三延时时间计算模块
140                      校正电路
160                      延时时间校正模块
20                       信号处理电路
221                      第六延时时间计算模块
S ref                     参考信号
S D1                      延时参考信号
S D2                      预设延时参考信号
S 1                       第一经转换参考信号
S 2                       第一经转换延时参考信号
S 3                       第二经转换预设延时参考信号
S 4                       第四经转换参考信号
S 5                       第五经转换延时参考信号
T 1                       第一待校正延时时间
T 2                       第二待校正延时时间
T 3                       第三待校正延时时间
T K                       校正后延时时间
λ                       增益系数
E P1                      结束点
E P2                      结束点
具体实施方式
以下揭示内容提供了多种实施方式或例示，其能用以实现本揭示内容的不同特征。下文所述之组件与配置的具体例子系用以简化本揭示内容。当可想见，这些叙述仅为例示，其本意并非用于限制本揭示内容。举例来说，在下文的描述中，将一第一特征形成于一第二特征上或之上，可能包括某些实施例其中所述的第一与第二特征彼此直接接触；且也可能包括某些实施例其中还有额外的组件形 成于上述第一与第二特征之间，而使得第一与第二特征可能没有直接接触。此外，本揭示内容可能会在多个实施例中重复使用组件符号和/或标号。此种重复使用乃是基于简洁与清楚的目的，且其本身不代表所讨论的不同实施例和/或组态之间的关系。
再者，在此处使用空间上相对的词汇，譬如「之下」、「下方」、「低于」、「之上」、「上方」及与其相似者，可能是为了方便说明图中所绘示的一组件或特征相对于另一或多个组件或特征之间的关系。这些空间上相对的词汇其本意除了图中所绘示的方位之外，还涵盖了装置在使用或操作中所处的多种不同方位。可能将所述设备放置于其他方位(如，旋转90度或处于其他方位)，而这些空间上相对的描述词汇就应该做相应的解释。
虽然用以界定本申请较广范围的数值范围与参数皆是约略的数值，此处已尽可能精确地呈现具体实施例中的相关数值。然而，任何数值本质上不可避免地含有因个别测试方法所致的标准偏差。在此处，「约」通常系指实际数值在一特定数值或范围的正负10％、5％、1％或0.5％之内。或者是，「约」一词代表实际数值落在平均值的可接受标准误差之内，视本申请所属技术领域中具有通常知识者的考虑而定。当可理解，除了实验例之外，或除非另有明确的说明，此处所用的所有范围、数量、数值与百分比(例如用以描述材料用量、时间长短、温度、操作条件、数量比例及其他相似者)均经过「约」的修饰。因此，除非另有相反的说明，本说明书与附随申请专利范围所揭示的数值参数皆为约略的数值，且可视需求而更动。至少应将这些数值参数理解为所指出的有效位数与套用一般进位法所得到的数值。在此处，将数值范围表示成由一端点至另一端点或介于二端点之间；除非另有说明，此处所述的数值范围皆包括端点。
互相关(cross-correlation)技术是目前常见的用于量测两个信号间的延时时间的方法。实现互相关技术的硬件例如包括互相关模块、峰值搜寻(peak search)模块以及用于将抽头延时(tap delay)转换到延时时间的转换模块。互相关技术的操作包括，例如:互相关 模块先将参考信号(reference signal)与延时信号(delayed signal)进行互相关运算，其中延时参考信号为参考信号经过延时时间而产生。接着，峰值搜寻模块搜寻互相关结果的峰值。转换模块将该峰值所对应的指标(index)根据取样频率(sampling frequency)转换到时间后，即为上述的延时时间。
理想上，参考信号及延时信号之间的区别仅为两者之间的延时时间。又，因为两者的例如波形及幅值大致上相同，因此两者互相关程度是相对高的。然而，在实际应用上，因成本考虑，用于储存参考信号与延时信号的内存(memory)的存储空间是给定的并因此受限。因此，存储在存储空间的参考信号的信号包络(signal envelope)的结束点(end-point)与延时信号的信号包络的结束点在幅值上均可能为非零数值，甚至两者的结束点的差值还可能接近参考信号的峰值或延时信号的峰值，如图1所示。
图1的信号波形图说明参考信号与延时信号的信号包络的结束点为非零数值的情况。横轴代表时间，单位为秒；以及纵轴代表幅值，单位可为任意单位。参照图1，参考信号的结束点E P1的幅值为非零数值，以及延时信号的结束点E P2的幅值为非零数值。
在这种情况下，由于结束点E P1及E P2的幅值为非零数值，因此参考信号与延时信号两者互相关程度是相对低的。若对这样的参考信号与延时信号直接进行互相关运算，得到的延时时间的延时误差将会难以预测，如图2所示。据此得到的延时时间的准确度会相对的低。
图2的模拟示意图说明对图1的参考信号与延时信号直接进行互相关运算得到的延时误差对延时时间的关系。纵轴代表延时时间，单位为秒；以及横轴代表延时误差，单位为秒。参照图2，延时误差对延时时间的关系相对的复杂，这是因为延时误差会随着结束点E P1及E P2的幅值大小而变化。综上所述，对结束点的幅值为非零数值的参考信号与延时信号直接进行互相关运算所得到的延时时间的准确度相对的低。延时误差难以达到一定的精准度，例如约100皮 秒(picosecond，ps)。
可采用以下两种方法解决上述问题。方法一，增加内存的存储空间以存储完整的参考信号与完整的延时信号。完整的参考信号与完整的延时信号各自的起始点与结束点的幅值趋近于零。因此，不会发生如图2所说明的问题。方法二，减少超声波传感器(ultrasonic transducer)的激发源产生的脉波的数量，藉此缩短参考信号的长度与延时信号的长度，以使缩短的参考信号及缩短的延时信号能完整的存储在给定的存储空间中。
然而，方法一的增加内存的存储空间的方式不但会使成本变高，还会增长整个系统的运行时间，进而导致整个系统的功耗增加。在方法二中，参考信号的长度与延时信号的长度被缩短，但整个系统的噪声维持不变。因此，参考信号的信噪比与延时信号的信噪比被显着的降低，进而导致延时误差的增加。
图3为本申请信号处理电路10的实施例的方块示意图。参照图3，信号处理电路10包括第四窗函数模块104、第五窗函数模块105、第三延时时间计算模块123、校正电路140以及延时时间校正模块160。
第四窗函数模块104用来依据窗函数将参考信号S ref转换为第四经转换参考信号S 4。在一些实施例中，窗函数包括三角窗、汉宁窗(Hann Window)、汉明窗(Hamming Window)、布莱克曼窗(Blackman Window)、布莱克曼-哈里斯窗(Blackman-Harris Window)、平顶窗(Flattopwin Window)、余弦窗或高斯窗。基于窗函数的原理，第四经转换参考信号S 4的信号包络的起始点与结束点的幅值趋近于零。
第五窗函数模块105用来依据窗函数将延时参考信号S D1转换为第五经转换延时参考信号S 5。延时参考信号S D1为参考信号S ref经过第一延时时间而产生。第一延时时间为电路设计者欲求得的时间参数。同理，基于窗函数的原理，第五经转换延时参考信号S 5的信号包络的起始点与结束点的幅值趋近于零。应注意的是，在本实施例中，系绘示出两个相互独立的第四窗函数模块104及第五窗函数模 块105，然而本申请不以此数量为限。在一些实施例中，两个相互独立的第四窗函数模块104及第五窗函数模块105可被单一个窗函数模块所取代。或者，两个第四窗函数模块104及第五窗函数模块105可通过数量超过二的窗函数模块来实施及取代。
第三延时时间计算模块123，耦接于第四窗函数模块104及第五窗函数模块105、通过接收第四经转换参考信号S 4及第五经转换延时参考信号S 5产生第三待校正延时时间T 3。第三待校正延时时间T 3和第一延时时间之间具有第三延时误差。详言之，第三延时时间计算模块123采用互相关技术进行操作。互相关技术的操作包括，例如:先将第四经转换参考信号S 4与第五经转换延时参考信号S 5进行互相关运算。接着，搜寻互相关结果的峰值。该峰值对应的指标(index)根据取样频率(sampling frequency)转换到时间后，即为上述的第三待校正延时时间T 3。
此外，由于第三待校正延时时间T 3系基于窗函数而得，第三延时误差和第三待校正延时时间T 3的比值的线性度相关于上述选用的窗函数。详言之，基于窗函数，相关于第四经转换参考信号S 4的结束点的幅值及相关于第五经转换延时参考信号S 5的结束点的幅值趋近于零。因此，第四经转换参考信号S 4及第五经转换延时参考信号S 5两者互相关程度是相对高的。对这样的第四经转换参考信号S 4及第五经转换延时参考信号S 5进行互相关运算，得到的第三待校正延时时间T 3的延时误差能被较佳地预测，如图4所示。
图4的模拟示意图说明本申请信号处理电路10的第三延时时间计算模块123产生的第三待校正延时时间T 3与第三待校正延时时间T 3的第三延时误差的关系。纵轴代表第三待校正延时时间T 3，单位为秒；以及横轴代表第三待校正延时时间T 3的第三延时误差，单位为秒。参照图4，第三延时误差对第三待校正延时时间T 3的关系相对的简单，相对于图2显示的延时误差对校正延时时间的关系。在下文中，于适当处，延时时间的延时误差对延时时间的比值可称为误差增益。在一些实施例中，第三延时误差和第三待校正延时时间 T 3的比值在第三待校正延时时间T 3改变时实质上保持不变，亦即，相关于第三待校正延时时间T 3的误差增益趋近于线性。利用第三延时误差对第三待校正延时时间T 3的关系相对的简单的特性，通过产生相关于第三待校正延时时间T 3的增益系数，再基于第三待校正延时时间T 3及其增益系数产生出校正后延时时间T K。校正后延时时间T K的延时误差在校正后延时时间T K改变时实质上保持为零，或趋近于零，详细说明于图6。据此，无论第一延时时间的延时程度大小，校正后延时时间T K均能相对准确的反应出第一延时时间。因此，校正后延时时间T K的准确度相对较高。
参回至图3，校正电路140用来通过接收参考信号S ref和延时参考信号S D1产生出相关于第三待校正延时时间T 3的增益系数λ。
延时时间校正模块160耦接于校正电路140及第三延时时间计算模块123，并基于校正系数λ和第三待校正延时时间T 3产生出校正后延时时间T K。由于第三延时误差对第三待校正延时时间T 3的关系相对的简单，无论第一延时时间的延时程度大小，校正后延时时间T K均能相对准确的反应出第一延时时间。
图5为本申请信号处理电路10的校正电路140的实施例的方块示意图。参照图5，校正电路140包括第一窗函数模块101、第二窗函数模块102、第三窗函数模块103、第一延时时间计算模块121、第二延时时间计算模块122、延时模块180及计算模块190。
第一窗函数模块101用来依据窗函数将参考信号S ref转换为第一经转换参考信号S 1。基于窗函数的原理，第一经转换参考信号S 1的信号包络的起始点与结束点的幅值趋近于零。
第二窗函数模块102用来依据窗函数将延时参考信号 SD1转换为第二经转换延时参考信号S 2。基于窗函数的原理，第二经转换延时参考信号S 2的信号包络的起始点与结束点的幅值趋近于零。
第三窗函数模块103用来依据窗函数将预设延时参考信号S D2转换为第三经转换预设延时参考信号S 3，其中延时模块108基于预 设的第二延时时间将延时参考信号S D1调整为预设延时参考信号S D2。第二延时时间为已知，并可为电路设计者所设计。在一些实施例中，第二延时时间为一或多个取样周期。
第一延时时间计算模块121通过接收第一经转换参考信号S 1及第二经转换延时参考信号S 2产生第一待校正延时时间T 1，其中第一待校正延时时间T 1和第一延时时间之间具有第一延时误差。在一些实施例中，第一延时误差实质相同于第三延时误差。第一延时时间计算模块121的操作原理相同于第三延时时间计算模块123，于此不再赘述。此外，由于第一待校正延时时间T 1系基于窗函数而得，第一延时误差和第一待校正延时时间T 1的比值的线性度相关于上述选用的窗函数且第一待校正延时时间T 1的时间特性能相对准确的反应出第一延时时间的时间特性。
第二延时时间计算模块122通过接收第一经转换参考信号S 1及第三经转换预设延时参考信号S 3产生第二待校正延时时间T 2，其中第二延时时间及第一延时时间的总和与第二待校正延时时间T 2之间具有第二延时误差。第二延时时间计算模块122的操作原理相同于第三延时时间计算模块123，于此不再赘述。此外，由于第二待校正延时时间T 2系基于窗函数而得，第二延时误差和第二待校正延时时间T 2的比值的线性度相关于上述选用的窗函数且第二待校正延时时间T 2的时间特性能相对准确的反应出第一延时时间及第二延时时间的总和的时间特性。在一些实施例中，第二延时误差和第二待校正延时时间T 2的比值实质相同于第一延时误差和第一待校正延时时间T 1的比值，且实质相同于第三延时误差和第三待校正延时时间T 3的比值。
计算模块190耦接于第一延时时间计算模块121及第二延时时间计算模块122，并用来基于第一待校正延时时间T 1及第二待校正延时时间T 2计算出增益系数λ。在一些实施例中，计算模块190包括复数个逻辑运算电路以实现下方的方程式(1)来计算出增益系数λ。增益系数λ可表示如下：
Figure PCTCN2019078254-appb-000001
，其中λ代表所述增益系数；T 1代表第一待校正延时时间；T 2代表第二待校正延时时间；以及M代表所述第二延时时间。
由于相关于第一待校正延时时间T 1的增益系数实质上为常数及以及相关于第二待校正延时时间T 2的增益系数实质上为常数，因此增益系数λ可视为常数。据此，第一待校正延时时间T 1及第二待校正延时时间T 2的差值与第二延时时间M成正比。又，因为第二延时时间M实质上为常数，因此第一待校正延时时间T 1及第二待校正延时时间T 2的差值与增益系数λ成正比。
又，增益系数λ还可表示如下方的方程式(2)：
λ＝(1+G)  (2)
，其中G代表第一延时误差和第一待校正延时时间的比值。
再参回至图3，延时时间校正模块160基于校正系数λ和基于第三待校正延时时间T 3产生出校正后延时时间T K。在一些实施例中，延时时间校正模块160包括复数个逻辑运算电路以实现下方的方程式(3)来计算出校正后延时时间T K。校正后延时时间T K表示如下：
Figure PCTCN2019078254-appb-000002
，其中T K代表校正后延时时间。
在本实施例中，第一延时时间计算模块121及第二延时时间计算模块122各包括互相关模块、耦接于互相关模块的峰值搜寻模块以及耦接于峰值搜寻模块的转换模块。
第一延时时间计算模块121的互相关模块对所述第一经转换参考信号S 1及第二经转换延时参考信号S 2进行互相关运算。第一延时时间计算模块121的峰值搜寻模块搜寻第一延时时间计算模块121 的互相关模块提供的互相关结果的峰值。第一延时时间计算模块121的转换模块将第一延时时间计算模块121的峰值搜寻模块提供的峰值转换为第一待校正延时时间T 1。
第二延时时间计算模块122的互相关模块对第一经转换参考信号S 1及第三经转换预设延时参考信号S 3进行互相关运算。第二延时时间计算模块122的峰值搜寻模块搜寻第二延时时间计算模块122的互相关模块提供的互相关结果的峰值。第二延时时间计算模块122的转换模块将第二延时时间计算模块122的峰值搜寻模块提供的峰值转换为第二待校正延时时间T 2。
图6的模拟示意图说明依据图2与图4得到的延时误差对延时时间的关系，其中模拟结果1是对应图2的模拟结果，即通过直接对参考信号及延时信号直接进行互相关运算，未经过窗函数转换得到的延时误差对延时时间的关系；模拟结果2是对应图4的校正后模拟结果，即经过窗函数转换得到的延时误差对延时时间的关系。参照图6，纵轴代表延时时间，单位为秒；以及横轴代表延时时间的延时误差，单位为秒。如图6所示，模拟结果1的校正后延时时间T K的延时误差在校正后延时时间T K改变时，相较于未经校正的模拟结果2来说变化较小，在某些实施例中，模拟结果1的校正后延时时间T K的延时误差在校正后延时时间T K改变时实质上保持不变，或趋近于零。据此，无论第一延时时间的延时程度大小，校正后延时时间T K均能相对准确的反应出第一延时时间。因此，校正后延时时间T K的准确度相对较高。
相对的，对于通过直接对参考信号及延时信号直接进行互相关运算所计算出的延时时间来说，因为延时误差会随着结束点的幅值大小而变化。因此，对具有此种结束点的参考信号与延时信号直接进行互相关运算所得到的延时时间的准确度相对较低。延时误差难以达到一定的精准度，例如约100皮秒。
图7为本申请另一信号处理电路20的实施例的方块示意图。参照图7，信号处理电路20系通过将图5的校正电路140与图3的信 号处理电路10中具有相同功能的方块及电路进行整并而成。整并后，信号处理电路20的电路架构类似于图5的校正电路140的电路架构，差别在于信号处理电路20包括第六延时时间计算模块221。
第六延时时间计算模块221的功能类似于图5的第一延时时间计算模块121，差别在于，第六延时时间计算模块221除了将第一待校正延时时间T 1提供给延时时间校正模块160，还提供给计算模块190。
在一些实施例中，上述的信号处理电路10可以使用半导体工艺来实现，例如本申请另提出一种芯片，包括信号处理电路10，且所述芯片可以是通过不同工艺来实现的半导体芯片。
在一些实施例中，上述的信号处理电路20可以使用半导体工艺来实现，例如本申请另提出一种芯片，包括信号处理电路20，且所述芯片可以是通过不同工艺来实现的半导体芯片。
在一些实施例中，上述的校正电路140可以使用半导体工艺来实现，例如本申请另提出一种芯片，包括校正电路140，且所述芯片可以是通过不同工艺来实现的半导体芯片。
上文的叙述简要地提出了本申请某些实施例之特征，而使得本申请所属技术领域具有通常知识者能够更全面地理解本揭示内容的多种态样。本申请所属技术领域具有通常知识者当可明了，其可轻易地利用本揭示内容作为基础，来设计或更动其他工艺与结构，以实现与此处所述之实施方式相同的目的和/或达到相同的优点。本申请所属技术领域具有通常知识者应当明白，这些均等的实施方式仍属于本揭示内容之精神与范围，且其可进行各种变更、替代与更动，而不会悖离本揭示内容之精神与范围。

Claims (16)

  1. 一种校正电路，用来接收参考信号以及延时参考信号，并根据参考信号以及延时参考信号产生增益系数，其中所述延时参考信号为所述参考信号经过第一延时时间而产生，其特征在于，所述校正电路包括：
    延时模块，用来基于预设的第二延时时间将所述延时参考信号调整为默认延时参考信号；
    第一窗函数模块，用来依据窗函数将所述参考信号转换为第一经转换参考信号；
    第二窗函数模块，用来依据所述窗函数将所述延时参考信号转换为第一经转换延时参考信号；
    第三窗函数模块，用来依据所述窗函数将所述预设延时参考信号转换为经转换预设延时参考信号；
    第一延时时间计算模块，通过接收所述第一经转换参考信号及所述第一经转换延时参考信号产生第一待校正延时时间，其中所述第一待校正延时时间和所述第一延时时间之间具有第一延时误差；
    第二延时时间计算模块，通过接收所述第一经转换参考信号及所述经转换预设延时参考信号产生第二待校正延时时间；以及
    计算模块，用来基于所述第一待校正延时时间及所述第二待校正延时时间计算出所述增益系数。
  2. 如权利要求1所述的校正电路，其中所述第一延时时间计算模块及所述第二延时时间计算模块各包括：互相关模块、耦接于所述互相关模块的峰值搜寻模块以及耦接于所述峰值搜寻模块的转换模块，
    其中所述第一延时时间计算模块的互相关模块对所述第一 经转换参考信号及所述第一经转换延时参考信号进行互相关运算，所述第一延时时间计算模块的峰值搜寻模块搜寻所述第一延时时间计算模块的互相关模块提供的互相关结果的峰值，所述第一延时时间计算模块的转换模块将所述第一延时时间计算模块的峰值搜寻模块提供的峰值转换为所述第一待校正延时时间，以及
    其中所述第二延时时间计算模块的互相关模块对所述第一经转换参考信号及所述经转换预设延时参考信号进行互相关运算，所述第二延时时间计算模块的峰值搜寻模块搜寻所述第二延时时间计算模块的互相关模块提供的互相关结果的峰值，所述第二延时时间计算模块的转换模块将所述第二延时时间计算模块的峰值搜寻模块提供的峰值转换为所述第二待校正延时时间。
  3. 如权利要求1所述的校正电路，其中所述第二延时时间及所述第一延时时间的总和与所述第二待校正延时时间之间具有第二延时误差。
  4. 如权利要求3所述的校正电路，其中所述第一延时误差和所述第一待校正延时时间的比值实质相同于所述第二延时误差和第二待校正延时时间的比值。
  5. 如权利要求1所述的校正电路，其中所述第一待校正延时时间及所述第二待校正延时时间的差值与所述第二延时时间成正比。
  6. 如权利要求5所述的校正电路，其中所述第一待校正延时时间及所述第二待校正延时时间的差值与所述增益系数成正比。
  7. 如权利要求6所述的校正电路，其中所述增益系数表示如下：
    Figure PCTCN2019078254-appb-100001
    ，其中T 2代表所述第二待校正延时时间；T 1代表所述第一 待校正延时时间；λ代表所述增益系数；以及M代表所述第二延时时间。
  8. 如权利要求7所述的校正电路，其中所述增益系数表示如下：
    λ＝(1+G)
    ，其中G代表所述第一延时误差和所述第一待校正延时时间的比值。
  9. 如权利要求1所述的校正电路，其中所述第一延时误差和所述第一待校正延时时间的比值的线性度相关于所述窗函数。
  10. 如权利要求9所述的校正电路，其中所述窗函数包括：三角窗、汉宁窗(Hann Window)、汉明窗(Hamming Window)、布莱克曼窗(Blackman Window)、布莱克曼-哈里斯窗(Blackman-Harris Window)、平顶窗(Flattopwin Window)、余弦窗或高斯窗。
  11. 如权利要求1所述的校正电路，其中所述第一延时时间计算模块对所述第一经转换参考信号及所述第一经转换延时参考信号施以互相关运算以产生所述第一待校正延时时间，以及所述第二延时时间计算模块对所述第一经转换参考信号及所述经转换预设延时参考信号施以所述互相关运算以产生所述第二待校正延时时间。
  12. 一种信号处理电路，其特征在于，所述信号处理电路包括：
    如权利要求1至11所述的校正电路；以及
    延时时间校正模块，耦接于所述校正电路，并依据所述第一待校正延时时间以及所述增益系数来产生校正后延时时间。
  13. 如权利要求12所述的信号处理电路，其中所述校正后延时时间表示如下：
    Figure PCTCN2019078254-appb-100002
    ，其中T K代表所述校正后延时时间；λ代表所述增益系数； 以及T 1代表所述第一待校正延时时间。
  14. 一种信号处理电路，其特征在于，所述信号处理电路包括：
    第四窗函数模块，用来依据所述窗函数将所述参考信号转换为第二经转换参考信号；
    第五窗函数模块，用来依据所述窗函数将所述延时参考信号转换为第二经转换延时参考信号；
    第三延时时间计算模块，耦接于所述第四窗函数模块及所述第五窗函数模块，并通过接收所述第二经转换参考信号及所述第二经转换延时参考信号产生第三待校正延时时间，其中所述第三待校正延时时间和所述第一延时时间之间具有第三延时误差；
    如权利要求1至11所述的校正电路；以及
    延时时间校正模块，耦接于所述第三延时时间计算模块及所述校正电路，并依据所述第三待校正延时时间以及所述增益系数来产生校正后延时时间。
  15. 一种芯片，其特征在于，所述芯片包括：
    如权利要求1-11任一项中所述的校正电路。
  16. 一种芯片，其特征在于，所述芯片包括：
    如权利要求12-14一项中所述的信号处理电路。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107879A (en) * 1996-12-06 2000-08-22 Nippon Telegraph & Telephone Corp. Automatic dynamic range control circuit
CN101023614A (zh) * 2004-07-09 2007-08-22 电力波技术公司 在采用自适应预失真技术的通信系统中校正数字定时误差的系统和方法
CN102075486A (zh) * 2011-01-20 2011-05-25 深圳市阿派斯实业有限公司 一种ofdm系统的同步方法
CN103454497A (zh) * 2013-09-10 2013-12-18 南京理工大学 基于改进加窗离散傅立叶变换的相位差测量方法
CN109215667A (zh) * 2017-06-29 2019-01-15 华为技术有限公司 时延估计方法及装置

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AUPN606095A0 (en) * 1995-10-19 1995-11-09 AGL Consultancy Pty. Limited Digital speed determination in ultrasonic flow measurements
DE19611233A1 (de) * 1996-03-21 1997-09-25 Siemens Ag Verfahren zur Laufzeitmessung eines elektrischen, elektromagnetischen oder akustischen Signals
JPH1188125A (ja) * 1997-09-03 1999-03-30 Sony Corp ディジタル制御発振回路およびｐｌｌ回路
TW538597B (en) * 1998-03-31 2003-06-21 Fujitsu General Co Ltd Phase lock loop circuit
DE19841154C2 (de) * 1998-09-09 2002-11-07 Holger Loehmer Verfahren und Vorrichtung zur Messung der Laufzeit von Schallwellen
KR100846773B1 (ko) * 2002-04-11 2008-07-16 삼성전자주식회사 워블 에러 검출 및 정정 장치와 그를 이용한 위상 동기루프 회로
JP3669580B2 (ja) * 2002-05-24 2005-07-06 学校法人慶應義塾 超音波流速分布及び流量計
JP3919176B2 (ja) * 2002-05-28 2007-05-23 シャープ株式会社 補正回路、遅延回路およびリングオシレータ回路
GB2397887A (en) * 2003-01-30 2004-08-04 Flotec Uk Ltd Ultrasonic gas composition analysis device
AT6511U3 (de) * 2003-07-16 2004-09-27 Avl List Gmbh Ultraschall-gasdurchflusssensor sowie vorrichtung zur messung von abgas-strömungen von verbrennungskraftmaschinen sowie ein verfahren zur ermittlung des durchflusses von gasen
CN100442347C (zh) * 2003-07-28 2008-12-10 索尼株式会社 延迟时间校正电路、视频数据处理电路以及平板显示设备
US8162837B2 (en) * 2005-06-13 2012-04-24 Spentech, Inc. Medical doppler ultrasound system for locating and tracking blood flow
CN101242507B (zh) * 2007-02-08 2011-08-24 佛山市顺德区顺达电脑厂有限公司 自动校时装置及其处理方法
CN101308517B (zh) * 2007-03-21 2010-12-08 台湾积体电路制造股份有限公司 检测并校正半导体装置的方法
DE112009002120B4 (de) * 2008-10-06 2015-10-01 Mitsubishi Electric Corporation Signalempfangsvorrichtung und Signalübertragungssystem
EP2356408B1 (de) * 2008-11-21 2015-07-01 Flexim Flexible Industriemesstechnik Gmbh Verfahren und vorrichtung zur kalibrierung von messumformern von ultraschall-durchflussmessgeräten
DE102009046562A1 (de) * 2009-11-10 2011-05-12 Robert Bosch Gmbh Verfahren und Vorrichtung zur Ultraschall-Laufzeitmessung
US8648612B2 (en) * 2010-07-09 2014-02-11 Rosemount Tank Radar Ab Calibration of a distance measuring device
US8837653B2 (en) * 2012-06-08 2014-09-16 Deere & Company High frequency signal receiver with self-calibrated group delay compensation
US9154263B1 (en) * 2014-03-31 2015-10-06 King Fahd University Of Petroleum And Minerals Evaluation of compressed sensing in UWB systems with NBI
US10309813B2 (en) * 2015-05-15 2019-06-04 Reliance Worldwide Corporation Method and system for fluid flow rate measurement
WO2017040267A1 (en) * 2015-08-28 2017-03-09 Soneter, Inc. Flow meter configuration and calibration
US10330508B2 (en) * 2015-12-09 2019-06-25 Texas Instruments Incorporated Ultrasonic flowmeter using windowing of received signals
FR3050828B1 (fr) * 2016-04-28 2019-06-21 Safran Aircraft Engines Procede de determination d'une vitesse d'ecoulement d'un fluide s'ecoulant dans un troncon de conduite et dispositif associe
JP2017215171A (ja) * 2016-05-30 2017-12-07 国立研究開発法人産業技術総合研究所 流速分布の計測方法及びその装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107879A (en) * 1996-12-06 2000-08-22 Nippon Telegraph & Telephone Corp. Automatic dynamic range control circuit
CN101023614A (zh) * 2004-07-09 2007-08-22 电力波技术公司 在采用自适应预失真技术的通信系统中校正数字定时误差的系统和方法
CN102075486A (zh) * 2011-01-20 2011-05-25 深圳市阿派斯实业有限公司 一种ofdm系统的同步方法
CN103454497A (zh) * 2013-09-10 2013-12-18 南京理工大学 基于改进加窗离散傅立叶变换的相位差测量方法
CN109215667A (zh) * 2017-06-29 2019-01-15 华为技术有限公司 时延估计方法及装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3751238A4 *

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