WO2020181852A1

WO2020181852A1 - Clock synchronization circuit, clock synchronization method and seabed seismograph

Info

Publication number: WO2020181852A1
Application number: PCT/CN2019/124193
Authority: WO
Inventors: 王宜志; 杨挺; 刘丹; 黄信峰; 黄志鹏; 潘谟晗; 杜浩然; 杨港
Original assignee: 南方科技大学
Priority date: 2019-03-14
Filing date: 2019-12-10
Publication date: 2020-09-17
Also published as: CN109738954A; CN109738954B

Abstract

Disclosed are a clock synchronization circuit, a clock synchronization method and a seabed seismograph. The clock synchronization circuit comprises: a main clock circuit (11), at least one seismic data collection circuit (12), a microprocessor control circuit (13) and at least two frequency division circuits (14), wherein the at least two frequency division circuits (14) comprise a first frequency division circuit (141) and a second frequency division circuit (142); the main clock circuit (11) is configured to generate a main clock signal; the first frequency division circuit (141) is connected to the main clock circuit (11); each seismic data collection circuit (12) is connected to the first frequency division circuit (141); the second frequency division circuit (142) is connected to the main clock circuit (11); and the microprocessor control circuit (13) is connected to the second frequency division circuit (142). The clock synchronization method comprises: a first frequency division circuit (141) carrying out frequency division processing on a main clock signal to obtain a seismic data collection clock signal, and a seismic data collection circuit (12) acquiring the seismic data collection clock signal (110) by means of the first frequency division circuit (141); and a second frequency division circuit (142) carrying out frequency division processing on the main clock signal to obtain a real-time clock signal, and a microprocessor control circuit (13) acquiring the real-time clock signal (120) by means of the second frequency division circuit (142). The seabed seismograph comprises the clock synchronization circuit.

Description

Clock synchronization circuit, clock synchronization method and seabed seismograph

This disclosure claims the priority of a Chinese patent application filed with the Chinese Patent Office with an application number of 201910194086.9 on March 14, 2019. The entire content of the above application is incorporated into this disclosure by reference.

Technical field

The embodiment of the present invention relates to the field of surveying instruments, for example, to a clock synchronization circuit, a clock synchronization method, and a seabed seismograph.

Background technique

An undersea seismograph (OBS) is a recording instrument that is placed on the seabed and can directly receive artificial or natural seismic signals. Compared with conventional seismic data, the data recorded by an undersea seismograph has many advantages. In the seabed, its data records are not easily affected by water noise and jitter, so it has a higher signal-to-noise ratio. In addition, the seabed seismograph also provides a wide-azimuth observation system, which is conducive to the imaging of the formation under the complex overburden (such as salt dome) and the analysis of the angle-related reflectivity. The data processing of the seabed seismograph mainly involves the arrival time of the seismic wave, and the accuracy of the time is very high, so the time accuracy of the seabed seismograph data recording system is very important. In related technologies, each module of the submarine seismograph uses independent clock crystal oscillators, which may easily cause time disturbances among the various modules of the submarine seismograph, making the time accuracy of the submarine seismograph data record low.

Summary of the invention

This article provides a clock synchronization circuit, a clock synchronization method and a seabed seismograph to improve the time accuracy of the seabed seismograph.

In the first aspect, an embodiment of the present invention provides a clock synchronization circuit, including:

Main clock circuit, at least one seismic data acquisition circuit, microprocessor control circuit and at least two frequency dividing circuits;

The at least two frequency dividing circuits include a first frequency dividing circuit and a second frequency dividing circuit;

The master clock circuit is configured to generate a master clock signal;

The first frequency dividing circuit is connected to the main clock circuit, and the first frequency dividing circuit is configured to perform frequency division processing on the main clock signal to obtain a seismic data acquisition clock signal;

Each of the seismic data acquisition circuits is connected to the first frequency dividing circuit, and the seismic data acquisition circuit is configured to acquire the seismic data acquisition clock signal through the first frequency dividing circuit;

The second frequency divider circuit is connected to the main clock circuit, and the second frequency divider circuit is configured to perform frequency division processing on the main clock signal to obtain a real-time clock signal;

The microprocessor control circuit is connected to the second frequency divider circuit, and the microprocessor control circuit is configured to obtain the real-time clock signal through the second frequency divider circuit.

In the second aspect, an embodiment of the present invention also provides a clock synchronization method for any clock synchronization circuit described in the first aspect, and the method includes:

The first frequency dividing circuit performs frequency dividing processing on the master clock signal to obtain a seismic data acquisition clock signal, and the seismic data acquisition circuit obtains the seismic data acquisition clock signal through the first frequency dividing circuit;

The second frequency dividing circuit performs frequency dividing processing on the main clock signal to obtain a real-time clock signal, and the microprocessor control circuit obtains the real-time clock signal through the second frequency dividing circuit.

In a third aspect, an embodiment of the present invention also provides a seabed seismograph, including any clock synchronization circuit described in the first aspect.

Description of the drawings

FIG. 1 is a schematic structural diagram of a clock synchronization circuit provided by an embodiment of the present invention;

2 is a schematic structural diagram of another clock synchronization circuit provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of yet another clock synchronization circuit provided by an embodiment of the present invention;

4 is a schematic flowchart of a clock synchronization method provided by an embodiment of the present invention;

5 is a schematic flowchart of another clock synchronization method provided by an embodiment of the present invention;

6 is a schematic flowchart of yet another clock synchronization method provided by an embodiment of the present invention;

FIG. 7 is a flowchart of a clock synchronization method provided by an embodiment of the present invention.

detailed description

The text will be further described in detail below in conjunction with the drawings and embodiments. It can be understood that the specific embodiments described here are only used to explain the text, but not to limit the text. In addition, it should be noted that, for ease of description, only a part of the structure related to this document is shown in the drawings instead of all of the structure.

Fig. 1 is a schematic structural diagram of a clock synchronization circuit provided by an embodiment of the present invention. As shown in Fig. 1, the clock synchronization circuit provided by an embodiment of the present invention includes: a master clock circuit 11, at least one seismic data acquisition circuit 12, and a microprocessor The controller control circuit 13 and at least two frequency dividing circuits 14; the at least two frequency dividing circuits 14 include a first frequency dividing circuit 141 and a second frequency dividing circuit 142; the master clock circuit 11 is configured to generate a master clock signal; The frequency circuit 141 is connected to the main clock circuit 11 and is configured to perform frequency division processing on the main clock signal to obtain a seismic data acquisition clock signal; the seismic data acquisition circuit 12 is connected to the first frequency dividing circuit 141 and is configured to obtain a seismic data acquisition clock Signal; the second frequency divider circuit 142 is connected to the main clock circuit 11 and is configured to perform frequency division processing on the main clock signal to obtain a real-time clock signal; the microprocessor control circuit 13 is connected to the second frequency divider circuit 142 and is configured to obtain Real-time clock signal.

The technical solution of the embodiment of the present invention uses one master clock circuit 11 and at least two frequency dividing circuits 14 to perform frequency division processing on the master clock signal to obtain seismic data acquisition clock signals and real-time clock signals. The seismic data acquisition circuit 12 and the microprocessor The clock signal of the device control circuit 13 comes from the same master clock circuit 11, which solves the problem of time disorder between modules caused by the use of independent clock crystal oscillators in the various modules of the submarine seismograph in the related art, and realizes the submarine earthquake with high time accuracy. instrument.

In some embodiments, the at least two frequency dividing circuits 14 further include a third frequency dividing circuit 143; the third frequency dividing circuit 143 is connected to the main clock circuit 11 and is configured to perform frequency division processing on the main clock signal to obtain the second pulse signal ; The microprocessor control circuit 13 is connected to the third frequency dividing circuit 143 and is configured to obtain the second pulse signal.

In some embodiments, the second frequency dividing circuit 142 is directly connected to the main clock circuit 11; in the embodiment shown in FIG. 1, the second frequency dividing circuit 142 is connected to the main clock circuit 11 through the first frequency dividing circuit 141 .

In some embodiments, the third frequency dividing circuit 143 is directly connected to the main clock circuit; in some embodiments, the third frequency dividing circuit 143 is connected to the main clock circuit through the first frequency dividing circuit 141 and/or the second frequency dividing circuit 142 The circuit 11 is connected, and those skilled in the art can modify the parameters of the frequency divider circuit to adopt different connection modes, so as to change and adjust the connection mode of the frequency divider circuit and the master clock circuit without departing from the protection scope of this document.

In some embodiments, the second frequency dividing circuit 142 is provided independently (as shown in FIG. 1 ); in some embodiments, it is integrated in the microprocessor control circuit 13. Exemplarily, FIG. 2 is a schematic structural diagram of another clock synchronization circuit provided by an embodiment of the present invention. As shown in FIG. 2, the second frequency divider circuit 142 is integrated in the microprocessor control circuit 13, and the microprocessor control circuit 13 is connected to the main clock circuit 11 through the first frequency dividing circuit 141, and the internal second frequency dividing circuit 142 performs frequency division processing on the main clock signal to obtain the real-time clock signal, and the second frequency dividing circuit 142 is integrated in the microprocessor The inside of the control circuit 13 is beneficial to reduce the size of the clock synchronization circuit.

In some embodiments, the microprocessor control circuit 13 is connected to the seismic data acquisition circuit 12, and the microprocessor control circuit 13 is configured to acquire and process the seismic data. In some embodiments, the seismic data acquisition circuit 12 is configured to acquire seismic data; the microprocessor control circuit 13 is connected to each of the seismic data acquisition circuits 12, and the microprocessor control circuit 13 is configured In order to obtain seismic data through the seismic data acquisition circuit 12, and process the acquired seismic data.

Continuing to refer to FIG. 1, optionally, the clock synchronization circuit provided by the embodiment of the present invention further includes a GPS module 15. The GPS module 15 is connected to the microprocessor control circuit 13, and is configured to provide a standard for the microprocessor control circuit 13. The second pulse signal (Pulse Per Second, PPS) and the world clock signal (UTC), the microprocessor control circuit 13 is also used for the management and calculation of each clock.

Continuing to refer to FIG. 1, optionally, the clock synchronization circuit provided by the embodiment of the present invention further includes a power supply 16, which is respectively connected to the main clock circuit 11, the seismic data acquisition circuit 12, the microprocessor control circuit 13, and the frequency dividing circuit. 14 is electrically connected to the GPS module 15, and the power supply 16 is configured to supply power to the main clock circuit 11, the seismic data acquisition circuit 12, the microprocessor control circuit 13, the frequency divider circuit 14, and the GPS module 15 respectively.

Exemplarily, FIG. 3 is a schematic structural diagram of another clock synchronization circuit provided by an embodiment of the present invention. As shown in FIG. 3, the main clock circuit 11 uses a 16.384Mhz high-precision temperature-compensated quartz crystal resonator TCXO (Temperature Compensate X'tal (crystal) Oscillator, TCXO), is configured to provide the master clock signal. The clock synchronization circuit provided by the embodiment of the present invention includes four frequency dividing circuits, which are a first frequency dividing circuit 141, a second frequency dividing circuit 142, a third frequency dividing circuit 143, and a fourth frequency dividing circuit 144. The embodiment of the present invention The provided clock synchronization circuit also includes two seismic data acquisition circuits (ADC) 12, namely a first seismic data acquisition circuit 121 and a second seismic data acquisition circuit 122, wherein the first frequency dividing circuit 141 is connected to the main clock circuit 11. , Is configured to perform frequency division processing on the master clock signal to obtain a seismic data acquisition clock signal; the first seismic data acquisition circuit 121 is connected to the first frequency division circuit 141, and is configured to acquire the seismic data required by the first seismic data acquisition circuit 121 Data acquisition clock signal; the fourth frequency dividing circuit 144 is connected to the first frequency dividing circuit 141 and the second seismic data acquisition circuit 122, and is configured to acquire the seismic data required by the second seismic data acquisition circuit 122 to acquire the clock signal; The second frequency dividing circuit 142 is connected to the fourth frequency dividing circuit 144 and is configured to obtain a real-time clock signal, wherein the real-time clock signal is transmitted to the real-time clock of the seabed seismograph, and the real-time clock is used to set the system time of the seabed seismograph; The three frequency dividing circuit 143 is connected to the second frequency dividing circuit 142 and is configured to obtain the second pulse signal; the microprocessor control circuit 13 is connected to the second frequency dividing circuit 142 and the third frequency dividing circuit 143 and is configured to obtain a real-time clock For signals and second pulse signals, the microprocessor control circuit 13 is connected to the first seismic data acquisition circuit 121 and the second seismic data acquisition circuit 122, and is configured to acquire seismic data and process the seismic data. Optionally, the first frequency dividing circuit 141 adopts a frequency dividing circuit of 10, and is configured to generate the 1.6384Mhz seismic data acquisition clock signal required by the first seismic data acquisition circuit 121; the fourth frequency dividing circuit 144 adopts a frequency dividing circuit of 2 , Is configured to generate the 0.8192Mhz seismic data acquisition clock signal required by the second seismic data acquisition circuit 122; the second frequency divider circuit 142 uses a 25 divider circuit and is configured to generate a 32.768Khz real-time clock signal; The frequency circuit 143 adopts a 32768 frequency divider circuit and is configured to generate a second pulse signal. The GPS module 15 is connected to the microprocessor control circuit 13, and is configured to provide the standard pulse signal (Pulse Per Second, PPS) and the world clock signal (UTC) to the microprocessor control circuit 13. The microprocessor control circuit 13 is also Configured for the management and calculation of each clock, so that the system time of the seabed seismograph and the GPS module provide the standard second pulse signal and the world clock signal for calibration and synchronization, and realize the microsecond synchronization between the system time of the seabed seismograph and the world standard time .

The technical solution of the embodiment of the present invention uses one master clock circuit 11 and at least two frequency dividing circuits 14 to perform frequency division processing on the master clock signal to obtain seismic data acquisition clock signals and real-time clock signals. The seismic data acquisition circuit 12 and the microprocessor The clock signal of the device control circuit 13 comes from the same master clock circuit 11, which solves the problem of time disorder between modules caused by the use of independent clock crystal oscillators in the submarine seismograph modules in the related art, and realizes the microsecond synchronization of multi-channel seismic data. , To make the time system of the seabed seismograph more accurate, ensure the validity of the seismic data, and avoid the use of multiple crystal oscillators, and reduce the power consumption of the seabed seismograph. The technical solution of the embodiment of the present invention also adopts the GPS module to provide the standard second pulse signal and the world clock signal. The subsea seismograph is synchronized with the standard second pulse signal and the world clock signal provided by the GPS module to realize the subsea seismograph and the world standard time. The microsecond synchronization enables the comparison and analysis of the seismic data of the seabed seismograph and the seismic data of other stations, ensuring more accurate data analysis among different seabed seismograph stations in the same batch.

Based on the same inventive concept, the embodiment of the present invention also provides a clock synchronization method for any clock synchronization circuit provided in the above embodiment. The same or corresponding structure and the explanation of terms as the above embodiment will not be repeated here. , FIG. 4 is a schematic flowchart of a clock synchronization method provided by an embodiment of the present invention. As shown in FIG. 4, the method includes the following steps:

Step 110: The seismic data acquisition circuit divides the frequency of the master clock signal by the first frequency dividing circuit to obtain the seismic data acquisition clock signal.

Step 120: The microprocessor control circuit divides the frequency of the main clock signal through the second frequency divider circuit to obtain a real-time clock signal.

In the technical solution provided in this embodiment, there is no requirement for a sequence between step 110 and step 110, and those skilled in the art can change the foregoing sequence without departing from the scope of protection herein.

The technical solution of the embodiment of the present invention uses the frequency division method to divide the main clock signal to obtain the seismic data acquisition clock signal and the real-time clock signal, which solves the inter-module time caused by the use of independent clock crystal oscillators for each module of the seabed seismograph in the related art The problem of turbulence makes the seabed seismograph have high time accuracy.

FIG. 5 is a schematic flowchart of another clock synchronization method provided by an embodiment of the present invention. As shown in FIG. 5, optionally, the clock synchronization method provided by an embodiment of the present invention may include:

Step 210: The seismic data acquisition circuit divides the frequency of the master clock signal through the first frequency dividing circuit to obtain the seismic data acquisition clock signal.

Step 220: The microprocessor control circuit divides the frequency of the main clock signal through the second frequency divider circuit to obtain a real-time clock signal.

Step 230: The microprocessor control circuit divides the frequency of the main clock signal through the third frequency divider circuit to obtain the second pulse signal.

The clock synchronization circuit also includes a GPS module 15. The GPS module 15 is connected to the microprocessor control circuit 13. As shown in FIG. 4, optionally, the clock synchronization method provided by the embodiment of the present invention further includes:

Step 240: The microprocessor control circuit performs a first time synchronization operation on the real-time clock signal according to the world time signal provided by the GPS module, and the first time synchronization operation is accurate to the second level.

Step 250: The microprocessor control circuit performs a second time synchronization operation on the real-time clock signal according to the standard second pulse signal provided by the GPS module, and the second time synchronization operation is accurate to within 1 millisecond.

In the technical solution provided in this embodiment, there is no requirement for a sequence between step 210, step 220, and step 230, and those skilled in the art can change the foregoing sequence without departing from the scope of protection herein.

FIG. 6 is a schematic flowchart of another clock synchronization method provided by an embodiment of the present invention. On the basis of the technical solution provided in the previous embodiment, the embodiment of the present invention refines step 250, which is the same as or The explanation of the corresponding terms will not be repeated here.

In some embodiments, the microprocessor control circuit performs a second time synchronization operation on the real-time clock signal according to the standard second pulse signal provided by the GPS module, and the second time synchronization operation is accurate to 1 millisecond Include:

The microprocessor control circuit obtains the first real-time clock signal according to the arrival time of the first falling edge of the standard second pulse signal, and the first real-time clock signal is accurate to the microsecond level.

The microprocessor control circuit obtains a second real-time clock signal according to the arrival time of the second falling edge of the standard second pulse signal, and the second real-time clock signal is accurate to the microsecond level; the first falling edge and the The second falling edge is two adjacent falling edges of the standard second pulse signal in the standard second pulse signal.

Determine whether the standard second pulse signal is a continuous pulse signal according to the time difference between the second real-time clock signal and the first real-time clock signal, and calculate the second pulse signal when the standard second pulse signal is a continuous pulse signal The pulse error with the standard second pulse signal.

The pulse error is added to the real-time clock signal.

In some embodiments, the microprocessor control circuit performs a first time synchronization operation on the real-time clock signal according to the world time signal provided by the GPS module, and the first time synchronization operation is accurate to the second level before , The clock synchronization method further includes:

The microprocessor control circuit acquires the standard second pulse signal and the world time signal provided by the GPS module multiple times;

It is determined that the GPS module is stable according to that the standard second pulse signal and the world time signal obtained multiple times are correct signals.

As shown in FIG. 6, the clock synchronization method provided by the embodiment of the present invention may include the following steps:

Step 401: The seismic data acquisition circuit divides the frequency of the master clock signal by the first frequency dividing circuit to obtain the seismic data acquisition clock signal.

Step 402: The microprocessor control circuit divides the frequency of the main clock signal through the second frequency divider circuit to obtain the real-time clock signal.

Step 403: The microprocessor control circuit divides the frequency of the main clock signal through the third frequency divider circuit to obtain the second pulse signal.

Step 404: The microprocessor control circuit acquires the standard second pulse signal and the world time signal provided by the GPS module multiple times.

Step 405: Determine that the GPS module is stable according to the multiple times that the standard second pulse signal and the world time signal are correct signals.

Step 406: The microprocessor control circuit performs a first time synchronization operation on the real-time clock signal according to the world time signal provided by the GPS module, and the first time synchronization operation is accurate to the second level.

Step 407: The microprocessor control circuit obtains a first real-time clock signal according to the arrival time of the first falling edge of the standard second pulse signal, and the first real-time clock signal is accurate to the microsecond level.

Step 408: The microprocessor control circuit obtains a second real-time clock signal according to the arrival time of the second falling edge of the standard second pulse signal, and the second real-time clock signal is accurate to the microsecond level; the first falling edge And the second falling edge are two adjacent falling edges of the standard second pulse signal in the standard second pulse signal.

Optionally, the microprocessor control circuit can also obtain the first real-time clock signal and the second real-time clock signal according to the rising edge of the standard second pulse signal.

Step 409: Determine whether the standard second pulse signal is a continuous pulse signal according to the time difference between the second real time clock signal and the first real time clock signal, and calculate when the standard second pulse signal is a continuous pulse signal The pulse error between the second pulse signal and the standard second pulse signal.

Step 410: Add the pulse error to the real-time clock signal.

Exemplarily, FIG. 7 is a flowchart of a clock synchronization method provided by an embodiment of the present invention. Referring to FIG. 7, first, start the GPS module. Among them, after turning on the seabed seismograph and ensuring that the microprocessor control circuit (MCU) is working normally, turn on the power of the GPS module, start the GPS module, and wait for the GPS module to obtain the correct standard second pulse signal (Pulse Per Second) and the world clock Signal (UTC).

Then, the microprocessor control circuit acquires the standard second pulse signal and the world time signal provided by the GPS module multiple times and determines that the GPS module is stable according to the correct signal of the standard second pulse signal and the world time signal acquired multiple times. Among them, the serial port information provided by the GPS module contains an identifier indicating whether the signal is correct. The microprocessor control circuit determines whether the standard second pulse signal and the world time signal provided by the GPS module are correct by distinguishing the identifier. The control circuit obtains the correct standard second pulse signal and world time signal more than 10 times to ensure the stability of the GPS module.

The microprocessor control circuit performs the first time synchronization operation on the real-time clock signal according to the world time signal provided by the GPS module, and the first time synchronization operation is accurate to the second level. Among them, the time information such as year, month, day, hour, minute, and second contained in the serial port information output by the GPS module is used to synchronize the real-time clock signal, thereby completing time synchronization with an accuracy of seconds.

The microprocessor control circuit obtains the first real-time clock signal according to the arrival time of the first falling edge of the standard second pulse signal, and the first real-time clock signal is accurate to the microsecond level. Among them, the microprocessor control circuit judges whether the first falling edge of the standard second pulse signal comes, and when the microprocessor control circuit captures the first falling edge of the standard second pulse signal, it reads the first real-time clock signal at this moment, Accurate the first real-time clock signal to the microsecond level and save it.

The microprocessor control circuit obtains the second real-time clock signal according to the arrival time of the second falling edge of the standard second pulse signal. The second real-time clock signal is accurate to the microsecond level; the first falling edge and the second falling edge are in the standard second pulse signal The falling edges of two adjacent standard second pulse signals. Among them, after acquiring the first real-time clock signal, the microprocessor control circuit waits for the falling edge of the next standard second pulse signal to arrive. The falling edge of the next standard second pulse signal is the second falling edge of the standard second pulse signal. The microprocessor control circuit captures the second falling edge of the standard second pulse signal, then acquires the second real-time clock signal at this moment, and saves the second real-time clock signal to the microsecond level.

Determine whether the standard second pulse signal is a continuous pulse signal according to the time difference between the second real-time clock signal and the first real-time clock signal, and calculate the difference between the second pulse signal and the standard second pulse signal when the standard second pulse signal is a continuous pulse signal Pulse error. Among them, if the value differs by one second, it means that the two PPS intervals are continuous. The microprocessor control circuit makes the time difference between the second real-time clock signal and the first real-time clock signal, and judges whether the difference is one second, if the microprocessor control circuit judges the time between the second real-time clock signal and the first real-time clock signal If the difference is one second, the standard second pulse signal is determined to be a continuous pulse signal. Otherwise, the standard second pulse signal is not a continuous pulse signal. At this time, the first real-time clock signal needs to be obtained again according to the arrival time of the first falling edge of the standard second pulse signal . If the standard second pulse signal is a continuous pulse signal, the error between the second pulse signal and the standard second pulse signal below the second accuracy or the error below the millisecond level is the actual error between the submarine seismograph system time and the world standard time, which is calculated by the counter The pulse error between the second pulse signal and the standard second pulse signal.

The pulse error is added to the real-time clock signal. Among them, the number of pulse errors is added to the pulse counter in the real-time clock (RTC) to eliminate the error between the time of the real-time clock signal and the standard second pulse signal, thereby completing the time of the real-time clock signal and the world standard time in milliseconds For the following time synchronization, turn off the GPS module after completing the time synchronization to reduce energy consumption.

The technical solution of the embodiment of the present invention uses the frequency division method to divide the main clock signal to obtain the seismic data acquisition clock signal and the real-time clock signal, which solves the inter-module time caused by the use of independent clock crystal oscillators for each module of the seabed seismograph in the related art The problem of turbulence makes the seabed seismograph have higher time accuracy and lower power consumption, and ensures the validity of seismic data. The technical solution of the embodiment of the present invention also realizes the microsecond synchronization between the system time of the seabed seismograph and the world standard time by matching the real-time clock signal and the second pulse signal with the standard second pulse signal and the world clock signal provided by the GPS module. , It can achieve the maximum time error between the system time of the seabed seismograph and the world standard time within 30us, ensuring that the design requirements of accurate synchronization within 1ms are met, so that the seismic data of the seabed seismograph can be compared with the seismic data of other stations The analysis ensures more accurate data analysis between different seabed seismograph stations in the same batch.

Based on the same inventive concept, an embodiment of the present invention also provides a submarine seismograph, which includes any clock synchronization circuit provided in the foregoing embodiment. The same or corresponding structure and terminology explanations as in the foregoing embodiment are not repeated here.

The embodiment of the present invention uses one master clock circuit and at least two frequency dividing circuits to perform frequency division processing on the master clock signal to obtain the seismic data acquisition clock signal and the real-time clock signal, so that the clock signals of each module are consistent, which solves the problem of Each module of the seabed seismograph uses independent clock crystal oscillators to cause the problem of time disorder between modules, and realizes a seabed seismograph with high time accuracy.

Claims

A clock synchronization circuit, including:

Main clock circuit, at least one seismic data acquisition circuit, microprocessor control circuit and at least two frequency dividing circuits;

The at least two frequency dividing circuits include a first frequency dividing circuit and a second frequency dividing circuit;

The master clock circuit is configured to generate a master clock signal;

The first frequency dividing circuit is connected to the main clock circuit, and the first frequency dividing circuit is configured to perform frequency division processing on the main clock signal to obtain a seismic data acquisition clock signal;

Each of the seismic data acquisition circuits is connected to the first frequency dividing circuit, and the seismic data acquisition circuit is configured to acquire the seismic data acquisition clock signal through the first frequency dividing circuit;

The second frequency divider circuit is connected to the main clock circuit, and the second frequency divider circuit is configured to perform frequency division processing on the main clock signal to obtain a real-time clock signal;

The microprocessor control circuit is connected to the second frequency divider circuit, and the microprocessor control circuit is configured to obtain the real-time clock signal through the second frequency divider circuit.
The clock synchronization circuit according to claim 1, wherein the second frequency divider circuit is directly connected to the main clock circuit; or,

The second frequency divider circuit is connected to the main clock circuit through the first frequency divider circuit.
The clock synchronization circuit according to claim 1, wherein the at least two frequency dividing circuits further comprise a third frequency dividing circuit;

The third frequency dividing circuit is connected to the main clock circuit, and the third frequency dividing circuit is configured to perform frequency dividing processing on the main clock signal to obtain a second pulse signal;

The microprocessor control circuit is connected to the third frequency divider circuit, and the microprocessor control circuit is configured to obtain the second pulse signal through the third frequency divider circuit.
The clock synchronization circuit according to claim 3, wherein the third frequency divider circuit is directly connected to the main clock circuit; or,

The third frequency divider circuit is connected to the main clock circuit through the first frequency divider circuit; or,

The third frequency divider circuit is connected to the main clock circuit through the second frequency divider circuit; or,

The third frequency divider circuit is connected to the main clock circuit through the first frequency divider circuit and the second frequency divider circuit.
The clock synchronization circuit according to claim 1, wherein the microprocessor control circuit is connected to each of the seismic data acquisition circuits, and the microprocessor control circuit is configured to acquire seismic data and to control the seismic data To process.
The clock synchronization circuit according to claim 1, further comprising a GPS module connected to the microprocessor control circuit, and the GPS module is configured to provide a standard second pulse signal to the microprocessor control circuit And the world clock signal.
The clock synchronization circuit according to claim 6, further comprising a power supply, the power supply is respectively connected with the main clock circuit, each of the seismic data acquisition circuit, the microprocessor control circuit, and each of the frequency dividing circuits Is electrically connected to the GPS module, and the power supply is configured to supply the main clock circuit, each seismic data acquisition circuit, the microprocessor control circuit, each frequency dividing circuit, and the GPS Module power supply.
A clock synchronization method for the clock synchronization circuit of any one of claims 1-7, the clock synchronization method comprising:

The first frequency dividing circuit performs frequency dividing processing on the master clock signal to obtain a seismic data acquisition clock signal, and the seismic data acquisition circuit obtains the seismic data acquisition clock signal through the first frequency dividing circuit;

The second frequency dividing circuit performs frequency dividing processing on the main clock signal to obtain a real-time clock signal, and the microprocessor control circuit obtains the real-time clock signal through the second frequency dividing circuit.
The clock synchronization method according to claim 8, wherein the at least two frequency dividing circuits further comprise a third frequency dividing circuit;

The clock synchronization method further includes:

The third frequency dividing circuit performs frequency dividing processing on the main clock signal to obtain the second pulse signal, and the microprocessor control circuit obtains the second pulse signal through the third frequency dividing circuit.
The clock synchronization method according to claim 9, wherein the clock synchronization circuit further comprises a GPS module, and the GPS module is connected to the microprocessor control circuit;

The clock synchronization method further includes:

The microprocessor control circuit performs a first time synchronization operation on the real-time clock signal according to the world time signal provided by the GPS module, and the first time synchronization operation is accurate to the second level;

The microprocessor control circuit performs a second time synchronization operation on the real-time clock signal according to the standard second pulse signal provided by the GPS module, and the second time synchronization operation is accurate to within 1 millisecond.
The clock synchronization method according to claim 10, wherein the microprocessor control circuit performs a second time synchronization operation on the real-time clock signal according to the standard second pulse signal provided by the GPS module, and the second time synchronization The operation is accurate to within 1 millisecond, including:

The microprocessor control circuit obtains the first real-time clock signal according to the arrival time of the first falling edge of the standard second pulse signal, and the first real-time clock signal is accurate to the microsecond level;

The microprocessor control circuit obtains a second real-time clock signal according to the arrival time of the second falling edge of the standard second pulse signal, and the second real-time clock signal is accurate to the microsecond level; the first falling edge and the The second falling edge is two adjacent falling edges of the standard second pulse signal in the standard second pulse signal;

Determine whether the standard second pulse signal is a continuous pulse signal according to the time difference between the second real-time clock signal and the first real-time clock signal, and calculate the second pulse signal when the standard second pulse signal is a continuous pulse signal Pulse error with the standard second pulse signal;

The pulse error is added to the real-time clock signal.
The clock synchronization method according to claim 10, wherein the microprocessor control circuit performs a first time synchronization operation on the real-time clock signal according to the world time signal provided by the GPS module, and the first time Before the synchronization operation is accurate to the second level, the clock synchronization method further includes:

The microprocessor control circuit acquires the standard second pulse signal and the world time signal provided by the GPS module multiple times;

It is determined that the GPS module is stable according to that the standard second pulse signal and the world time signal obtained multiple times are correct signals.
A submarine seismograph, comprising the clock synchronization circuit according to any one of claims 1-7.