CN206564608U - A kind of clock service module - Google Patents
A kind of clock service module Download PDFInfo
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- CN206564608U CN206564608U CN201621481847.7U CN201621481847U CN206564608U CN 206564608 U CN206564608 U CN 206564608U CN 201621481847 U CN201621481847 U CN 201621481847U CN 206564608 U CN206564608 U CN 206564608U
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Abstract
The utility model embodiment is related to Time synchronization technique field, more particularly to a kind of clock service module, and clock service module is inserted in interchanger clamp rail, and clock service module includes：Box body and box body is placed in interior external clock reference input block, FPGA, Main Processor Unit and output unit, two relative outsides of box body are respectively arranged with cartridge activity ear component, clock service module is taken out from clamp rail by pulling cartridge activity ear component, because FPGA can determine the clock source of clock service module subsequent time from the external clock reference of successfully decoded, it is not the clock source for the quality selection subsequent time for being based only on clock signal, it is possible to increase the degree of accuracy of clock server internal reference reference time.Further, since cartridge activity ear component is respectively arranged with two relative outsides of box body, it is thus possible to enough by pulling cartridge activity ear component by the convenient taking-up from the clamp rail of interchanger of clock service module.
Description
Technical field
The utility model embodiment is related to Time synchronization technique field, more particularly to a kind of clock service module.
Background technology
In the prior art, by using Big Dipper BDS, (BeiDou Navigation Satellite System, the Big Dipper is defended
Star navigation system), the external timing signal such as GPS (Global Positioning System, global positioning system) set up clock
The server internal reference time, and completed using various time output signals with all by time dissemination system and the time of equipment
It is synchronous.
And be internally how to select local clock source on clock server, at present mostly by believing external clock
Number the mode that is detected of quality select local clock source, can not be with clock service and due to the quality of clock signal
Device current internal reference time sets up association, therefore, when selecting local by way of detecting external timing signal quality
Zhong Yuan, reduces the degree of accuracy of clock server internal reference reference time.
Utility model content
The utility model embodiment provides a kind of clock service module, when being referred to improve clock server internal reference
Between the degree of accuracy.
The utility model embodiment provides a kind of clock service module, and the clock service module is inserted in interchanger clamp rail
On, the clock service module includes：Box body and box body is placed in interior external clock reference input block, FPGA, main place
Unit and output unit are managed, two relative outsides of the box body are respectively arranged with cartridge activity ear component, by pulling
Cartridge activity ear component is stated to take out the clock service module from the clamp rail；
The external clock reference input block, for providing input interface for external clock reference, and receives external clock reference
Clock signal；
The FPGA is electrically connected with the external clock reference input block, for multiple external clock references to receiving
Clock signal decoded, the first valid clock source is determined from the external clock reference of successfully decoded；Have for each first
Clock source is imitated, the difference of the very first time and the second time are determined, by the difference between the very first time and second time
The first valid clock source less than first threshold is defined as available clock source, and from it is described can be with determining the clock in clock source
The clock source of service module subsequent time；The very first time is the first efficient clock source time, and second time is
The fiducial time that the clock source at the clock service module current time is provided；
The output unit is electrically connected with the FPGA, during for being exported according to the clock source of the clock service module
Clock signal；
The Main Processor Unit is electrical with the FPGA, the external clock reference input block and the output unit respectively
Connection, for being controlled to the FPGA, the external clock reference input block and the output unit.
Alternatively, the FPGA, is additionally operable to when the clock source at current time can be used in clock source described in, it is determined that
In the case that the time difference of the clock source at current time currently provided time and second time are more than Second Threshold, root
According to the priority with clock source, the clock source of subsequent time is redefined；Determine the clock source at current time with it is described
In the case that the time difference of second time is not more than Second Threshold, keep the clock source at current time constant in subsequent time；Institute
The clock source for stating clock service module current time is one in the multiple external clock reference.
Alternatively, the FPGA, is additionally operable to when the clock source at current time can be used in clock source described in, according to
The priority with clock source, redefines the clock source of subsequent time.
Alternatively, the FPGA, is additionally operable in initialization, by the multiple effective second valid clock source institutes received
The corresponding time is asked poor two-by-two, two minimum the second valid clock sources of time difference is determined, by described two clock sources
The second higher valid clock source of middle priority as the clock server clock source.
Alternatively, the FPGA, when being additionally operable to measure each outside in the external clock reference of the successfully decoded respectively
Zhong Yuan the 3rd time and the 4th time, the 3rd time are time of the external clock reference at the selected moment, and the 4th time was
Time of the external clock reference in the later moment in time at the selected moment；By the difference between the 3rd time and the 4th time
Value is determined as the first valid clock source less than the external clock reference of the 3rd threshold value.
Alternatively, the cartridge activity ear component is set with detachable on the outside of the box body.
Alternatively, the cartridge activity ear component includes being provided with flat board, the flat board with the outside of the box body blocking
The cartridge part of box a, end of the flat board is provided with ear part, and the ear part passes through riveting and the box body of rising
It is fixed.
Alternatively, the box body has been also housed within PMU, one end of the PMU and the main place
Unit electrical connection is managed, the other end of the PMU is electrically connected with power subsystem；
The PMU is used to provide power supply by the power subsystem for the clock server, and is used for
The Main Processor Unit is powered or powered off.
Alternatively, the box body has been also housed within network Transmit-Receive Unit, the network Transmit-Receive Unit and the Main Processor Unit
Connection, the network Transmit-Receive Unit, for the configuration and management by clock service module described in real-time performance.
Alternatively, the external clock reference is GPS clock signal source, big-dipper satellite clock source, IRIG-B clock sources, PTP
Clock source, TOD source, 1PPS clock sources, 1PPS+TOD clock sources.
A kind of clock service module that above-described embodiment is provided, the clock service module is inserted in interchanger clamp rail,
The clock service module includes：Box body and box body is placed in interior external clock reference input block, FPGA, main process task list
Member and output unit, two relative outsides of the box body are respectively arranged with cartridge activity ear component, by pulling the card
Box activity ear component takes out the clock service module from the clamp rail；The external clock reference input block, is used for
Input interface is provided for external clock reference, and receives the clock signal of external clock reference；The FPGA and the external clock reference
Input block is electrically connected with, and the clock signal for multiple external clock references to receiving is decoded, from successfully decoded
The first valid clock source is determined in external clock reference；For each first valid clock source, the very first time and the second time are determined
Difference, by the difference between the very first time and second time be less than first threshold the first valid clock source it is true
It is set to available clock source, and the clock source that the clock service module subsequent time is determined in clock source can be used from described；It is described
The very first time is the first efficient clock source time, and second time is the clock at the clock service module current time
The fiducial time that source is provided；The output unit and the FPGA are electrically connected with, for according to the clock service module when
Zhong Yuan exports clock signal；The Main Processor Unit respectively with the FPGA, the external clock reference input block and described defeated
Go out unit electric connection, for being controlled to the FPGA, the external clock reference input block and the output unit.Can
To find out, because the FPGA clock signals that can be used in multiple external clock references to receiving are decoded, from successfully decoded
External clock reference in determine the first valid clock source；For each first valid clock source, when determining that the very first time is with second
Between difference, by the difference between the very first time and second time be less than first threshold the first valid clock source it is true
It is set to available clock source, and the clock source that the clock service module subsequent time is determined in clock source can be used from described, not
It is the clock source for the quality selection subsequent time for being based only on clock signal, therefore, it is possible to improve clock server internal reference
The degree of accuracy of reference time.Further, since cartridge activity ear component is respectively arranged with two relative outsides of box body, because
This, additionally it is possible to is by pulling cartridge activity ear component easily to take clock service module from the clamp rail of interchanger
Go out.
Brief description of the drawings
, below will be to needed for embodiment description in order to illustrate more clearly of the technical scheme in the utility model embodiment
The accompanying drawing to be used is briefly introduced.
A kind of electrical block diagram for clock service module that Fig. 1 provides for the utility model embodiment；
The positive structure schematic for the clock service module that Fig. 2 provides for the utility model embodiment；
The structural representation for the cartridge activity ear component that Fig. 3 a~Fig. 3 f provide for the utility model embodiment；
The electrical block diagram for another clock service module that Fig. 4 provides for the utility model embodiment.
Embodiment
In order that the purpose of this utility model, technical scheme and beneficial effect are more clearly understood, below in conjunction with accompanying drawing and
Embodiment, the utility model is further elaborated.It should be appreciated that specific embodiment described herein is only used to
The utility model is explained, is not used to limit the utility model.
The utility model embodiment provides a kind of clock service module, and the clock service module is inserted in interchanger clamp rail
On.
Fig. 1 illustrates a kind of circuit structure signal of clock service module of the utility model embodiment offer
Figure, as shown in figure 1, the clock service module may include：
Box body 1 and the external clock reference input block 2 being placed in box body, FPGA3, Main Processor Unit 4 and output are single
Member 5, and two relative outsides of box body 1 are respectively arranged with cartridge activity ear component 6, by pulling cartridge activity ear group
Part 6 takes out clock service module from the clamp rail of interchanger.
Wherein, external clock reference input block 2, for providing input interface for external clock reference, and for receiving outside
The clock signal of clock source.
FPGA3 is electrically connected with external clock reference input block, the clock for multiple external clock references to receiving
Signal is decoded, and the first valid clock source is determined from the external clock reference of successfully decoded, for each first efficient clock
Source, determines the difference of the very first time and the second time, and the difference between the very first time and the second time is less than into first threshold
First valid clock source is defined as available clock source, and determines from available clock source the clock service module subsequent time
Clock source, the very first time is the first efficient clock source time, and second time is clock service module current time
The fiducial time that clock source is provided.
Wherein, clock service module can receive multiple clock sources, and clock service module needs to select from multiple clock sources
A clock source is selected as clock source fiducial time is provided, at the time of different, clock service module be possible to selection it is different when
Zhong Yuan provides fiducial time.The clock source at clock service module current time is also referred to as clock service module and used at current time
Clock source.Clock source of the equipment in subsequent time is determined from available clock source, it is, determining equipment from available clock
The clock source used in subsequent time.
Output unit 5 and FPGA3 is electrically connected with, for exporting clock signal according to the clock source of clock service module.
Main Processor Unit 4 is electrically connected with external clock reference input block 2, FPGA3 and output unit 5 respectively, is used for
External clock reference input block 2, FPGA3 and output unit 5 are controlled.
Optionally, in order to more easily take out clock service module from the clamp rail of interchanger, cartridge activity ear group
Part 6 can also be multiple.
The positive structure schematic for the clock service module that Fig. 2 provides for the utility model embodiment, as shown in Fig. 2 when
The each outside of the box body 1 of clock service module, which can be set, two cartridge movable components 6.
Optionally, for convenient disassembly, cartridge activity ear component 6 and the detachable setting in the outside of box body 1.
The structure that Fig. 3 a~Fig. 3 f illustrate the cartridge activity ear component 6 of the utility model embodiment offer is shown
It is intended to, as shown in Fig. 3 a~Fig. 3 f, cartridge activity ear component 6 may include：
Flat board 61 and cartridge part 62 with cartridge on the outside of box body is provided with flat board 61, in addition, in flat board 61
One end is additionally provided with ear part 63, and ear part 63 is fixed by riveting of rising with box body 1.
As shown in Fig. 2 two relative outsides of box body 1 are respectively arranged with cartridge activity ear component 6.The each outside of box body
There are two sets of cartridge activity ear components 6 respectively up and down.When needing to take out box body from interchanger clamp rail, anchor rivet bush is unclamped,
Ear part is separated with box body, pull ear part to drive box body to be taken out from clamp rail, then, will by cartridge part
Cartridge ear component is separated with whole box body.
Specifically, when external clock reference input block 2, for providing input interface for external clock reference, and for receiving
During the clock signal of external clock reference, external clock reference input block 2 can be used for receiving but being not limited to GPS clock signal source, north
Struggle against satellite clock source, IRIG-B (Inter Range Instrumentation Group, U.S. target range instrument group) clock source,
GLONASS (GLOBAL NAVIGATION SATELLITE SYSTEM, GPS) clock source, clock synchronization compliant with precision time protocol source,
1PPS clock sources, TOD (Time of Day, Time of Day information) clock sources and 1PPS+TOD clock sources.
Specifically, when output unit 5 is used to export clock signal according to the clock source of clock service module, PTP can be passed through
(Network Time Protocol, network time assists by (Precision Time Protocol, Precision Time Protocol), NTP
View) and the various ways such as IRIG-B be that miscellaneous equipment carries out time service.
Optionally, the clock source that FPGA3 can be additionally used at current time is included in available clock source, determines current time
Clock source currently provided time and the second time time difference be more than threshold value in the case of, according to can be with clock source it is excellent
First level, redefines the clock source of subsequent time；Determine the clock source at current time currently provided time and the second time
Time difference be not more than Second Threshold in the case of, keep the clock source at current time constant in subsequent time, clock clothes
The clock source at business module current time is one in multiple external clock references.Then, FPGA3 can be exported by output unit 5
Clock signal.
Optionally, the clock source that FPGA3 can be additionally used at current time is included in available clock source, according to can use clock
The priority in source, redefines the clock source of subsequent time.
Optionally, FPGA3 can be additionally used in initialization, and the multiple effective second valid clock source institutes received are right
The time answered is asked poor two-by-two, determines two minimum the second valid clock sources of time difference, by this two second it is effective when
The second higher valid clock source of Zhong Yuanzhong priority is as the clock source of clock server, and then, FPGA3 can be single by exporting
Member 5 exports clock signal..
Optionally, FPGA3 can also be used to measure each external clock reference in the external clock reference of successfully decoded respectively
3rd time and the 4th time, the 3rd time are time of the external clock reference at the selected moment, when the 4th time is outside
Difference between 3rd time and the 4th time is less than by Zhong Yuan in the time of the later moment in time at the selected moment
The external clock reference of 3rd threshold value is determined as the first valid clock source.
Specifically, when the FPGA3 clock signals for being used for multiple external clock references to receiving are decoded, can be right first
The head of code element, the tail of code element of the respective output of multiple clock sources are differentiated, in the code of the respective output to multiple clock sources
After head, the tail of code element of member are determined, each field to the code element of the respective output of multiple clock sources is parsed, and then will
Each field of the code element of the respective output of multiple clock sources is corresponded in codec register and stored, multiple required for finally confirming
Whether the state of the code element of the respective output of clock source complete, that is, judges the respective output of multiple clock sources required for confirmation
Whether all fields meet the requirements, if all fields of the respective output of required multiple clock sources meet the requirements, solve
Code success, otherwise decoding failure.
Specifically, FPGA3 is used for after the clock signal of multiple external clock references to receiving decodes, from being decoded into
When determining the first valid clock source in the external clock reference of work(, the clock letter of multiple clock sources after successfully decoded can be first determined whether
Number quality, that is, whether judge the antenna condition of each clock source, satellitosis, leap second, precision, quality and effective marker position
Meet the requirements, for antenna condition, satellitosis, leap second, precision, the satisfactory clock of quality and effective marker position
Source, continues to measure the clock signal of satisfactory clock source, so that it is determined that going out the first valid clock source.
Specifically, time i.e. threeth of each clock source in satisfactory clock source at the selected moment can be measured respectively
The time for the later moment in time that each clock source in time and satisfactory clock source selectes the moment was the 4th time, and will
Difference between 3rd time and the 4th time is less than the clock source of the 3rd threshold value, is determined as the first valid clock source.
Specifically, 1PPS (the pulse per of each clock source in satisfactory clock source can be measured respectively
Second, pulse per second (PPS)), will each satisfactory clock source time and the clock source of the clock signal at the selected moment
Clock signal is measured in the time of the later moment in time at selected moment to be compared, if the clock letter of each satisfactory clock source
Number the selected moment time and the 3rd threshold should be more than with the difference of the clock signal of clock source between the time of later moment in time
Value, then judge the clock source as inactive clock source, if the clock signal of each satisfactory clock source the selected moment when
Between difference with the clock signal of the clock source between the time at latter selected moment be less than the 3rd threshold value, then when can determine that this
Zhong Yuanwei valid clock sources.
On the basis of the clock service modular structure shown in Fig. 1, PMU can be also equipped with box body 1
7 and network Transmit-Receive Unit 8, it is shown in Figure 4.
Wherein, one end of PMU 7 is electrically connected with Main Processor Unit 4, the other end and the electricity of PMU 7
Source unit (not shown) is electrically connected, and it is the clock service that PMU 7, which is used for by the power subsystem,
Module provides power supply, and for Main Processor Unit 4 to be powered or powered off.
Network Transmit-Receive Unit 8 is connected with Main Processor Unit, and network Transmit-Receive Unit 8 is when being used for by described in real-time performance
The configuration and management of clock service module.
According to the above as can be seen that because FPGA can be used in the clock letter of multiple external clock references to receiving
Number decoded, the first valid clock source is determined from the external clock reference of successfully decoded；For each first valid clock source,
The difference of the very first time and the second time are determined, the difference between the very first time and second time is less than the first threshold
First valid clock source of value is defined as available clock source, and from it is described can be with being determined in clock source under the clock service module
The clock source at one moment, is not the clock source for the quality selection subsequent time for being based only on clock signal, therefore, it is possible to improve
The degree of accuracy of clock server internal reference reference time.Further, since being respectively arranged with card in two relative outsides of box body
Box activity ear component, it is thus possible to it is enough by pull cartridge activity ear component by clock service module can easily from
Taken out in the clamp rail of interchanger.
It should be understood by those skilled in the art that, embodiment of the present utility model can be provided as method or computer program
Product.Therefore, in terms of the utility model can be using complete hardware embodiment, complete software embodiment or combination software and hardware
Embodiment form.Moreover, the utility model can be used wherein includes computer usable program code one or more
Computer-usable storage medium (include but is not limited to magnetic disk storage, CD-ROM, optical memory etc.) on the calculating implemented
The form of machine program product.
The utility model is produced with reference to according to the method, equipment (system) and computer program of the utility model embodiment
The flow chart and/or block diagram of product is described.It should be understood that can be in computer program instructions implementation process figure and/or block diagram
Each flow and/or square frame and the flow in flow chart and/or block diagram and/or the combination of square frame.These meters can be provided
Calculation machine programmed instruction is to the place of all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing devices
Manage device to produce a machine so that the instruction for passing through computer or the computing device of other programmable data processing devices is produced
It is raw to be used to realize the function of specifying in one flow of flow chart or multiple flows and/or one square frame of block diagram or multiple square frames
Device.
These computer program instructions, which may be alternatively stored in, can guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works so that the instruction being stored in the computer-readable memory, which is produced, to be included referring to
Make the manufacture of device, the command device realize in one flow of flow chart or multiple flows and/or one square frame of block diagram or
The function of being specified in multiple square frames.
These computer program instructions can be also loaded into computer or other programmable data processing devices so that in meter
Series of operation steps is performed on calculation machine or other programmable devices to produce computer implemented processing, thus in computer or
The instruction performed on other programmable devices is provided for realizing in one flow of flow chart or multiple flows and/or block diagram one
The step of function of being specified in individual square frame or multiple square frames.
Although having been described for preferred embodiment of the present utility model, those skilled in the art once know substantially
Creative concept, then can make other change and modification to these embodiments.So, appended claims are intended to be construed to bag
Include preferred embodiment and fall into having altered and changing for the utility model scope.
Obviously, those skilled in the art can carry out various changes and modification without departing from this practicality to the utility model
New spirit and scope.So, if these modifications and variations of the present utility model belong to the utility model claim and
Within the scope of its equivalent technologies, then the utility model is also intended to comprising including these changes and modification.
Claims (10)
1. a kind of clock service module, it is characterised in that the clock service module is inserted in interchanger clamp rail, the clock
Service module includes：Box body and box body is placed in interior external clock reference input block, FPGA, Main Processor Unit and output
Unit, two relative outsides of the box body are respectively arranged with cartridge activity ear component, by pulling the cartridge activity ear
Piece component takes out the clock service module from the clamp rail；
The external clock reference input block, for providing input interface for external clock reference, and receive external clock reference when
Clock signal；
The FPGA and the external clock reference input block are electrically connected with, for multiple external clock references to receiving when
Clock signal is decoded, and the first valid clock source is determined from the external clock reference of successfully decoded；For each first it is effective when
Zhong Yuan, determines the difference of the very first time and the second time, and the difference between the very first time and second time is less than
First valid clock source of first threshold is defined as available clock source, and from it is described can be with determining the clock service in clock source
The clock source of module subsequent time；The very first time is the first efficient clock source time, and second time is described
The fiducial time that the clock source at clock service module current time is provided；
The output unit is electrically connected with the FPGA, for exporting clock letter according to the clock source of the clock service module
Number；
The Main Processor Unit electrically connects with the FPGA, the external clock reference input block and the output unit respectively
Connect, for being controlled to the FPGA, the external clock reference input block and the output unit.
2. clock service module as claimed in claim 1, it is characterised in that the FPGA, be additionally operable to current time when
When Zhong Yuan can be used in clock source described in, when determining that the clock source at the current time currently provided time is with described second
Between time difference be more than Second Threshold in the case of, according to the priority with clock source, redefine subsequent time
Clock source；In the case of determining that the clock source at current time is not more than Second Threshold with the time difference of second time, under
One moment kept the clock source at current time constant；The clock source at the clock service module current time is the multiple outside
One in clock source.
3. clock service module as claimed in claim 2, it is characterised in that the FPGA, be additionally operable to current time when
Zhong Yuan be included in it is described when can use in clock source, according to the priority with clock source, redefine subsequent time when
Zhong Yuan.
4. clock service module as claimed in claim 1, it is characterised in that the FPGA, is additionally operable to, in initialization, to connect
The time corresponding to multiple effective second valid clock sources received is asked poor two-by-two, determines two of time difference minimum
Second valid clock source, regard the second higher valid clock source of priority in described two clock sources as the clock server
Clock source.
5. clock service module as claimed in claim 1, it is characterised in that the FPGA, is additionally operable to measure the solution respectively
The 3rd time and the 4th time of each external clock reference in the successful external clock reference of code, when the 3rd time is outside
Zhong Yuan is in the time at selected moment, and the 4th time was time of the external clock reference in the later moment in time at the selected moment；By institute
The external clock reference that the difference between the 3rd time and the 4th time is less than the 3rd threshold value is stated, is determined as the first efficient clock
Source.
6. the clock service module as described in any one of claim 1 to 5, it is characterised in that the cartridge activity ear component
Set with detachable on the outside of the box body.
7. clock service module as claimed in claim 6, it is characterised in that the cartridge activity ear component includes flat board,
The cartridge part with cartridge on the outside of the box body is provided with the flat board, an end of the flat board is provided with ear portion
Part, the ear part is fixed by riveting of rising with the box body.
8. clock service module as claimed in claim 1, it is characterised in that the box body has been also housed within PMU,
One end of the PMU is electrically connected with the Main Processor Unit, the other end and the power supply list of the PMU
Member electrical connection；
The PMU is used to provide power supply by the power subsystem for the clock server, and for institute
Main Processor Unit is stated to be powered or power off.
9. the clock service module as described in claim 1 or 8, it is characterised in that it is single that the box body has been also housed within network transmitting-receiving
Member, the network Transmit-Receive Unit is connected with the Main Processor Unit, the network Transmit-Receive Unit, for by described in real-time performance
The configuration and management of clock service module.
10. the clock service module as described in claim 1 or 8, it is characterised in that the external clock reference is believed for gps clock
Number source, big-dipper satellite clock source, IRIG-B clock sources, clock synchronization compliant with precision time protocol source, TOD source, 1PPS clock sources, 1PPS+TOD clocks
Source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621481847.7U CN206564608U (en) | 2016-12-31 | 2016-12-31 | A kind of clock service module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621481847.7U CN206564608U (en) | 2016-12-31 | 2016-12-31 | A kind of clock service module |
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| Publication Number | Publication Date |
|---|---|
| CN206564608U true CN206564608U (en) | 2017-10-17 |
Family
ID=60028685
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| Application Number | Title | Priority Date | Filing Date |
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| CN201621481847.7U Active CN206564608U (en) | 2016-12-31 | 2016-12-31 | A kind of clock service module |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110971330B (en) * | 2019-11-20 | 2021-01-26 | 京信通信系统（中国）有限公司 | Time service server system and leap second automatic adjustment method |
| CN112748758A (en) * | 2020-12-28 | 2021-05-04 | 深兰人工智能(深圳)有限公司 | Clock source selection method and device, electronic equipment and storage medium |
-
2016
- 2016-12-31 CN CN201621481847.7U patent/CN206564608U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110971330B (en) * | 2019-11-20 | 2021-01-26 | 京信通信系统（中国）有限公司 | Time service server system and leap second automatic adjustment method |
| CN112748758A (en) * | 2020-12-28 | 2021-05-04 | 深兰人工智能(深圳)有限公司 | Clock source selection method and device, electronic equipment and storage medium |
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