CN209433024U - Clock synchronization circuit and ocean bottom seismograph - Google Patents

Abstract

The utility model discloses a clock synchronous circuit and a seabed seismograph, wherein the clock synchronous circuit comprises: a main clock circuit, at least one seismic data acquisition circuit, a microprocessor control circuit and at least two frequency division circuits; at least two frequency division circuits The frequency circuit includes a first frequency division circuit and a second frequency division circuit; the main clock circuit is used to generate a main clock signal; the first frequency division circuit is connected to the main clock circuit, and is used to perform frequency division processing on the main clock signal to obtain seismic data acquisition A clock signal; the seismic data acquisition circuit is connected to the first frequency division circuit for obtaining the seismic data acquisition clock signal; the second frequency division circuit is connected to the main clock circuit for frequency division processing of the main clock signal to obtain a real-time clock signal; The microprocessor control circuit is connected with the second frequency division circuit for obtaining the real-time clock signal. The clock synchronization circuit provided by the embodiment of the utility model has high time precision and low power consumption.

Description

A Clock Synchronization Circuit and Seabed Seismograph

technical field

The embodiment of the utility model relates to the field of surveying instruments, in particular to a clock synchronization circuit and a seabed seismograph.

Background technique

An undersea seismograph (OBS) is a recording instrument placed on the seabed that can directly receive artificial or natural seismic signals. Compared with conventional seismic data, the data recorded by an undersea seismograph has many advantages. For example, an undersea seismograph is deployed in On the seabed, its data recording is not easily affected by water noise and jitter, so it has a higher signal-to-noise ratio. In addition, ocean bottom seismographs also provide a wide-azimuth observation system that facilitates imaging of strata beneath complex overburdens such as salt domes and analysis of angle-dependent reflectivity. The data processing of the submarine seismograph mainly involves the arrival time of the seismic wave, which requires very high accuracy of time, so the time accuracy of the submarine seismograph data recording system is very important. Each module of the existing seabed seismograph uses an independent clock crystal oscillator, which easily leads to time disorder among the various modules of the seabed seismograph, making the time accuracy of the data recorded by the seabed seismograph not high.

Utility model content

The utility model provides a clock synchronous circuit and a seabed seismograph to improve the time accuracy of the seabed seismograph.

In the first aspect, the embodiment of the utility model provides a clock synchronization circuit, including:

a main clock circuit, at least one seismic data acquisition circuit, a microprocessor control circuit and at least two frequency dividing circuits;

The at least two frequency division circuits include a first frequency division circuit and a second frequency division circuit;

The master clock circuit is used to generate a master clock signal;

The first frequency division circuit is connected to the main clock circuit, and is used to perform frequency division processing on the main clock signal to obtain a seismic data acquisition clock signal;

The seismic data acquisition circuit is connected to the first frequency division circuit for acquiring the seismic data acquisition clock signal;

The second frequency division circuit is connected to the main clock circuit, and is used to perform frequency division processing on the main clock signal to obtain a real-time clock signal;

The microprocessor control circuit is connected to the second frequency division circuit for obtaining the real-time clock signal.

Optionally, the second frequency division circuit is directly connected to the main clock circuit, or the second frequency division circuit is connected to the main clock circuit through the first frequency division circuit.

Optionally, the at least two frequency division circuits further include a third frequency division circuit;

The third frequency division circuit is connected to the main clock circuit, and is used to perform frequency division processing on the main clock signal to obtain a second pulse signal;

The microprocessor control circuit is connected with the third frequency division circuit for acquiring the second pulse signal.

Optionally, the third frequency division circuit is directly connected to the main clock circuit, or the third frequency division circuit is connected to the main clock circuit through the first frequency division circuit and/or the second frequency division circuit. Clock circuit connection.

Optionally, the microprocessor control circuit is connected to the seismic data acquisition circuit for acquiring seismic data and processing the seismic data.

Optionally, the clock synchronization circuit further includes a GPS module connected to the microprocessor control circuit for providing standard second pulse signals and world clock signals to the microprocessor control circuit.

Optionally, the clock synchronization circuit also includes a power supply, which is connected to the main clock circuit, the seismic data acquisition circuit, the microprocessor control circuit, the frequency dividing circuit and the GPS module respectively. connected to supply power to the main clock circuit, the seismic data acquisition circuit, the microprocessor control circuit, the frequency dividing circuit and the GPS module respectively.

In the second aspect, the embodiment of the present utility model also provides a submarine seismograph, including any clock synchronization circuit described in the first aspect.

The embodiment of the utility model uses a master clock circuit, and uses at least two frequency division circuits to perform frequency division processing on the master clock signal to obtain a seismic data acquisition clock signal and a real-time clock signal, so that the clock signals of each module are consistent, which solves the existing problem. In the technology, each module of the seabed seismograph uses an independent clock crystal to cause time disorder between modules, and realizes a seabed seismograph with high time accuracy.

Description of drawings

Fig. 1 is a schematic structural diagram of a clock synchronization circuit provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of another clock synchronization circuit provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of another clock synchronization circuit provided by an embodiment of the present invention;

Fig. 4 is a schematic flow chart of a clock synchronization method provided by an embodiment of the present invention;

FIG. 5 is a schematic flow chart of another clock synchronization method provided by an embodiment of the present invention;

FIG. 6 is a schematic flowchart of another clock synchronization method provided by an embodiment of the present invention;

FIG. 7 is a flowchart of a clock synchronization method provided by an embodiment of the present invention.

Detailed ways

Below in conjunction with accompanying drawing and embodiment the utility model is described in further detail. It can be understood that the specific embodiments described here are only used to explain the utility model, rather than limit the utility model. In addition, it should be noted that, for the convenience of description, only some structures related to the present utility model are shown in the drawings but not all structures.

Fig. 1 is the structural representation of a kind of clock synchronous circuit provided by the utility model embodiment, as shown in Fig. 1, the clock synchronous circuit provided by the utility model embodiment comprises: master clock circuit 11, at least one seismic data acquisition circuit 12, Microprocessor control circuit 13 and at least two frequency division circuits 14; At least two frequency division circuits 14 include a first frequency division circuit 141 and a second frequency division circuit 142; the main clock circuit 11 is used to generate a main clock signal; the first The frequency division circuit 141 is connected with the main clock circuit 11, and is used to divide the main clock signal to obtain the seismic data acquisition clock signal; the seismic data acquisition circuit 12 is connected with the first frequency division circuit 141, and is used to obtain the seismic data acquisition clock signal ; The second frequency division circuit 142 is connected with the main clock circuit 11, and is used for carrying out frequency division processing to the main clock signal to obtain a real-time clock signal; the microprocessor control circuit 13 is connected with the second frequency division circuit 142, for obtaining the real-time clock signal .

The technical scheme of the embodiment of the utility model uses a main clock circuit 11, utilizes at least two frequency division circuits 14 to carry out frequency division processing on the main clock signal to obtain the seismic data acquisition clock signal and the real-time clock signal, the seismic data acquisition circuit 12 and the micro The clock signal of the processor control circuit 13 comes from the same master clock circuit 11, which solves the problem of inter-module time disorder caused by the use of independent clock crystal oscillators in each module of the seabed seismograph in the prior art, and realizes a high time accuracy Undersea Seismograph.

Optionally, at least two frequency division circuits 14 also include a third frequency division circuit 143; the third frequency division circuit 143 is connected to the main clock circuit 11, and is used to divide the main clock signal to obtain the second pulse signal; The controller control circuit 13 is connected to the third frequency division circuit 143 for obtaining the second pulse signal.

Optionally, the second frequency division circuit 142 is directly connected to the main clock circuit 11 , or as shown in FIG. 1 , the second frequency division circuit 142 is connected to the main clock circuit 11 through the first frequency division circuit 141 .

Optionally, the third frequency division circuit 143 is directly connected to the main clock circuit, or the third frequency division circuit 143 is connected to the main clock circuit 11 through the first frequency division circuit 141 and/or the second frequency division circuit 142. Personnel can adopt different connection modes by modifying the parameters of the frequency division circuit, so as to change and adjust the connection mode between the frequency division circuit and the main clock circuit without departing from the protection scope of the present invention.

Optionally, the second frequency dividing circuit 142 is set independently (as shown in FIG. 1 ), or is integrated in the microprocessor control circuit 13 . Exemplary, Fig. 2 is the structure diagram of another kind of clock synchronous circuit that the utility model embodiment provides, as shown in Fig. 2, the second frequency division circuit 142 is integrated in the interior of microprocessor control circuit 13, and microprocessor control The circuit 13 is connected with the main clock circuit 11 through the first frequency division circuit 141, and carries out frequency division processing to the main clock signal through the second frequency division circuit 142 inside to obtain the real-time clock signal, and the second frequency division circuit 142 is integrated in the microprocessor The inside of the controller control circuit 13 is beneficial to reduce the volume of the clock synchronization circuit.

Optionally, the microprocessor control circuit 13 is connected to the seismic data acquisition circuit 12 for acquiring seismic data and processing the seismic data.

Continue to refer to shown in Fig. 1, optional, the clock synchronous circuit that the utility model embodiment provides also comprises GPS module 15, and GPS module 15 is connected with microprocessor control circuit 13, is used to provide standard to microprocessor control circuit 13 The second pulse signal (Pulse Per Second, PPS) and the world clock signal (UTC), the microprocessor control circuit 13 is also used for the management and calculation of each clock.

Continue to refer to shown in Fig. 1, optional, the clock synchronous circuit that the utility model embodiment provides also comprises power supply 16, and power supply 16 is respectively connected with main clock circuit 11, seismic data acquisition circuit 12, microprocessor control circuit 13, frequency division The circuit 14 is electrically connected to the GPS module 15, and is used to supply power to the main clock circuit 11, the seismic data acquisition circuit 12, the microprocessor control circuit 13, the frequency division circuit 14 and the GPS module 15, respectively.

Exemplary, Fig. 3 is the structure schematic diagram of another kind of clock synchronous circuit that the utility model embodiment provides, as shown in Fig. Compensate X'tal (crystal) Oscillator, TCXO), used to provide the main clock signal. The clock synchronization circuit provided by the embodiment of the utility model includes four frequency division circuits, which are respectively the first frequency division circuit 141, the second frequency division circuit 142, the third frequency division circuit 143 and the fourth frequency division circuit 144. The clock synchronization circuit provided by the embodiment also includes two seismic data acquisition circuits (ADC) 12, which are respectively a first seismic data acquisition circuit 121 and a second seismic data acquisition circuit 122, wherein the first frequency division circuit 141 and the main clock circuit 11 connection, used to carry out frequency division processing to the main clock signal to obtain the seismic data acquisition clock signal; Data acquisition clock signal; the fourth frequency division circuit 144 is connected with the first frequency division circuit 141 and the second seismic data acquisition circuit 122, for obtaining the required seismic data acquisition clock signal of the second seismic data acquisition circuit 122; the second division Frequency circuit 142 is connected with the 4th frequency dividing circuit 144, is used to obtain real-time clock signal, and wherein, real-time clock signal is transmitted to the real-time clock of seabed seismograph, and real-time clock is used for setting the system time of seabed seismograph; The 3rd frequency-dividing circuit 143 is connected with the second frequency division circuit 142 for obtaining the second pulse signal; the microprocessor control circuit 13 is connected with the second frequency division circuit 142 and the third frequency division circuit 143 for obtaining the real-time clock signal and the second pulse signal, The microprocessor control circuit 13 is connected with the first seismic data acquisition circuit 121 and the second seismic data acquisition circuit 122 for acquiring seismic data and processing the seismic data. Optionally, the first frequency division circuit 141 adopts a frequency division circuit by 10, which is used to generate the seismic data acquisition clock signal of 1.6384Mhz required by the first seismic data acquisition circuit 121; the fourth frequency division circuit 144 adopts a frequency division circuit by 2, Used to generate the seismic data acquisition clock signal of 0.8192Mhz required by the second seismic data acquisition circuit 122; the second frequency division circuit 142 adopts a 25 frequency division circuit to generate a real-time clock signal of 32.768Khz; the third frequency division circuit 143 32768 frequency division circuit is used to generate second pulse signal. GPS module 15 is connected with microprocessor control circuit 13, is used to provide standard second pulse signal (Pulse Per Second, PPS) and world clock signal (UTC) to microprocessor control circuit 13, and microprocessor control circuit 13 is also used for The management and calculation of each clock, so that the system time of the submarine seismograph is synchronized with the standard second pulse signal and the world clock signal provided by the GPS module, and the microsecond-level synchronization between the system time of the submarine seismograph and the world standard time is realized.

The technical scheme of the embodiment of the utility model uses a main clock circuit 11, utilizes at least two frequency division circuits 14 to carry out frequency division processing on the main clock signal to obtain the seismic data acquisition clock signal and the real-time clock signal, the seismic data acquisition circuit 12 and the micro The clock signal of the processor control circuit 13 comes from the same main clock circuit 11, which solves the problem of inter-module time disorder caused by the use of independent clock crystal oscillators in each module of the submarine seismograph in the prior art, and realizes multi-channel seismic data in microseconds Level synchronization makes the time system of the submarine seismograph more accurate, ensures the validity of the seismic data, avoids the use of multiple crystal oscillators, and reduces the power consumption of the submarine seismograph. The technical solution of the utility model embodiment also adopts the GPS module to provide the standard second pulse signal and the world clock signal. The microsecond-level synchronization of time enables comparative analysis of the seismic data of the submarine seismograph and that of other stations, ensuring more accurate data analysis between different submarine seismograph stations of the same release batch.

Based on the same concept of the utility model, the embodiment of the utility model also provides a clock synchronization method, which is used for any clock synchronization circuit provided in the above embodiment, and the explanation of the same or corresponding structure and terms as the above embodiment is not described here. To repeat, Figure 4 is a schematic flow diagram of a clock synchronization method provided by an embodiment of the present invention, as shown in Figure 4, the method includes the following steps:

Step 110, the seismic data acquisition circuit divides the main clock signal by the first frequency division circuit to obtain the seismic data acquisition clock signal.

Step 120, the microprocessor control circuit divides the frequency of the main clock signal through the second frequency division circuit to obtain a real-time clock signal.

In the technical solution provided by this embodiment, there is no order requirement between step 210 and step 220, and those skilled in the art can change the above order without departing from the protection scope of the present invention.

The technical solution of the embodiment of the utility model adopts the frequency division method to divide the main clock signal to obtain the seismic data acquisition clock signal and the real-time clock signal, which solves the problem that each module of the submarine seismograph in the prior art uses an independent clock crystal oscillator The problem of time disorder makes the submarine seismograph have high time accuracy.

Figure 5 is a schematic flowchart of another clock synchronization method provided by the embodiment of the present invention, as shown in Figure 5, optionally, the clock synchronization method provided by the embodiment of the present invention may include:

Step 210, the seismic data acquisition circuit divides the main clock signal by the first frequency division circuit to obtain the seismic data acquisition clock signal.

Step 220, the microprocessor control circuit divides the frequency of the main clock signal by the second frequency division circuit to obtain a real-time clock signal.

Step 230, the microprocessor control circuit divides the frequency of the main clock signal through the third frequency division circuit to obtain the second pulse signal.

Clock synchronization circuit also includes GPS module 15, and GPS module 15 is connected with microprocessor control circuit 13, continue to refer to shown in Figure 4, optional, the clock synchronization method that the utility model embodiment provides also includes:

Step 240, the microprocessor control circuit performs the first time synchronization operation on the real-time clock signal according to the world time signal provided by the GPS module, and the first time synchronization operation is accurate to the second level.

Step 250, the microprocessor control circuit performs a second time synchronization operation on the real-time clock signal according to the standard second pulse signal provided by the GPS module, and the second time synchronization operation is accurate to within 1 millisecond.

In the technical solution provided by this embodiment, there is no order requirement among steps 210, 220 and 230, and those skilled in the art can change the above order without departing from the protection scope of the present invention.

Fig. 6 is a schematic flowchart of another clock synchronization method provided by the embodiment of the present invention. On the basis of the technical solution provided by the previous embodiment, the embodiment of the present invention further refines step 250, which is different from the above-mentioned implementation The explanations of terms that are the same as or corresponding to the examples are not repeated here.

Optionally, the microprocessor control circuit performs a second time synchronization operation on the real-time clock signal according to the standard second pulse signal provided by the GPS module, and the second time synchronization operation is accurate to within 1 millisecond, include:

The microprocessor control circuit acquires the first real-time clock signal according to the arrival time of the first falling edge of the standard second pulse signal, and the first real-time clock signal is accurate to microsecond level.

The microprocessor control circuit acquires a second real-time clock signal according to the arrival time of the second falling edge of the standard second pulse signal, and the second real-time clock signal is accurate to the microsecond level; the first falling edge and the The second falling edge is two adjacent falling edges of the standard second pulse signal in the standard second pulse signal.

Judging whether the standard second pulse signal is a continuous pulse signal according to the time difference between the second real-time clock signal and the first real-time clock signal, and calculating the second pulse signal when the standard second pulse signal is a continuous pulse signal The pulse error between the standard second pulse signal.

The pulse error is added to the real time clock signal.

Optionally, the microprocessor control circuit performs the first time synchronization operation on the real-time clock signal according to the world time signal provided by the GPS module, and the first time synchronization operation is accurate to the second level before it also includes :

The microprocessor control circuit repeatedly obtains the standard second pulse signal and the world time signal provided by the GPS module;

It is determined that the GPS module is stable according to that the standard second pulse signal and the world time signal acquired multiple times are correct signals.

Based on the above refinement and addition, as shown in Figure 6, the clock synchronization method provided by the embodiment of the present invention may include the following steps:

Step 401, the seismic data acquisition circuit divides the main clock signal by the first frequency division circuit to obtain the seismic data acquisition clock signal.

Step 402, the microprocessor control circuit divides the frequency of the main clock signal by the second frequency division circuit to obtain a real-time clock signal.

Step 403, the microprocessor control circuit divides the main clock signal by the third frequency division circuit to obtain the second pulse signal.

Step 404, the microprocessor control circuit obtains the standard second pulse signal and the world time signal provided by the GPS module multiple times.

Step 405. Determine that the GPS module is stable according to the standard second pulse signal and the world time signal acquired multiple times are correct signals.

Step 406, the microprocessor control circuit performs the first time synchronization operation on the real-time clock signal according to the world time signal provided by the GPS module, and the first time synchronization operation is accurate to the second level.

Step 407, the microprocessor control circuit acquires a first real-time clock signal according to the arrival time of the first falling edge of the standard second pulse signal, and the first real-time clock signal is accurate to microsecond level.

Step 408, the microprocessor control circuit acquires a second real-time clock signal according to the arrival time of the second falling edge of the standard second pulse signal, and the second real-time clock signal is accurate to the microsecond level; the first falling edge and the second falling edge are two adjacent falling edges of the standard second pulse signal in the standard second pulse signal.

Wherein, optionally, the microprocessor control circuit can also acquire the first real-time clock signal and the second real-time clock signal according to the rising edge of the standard second pulse signal, which is not limited in the present invention.

Step 409, judge whether the standard second pulse signal is a continuous pulse signal according to the time difference between the second real-time clock signal and the first real-time clock signal, and calculate when the standard second pulse signal is a continuous pulse signal The pulse error between the second pulse signal and the standard second pulse signal.

Step 410, adding the pulse error into the real-time clock signal.

Exemplarily, FIG. 7 is a flow chart of a clock synchronization method provided by an embodiment of the present invention. Referring to FIG. 7 , firstly, start the GPS module. Among them, after turning on the seabed seismograph and ensuring that the microprocessor control circuit (MCU) works normally, turn on the power of the GPS module, start the GPS module, and wait for the GPS module to obtain the correct standard pulse per second signal (PulsePer Second, PPS) and world clock signal (UTC).

Then, the microprocessor control circuit obtains the standard second pulse signal and the world time signal provided by the GPS module for many times and determines that the GPS module is stable according to the standard second pulse signal and the world time signal obtained many times are correct signals. Among them, the serial port information provided by the GPS module includes an identifier whether the signal is correct, and the microprocessor control circuit confirms whether the standard second pulse signal and the world time signal provided by the GPS module are correct by distinguishing the identifier. The control circuit obtains more than 10 correct standard second pulse signals and world time signals to ensure the stability of the GPS module.

The microprocessor control circuit performs the first time synchronization operation on the real-time clock signal according to the world time signal provided by the GPS module, and the first time synchronization operation is accurate to the second level. Among them, the time information such as year, month, day, hour, minute, and second included in the serial port information output by the GPS module is used to synchronize the real-time clock signal, thereby completing time synchronization with an accuracy of second level.

The microprocessor control circuit acquires the first real-time clock signal according to the arrival time of the first falling edge of the standard second pulse signal, and the first real-time clock signal is accurate to microsecond level. Wherein, the microprocessor control circuit judges whether the first falling edge of the standard second pulse signal arrives, and when the microprocessor control circuit captures the first falling edge of the standard second pulse signal, then reads the first real-time clock signal at this moment, The first real-time clock signal is accurate to microsecond level and saved.

The microprocessor control circuit obtains the second real-time clock signal according to the arrival time of the second falling edge of the standard second pulse signal, and the second real-time clock signal is accurate to the microsecond level; the first falling edge and the second falling edge are in the standard second pulse signal Falling edges of two adjacent standard second pulse signals. Wherein, after obtaining the first real-time clock signal, the microprocessor control circuit waits for the falling edge of the next standard second pulse signal to arrive, and the falling edge of the next standard second pulse signal is the second falling edge of the standard second pulse signal. The microprocessor control circuit captures the second falling edge of the standard second pulse signal, then acquires the second real-time clock signal at this moment, and stores the second real-time clock signal accurately to the microsecond level.

Judge whether the standard second pulse signal is a continuous pulse signal according to the time difference between the second real-time clock signal and the first real-time clock signal, and calculate the time difference between the second pulse signal and the standard second pulse signal when the standard second pulse signal is a continuous pulse signal pulse error. Among them, if the value differs by one second, it means that the two PPS intervals are continuous. The microprocessor control circuit makes a difference between the time of the second real clock signal and the first real clock signal, and judges whether the difference is one second, if the microprocessor control circuit judges the time of the second real clock signal and the first real clock signal If the difference is one second, it is determined that the standard second pulse signal is a continuous pulse signal. Otherwise, the standard second pulse signal is not a continuous pulse signal. At this time, the first real-time clock signal needs to be acquired again according to the arrival time of the first falling edge of the standard second pulse signal. . If the standard second pulse signal is a continuous pulse signal, at this time, the error between the second pulse signal and the standard second pulse signal below the second precision or the error below the millisecond level is the actual error between the submarine seismograph system time and the universal standard time, calculated by the counter The pulse error between the second pulse signal and the standard second pulse signal.

Adds pulse error to the real-time clock signal. Among them, the number of pulse errors is added to the pulse counter in the real-time clock (RTC), thereby eliminating the error between the time of the real-time clock signal and the standard second pulse signal, thereby completing the time of the real-time clock signal and the world standard millisecond level For the following time synchronization, turn off the GPS module after the time synchronization is completed to reduce energy consumption.

The technical solution of the embodiment of the utility model adopts the frequency division method to divide the main clock signal to obtain the seismic data acquisition clock signal and the real-time clock signal, which solves the problem that each module of the submarine seismograph in the prior art uses an independent clock crystal oscillator The problem of temporal disorder makes the submarine seismograph have high time accuracy and low power consumption, and ensures the validity of seismic data. The technical solution of the embodiment of the utility model also realizes the system time of the seabed seismograph and the microsecond level of the world standard time by synchronizing the real-time clock signal and the second pulse signal with the standard second pulse signal and the world clock signal provided by the GPS module Synchronization, the maximum time error between the system time of the submarine seismograph and the universal standard time is within 30us, and the design requirement of accurate synchronization within 1ms is guaranteed, so that the seismic data of the submarine seismograph and the seismic data of other stations can be synchronized The comparative analysis ensures more accurate data analysis among different submarine seismograph stations of the same launch batch.

Based on the same concept of the utility model, the embodiment of the utility model also provides a submarine seismograph, including any clock synchronization circuit provided by the above embodiment, and the same or corresponding structure and terminology as the above embodiment are not explained here. repeat.

Note that the above are only preferred embodiments of the present invention and the applied technical principles. Those skilled in the art will understand that the utility model is not limited to the specific embodiments described here, and various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the utility model. Therefore, although the utility model has been described in detail through the above embodiments, the utility model is not limited to the above embodiments, and can also include more other equivalent embodiments without departing from the concept of the utility model. The scope of the present invention is determined by the appended claims.

Claims (8)

1. a kind of clock synchronization circuit characterized by comprising

Master clock circuit, at least one earthquake data acquisition circuit, microprocessor control circuit and at least two frequency dividing circuits；

At least two frequency dividing circuits include the first frequency dividing circuit and the second frequency dividing circuit；

The master clock circuit is for generating master clock signal；

First frequency dividing circuit is connect with the master clock circuit, is obtained for carrying out scaling down processing to the master clock signal Earthquake data acquisition clock signal；

The earthquake data acquisition circuit is connect with first frequency dividing circuit, for obtaining the earthquake data acquisition clock letter Number；

Second frequency dividing circuit is connect with the master clock circuit, is obtained for carrying out scaling down processing to the master clock signal Real-time clock signal；

The microprocessor control circuit is connect with second frequency dividing circuit, for obtaining the real-time clock signal.

2. clock synchronization circuit according to claim 1, which is characterized in that second frequency dividing circuit directly with the master Clock circuit connection or second frequency dividing circuit are connect by first frequency dividing circuit with the master clock circuit.

3. clock synchronization circuit according to claim 1, which is characterized in that at least two frequency dividing circuit further includes Divide-by-3 circuit；

The third frequency dividing circuit is connect with the master clock circuit, is obtained for carrying out scaling down processing to the master clock signal Second pulse signal；

The microprocessor control circuit is connect with the third frequency dividing circuit, for obtaining the second pulse signal.

4. clock synchronization circuit according to claim 3, which is characterized in that the third frequency dividing circuit directly with the master Clock circuit connection or the third frequency dividing circuit by first frequency dividing circuit and/or second frequency dividing circuit with The master clock circuit connection.

5. clock synchronization circuit according to claim 1, which is characterized in that the microprocessor control circuit is with described Data acquisition circuit connection is shaken, for obtaining seismic data and handling the seismic data.

6. clock synchronization circuit according to claim 1, which is characterized in that further include GPS module, the GPS module with The microprocessor control circuit connection, for providing standard second pulse signal and universal time to the microprocessor control circuit Clock signal.

7. clock synchronization circuit according to claim 6, which is characterized in that further include power supply, the power supply respectively with institute State master clock circuit, the earthquake data acquisition circuit, the microprocessor control circuit, the frequency dividing circuit and the GPS Module electrical connection, for respectively to the master clock circuit, the earthquake data acquisition circuit, microprocessor control electricity Road, the frequency dividing circuit and GPS module power supply.

8. a kind of submarine seismograph, which is characterized in that including the described in any item clock synchronization circuits of claim 1-7.