CN109738954B - Clock synchronization circuit, clock synchronization method and submarine seismograph - Google Patents
Clock synchronization circuit, clock synchronization method and submarine seismograph Download PDFInfo
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- CN109738954B CN109738954B CN201910194086.9A CN201910194086A CN109738954B CN 109738954 B CN109738954 B CN 109738954B CN 201910194086 A CN201910194086 A CN 201910194086A CN 109738954 B CN109738954 B CN 109738954B
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- G—PHYSICS
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- G01V—GEOPHYSICS; GRAVITATIONAL MEASUREMENTS; DETECTING MASSES OR OBJECTS; TAGS
- G01V1/00—Seismology; Seismic or acoustic prospecting or detecting
- G01V1/38—Seismology; Seismic or acoustic prospecting or detecting specially adapted for water-covered areas
Abstract
The invention discloses a clock synchronization circuit, a clock synchronization method and a submarine seismograph, wherein the clock synchronization circuit comprises the following components: the system comprises a main clock circuit, at least one seismic data acquisition circuit, a microprocessor control circuit and at least two frequency dividing circuits; the at least two frequency dividing circuits comprise a first frequency dividing circuit and a second frequency dividing circuit; the master clock circuit is used for generating a master clock signal; the first frequency dividing circuit is connected with the main clock circuit and is used for carrying out frequency division processing on the main clock signal to obtain a seismic data acquisition clock signal; the seismic data acquisition circuit is connected with the first frequency division circuit and is used for acquiring a seismic data acquisition clock signal; the second frequency division circuit is connected with the main clock circuit and is used for carrying out frequency division processing on the main clock signal to obtain a real-time clock signal; the microprocessor control circuit is connected with the second frequency division circuit and is used for acquiring the real-time clock signal.
Description
Technical Field
The embodiment of the invention relates to the field of surveying instruments, in particular to a clock synchronization circuit, a clock synchronization method and a submarine seismograph.
Background
A seafloor seismograph (OBS) is a recording instrument placed on the ocean floor and capable of directly receiving artificial or natural seismic signals, and compared with conventional seismic data, data recorded by the seafloor seismograph has various advantages, for example, the seafloor seismograph is arranged on the ocean floor, and the data recording is not easily affected by noise and jitter of a water body, so that the seafloor seismograph has higher signal to noise ratio. In addition, the ocean bottom seismograph also provides a wide-azimuth observation system, which is beneficial to imaging the stratum under a complex covering layer (such as a salt dome) and analyzing the reflectivity related to angles. The data processing of the submarine seismograph mainly relates to the arrival time of seismic waves, and the time accuracy requirement is very high, so that the time accuracy of the submarine seismograph data recording system is very important. Each module of the existing submarine seismograph adopts an independent clock crystal oscillator, so that time disorder among each module of the submarine seismograph is easy to occur, and the time accuracy of data recording of the submarine seismograph is low.
Disclosure of Invention
The invention provides a clock synchronization circuit, a clock synchronization method and a submarine seismograph, which are used for improving the time accuracy of the submarine seismograph.
In a first aspect, an embodiment of the present invention provides a clock synchronization circuit, including:
the system comprises a main clock circuit, at least one seismic data acquisition circuit, a microprocessor control circuit and at least two frequency dividing circuits;
the at least two frequency dividing circuits comprise a first frequency dividing circuit and a second frequency dividing circuit;
the master clock circuit is used for generating a master clock signal;
the first frequency dividing circuit is connected with the main clock circuit and is used for carrying out frequency division processing on the main clock signal to obtain a seismic data acquisition clock signal;
the seismic data acquisition circuit is connected with the first frequency division circuit and is used for acquiring the seismic data acquisition clock signal;
the second frequency division circuit is connected with the main clock circuit and is used for carrying out frequency division processing on the main clock signal to obtain a real-time clock signal;
the microprocessor control circuit is connected with the second frequency division circuit and is used for acquiring the real-time clock signal.
Optionally, the second frequency division circuit is directly connected with the master clock circuit, or the second frequency division circuit is connected with the master clock circuit through the first frequency division circuit.
Optionally, the at least two frequency dividing circuits further include a third frequency dividing circuit;
the third frequency dividing circuit is connected with the main clock circuit and is used for carrying out frequency division processing on the main clock signal to obtain a second pulse signal;
the microprocessor control circuit is connected with the third frequency dividing circuit and is used for acquiring the second pulse signal.
Optionally, the third frequency dividing circuit is directly connected with the master clock circuit, or the third frequency dividing circuit is connected with the master clock circuit through the first frequency dividing circuit and/or the second frequency dividing circuit.
Optionally, the microprocessor control circuit is connected with the seismic data acquisition circuit and is used for acquiring seismic data and processing the seismic data.
Optionally, the clock synchronization circuit further includes a GPS module, which is connected to the microprocessor control circuit and configured to provide the microprocessor control circuit with a standard second pulse signal and a world clock signal.
Optionally, the clock synchronization circuit further includes a power source, where the power source is electrically connected to the master clock circuit, the seismic data acquisition circuit, the microprocessor control circuit, the frequency dividing circuit, and the GPS module, and is configured to supply power to the master clock circuit, the seismic data acquisition circuit, the microprocessor control circuit, the frequency dividing circuit, and the GPS module, respectively.
In a second aspect, an embodiment of the present invention further provides a clock synchronization method, for any clock synchronization circuit in the first aspect, where the method includes:
the seismic data acquisition circuit carries out frequency division on the main clock signal through a first frequency division circuit to acquire a seismic data acquisition clock signal;
the microprocessor control circuit divides the frequency of the main clock signal through the second frequency division circuit to obtain a real-time clock signal.
Optionally, the clock synchronization method further includes:
the microprocessor control circuit divides the frequency of the main clock signal through the third frequency division circuit to obtain a second pulse signal.
Optionally, the clock synchronization circuit further includes a GPS module, and the GPS module is connected to the microprocessor control circuit;
the clock synchronization method further comprises the following steps:
the microprocessor control circuit performs a first time synchronization operation on the real-time clock signal according to the world time signal provided by the GPS module, wherein the first time synchronization operation is accurate to a second level;
and the microprocessor control circuit performs a second time synchronization operation on the real-time clock signal according to the standard second pulse signal provided by the GPS module, wherein the second time synchronization operation is accurate to within 1 millisecond.
Optionally, the microprocessor control circuit performs a second time synchronization operation on the real-time clock signal according to a standard second pulse signal provided by the GPS module, where the second time synchronization operation is accurate to within 1 millisecond, and includes:
the microprocessor control circuit acquires a first real-time clock signal according to the arrival time of a first falling edge of the standard second pulse signal, and the first real-time clock signal is accurate to a microsecond level;
the microprocessor control circuit acquires a second real-time clock signal according to the arrival time of a second falling edge of the standard second pulse signal, and the second real-time clock signal is accurate to a microsecond level; the first falling edge and the second falling edge are adjacent two standard second pulse signal falling edges in the standard second pulse signals;
judging whether the standard pulse-second signal is a continuous pulse signal according to the time difference value of the second real-time clock signal and the first real-time clock signal, and calculating a pulse error between the pulse-second signal and the standard pulse-second signal when the standard pulse-second signal is the continuous pulse signal;
the pulse error is added to the real time clock signal.
Optionally, the microprocessor control circuit performs a first time synchronization operation on the real-time clock signal according to the universal time signal provided by the GPS module, where the first time synchronization operation is accurate to a second level, and further includes:
the microprocessor control circuit acquires a standard second pulse signal and a world time signal provided by the GPS module for a plurality of times;
and determining that the GPS module is stable according to the fact that the standard second pulse signal and the world time signal which are acquired for many times are correct signals.
In a third aspect, embodiments of the present invention also provide a marine seismometer comprising any of the clock synchronization circuits of the first aspect.
According to the embodiment of the invention, the master clock signal is subjected to frequency division processing by using at least two frequency division circuits to obtain the seismic data acquisition clock signal and the real-time clock signal, so that the clock signals of all modules are consistent, the problem of inter-module time disorder caused by the fact that all modules of the submarine seismograph use independent clock crystals in the prior art is solved, and the submarine seismograph with high time accuracy is realized.
Drawings
Fig. 1 is a schematic diagram of a clock synchronization circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another clock synchronization circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a clock synchronization circuit according to an embodiment of the present invention;
fig. 4 is a schematic flow chart of a clock synchronization method according to an embodiment of the present invention;
FIG. 5 is a flowchart of another clock synchronization method according to an embodiment of the present invention;
FIG. 6 is a flowchart of another clock synchronization method according to an embodiment of the present invention;
fig. 7 is a flowchart of a clock synchronization method according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Fig. 1 is a schematic structural diagram of a clock synchronization circuit according to an embodiment of the present invention, where, as shown in fig. 1, the clock synchronization circuit according to the embodiment of the present invention includes: a main clock circuit 11, at least one seismic data acquisition circuit 12, a microprocessor control circuit 13 and at least two frequency dividing circuits 14; the at least two frequency dividing circuits 14 include a first frequency dividing circuit 141 and a second frequency dividing circuit 142; the master clock circuit 11 is used for generating a master clock signal; the first frequency dividing circuit 141 is connected to the master clock circuit 11, and is configured to perform frequency division processing on the master clock signal to obtain a seismic data acquisition clock signal; the seismic data acquisition circuit 12 is connected with the first frequency division circuit 141 and is used for acquiring a seismic data acquisition clock signal; the second frequency dividing circuit 142 is connected to the master clock circuit 11, and is configured to perform frequency division processing on the master clock signal to obtain a real-time clock signal; the microprocessor control circuit 13 is connected to the second frequency dividing circuit 142 for acquiring a real-time clock signal.
According to the technical scheme provided by the embodiment of the invention, the main clock circuit 11 is used, at least two frequency dividing circuits 14 are used for carrying out frequency division processing on the main clock signals to obtain the seismic data acquisition clock signals and the real-time clock signals, the clock signals of the seismic data acquisition circuit 12 and the microprocessor control circuit 13 come from the same main clock circuit 11, the problem of inter-module time disorder caused by the fact that each module of the submarine seismograph uses independent clock crystal oscillator in the prior art is solved, and the submarine seismograph with high time accuracy is realized.
Optionally, the at least two frequency dividing circuits 14 further comprise a third frequency dividing circuit 143; the third frequency dividing circuit 143 is connected to the master clock circuit 11, and is configured to perform frequency dividing processing on the master clock signal to obtain a second pulse signal; the microprocessor control circuit 13 is connected to the third frequency dividing circuit 143 for acquiring the second pulse signal.
Alternatively, the second frequency dividing circuit 142 is directly connected to the master clock circuit 11, or as shown in fig. 1, the second frequency dividing circuit 142 is connected to the master clock circuit 11 through the first frequency dividing circuit 141.
Optionally, the third frequency dividing circuit 143 is directly connected to the master clock circuit, or the third frequency dividing circuit 143 is connected to the master clock circuit 11 through the first frequency dividing circuit 141 and/or the second frequency dividing circuit 142, and a person skilled in the art can modify parameters of the frequency dividing circuits to use different connection modes, so that the connection modes of the frequency dividing circuits and the master clock circuit are changed and adjusted without departing from the protection scope of the present invention.
Alternatively, the second frequency dividing circuit 142 may be provided separately (as shown in fig. 1) or integrated into the microprocessor control circuit 13. Fig. 2 is a schematic diagram of another clock synchronization circuit according to an embodiment of the present invention, as shown in fig. 2, a second frequency dividing circuit 142 is integrated inside the microprocessor control circuit 13, the microprocessor control circuit 13 is connected to the master clock circuit 11 through the first frequency dividing circuit 141, and performs frequency division processing on the master clock signal through the second frequency dividing circuit 142 to obtain a real-time clock signal, and integrating the second frequency dividing circuit 142 inside the microprocessor control circuit 13 is beneficial to reducing the volume of the clock synchronization circuit.
Optionally, the microprocessor control circuit 13 is connected to the seismic data acquisition circuit 12, and is used for acquiring and processing the seismic data.
With continued reference to fig. 1, optionally, the clock synchronization circuit provided in the embodiment of the present invention further includes a GPS module 15, where the GPS module 15 is connected to the microprocessor control circuit 13, and is configured to provide a standard Pulse Per Second (PPS) signal and a Universal Time Clock (UTC) signal to the microprocessor control circuit 13, and the microprocessor control circuit 13 is further configured to manage and calculate each clock.
With continued reference to fig. 1, optionally, the clock synchronization circuit provided in the embodiment of the present invention further includes a power supply 16, where the power supply 16 is electrically connected to the main clock circuit 11, the seismic data acquisition circuit 12, the microprocessor control circuit 13, the frequency dividing circuit 14, and the GPS module 15, respectively, and is configured to supply power to the main clock circuit 11, the seismic data acquisition circuit 12, the microprocessor control circuit 13, the frequency dividing circuit 14, and the GPS module 15, respectively.
For example, fig. 3 is a schematic diagram of a clock synchronization circuit according to another embodiment of the present invention, as shown in fig. 3, a high-precision temperature compensated quartz crystal resonator TCXO (Temperature Compensate X' al (TCXO)) of 16.384Mhz is used for providing a master clock signal in the master clock circuit 11. The clock synchronization circuit provided by the embodiment of the invention comprises four frequency division circuits, namely a first frequency division circuit 141, a second frequency division circuit 142, a third frequency division circuit 143 and a fourth frequency division circuit 144, and also comprises two seismic data acquisition circuits (ADC) 12, namely a first seismic data acquisition circuit 121 and a second seismic data acquisition circuit 122, wherein the first frequency division circuit 141 is connected with a main clock circuit 11 and is used for performing frequency division processing on a main clock signal to obtain a seismic data acquisition clock signal; the first seismic data acquisition circuit 121 is connected with the first frequency division circuit 141 and is used for acquiring a seismic data acquisition clock signal required by the first seismic data acquisition circuit 121; the fourth frequency dividing circuit 144 is connected to the first frequency dividing circuit 141 and the second seismic data acquisition circuit 122, and is configured to acquire a seismic data acquisition clock signal required by the second seismic data acquisition circuit 122; the second frequency dividing circuit 142 is connected to the fourth frequency dividing circuit 144, and is configured to obtain a real-time clock signal, where the real-time clock signal is transmitted to a real-time clock of the seafloor seismograph, and the real-time clock is used for setting a system time of the seafloor seismograph; the third frequency dividing circuit 143 is connected to the second frequency dividing circuit 142, and is used for acquiring a second pulse signal; the microprocessor control circuit 13 is connected to the second frequency dividing circuit 142 and the third frequency dividing circuit 143, and is used for acquiring a real-time clock signal and a second pulse signal, and the microprocessor control circuit 13 is connected to the first seismic data acquisition circuit 121 and the second seismic data acquisition circuit 122, and is used for acquiring and processing seismic data. Optionally, the first frequency dividing circuit 141 is a frequency dividing circuit 10, and is configured to generate a 1.6384Mhz seismic data acquisition clock signal required by the first seismic data acquisition circuit 121; the fourth frequency dividing circuit 144 adopts a frequency dividing circuit of 2 for generating a 0.8192Mhz seismic data acquisition clock signal required by the second seismic data acquisition circuit 122; the second frequency dividing circuit 142 employs a 25 frequency dividing circuit for generating a real-time clock signal of 32.768 Khz; the third frequency dividing circuit 143 employs a 32768 frequency dividing circuit for generating a second pulse signal. The GPS module 15 is connected to the microprocessor control circuit 13, and is configured to provide a standard Pulse Per Second (PPS) signal and a universal time signal (UTC) to the microprocessor control circuit 13, where the microprocessor control circuit 13 is further configured to manage and calculate each clock, so that the system time of the seafloor seismograph is calibrated and synchronized with the standard Pulse Per Second signal and the universal time signal provided by the GPS module, and microsecond synchronization between the system time of the seafloor seismograph and the universal standard time is achieved.
According to the technical scheme, the master clock circuit 11 is used, at least two frequency dividing circuits 14 are used for carrying out frequency division processing on the master clock signals to obtain the seismic data acquisition clock signals and the real-time clock signals, the clock signals of the seismic data acquisition circuit 12 and the microprocessor control circuit 13 come from the same master clock circuit 11, the problem of time disorder among modules caused by the fact that independent clock crystal oscillators are used for all modules of the submarine seismograph in the prior art is solved, microsecond synchronization of multichannel seismic data is achieved, a submarine seismograph time system is more accurate, validity of the seismic data is guaranteed, the use of multiple crystal oscillators is avoided, and power consumption of the submarine seismograph is reduced. The technical scheme of the embodiment of the invention also adopts the GPS module to provide the standard second pulse signal and the world clock signal, and the submarine seismograph is calibrated and synchronized with the GPS module to realize microsecond synchronization of the submarine seismograph and the world standard time, so that the seismic data of the submarine seismograph and the seismic data of other stations can be compared and analyzed, and the data analysis between different submarine seismograph stations in the same put batch can be ensured to be more accurate.
Based on the same inventive concept, the embodiment of the present invention further provides a clock synchronization method, which is used for any clock synchronization circuit provided in the above embodiment, and the explanation of the same or corresponding structure and terms as those of the above embodiment is not repeated herein, and fig. 4 is a schematic flow chart of a clock synchronization method provided in the embodiment of the present invention, as shown in fig. 4, and the method includes the following steps:
step 110, the seismic data acquisition circuit divides the frequency of the master clock signal through the first frequency division circuit to acquire a seismic data acquisition clock signal.
Step 120, the microprocessor control circuit divides the frequency of the master clock signal by the second frequency division circuit to obtain a real-time clock signal.
In the technical solution provided in this embodiment, no sequence requirement exists between the step 210 and the step 220, and a person skilled in the art can change the sequence without departing from the protection scope of the present invention.
According to the technical scheme provided by the embodiment of the invention, the main clock signal is subjected to frequency division to obtain the seismic data acquisition clock signal and the real-time clock signal, so that the problem of inter-module time disorder caused by the fact that each module of the submarine seismograph uses an independent clock crystal oscillator in the prior art is solved, and the submarine seismograph has higher time accuracy.
Fig. 5 is a flow chart of another clock synchronization method provided by an embodiment of the present invention, and as shown in fig. 5, optionally, the clock synchronization method provided by the embodiment of the present invention may include:
step 210, the seismic data acquisition circuit divides the frequency of the master clock signal by the first frequency division circuit to acquire a seismic data acquisition clock signal.
Step 220, the microprocessor control circuit divides the frequency of the master clock signal by the second frequency division circuit to obtain a real-time clock signal.
Step 230, the microprocessor control circuit divides the frequency of the master clock signal by the third frequency division circuit to obtain a second pulse signal.
The clock synchronization circuit further includes a GPS module 15, where the GPS module 15 is connected to the microprocessor control circuit 13, and referring to fig. 4, optionally, the clock synchronization method provided by the embodiment of the present invention further includes:
step 240, the microprocessor control circuit performs a first time synchronization operation on the real-time clock signal according to the universal time signal provided by the GPS module, where the first time synchronization operation is accurate to a second level.
Step 250, the microprocessor control circuit performs a second time synchronization operation on the real-time clock signal according to the standard second pulse signal provided by the GPS module, where the second time synchronization operation is accurate to within 1 millisecond.
In the technical solution provided in this embodiment, no sequence is required between step 210, step 220 and step 230, and a person skilled in the art can change the sequence without departing from the scope of the present invention.
Fig. 6 is a flowchart of another clock synchronization method according to an embodiment of the present invention, where step 250 is further refined based on the technical solution provided in the previous embodiment, and explanation of the same or corresponding terms as those of the previous embodiment is not repeated herein.
Optionally, the microprocessor control circuit performs a second time synchronization operation on the real-time clock signal according to a standard second pulse signal provided by the GPS module, where the second time synchronization operation is accurate to within 1 millisecond, and includes:
the microprocessor control circuit acquires a first real-time clock signal according to the arrival time of a first falling edge of the standard second pulse signal, and the first real-time clock signal is accurate to a microsecond level.
The microprocessor control circuit acquires a second real-time clock signal according to the arrival time of a second falling edge of the standard second pulse signal, and the second real-time clock signal is accurate to a microsecond level; the first falling edge and the second falling edge are adjacent two standard second pulse signal falling edges in the standard second pulse signal.
Judging whether the standard pulse-second signal is a continuous pulse signal according to the time difference value of the second real-time clock signal and the first real-time clock signal, and calculating a pulse error between the pulse-second signal and the standard pulse-second signal when the standard pulse-second signal is the continuous pulse signal.
The pulse error is added to the real time clock signal.
Optionally, the microprocessor control circuit performs a first time synchronization operation on the real-time clock signal according to the universal time signal provided by the GPS module, where the first time synchronization operation is accurate to a second level, and further includes:
the microprocessor control circuit acquires a standard second pulse signal and a world time signal provided by the GPS module for a plurality of times;
and determining that the GPS module is stable according to the fact that the standard second pulse signal and the world time signal which are acquired for many times are correct signals.
Based on the refinement and the addition, as shown in fig. 6, the clock synchronization method provided by the embodiment of the invention may include the following steps:
step 401, the seismic data acquisition circuit divides the frequency of the master clock signal through the first frequency division circuit to acquire a seismic data acquisition clock signal.
Step 402, the microprocessor control circuit divides the frequency of the master clock signal by the second frequency division circuit to obtain a real-time clock signal.
Step 403, the microprocessor control circuit divides the frequency of the master clock signal by the third frequency division circuit to obtain a second pulse signal.
Step 404, the microprocessor control circuit acquires the standard second pulse signal and the world time signal provided by the GPS module for a plurality of times.
And step 405, determining that the GPS module is stable according to the standard second pulse signal and the world time signal which are acquired for many times are correct signals.
Step 406, the microprocessor control circuit performs a first time synchronization operation on the real-time clock signal according to the world time signal provided by the GPS module, where the first time synchronization operation is accurate to a second level.
Step 407, the microprocessor control circuit obtains a first real-time clock signal according to the arrival time of the first falling edge of the standard second pulse signal, where the first real-time clock signal is accurate to a microsecond level.
Step 408, the microprocessor control circuit obtains a second real-time clock signal according to the arrival time of the second falling edge of the standard second pulse signal, wherein the second real-time clock signal is accurate to a microsecond level; the first falling edge and the second falling edge are adjacent two standard second pulse signal falling edges in the standard second pulse signal.
Optionally, the microprocessor control circuit may also acquire the first real-time clock signal and the second real-time clock signal according to a rising edge of the standard second pulse signal, which is not limited in the present invention.
Step 409, determining whether the standard pulse-second signal is a continuous pulse signal according to the time difference between the second real-time clock signal and the first real-time clock signal, and calculating a pulse error between the pulse-second signal and the standard pulse-second signal when the standard pulse-second signal is the continuous pulse signal.
Step 410, adding the pulse error to the real time clock signal.
Fig. 7 is a flowchart of a clock synchronization method according to an embodiment of the present invention, and referring to fig. 7, a GPS module is started first. After the submarine seismograph is started and a microprocessor control circuit (MCU) is ensured to work normally, a GPS module power supply is started, and the GPS module is started to wait for the GPS module to acquire a correct standard Pulse Per Second (PPS) signal and a Universal Time Clock (UTC).
And then, the microprocessor control circuit acquires the standard second pulse signal and the world time signal provided by the GPS module for a plurality of times and determines that the GPS module is stable according to the correct signals of the standard second pulse signal and the world time signal which are acquired for a plurality of times. The serial port information provided by the GPS module is provided with an identifier for judging whether the signal is correct or not, and the microprocessor control circuit confirms whether the standard second pulse signal and the world time signal provided by the GPS module are correct or not by judging the identifier, and the microprocessor control circuit acquires the correct standard second pulse signal and the world time signal for more than 10 times so as to ensure the stability of the GPS module.
The microprocessor control circuit performs a first time synchronization operation on the real-time clock signal according to the world time signal provided by the GPS module, wherein the first time synchronization operation is accurate to a second level. The real-time clock signal is synchronized by using time information such as year, month, day, time and second contained in serial port information output by the GPS module, so that time synchronization with accuracy of second level is completed.
The microprocessor control circuit acquires a first real-time clock signal according to the arrival time of a first falling edge of the standard second pulse signal, and the first real-time clock signal is accurate to a microsecond level. The microprocessor control circuit judges whether the first falling edge of the standard second pulse signal comes or not, and when the microprocessor control circuit captures the first falling edge of the standard second pulse signal, the microprocessor control circuit reads the first real-time clock signal at the moment, and the first real-time clock signal is accurate to a microsecond level and stored.
The microprocessor control circuit acquires a second real-time clock signal according to the arrival time of a second falling edge of the standard second pulse signal, and the second real-time clock signal is accurate to a microsecond level; the first falling edge and the second falling edge are adjacent two falling edges of the standard second pulse signals. After the first real-time clock signal is acquired, the microprocessor control circuit waits for the falling edge of the next standard second pulse signal to arrive, wherein the falling edge of the next standard second pulse signal is the second falling edge of the standard second pulse signal, and when the microprocessor control circuit captures the second falling edge of the standard second pulse signal, the second real-time clock signal at the moment is acquired, and the second real-time clock signal is accurately in a microsecond level and stored.
And judging whether the standard pulse-per-second signal is a continuous pulse signal according to the time difference value of the second real-time clock signal and the first real-time clock signal, and calculating the pulse error between the pulse-per-second signal and the standard pulse-per-second signal when the standard pulse-per-second signal is the continuous pulse signal. Wherein if the values differ by one second this two PPS intervals are consecutive. The microprocessor control circuit makes a difference between the time of the second real-time clock signal and the time of the first real-time clock signal to judge whether the difference is one second, if the microprocessor control circuit judges that the time difference between the second real-time clock signal and the first real-time clock signal is one second, the microprocessor control circuit judges that the standard second pulse signal is a continuous pulse signal, otherwise, the standard second pulse signal is not the continuous pulse signal, and at the moment, the first real-time clock signal needs to be acquired again according to the arrival time of the first falling edge of the standard second pulse signal. If the standard pulse per second signal is a continuous pulse signal, at the moment, the error below the second precision of the pulse per second signal and the standard pulse per second signal or the error below the millisecond level is the actual error of the system time of the submarine seismograph and the world standard time, and the pulse error between the pulse per second signal and the standard pulse per second signal is calculated through a counter.
The pulse error is added to the real time clock signal. The pulse error number is increased to a pulse counter in a real-time clock (RTC), so that the error between the time of a real-time clock signal and a standard second pulse signal is eliminated, the time synchronization of the real-time clock signal and the time below the world standard time millisecond level is completed, the GPS module is closed after the time synchronization is completed, and the energy consumption is reduced.
According to the technical scheme, the frequency division method is adopted to divide the main clock signal to obtain the seismic data acquisition clock signal and the real-time clock signal, so that the problem of inter-module time disorder caused by the fact that each module of the submarine seismograph uses an independent clock crystal oscillator in the prior art is solved, the submarine seismograph has higher time accuracy and lower power consumption, and the effectiveness of seismic data is ensured. The technical scheme of the embodiment of the invention also provides the standard second pulse signal and the world clock signal for calibration synchronization by the real-time clock signal and the second pulse signal with the GPS module, so that microsecond synchronization of the system time of the submarine seismograph and the world standard time is realized, the time error of the system time of the submarine seismograph and the world standard time is up to 30us, the design requirement of accurate synchronization of the error within 1ms is ensured to be met, the seismic data of the submarine seismograph and the seismic data of other stations can be compared and analyzed, and more accurate data analysis among different submarine seismograph stations in the same put batch is ensured.
Based on the same inventive concept, the embodiments of the present invention further provide a seafloor seismograph, which includes any clock synchronization circuit provided in the above embodiments, and the explanation of the same or corresponding structures and terms as those of the above embodiments is not repeated herein.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (3)
1. A clock synchronization method for a clock synchronization circuit is characterized in that,
the clock synchronization circuit includes:
the system comprises a main clock circuit, at least one seismic data acquisition circuit, a microprocessor control circuit and at least two frequency dividing circuits;
the at least two frequency dividing circuits comprise a first frequency dividing circuit and a second frequency dividing circuit;
the master clock circuit is used for generating a master clock signal;
the first frequency dividing circuit is connected with the main clock circuit and is used for carrying out frequency division processing on the main clock signal to obtain a seismic data acquisition clock signal;
the seismic data acquisition circuit is connected with the first frequency division circuit and is used for acquiring the seismic data acquisition clock signal;
the second frequency division circuit is connected with the main clock circuit and is used for carrying out frequency division processing on the main clock signal to obtain a real-time clock signal;
the microprocessor control circuit is connected with the second frequency division circuit and is used for acquiring the real-time clock signal;
the second frequency division circuit is directly connected with the main clock circuit, or the second frequency division circuit is connected with the main clock circuit through the first frequency division circuit;
the at least two frequency dividing circuits further comprise a third frequency dividing circuit;
the third frequency dividing circuit is connected with the main clock circuit and is used for carrying out frequency division processing on the main clock signal to obtain a second pulse signal;
the microprocessor control circuit is connected with the third frequency dividing circuit and is used for acquiring the second pulse signal;
the clock synchronization method comprises the following steps:
the seismic data acquisition circuit carries out frequency division on the main clock signal through a first frequency division circuit to acquire a seismic data acquisition clock signal;
the microprocessor control circuit divides the frequency of the main clock signal through the second frequency division circuit to obtain a real-time clock signal;
the microprocessor control circuit divides the frequency of the main clock signal through a third frequency division circuit to obtain a second pulse signal;
the clock synchronization circuit also comprises a GPS module, and the GPS module is connected with the microprocessor control circuit;
the clock synchronization method further comprises the following steps:
the microprocessor control circuit performs a first time synchronization operation on the real-time clock signal according to the world time signal provided by the GPS module, wherein the first time synchronization operation is accurate to a second level;
and the microprocessor control circuit performs a second time synchronization operation on the real-time clock signal according to the standard second pulse signal provided by the GPS module, wherein the second time synchronization operation is accurate to within 1 millisecond.
2. The method of claim 1, wherein the microprocessor control circuit performs a second time synchronization operation on the real-time clock signal according to a standard second pulse signal provided by the GPS module, the second time synchronization operation being accurate to within 1 millisecond, comprising:
the microprocessor control circuit acquires a first real-time clock signal according to the arrival time of a first falling edge of the standard second pulse signal, and the first real-time clock signal is accurate to a microsecond level;
the microprocessor control circuit acquires a second real-time clock signal according to the arrival time of a second falling edge of the standard second pulse signal, and the second real-time clock signal is accurate to a microsecond level; the first falling edge and the second falling edge are adjacent two standard second pulse signal falling edges in the standard second pulse signals;
judging whether the standard pulse-second signal is a continuous pulse signal according to the time difference value of the second real-time clock signal and the first real-time clock signal, and calculating a pulse error between the pulse-second signal and the standard pulse-second signal when the standard pulse-second signal is the continuous pulse signal;
the pulse error is added to the real time clock signal.
3. The clock synchronization method of claim 1, wherein the microprocessor control circuit performs a first time synchronization operation on the real-time clock signal according to a world time signal provided by the GPS module, the first time synchronization operation being accurate to a second level before:
the microprocessor control circuit acquires a standard second pulse signal and a world time signal provided by the GPS module for a plurality of times;
and determining that the GPS module is stable according to the fact that the standard second pulse signal and the world time signal which are acquired for many times are correct signals.
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| CN201910194086.9A CN109738954B (en) | 2019-03-14 | 2019-03-14 | Clock synchronization circuit, clock synchronization method and submarine seismograph |
| PCT/CN2019/124193 WO2020181852A1 (en) | 2019-03-14 | 2019-12-10 | Clock synchronization circuit, clock synchronization method and seabed seismograph |
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| CN112711075B (en) * | 2019-10-25 | 2024-03-26 | 中国石油天然气集团有限公司 | Clock calibration system of marine seismic node |
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| WO2020181852A1 (en) | 2020-09-17 |
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