WO2020179110A1 - Module semiconducteur et dispositif à semiconducteur - Google Patents

Module semiconducteur et dispositif à semiconducteur Download PDF

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Publication number
WO2020179110A1
WO2020179110A1 PCT/JP2019/035864 JP2019035864W WO2020179110A1 WO 2020179110 A1 WO2020179110 A1 WO 2020179110A1 JP 2019035864 W JP2019035864 W JP 2019035864W WO 2020179110 A1 WO2020179110 A1 WO 2020179110A1
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WO
WIPO (PCT)
Prior art keywords
connection terminal
circuit element
main board
connection
connection terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2019/035864
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English (en)
Japanese (ja)
Inventor
成瀬峰信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aisin AW Co Ltd
Original Assignee
Aisin AW Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aisin AW Co Ltd filed Critical Aisin AW Co Ltd
Priority to US17/311,469 priority Critical patent/US12027492B2/en
Priority to CN201980093575.3A priority patent/CN113557604A/zh
Priority to KR1020217025614A priority patent/KR20210116533A/ko
Priority to EP19917977.1A priority patent/EP3937234A4/fr
Publication of WO2020179110A1 publication Critical patent/WO2020179110A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H10W70/611—
    • H10W70/635—
    • H10W70/65—
    • H10W90/00—
    • H10W90/401—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10159—Memory
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10545—Related components mounted on both sides of the PCB
    • H10W72/248—
    • H10W72/267—
    • H10W90/724—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a semiconductor module including at least one semiconductor element, and a semiconductor device including the semiconductor module.
  • a plurality of chips (1A, 2B, 3B) such as a processor are mounted on one side of the package substrate (1), and a solder bump constituting an external connection terminal is formed on the other side.
  • a semiconductor module multi-chip module (MCM) in which (11) is arranged is disclosed (reference numerals in parentheses in the background art are those of the literature to be referred to).
  • the external connection terminals are often arranged collectively for the same function (or a function having a close relationship) in consideration of the wiring distance to the connection destination and the like.
  • the address pins (A) and the data pins (D) connected to the memory are arranged in a specific area in a concentrated manner (see, for example, FIGS. 3 and 40 of International Publication). ).
  • This multi-chip module has a rectangular ring-shaped four round external connection terminals, and the address pins (A) and the data pins (D) are the outermost round first round to the innermost round fourth round. It is arranged over. Therefore, it is difficult to draw out the wiring from all the terminals on the board surface (mounting surface) on which the package substrate (1) is mounted (the external connection terminals are connected). That is, it is necessary to wire a part of a plurality of external connection terminals having the same function through a through hole using a surface opposite to the mounting surface or an inner wiring layer.
  • microprocessors and the like, and the communication speed between microprocessors and peripheral devices have increased in recent years, and the frequency of signals connected to the external connection terminals of multichip modules has also increased.
  • Such high frequency signals are prone to reflection as they pass through the through holes and may reduce transmission reliability due to waveform distortion due to reflection.
  • the wiring may become long and the signal delay may increase due to passing through the through hole.
  • connection terminals of the semiconductor module According to the above background, it is desired to appropriately arrange the connection terminals of the semiconductor module according to the connection destination of the semiconductor module.
  • the first circuit element is mounted on the first surface
  • the second circuit element is mounted on the second surface opposite to the first surface.
  • a semiconductor module mounted on one surface and provided with at least one semiconductor element, the plurality of connections being arranged in a plurality of rectangular loops on the side of the facing surface facing the main board and connected to the main board.
  • a first connection terminal group which is a plurality of first connection terminals connected to the first circuit element via the main substrate
  • the second connection terminal includes a plurality of connection terminals.
  • the first connection terminal group includes a second connection terminal group which is a plurality of second connection terminals connected to the circuit element, and the first connection terminal group is arranged on the outer peripheral side of the second connection terminal group.
  • the semiconductor device in view of the above is, as one aspect, a main board, a semiconductor module that includes at least one semiconductor element and is mounted on the first surface of the main board, and a plurality of semiconductor modules that are mounted on the main board.
  • a semiconductor device comprising the above circuit element, wherein the circuit element is mounted on a first circuit element mounted on the first surface and a second surface opposite to the first surface.
  • a plurality of connection terminals connected to the main board, the semiconductor module including a circuit element, the semiconductor module being arranged in a plurality of rectangular loops on the side of the facing surface facing the main board.
  • the first circuit element and the first connection terminal on the first surface than the second connection terminal. That is, since the first circuit element and the semiconductor module are mounted on the first surface, the first circuit element and the first connection terminal are connected on the first surface without bypassing to the second surface through the through hole. can do. Since the second circuit element is mounted on the second surface opposite to the first surface on which the semiconductor module is mounted, it is possible to extend the wiring from the second connection terminal on the first surface. Good. In any case, the second connection terminal is connected to the connection terminal via a through hole.
  • the circuit element and the semiconductor module are efficiently connected. can do.
  • the connection terminals of the semiconductor module can be appropriately arranged according to the connection destination of the semiconductor module.
  • Schematic exploded perspective view of a semiconductor device Parts layout of semiconductor module Schematic block diagram showing an example of a system LSI A perspective plan view as seen in the V direction showing an example of the terminal arrangement of the semiconductor module.
  • Enlarged perspective plan view in V direction showing an example of terminal arrangement of a semiconductor module
  • Explanatory diagram showing the principle of differential transmission The figure which shows an example of the wiring of a pair of signals transmitted differentially
  • Sectional drawing which shows an example of a semiconductor device Plan view seen from the V direction showing an example of a land and a wiring pattern on the first surface of the main board
  • Perspective view in V direction showing an example of the wiring pattern on the second surface of the main board
  • Perspective view in V direction showing another example of the wiring pattern on the second surface of the main board.
  • This semiconductor device can be mounted in a vehicle, for example, and can be used as an ECU (Electronic Control Unit) for controlling in-vehicle information equipment.
  • ECU Electronic Control Unit
  • the application of the semiconductor device is not limited to this.
  • the semiconductor device 10 includes a main board 5 and at least one system LSI 2 (semiconductor element, processor), and the first surface (main board first surface) of the main board 5 is provided.
  • the semiconductor module 1 mounted on the surface 5a) and a plurality of circuit elements 50 mounted on the main board 5 are configured.
  • the circuit element 50 is a first circuit element 7 mounted on the first surface 5a of the main board and a second circuit element 6 mounted on the second surface 5b of the main board opposite to the first surface 5a of the main board.
  • the semiconductor module 1 includes a system LSI 2, a memory 3 that cooperates with the system LSI 2, and a module board 4 on which the system LSI 2 and the memory 3 are mounted.
  • the module board 4 has a SoC (System on a Chip) as a system LSI 2 and two SDRAMs (Synchronous Dynamic Random Access Memory) as a memory 3.
  • SoC System on a Chip
  • SDRAMs Synchronous Dynamic Random Access Memory
  • the SDRAM is preferably, for example, DDR3 (Double Data Rate 3) SDRAM, DDR4 (Double Data Rate 4) SDRAM, or the like.
  • SoC is illustrated as the system LSI 2, but the system LSI 2 may be a SiP (System in a Package).
  • the SoC also includes an ASIC (Application Specific Integrated Circuit) of a semi-custom LSI, an ASSP (Application Specific Standard Processor) of a general-purpose LSI, and the like.
  • the ASIC is not limited to a gate array and a cell-based IC (standard cell), but also includes a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array) and a PLA (Programmable Logic Array).
  • SDRAM is illustrated as the memory 3 here, it does not prevent that it is a memory having another structure such as a flash memory or an SRAM (Static RAM).
  • the schematic block diagram of FIG. 3 shows an example of the system LSI 2.
  • the system LSI 2 includes a CPU core (CPU CORE) 22, a GPU core (GPU CORE) 23, an audio DSP (Audio DSP), a memory interface (SDRAM I / F) 21, and a sound routing unit (SRU).
  • CPU CORE CPU core
  • GPU CORE GPU core
  • audio DSP Audio DSP
  • SDRAM I / F memory interface
  • SRU sound routing unit
  • display interface Display I/F
  • video capture VideoCapture
  • USB Universal Serial Bus
  • USB Universal Serial Bus
  • image recognition engine ImageRecognitionEngine
  • CAN Control Area Network
  • It has functional blocks such as 32, a serial ATA (Serial ATA) 31, and a video accelerator (Video Accelerator) 26.
  • the CPU core 22 is an arithmetic unit including a CPU (Central Processing Unit), which is the core of the system LSI 2.
  • the GPU core 23 is an arithmetic unit that mainly includes a GPU (Graphic Processing Unit), which is the core of image-related arithmetic processing.
  • the memory interface 21 is a functional unit that serves as an interface when the system LSI 2 writes data in the SDRAM as the memory 3, reads data from the SDRAM, and refreshes data stored in the SDRAM.
  • the audio DSP 24 is a DSP (Digital Signal Processor) that performs a process of decoding audio data configured in various compression formats and storage formats.
  • the sound routing unit 30 realizes acoustic effects such as surround playback by the speaker 102 via the audio codec device (Audio Codec) 101 or the like, or transmits audio information such as audio input to the microphone 103 to the audio codec device 101. It is an arithmetic unit for receiving via.
  • the video capture 28 is, for example, an arithmetic unit that acquires an image captured by the in-vehicle camera 104.
  • the image recognition engine 25 is an arithmetic unit including an ISP (Image Signal Processor) for performing image recognition based on the image captured by the vehicle-mounted camera 104 acquired by the video capture 28.
  • the video accelerator 26 is an arithmetic unit including an ISP for performing a process of decoding moving image data configured in various compression formats and storage formats.
  • the display interface 27 is an arithmetic unit that outputs an image captured by the vehicle-mounted camera 104 acquired by the video capture 28 or an image decoded by the video accelerator 26, depending on the display mode of the display 107 in the vehicle interior, for example.
  • Various information (characters, symbols, etc.) can be superimposed on the image captured by the vehicle-mounted camera 104 based on the recognition result of the image recognition engine 25, or the image can be partially emphasized.
  • the USB host 29 is an arithmetic unit that serves as an interface for connecting various USB-compatible devices 109 carried by the user, such as portable audio devices, smartphones, and digital cameras.
  • the serial ATA 31 is an arithmetic unit that interfaces with a hard disk drive (HDD) 105 and a DVD disk drive (DVD) 106.
  • the CAN 32 is an arithmetic unit that serves as an interface for communication in the vehicle via a CAN transceiver 108 in the vehicle.
  • the CPU core 22, the GPU core 23, the DSP, the ISP, etc. described above cooperate with the memory 3 in the respective arithmetic processing.
  • the semiconductor module 1 is configured as a multi-chip module including a system LSI 2, a memory 3 that cooperates with the system LSI, and a module substrate 4 on which these are mounted.
  • a system LSI 2 and a memory 3 are mounted on a module substrate first surface 4a, which is a substrate surface on one side of the module substrate 4 of the semiconductor module 1.
  • the module substrate second surface 4b (opposing surface facing the main substrate 5), which is the substrate surface on the other side of the module substrate 4, is connected to the main substrate 5.
  • connection terminals 8 (module terminals) to be formed are regularly arranged. Although details will be described later, the connection terminals 8 are arranged in a rectangular ring having a plurality of circumferences.
  • the connection terminal 8 includes a signal terminal for transmitting a signal and a power supply terminal for transmitting electric power.
  • the "signal terminal” includes an "input terminal”, an "output terminal”, and a "bidirectional terminal (input / output terminal)".
  • the system LSI 2 is configured with a plurality of functional blocks as described above, and the semiconductor module 1 as a multi-chip module also has a plurality of functional blocks.
  • each functional block cooperates with a specific circuit or device. Therefore, each functional block is connected to a specific circuit or device, or an interface circuit (receiver, driver) or connector of the device via the connection terminal 8.
  • the circuit element 50 shown in FIG. 1 corresponds to these specific circuits, devices, interface circuits, connectors, and the like.
  • an integrated circuit is illustrated as the first circuit element 7 and the second circuit element 6 as the circuit element 50.
  • the circuit element 50 is not limited to a single integrated circuit but a plurality of circuit components. It may be a circuit configured by.
  • connection terminals 8 arranged in the semiconductor module 1 are aggregated for each same function (function having a close relationship) in consideration of the position of the circuit element 50 to be connected, the wiring distance from the circuit element 50, and the like. It is arranged.
  • FIG. 4 is a perspective plan view showing an example of the terminal arrangement of the semiconductor module 1 in a plan view (view in the V direction) viewed in a direction V (see FIG. 1) orthogonal to the substrate surface of the main substrate 5.
  • FIG. 5 is an enlarged perspective plan view in a V direction showing an example of the terminal arrangement of the semiconductor module 1. As shown in FIG.
  • the plurality of connection terminals 8 includes a first connection terminal group T1 which is a plurality of first connection terminals 81 connected to the first circuit element 7 via the main board 5 and the main board 5.
  • a second connection terminal group T2 which is a plurality of second connection terminals 82 connected to the second circuit element 6 via the second connection terminal group T2.
  • the first connection terminal group T1 is arranged on the outer peripheral side of the second connection terminal group T2.
  • it is sufficient that a part of the first connection terminal group T1 is arranged on the outer peripheral side with respect to all of the second connection terminal group T2. For example, as shown in FIG.
  • a part of the first connection terminal group T1 and a part of the second connection terminal group T2 are both terminals on the third circumference from the outer peripheral side (a third connection terminal described later with reference to FIG. 5). It may be in a form including the annular connection terminal 8c).
  • each connecting terminal 8 arranged in a rectangular ring belongs to three groups.
  • the connection terminals 8 arranged on the outermost three circumferences are the outer peripheral side annular connection terminals 9a.
  • the first annular connection terminal 8a, the first annular connection terminal 8a, The two ring-shaped connection terminals 8b and the third ring-shaped connection terminals 8c are called.
  • the first annular connecting terminal 8a is the "outermost peripheral connecting terminal" arranged at the outermost periphery among the plurality of connecting terminals 8 arranged in a plurality of rectangular loops.
  • connection terminals 8 arranged on the inner circumference side of the outer circumference side annular connection terminal 9a with a gap of one connection terminal 8 interposed therebetween are inner circumference side annular connection terminals 9b.
  • the fourth annular connection terminal 8d When distinguishing the connection terminals 8 of each circumference of the inner circumference side annular connection terminal 9b arranged over two circumferences, the fourth annular connection terminal 8d, from the outer circumference side toward the inner circumference side, every fourth circumference. It is referred to as a fifth annular connecting terminal 8e.
  • connection terminals 8 arranged in a grid pattern at four locations are arranged in a grid pattern so as to be rotationally symmetrical four times on the inner side of the inner peripheral side annular connection terminal 9b with a space for one connection terminal 8 interposed therebetween.
  • Connection terminal 9c The 4-fold rotational symmetry (4-fold symmetry, 4-phase symmetry, 90-degree symmetry) refers to a shape that matches when rotated by 90 degrees with respect to the symmetry point P2.
  • the symmetry point P2 corresponds to the center of gravity of the outer shape of the semiconductor module 1 (module substrate 4) when viewed in the V direction.
  • connection terminal 94 When distinguishing the respective connection terminals 8 of the four inner peripheral side grid-shaped connection terminals 9c, the first grid-shaped connection terminal 91, the second grid-shaped connection terminal 92, the third grid-shaped connection terminal 93, and the fourth grid-shaped connection terminal 93, respectively. It is referred to as a grid-shaped connection terminal 94.
  • the first connection terminal group T1 is arranged on the outer peripheral side of the second connection terminal group T2.
  • the first connection terminal 81 included in the first connection terminal group T1 is the connection terminal 8 that transmits a signal having a higher frequency than the second connection terminal 82 included in the second connection terminal group T2.
  • the first connection terminal 81 is a signal connection terminal 8 that transmits information by a pair of differential signals (information is transmitted by differential transmission).
  • the in-vehicle camera 104 capable of outputting an image signal of 30 frames/sec or more at a high resolution of 4 million pixels or more and the video capture 28 may be connected by a differential signal.
  • the display interface 27 and the display 107 which output a video signal with a high resolution of full high-definition (1920 pixels ⁇ 1080 pixels) or higher, often transmit information by a differential signal, HDMI (registered trademark) (High-Definition Multimedia). Interface) Connected by standard.
  • HDMI registered trademark
  • High-Definition Multimedia High-Definition Multimedia. Interface
  • information is transmitted by a differential signal to both the USB host 29 and various USB compatible devices 109.
  • the connection terminal 8 used for these connections is the connection terminal 8 that transmits a high-frequency signal, and the connection terminal 8 that transmits a signal by a pair of differential signals.
  • the transmission speed of signals between the sound routing unit 30 and the audio codec device 101 and the transmission speed of signals between the CAN 32 and the CAN transceiver 108 are slower and lower than the above-mentioned image signals and video signals. Frequency.
  • these signals do not transmit one piece of information by a pair of differential signals, but in many cases, they are transmitted by a transmission method called single end using one signal line for one piece of information. To be done.
  • FIG. 6 shows the principle of differential transmission
  • FIGS. 7 and 8 show an example of wiring of a pair of differentially transmitted signals.
  • the driver DR on the signal sending side and the receiver RE on the signal receiving side are connected by a pair of differential signals of a positive signal Sp and a negative signal Sn.
  • the logic of the positive signal Sp and the negative signal Sn are inverted.
  • the receiver RE is configured to include, for example, a differential amplifier, subtracts the negative signal Sn from the positive signal Sp and outputs the differential output Sd.
  • CMOS Complementary Metal Oxide Semiconductor
  • a through current flows when the logic state changes, so that it is consumed when the frequency is high (when the logic change is large).
  • the current increases.
  • a current flows from the upper side of the CMOS element that outputs the positive signal Sp to the lower side of the CMOS element that outputs the negative signal Sn through the terminating resistor TM, and the other logic state.
  • a current flows from the upper side of the CMOS element that outputs the negative signal Sn to the lower side of the CMOS element that outputs the positive signal Sp via the terminating resistor TM. Therefore, in the differential transmission, a shoot-through current does not flow when the logic state changes like in single-ended signal transmission. Therefore, even if the frequency of the signal to be transmitted becomes high, the increase in current consumption is suppressed.
  • differential transmission is a transmission method with low power consumption and high noise resistance, and is suitable for high-speed signal transmission with high frequency and large current consumption.
  • the wiring is formed so that the negative signal wiring Wn reaching the receiver-side second land Lren via the second resistance land Ltm2 of the terminating resistor TM has substantially the same shape or symmetry.
  • the distance between the driver-side first land Ldrp and the receiver-side first land Lrep and the distance between the driver-side second land Ldrn and the receiver-side second land Lren are almost the same, but the circuit element 50 These distances may vary depending on the arrangement. In such a case, as shown in FIG. 8, the negative signal wiring Wn is bypassed and the wiring length is adjusted to be the same as the positive signal wiring Wp (equal length wiring).
  • wiring should be performed in a shape (path) that greatly disrupts the symmetry between the positive signal wiring Wp and the negative signal wiring Wn, rather than fine adjustment as in the case of equal-length wiring. It is also not preferable to bend the wiring or to wire through the through hole. In particular, bending the wiring at an angle equal to or less than a right angle or wiring the wiring through a through hole causes reflection of signals at those locations and disturbs the signal waveform. Therefore, it is preferable that the differential transmission signal is linearly transmitted on one substrate surface without passing through the through hole.
  • the eye pattern (EyePattern) (EyeDiagram) may be disturbed and deterioration of communication quality (transmission quality) may be observed.
  • the size (area) of the eye pattern (eye diagram) is smaller than in constant-speed signal transmission. Therefore, even if the signal is delayed in the same way, in high-speed signal transmission, the ratio of deviation to the size (area) of the eye pattern (eye diagram) becomes large, so that the eye pattern (eye diagram) ) Is easily disturbed.
  • FIG. 9 shows a schematic cross-sectional view of the semiconductor device 10.
  • the first annular connecting terminal 8a is connected to the first annular land L8a
  • the second annular connecting terminal 8b is connected to the second annular land L8b
  • the third annular connecting terminal 8c is connected to the third annular land L8c
  • the fourth The annular connection terminal 8d is connected to the fourth annular land L8d
  • the fifth annular connection terminal 8e is connected to the fifth annular land L8e.
  • the first circuit element 7 mounted on the first surface 5a of the main board together with the semiconductor module 1 is a circuit element 50 that transmits a signal to and from the semiconductor module 1 by differential transmission.
  • the first circuit element terminal 7T of the first circuit element 7 is an input terminal or an output terminal of a differential signal, and is connected to the first circuit element land L7.
  • the second circuit element 6 mounted on the second surface 5b of the main board is the circuit element 50 that transmits a signal by single end rather than differential transmission.
  • the second circuit element terminal 6T of the second circuit element 6 is an input terminal or an output terminal of a single-ended signal, and is connected to the second circuit element land L6.
  • the first circuit element land L7 to which the first circuit element terminal 7T of the differential signal is connected is connected to the first annular land L8a via the first wiring W1 on the first surface 5a of the main board.
  • the second circuit element land L6 to which the second circuit element terminal 6T of the single end signal is connected is connected to the fourth annular land L8d via the second wiring W2 and the through hole TH. That is, the first circuit element terminal 7T and the first annular connecting terminal 8a are connected on the same substrate surface (main substrate first surface 5a) without the through hole TH.
  • the second circuit element terminal 6T and the fourth ring-shaped connection terminal 8d are connected to each other through different through-holes TH through different board surfaces (main board first surface 5a and main board second surface 5b). ..
  • connection terminals 8 of the semiconductor module 1 are arranged on the module substrate second surface 4b, which is an opposing surface that faces the main substrate first surface 5a, and all the connection terminals 8 are connected to the main substrate first surface 5a. .. Therefore, in order to connect the first circuit element 7 and the semiconductor module 1 on the same substrate surface (here, the first surface 5a of the main substrate), the first connection terminal 81 to be connected is a rectangular annular connection terminal. It is preferable to be arranged on the outer side of eight. As shown in FIGS. 4 and 5, the first annular connecting terminal 8 a, which is the outermost peripheral connecting terminal, is assigned to the first connecting terminal 81. In other words, the first connection terminal group T1 that is the plurality of first connection terminals 81 includes the first annular connection terminal 8a that is the outermost peripheral connection terminal.
  • the second connection terminal 82 is a terminal that does not have a problem even if it is connected through the through hole TH, when the first annular connection terminal 8a is assigned to the second connection terminal 82, the frequency of the differential signal or the like is correspondingly increased. It may not be possible to assign a high signal to the first annular connection terminal 8a. Therefore, it is preferable that the first annular connection terminal 8a is not assigned to the second connection terminal 82. As shown in FIGS. 4 and 5, the second connection terminal group T2 that is the plurality of second connection terminals 82 does not include the first annular connection terminal 8a that is the outermost peripheral connection terminal.
  • 10 and 12 are plan views viewed from the V direction showing an example of a pattern of the land of the connection terminal 8 and the signal wiring W formed on the first surface 5a of the main substrate.
  • 11 and 13 are perspective plan views in the V direction showing an example of the pattern of the signal wiring W on the second surface 5b of the main substrate.
  • the land of the connection terminal 8 formed on the first surface 5a of the main board is indicated by a broken line so as to be easily compared with the first surface 5a of the main board.
  • 10 and 11 exemplify a configuration in which a maximum of two signal wirings can be passed between the lands of the adjacent connection terminals 8, and FIGS. 12 and 13 show the configuration between the lands of the adjacent connection terminals 8.
  • connection terminals 8 are connected to the lands formed on the first surface 5a of the main board, the "signal wiring that can be passed between the lands of the adjacent connection terminals 8 on the first surface 5a of the main board" is It is synonymous with “signal wiring that can be passed between the adjacent connection terminals 8" on the first surface 5a of the main board.
  • the main board first from the first annular land L8a, the second annular land L8b, and the third annular land L8c.
  • the first wiring W1 that can be connected to the first circuit element 7 can be pulled out through only one surface 5a. Therefore, the first annular connection terminal 8 a, the second annular connection terminal 8 b, and the third annular connection terminal 8 c can be assigned to the first connection terminal 81.
  • the grid-like land L9c to which the fourth ring-shaped land L8d, the fifth ring-shaped land L8e, and the inner peripheral side grid-like connection terminal 9c are connected does not have the first wiring W1 from the second ring-shaped land L8b and the third ring-shaped land L8c.
  • the signal wiring W can be pulled out from the first surface 5a of the main board.
  • the first wiring W1 cannot always be drawn out from the fourth annular land L8d, the fifth annular land L8e, and the grid-shaped land L9c. From these lands, as shown in FIG. 11, the second wiring W2 can be provided on the second surface 5b of the main board via the through hole TH. Therefore, it is preferable to assign the fourth annular connecting terminal 8d, the fifth annular connecting terminal 8e, and the inner peripheral side grid-like connecting terminal 9c to the second connecting terminal 82.
  • connection terminal 8 that can be assigned to the first connection terminal 81 is passed between the adjacent connection terminals 8 on the first surface 5a of the main board.
  • the number of signal wires that can be passed between the adjacent connection terminals 8 on the first surface 5a of the main substrate is n (n is a natural number).
  • the first connection terminal 81 is preferably the connection terminal 8 arranged from the outermost periphery to the (n+1)th circumference among the plurality of connection terminals 8 arranged in a plurality of rectangular loops.
  • the first circuit element 7 is mounted on the main board first surface 5a
  • the second circuit element 6 is mounted on the main board second surface 5b on the main board first surface 5a.
  • the connection terminals 8 of the semiconductor module 1 can be appropriately arranged according to the connection destination of the semiconductor module 1 including at least one semiconductor element (system LSI 2).
  • the first circuit element (7) is mounted on the first surface (5a), and the second surface (5b) on the opposite side of the first surface (5a) is the second.
  • a second connection terminal group (T2) which is a plurality of second connection terminals (82) connected to the second circuit element (6) via the first connection terminal group (T1). It is arranged on the outer peripheral side of the second connection terminal group (T2).
  • the semiconductor device (10) is a semiconductor that includes a main board (5) and at least one semiconductor element (2) and is mounted on the first surface (5a) of the main board (5).
  • a semiconductor device (10) including a module (1) and a plurality of circuit elements (50) mounted on the main board (5), wherein the circuit element (50) is the first surface (50).
  • a second circuit element (6) mounted on a second surface (5b) opposite to the first surface (5a)
  • the semiconductor module comprising: (1) includes a plurality of connection terminals (8) arranged in a rectangular ring having a plurality of circumferences on the side of the facing surface (4b) facing the main board (5) and connected to the main board (5).
  • the plurality of connection terminals (8) are first connection terminal groups (T1) which are a plurality of first connection terminals (81) connected to the first circuit element (7) via the main board (5). ) And the second connection terminal group (T2), which is a plurality of second connection terminals (82) connected to the second circuit element (6) via the main board (5).
  • the connection terminal group (T1) is arranged on the outer peripheral side of the second connection terminal group (T2).
  • the first circuit element (7) and the first connection terminal (7) on the first surface (5a) it becomes easier to connect the first circuit element (7) and the first connection terminal (7) on the first surface (5a) than the second connection terminal (82). That is, since the first circuit element (7) and the semiconductor module (1) are mounted on the first surface (5a), the first circuit element (7) and the semiconductor module (1) do not bypass to the second surface (5b) via the through hole (TH). The first circuit element (7) and the first connection terminal (7) can be connected on the first surface (5a). Since the second circuit element (6) is mounted on the second surface (5b) opposite to the first surface (5a) on which the semiconductor module (1) is mounted, the second connection terminal (82). Therefore, it is not necessary to extend the wiring on the first surface (5a).
  • the second connection terminal (82) is connected to the connection terminal (8) through the through hole (TH). Therefore, the first connection terminal group (T1) which is the plurality of first connection terminals (81) is arranged outside the second connection terminal group (T2) which is the plurality of second connection terminals (82). , The circuit element (50) and the semiconductor module (1) can be efficiently connected. As described above, according to this configuration, the connection terminals of the semiconductor module (1) can be appropriately arranged according to the connection destination of the semiconductor module (1).
  • connection terminal (8) arranged at the outermost circumference is used as the outermost circumference connection terminal (8a) and the first connection terminal group (T1).
  • the connection terminal (8) arranged at the outermost circumference is used as the outermost circumference connection terminal (8a) and the first connection terminal group (T1).
  • the connection terminal (8) arranged at the outermost circumference is used as the outermost circumference connection terminal (8a) and the first connection terminal group (T1).
  • the connection terminal (8) arranged at the outermost circumference is used as the outermost circumference connection terminal (8a) and the first connection terminal group (T1).
  • the second connection terminal group (T2) preferably does not include the outermost peripheral connection terminal (8a).
  • the outermost peripheral connection terminal (8a) When the outermost peripheral connection terminal (8a) is assigned to the first connection terminal (81), the first circuit element (7) and the first connection terminal (7) can be easily connected on the first surface (5a). it can. Since the second circuit element (6) is mounted on the second surface (5b), the second connection terminal (82) is a terminal connected via a through hole (TH). Therefore, when the outermost peripheral connection terminal (8a) is assigned to the second connection terminal (82), there is a possibility that the first connection terminal (81) cannot be assigned to the outermost connection terminal (8a). Therefore, it is preferable that the outermost connection terminal (8a) is not assigned to the second connection terminal (82).
  • the first connection terminal (81) is the connection terminal (8) that transmits a signal having a frequency higher than that of the second connection terminal (82).
  • a signal with a high frequency is more likely to be affected by the wiring length and wiring shape than a signal with a low frequency, and there is a high possibility that the transmission quality will be degraded.
  • the through hole (TH) tends to cause signal reflection, and the wiring length tends to be long due to the wiring going back and forth between the first surface (5a) and the second surface (5b). Therefore, it is preferable that signals having a relatively high frequency are connected on the same substrate surface without passing through a through hole (TH). Therefore, it is preferable that the connection terminal (8) for transmitting a signal having a relatively high frequency is the first connection terminal (81).
  • the number of signal wirings (W) that can be passed between the adjacent connection terminals (8) on the first surface (5a) is n (n is a natural number), and the first connection terminal (81) Is preferably the connection terminal (8) arranged from the outermost circumference to the (n+1)th circumference among the plurality of connection terminals (8) arranged in a plurality of rectangular loops.
  • the signal wiring (W) on the first surface (5a) is extended from the connection terminal (8) arranged on the inner peripheral side to the outside of the semiconductor module (1). In order to pull it out, it is necessary to pass the signal wiring (W) between the connection terminals (8) arranged on the outer peripheral side of the connection terminal (8) on the inner peripheral side.
  • the distance between the signal wiring (W) and the signal wiring (W) and the distance between the signal wiring (W) and the land for mounting the connection terminal (8) are determined by the voltage of the signal and the main board (5). ) Material, etc.
  • the number of signal wirings (W) that can pass between the adjacent connection terminals (8) is also defined by the signal voltage, the material of the main board (5), and the like.
  • the first connection terminal (81) is assigned according to the number of signal wirings (W) that can be passed between the adjacent connection terminals (8).

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structure Of Printed Boards (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Manufacturing & Machinery (AREA)

Abstract

Selon une destination de connexion de ce module semi-conducteur de la présente invention, des bornes de connexion du module semi-conducteur sont disposées de manière appropriée. Un module semi-conducteur (1) comporte au moins un élément semi-conducteur (2) monté sur une première surface (5a) d'un substrat principal (5) qui comporte un premier élément de circuit (7) monté sur la première surface (5a) et comporte un second élément de circuit (6) monté sur une seconde surface (5b). Une pluralité de bornes de connexion (8) comprennent un premier groupe de bornes de connexion (T1) qui comprend une pluralité de premières bornes de connexion (81) connectées au premier élément de circuit (7) par l'intermédiaire du substrat principal (5), et un second groupe de bornes de connexion (T2) qui comprend une pluralité de secondes bornes de connexion (82) connectées au second élément de circuit (6) par l'intermédiaire du substrat principal (5). Le premier groupe de bornes de connexion (T1) est disposé plus près du côté périphérique externe que le second groupe de bornes de connexion (T2).
PCT/JP2019/035864 2019-03-05 2019-09-12 Module semiconducteur et dispositif à semiconducteur Ceased WO2020179110A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US17/311,469 US12027492B2 (en) 2019-03-05 2019-09-12 Semiconductor module and semiconductor device
CN201980093575.3A CN113557604A (zh) 2019-03-05 2019-09-12 半导体模块和半导体装置
KR1020217025614A KR20210116533A (ko) 2019-03-05 2019-09-12 반도체 모듈 및 반도체 장치
EP19917977.1A EP3937234A4 (fr) 2019-03-05 2019-09-12 Module semiconducteur et dispositif à semiconducteur

Applications Claiming Priority (2)

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JP2019039470A JP7238481B2 (ja) 2019-03-05 2019-03-05 半導体モジュール及び半導体装置
JP2019-039470 2019-03-05

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EP (1) EP3937234A4 (fr)
JP (1) JP7238481B2 (fr)
KR (1) KR20210116533A (fr)
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WO (1) WO2020179110A1 (fr)

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CN113557605B (zh) * 2019-03-08 2025-11-11 株式会社爱信 半导体模块和半导体装置

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WO2002103793A1 (fr) 2001-06-07 2002-12-27 Renesas Technology Corp. Dispositif a semi-conducteurs et procede de fabrication associe

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JP3294490B2 (ja) * 1995-11-29 2002-06-24 株式会社日立製作所 Ｂｇａ型半導体装置
US7979983B2 (en) * 2007-04-04 2011-07-19 Cisco Technology, Inc. Connection an integrated circuit on a surface layer of a printed circuit board
US7757196B2 (en) * 2007-04-04 2010-07-13 Cisco Technology, Inc. Optimizing application specific integrated circuit pinouts for high density interconnect printed circuit boards
US7797663B2 (en) * 2007-04-04 2010-09-14 Cisco Technology, Inc. Conductive dome probes for measuring system level multi-GHZ signals
JP2010093109A (ja) * 2008-10-09 2010-04-22 Renesas Technology Corp 半導体装置、半導体装置の製造方法および半導体モジュールの製造方法
JP6115147B2 (ja) * 2013-01-22 2017-04-19 富士通株式会社 配線基板及びその設計方法
JP2015041647A (ja) * 2013-08-20 2015-03-02 船井電機株式会社 半導体パッケージ
US10446531B2 (en) * 2014-09-26 2019-10-15 Renesas Electronics Corporation Electronic device and semiconductor device
TW201816967A (zh) * 2016-10-28 2018-05-01 京瓷股份有限公司 佈線基板以及使用了該佈線基板的電子裝置

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WO2002103793A1 (fr) 2001-06-07 2002-12-27 Renesas Technology Corp. Dispositif a semi-conducteurs et procede de fabrication associe

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EP3937234A1 (fr) 2022-01-12
JP7238481B2 (ja) 2023-03-14
US12027492B2 (en) 2024-07-02
US20220028828A1 (en) 2022-01-27
EP3937234A4 (fr) 2022-04-27
CN113557604A (zh) 2021-10-26
KR20210116533A (ko) 2021-09-27
JP2020145259A (ja) 2020-09-10

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