WO2020175157A1 - Silicon carbide semiconductor device and method for manufacturing same - Google Patents

Silicon carbide semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2020175157A1
WO2020175157A1 PCT/JP2020/005592 JP2020005592W WO2020175157A1 WO 2020175157 A1 WO2020175157 A1 WO 2020175157A1 JP 2020005592 W JP2020005592 W JP 2020005592W WO 2020175157 A1 WO2020175157 A1 WO 2020175157A1
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Prior art keywords
layer
type
source region
silicon carbide
impurity concentration
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PCT/JP2020/005592
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French (fr)
Japanese (ja)
Inventor
竹内　有一
鈴木　克己
侑佑 山下
武寛 加藤
Original Assignee
株式会社デンソー
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Priority claimed from JP2020008376A external-priority patent/JP7140148B2/en
Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Priority to CN202311330705.5A priority Critical patent/CN117276345A/en
Priority to CN202080016354.9A priority patent/CN113498544B/en
Publication of WO2020175157A1 publication Critical patent/WO2020175157A1/en
Priority to US17/410,044 priority patent/US12057498B2/en

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    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/781—Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
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Definitions

  • the present disclosure relates to a semiconductor device having a semiconductor element having a 1 ⁇ /103 structure composed of silicon carbide (hereinafter referred to as "3 (3)") ⁇ 3 ⁇ 3 and a manufacturing method thereof.
  • a 3 ⁇ 3 semiconductor device having a wrench gate structure.
  • a type base region and an n + type source region are formed in order on the gate type drift layer, and the + type source region penetrates the type base region from the surface of the type source region.
  • the trench gate is formed so as to reach the type drift layer.
  • a type base region is epitaxially grown on the n-type drift layer, and then a 1! type impurity is ion-implanted into the type base region to implant a part of the type base region.
  • a 1! type impurity is ion-implanted into the type base region to implant a part of the type base region.
  • Patent Document 1 International Publication No. 2 0 1 6/0 6 3 6 4 4 Panfret
  • the film thickness variation during epitaxial growth increases as the film thickness grown increases, but the variation in the range of ion implantation is not so large, so the film thickness of the mold base region after ion implantation is small.
  • the variation corresponds to the thickness of the epitaxially grown film. Therefore, when the + type source region is formed by ion implantation with respect to the type base region, the variation in the thickness of the + type source region is small and the variation in the thickness of the type base region is large. Therefore, there is the problem of causing variations in the threshold V I.
  • the side surface of the trench gate is inclined when the trench gate is formed due to the influence of damage at the time of ion implantation. Therefore, there is a problem that the channel mobility is lowered and the trench gate is widened at the trench entrance side, which makes it difficult to miniaturize the device.
  • the inventors of the present invention examined formation of not only the type base region but also the gate + type source region by epitaxial growth. By doing so, the variation in thickness is distributed to each of the mold base region and the gate + type source region, so that it is possible to reduce the variation in thickness of the mold base region.
  • the gate + type source region it is necessary to introduce a high concentration of the n-type dopant gas into the epitaxial growth apparatus, and even after the formation of the n + type source region, the n-type dopant region is formed in the epitaxial growth apparatus. Remains and the growth reactor is contaminated. As a result, when the mold layer or the gate-shaped layer is subsequently formed, dopant contamination occurs and the control of the impurity concentration becomes unstable.
  • the present disclosure provides a 3-0 semiconductor device having a structure capable of improving the short-circuit withstand capability, suppressing the variation of the threshold V 1 and suppressing the inclination of the side surface of the trench gate, and easily controlling the impurity concentration, and a manufacturing method thereof. With the goal.
  • a semiconductor device is a substrate of the first or second conductivity type composed of 300, and is formed on a substrate and has an impurity concentration lower than that of the substrate. And a drift layer made of the first conductivity type 3 ⁇ and formed on the drift layer. ⁇ 2020/175157 3 (: 170? 2020/005592
  • the trench gate structure is composed of a plurality of lines arranged in stripes with one direction as the longitudinal direction, the interlayer insulating film that covers the gate electrode and the gate insulating film and the contact hole is formed, and the source region through the contact hole.
  • the semiconductor device includes a source electrode in ohmic contact and a drain electrode formed on the back surface side of the substrate, and the source region is composed of an epitaxial growth layer formed on the base region side.
  • the source region is composed of the first source region having a relatively low concentration and the second source region having a higher concentration. Then, the first source region is formed by epitaxial growth, and the second source region is formed by ion implantation. For this reason, it is possible to improve the short-circuit resistance, suppress the variation of the threshold value VI and suppress the inclination of the side surface of the trench gate, and make it possible to provide a semiconductor device with a structure of 3 ⁇ 3 semiconductor having a structure capable of easily managing the impurity concentration. Become.
  • Another aspect of the present disclosure relates to a method for manufacturing a 300 semiconductor device according to the above-described one aspect of the present disclosure.
  • a substrate of the first or second conductivity type consisting of 300 is prepared, and a substrate of the first conductivity type having a lower impurity concentration than the substrate (from 3 Of the first conductive layer over the drift layer and the base region of the second-conductivity type 300 made on the drift layer.
  • the first source region is formed on the first source region of the third conductivity type having a high impurity concentration, and is disposed on the base region side, and the first source region is formed on the first source region.
  • a source region having a second source region with a higher impurity concentration Forming a source region having a second source region with a higher impurity concentration, and forming a plurality of gate trenches deeper than the base region from the surface of the source region in stripes with one direction as the longitudinal direction.
  • a gate insulating film is formed on the inner wall surface of the gate trench
  • a trench gate structure is formed by forming a gate electrode on the gate insulating film, and a source electrode electrically connected to the source region is formed. And forming a drain electrode on the back surface side of the substrate.
  • the base region By forming the base region, the base region is formed by epitaxial growth, and by forming the source region, the first source region is formed.
  • the second source region is formed by ion-implanting the first conductivity type impurity into the first source region.
  • the first source region is formed by epitaxial growth, and the second source region is formed by ion implantation.
  • the short-circuit withstand capability can be improved, variations in the threshold V 1 and the inclination of the side surface of the trench gate can be suppressed, and the 3D (3 semiconductor device) structure can be manufactured in which the impurity concentration can be easily controlled.
  • a method of manufacturing a 3 ⁇ 3 semiconductor device includes a method of epitaxially growing 3 ⁇ 3 layers of a type that is a layer to be measured, and a 3 I 0 layer after epitaxial growth.
  • the surface electrons of the 3.0 layer are stabilized, and after stabilizing the surface electrons, a charge is applied to charge the surface of the 3.0 layer and then the surface potential of the 3.0 layer is changed. Measuring the concentration of n-type impurities in the 30 layer by measuring.
  • the surface potential of the 300 layer is measured. This makes it possible to accurately measure the n-type impurity concentration of the 300 layer.
  • FIG. 3 is a cross-sectional view of a 3 ⁇ 3 semiconductor device according to the first embodiment.
  • Fig. 2 is a perspective cross-sectional view of the three semiconductor devices shown in Fig. 1.
  • Fig. 3 is a diagram showing the results of an electron current density simulation conducted when the concentration of the entire source region is high.
  • Fig. 4 is a diagram showing the result of examination by simulation of electron current densities when the n- type source region is composed of a first source region and a second source region.
  • FIG. 5 is a diagram showing the results of examining changes in drain current by simulation while changing the impurity concentration in the first source region.
  • Fig. 6 is a diagram showing the results of a simulation study on the relationship between the on-resistance and the type impurity concentration of the first source region.
  • FIG. 7 is a perspective sectional view showing a manufacturing process of the semiconductor device 3 ⁇ 3 shown in Fig. 1.
  • FIG. 78 is a perspective cross-sectional view showing the manufacturing process of the semiconductor device 3 ⁇ 3 following FIG. 7
  • FIG. 7(:] is a perspective sectional view showing the manufacturing process of the semiconductor device 3 ⁇ 3 following FIG.
  • Fig. 7 ( 3 3 ⁇ 3 is a perspective cross-sectional view showing the manufacturing process of the semiconductor device
  • Fig. 70 is a perspective cross-sectional view showing the manufacturing process of a semiconductor device 3 ⁇ 3
  • FIG. 7C is a perspective sectional view showing the manufacturing process of the semiconductor device 3 ⁇ 3 following FIG.
  • Fig. 70 is a perspective cross-sectional view showing the manufacturing process of a semiconductor device 3 ⁇ 3 following FIG.
  • FIG. 8 A cross-sectional view of a 3 ⁇ 3 semiconductor device according to a second embodiment.
  • FIG. 9 is a diagram showing the results of examining the voltage distribution during reverse conduction when the entire region of the ⁇ -type source region has a high impurity concentration.
  • FIG. 6 is a diagram showing a result of examining a voltage distribution during reverse conduction.
  • Fig. 11 shows the results of examining the voltage distribution during reverse conduction in the case where the non-doped layer was provided.
  • FIG. 12 is a diagram showing a measurement flow of the n- type impurity concentration described in the third embodiment.
  • FIG. 13 is a perspective view showing how to measure the n- type impurity concentration described in the third embodiment.
  • Fig. 14 is a diagram showing the relationship between the exposure time to the atmosphere after the epitaxial growth of the mold layer and the measurement result of the concentration of the gate type.
  • FIG. 15 is a diagram showing the relationship between the density evaluation values before and after the 1 to 1 treatments.
  • FIG. 16 is a diagram showing a measurement flow of n- type impurity concentration described as another example of the third embodiment.
  • FIG. 17 is a diagram showing a measurement flow of n- type impurity concentration described in the fourth embodiment.
  • the first embodiment will be described.
  • an inverted vertical 1 ⁇ /103 stacking trench gate structure shown in FIGS. 1 and 2 is formed as a semiconductor element.
  • the vertical type 1 ⁇ / 1 0 3 mats shown in these figures are formed in the cell region of the semiconductor device of 3 ⁇ 3 semiconductor devices, and the outer peripheral withstand voltage structure is formed so as to surround the cell region.
  • 3 ⁇ 3 semiconductor devices are constructed, but only the vertical type 1 ⁇ /103 is shown here.
  • the vertical 1 ⁇ /1 ⁇ 3 mending machine intersects the width direction of the vertical 1 ⁇ /1 ⁇ 3 mending machine in the X direction and the X direction.
  • the depth direction of the vertical direction is the thickness direction or the depth direction of the vertical 1 ⁇ /1 ⁇ 3 knife, that is, the direction normal to the flat surface. ⁇ 2020/175 157 7 ⁇ (: 170? 2020 /005592
  • a 3+ semiconductor device uses a ++ type substrate 1 made of 300 as a semiconductor substrate.
  • an n ⁇ type layer 2 of 3 ⁇ 3 is formed on the main surface of the n+ type substrate 1.
  • the surface of the door + type substrate 1 is a (0 001) 3 surface, for example, the n-type impurity concentration is 5.9 1 0 18 / ⁇ , and the thickness is 100 °.
  • an n-type impurity concentration is set to 7. 0 1 0 15 ⁇ 2 0 X 1 0 16 / Rei_rei_1 3, the thickness is the 8 ⁇ .
  • n-type layer 2 On top of the n-type layer 2, there are 3 parts.” The part 3 and the electric field blocking layer 4 are formed, and the n-type layer 2 is located away from the n+ type substrate 1. At “”, it is connected to Mitsube Department 3.
  • the JFE section 3 and the electric field blocking layer 4 compose a saturation current suppressing layer, and both extend in the X direction and are alternately arranged in the vertical direction.
  • at least a part of the Ming part 3 and the electric field blocking layer 4 are respectively formed into a plurality of strips, that is, stripes, and are alternately arranged. It is said to be a side-by-side layout.
  • Each part of the striped portion of the Mending part 3, that is, each strip-shaped part has a width of, for example, 0.25, and a pitch of forming intervals is, for example, 0.6 to 2.
  • the thickness of the n-type layer is, for example, 1.5, and the n-type impurity concentration is set higher than that of the n-type layer 2, for example, 5.0 1 0 16 to 2.0 X 10 18 / ⁇ there is a 1 3.
  • the electric field blocking layer 4 is composed of a type impurity layer. I mentioned above ⁇ 2020/175 157 8 ⁇ (: 170? 2020 /005592
  • the electric field blocking layer 4 has a striped shape, and each strip-shaped portion of the striped electric field blocking layer 4 has a width of, for example, 0.15 and a thickness of, for example, 1.4. There is. Further, the electric field blocking layer 4 has, for example, a type impurity concentration of 3.0 X 1017 to 1. In the case of the present embodiment, the electric field blocking layer 4 has a constant type impurity concentration in the depth direction. The surface of the electric field blocking layer 4 opposite to the n ⁇ -type layer 2 is flush with the surface of the Mending part 3.
  • a closed type current spreading layer 5 made of 300 is formed on the Mending part 3 and the electric field blocking layer 4, a closed type current spreading layer 5 made of 300 is formed.
  • the n-type current distribution layer 5 is a layer that allows the current flowing through the channel to diffuse in the X direction, as will be described later.
  • the n- type impurity concentration is higher than that of the mold layer 2.
  • the gate-type current spreading layer 5 is extended in the direction of the bird's eye, and has the n-type impurity concentration equal to or higher than that of the Mitsube part 3, for example, a thickness of 0.5. Has been done.
  • the drift layer is referred to as a mold layer 2 for convenience sake.
  • the part 3 and the gate-type current spreading layer 5 are described separately, but these are both parts that form the drift layer and are connected to each other.
  • n-type current spreading layer 5 On the n-type current spreading layer 5, a type base region 6 of 300 is formed. A mold source region 8 is formed on the mold base region 6. The n- type source region 8 is formed on a portion of the type base region 6 corresponding to the n- type current spreading layer 5.
  • the type base region 6 is thinner than the electric field blocking layer 4 and has a low concentration of type impurities.
  • the type impurity concentration is 3 X 1 0 1 7/0 3. It is said that the thickness is from 0.4 to 0.60!
  • the n-type source region 8 has a structure in which the O-type impurity concentration is different between the type base region 6 side and the opposite side, that is, the element surface side. Specifically, the n- type source region 8 includes a first source region 8 3 arranged on the side of the type base region 6 and a second source region 8 3 arranged on the device surface side. It is said that. ⁇ 2020/175 157 9 (: 170? 2020/005592
  • the first source region 8 3 has a lower n- type impurity concentration than the second source region 8 13 and is composed of an epitaxial growth layer. Borders area 6.
  • the first source region 8 3, for example, n-type non-pure concentration is between 2. 0 X 1 0 ⁇ 1. ⁇ X 1 ⁇ 1 ⁇ / hundred 1 3 or less, a thickness ⁇ .
  • It is set to 2 to 0. 05 01, preferably 0. 3 0! or more.
  • the second source region 8 13 is a region for making contact with a source electrode 15 to be described later, and is composed of an ion-implanted layer, and has a high concentration of 1 ⁇ !-type impurities. There is. Second source region 8 spoon, for example n-type impurity concentration is set to 1. 0 X 1 0 1 8 ⁇ 5. 0 X 1 0 1 9 / Rei_rei_1 3, is the thickness ⁇ . 1 ⁇ . 2 ing.
  • the mold current distribution The mold deep layer 9 is formed in a portion where the layer 5 is not formed.
  • the mold deep layer 9 is a strip-shaped portion in which the striped portion of the Mending part 3 and the longitudinal direction of the electric field blocking layer 4 are crossed. It is laid out in stripes by arranging multiple lines in the X direction. Through the mold deep layer 9, the mold base region 6 and the electric field blocking layer 4 are electrically connected.
  • the formation pitch of the type deep layer 9 is matched with the cell pitch which is the formation interval of the trench gate structure described later, and the type deep layer 9 is arranged between the adjacent trench gate structures.
  • a trench gate structure is formed on the type base region 6 at a position corresponding to the type deep layer 9, that is, at a position different from the n-type source region 8 with the n-type source region 8 interposed therebetween.
  • the mold connecting layer 10 is formed at a position on the opposite side.
  • the mold connection layer 10 is a layer for electrically connecting by connecting the mold base region 6 and a source electrode 15 described later.
  • the type coupling layer 10 has a structure in which the type impurity concentration is different between the type base region 6 side and the opposite side, that is, the element surface side.
  • the mold connecting layer 10 is a mold base. ⁇ 2020/175 157 10 ⁇ (: 170? 2020 /005592
  • the carrier concentration that is, the type impurity concentration of the portion functioning as a carrier, is 2.0X10. 17 to 1. are set to be 0 X 1 0 19 / ⁇ 3.
  • the second region 10 ⁇ is a region having a depth similar to that of the second source region 8 ⁇ , and is a region for making contact with a source electrode 15 described later, and has a high concentration of type impurities.
  • the second region 1 ⁇ spoon, for example the type impurity concentration 2. is a ⁇ 1 018 ⁇ 1. 0x 1 020/0 01 3, thickness ⁇ . 2 ⁇ . 3 ⁇ ! As being.
  • the carrier concentration that is, the type impurity concentration of the portion functioning as a carrier is 2.
  • 0 1 Rei_18 ⁇ are to 1. so that 0X 1 020 / ⁇ 01 3.
  • the type coupling layer 10 is formed by ion implantation of type impurities into the n-type source region 8.
  • the type impurity concentration of the first region 1 and the second region 1013 means the concentration of the type impurities that function as carriers. Some of the type impurities are canceled with the type impurities contained in the first source region 83 before the implantation and do not function as carriers. Therefore, when forming the type coupling layer 10 by ion implantation, taking into account the activation rate, for example, a dose amount that is 2 to 10 times the type impurity concentration of the first source region 8 3 and the second source region 813. By injecting the type impurities with, the above type impurity concentration can be obtained.
  • n- type source region 8 and the type base region 6 are penetrated and an n- type current component is ⁇ 2020/175 157 1 1 ⁇ (: 170? 2020/005592
  • the gate wrench is deeper than the total thickness of the base region 6 and the gate source region 8 by a depth of 0.4 to reach 0.4, for example, to reach the diffusion layer 5.
  • the above-mentioned type base region 6 and n-type source region 8 are arranged so as to be in contact with the side surface of the gate trench 11.
  • the gate trench 11 has a width direction in the X direction in FIG. 2 and a direction intersecting the longitudinal direction of the Mending part 3 and the electric field block layer 4, here, a strip shape with the longitudinal direction as the longitudinal direction and the direction as the depth direction. It is formed with the layout of. Although not shown in FIGS.
  • the gate trenches 11 are in the form of stripes in which a plurality of gate trenches 11 are arranged at equal intervals in the X direction, and a type base region 6 is provided between them. A type source area 8 is placed. Further, the mold deep layer 9 and the mold coupling layer 10 are arranged at the intermediate position of each gate trench 11.
  • the type base region 6 is located between the n- type source region 8 and the n- type current spreading layer 5 during the operation of the vertical type 1 ⁇ /1 ⁇ 3.
  • Form a channel region that connects The inner wall surface of the gate trench 11 including the channel region is covered with the gate insulating film 12.
  • a gate electrode 13 composed of doped ⁇ 7-3I, and the inside of the gate trench 11 is filled with these gate insulating film 12 and gate electrode 13.
  • the trench gate structure is constructed.
  • the side walls of the gate trench 11 are substantially parallel to each other, and are rounded and inclined at the entrance side of the opening so that the opening width is slightly wider than the bottom. Has become. More specifically, the part of the side wall of the gate trench 11 that is in contact with the first source region 8 3 and the type base region 6 and the n-type current spreading layer 5 is almost parallel to the direction, and the second source region 8 3 The part in contact with the swallow is rounded and inclined.
  • an interlayer insulating film is formed on the surface of the n-type source region 8 and the surface of the gate electrode 13.
  • a source electrode 15 and a gate wiring layer are formed via 14.
  • the source electrode 15 and the gate wiring layer are composed of a plurality of metals, for example, I/I. At least 3 types of metal (3, ⁇ 2020/175 157 12 (: 170? 2020/005592
  • the part in contact with the n-type source region 8 is composed of a metal capable of ohmic contact with n-type 3 ⁇ 3.
  • at least the part of the plurality of metals that is in contact with the mold 3, specifically the second region 10 is made of a metal that is capable of ohmic contact with the mold 3 ⁇ 3.
  • the source electrode 15 is formed on the interlayer insulating film 14 and is electrically insulated from the part of the source electrode 30, the source electrode 15 is formed on the interlayer insulating film 14 through the contact hole formed in the interlayer insulating film 14. 8 and the mold deep layer 9 are in electrical contact.
  • a drain electrode 16 electrically connected to the n + type substrate 1 is formed on the back surface side of the n + type substrate 1.
  • a vertical 1/3 of a channel-type inverted trench gate structure is constructed.
  • a cell area is constructed by arranging multiple cells of such vertical type 1/103.
  • a 3 10 semiconductor device is formed by forming an outer periphery withstand voltage structure by a guard ring or the like (not shown) so as to surround the cell region in which such a vertical type 1/103 is formed. ..
  • a semiconductor device having a vertical type 1// 1 0 3 sets of 3 ⁇ 3 semiconductor devices has a source voltage 3 of 0 and a drain voltage V of 1 to 1.5 V, for example. In this state, it is operated by applying a gate voltage V 9 of 20 V to the gate electrode 13.
  • the vertical type 1//103 has a channel region formed in the type base region 6 which is in contact with the gate trench 11 when the gate voltage V 9 is applied. As a result, conduction is established between the gate type source region 8 and the n type current spreading layer 5.
  • the vertical IV! ⁇ 3 ⁇ is from the n + -type substrate 1 to the n _ -type layer 2 through the drift layer composed of the ⁇ section 3 and the n- type current spreading layer 5 From the region through the 1! type source region 8, an operation is performed in which a current flows between the drain and the source.
  • the vertical type 1//1 03 ken in such a semiconductor device is applied to an inverter circuit or the like provided with an upper arm and a lower arm
  • the vertical type 1//1 003 The parasitic diode built into the circuit works as a freewheeling diode.
  • the gate-type layer forming the drift layer such as the n ⁇ -type layer 2, the electric field blocking layer 4, and the type base region 6 are also included. ⁇ 2020/175 157 13 ⁇ (: 170? 2020 /005592
  • a parasitic diode is formed by a 1 ⁇ 1 junction with the type layer including the type deep layer 9, and this acts as a freewheeling diode.
  • the inverter circuit and the like are used when supplying an alternating current to a load such as an AC motor while using a DC power supply.
  • a load such as an AC motor
  • a DC power supply for example, in an inverter circuit or the like, a plurality of bridge circuits in which an upper arm and a lower arm are connected in series are connected in parallel to a DC power supply, and the upper arm and lower arm of each bridge circuit are alternately turned on and off repeatedly to load An alternating current is supplied to it.
  • each bridge circuit such as an inverter circuit
  • a load is generated by turning on the vertical IV! Current is supplied to. After that, turn off the vertical type 1 ⁇ /1 03 of the upper arm and turn on the vertical type
  • the parasitic diode provided in the vertical IV! The reverse conduction is performed by flowing the current between the source and the drain. In this way, the AC drive of the load is performed by the inverter circuit or the like.
  • a voltage of 120 V or higher is applied to the drain as the drain-source voltage 3.
  • the entire area of the gate-type source region 8 is composed of a high-concentration n-type impurity layer, the saturation current value at the time of load short-circuit becomes large, and it becomes impossible to obtain the short-circuit withstand capability of the semiconductor device. .. This is presumably because the 1! type source region 8 has a high concentration, so that a depleted region hardly occurs and the current flows in the entire region of the type source region 8.
  • the n-type source region 8 has a relatively low concentration of the first source region 8 3 and the second source region 8 has a higher concentration than that. It is possible to reduce the saturation current value when the load is short-circuited, because it is composed of 13 and 13. This is because the first source region 8 3 has a low concentration, so Depletion so that it enters the wide area of 8 3 ⁇ 2020/175 157 14 ⁇ (: 170? 2020 /005592
  • the source voltage 3 is 0, the gate voltage 9 is 20 and the drain voltage is 75 0.
  • the concentration of the gate-shaped impurity in the entire gate-shaped source region 8 is 1.
  • the gate type source region 8 is composed of the first source region 8 3 and the second source region 8 13 while the type impurity concentration of the first source region 8 3 is 1.0 1 0. and 1 6 / Rei_rei_1 3, and the ⁇ impurity concentration of the second source region 8 1_Rei and 1. 0 X 1 0 1 9 / Rei_rei_1 3.
  • the type source region 8 is composed of the first source region 8 3 and the second source region 8 13 while the type impurity concentration of the second source region 8 10 is 1.0 X 1 Then, the type impurity concentration of the first source region 83 is changed.
  • the electron current density in the first source region 8 3 is You can see that it is getting smaller. This is because the first source area 8 3 ⁇ 2020/175 157 15 ⁇ (: 170? 2020/005592
  • depletion occurs so that it enters the wide area of the first source region 8 3 and current does not flow in the depleted portion.
  • the saturation current value at the time of load short-circuiting can be reduced by using the third and second source regions 813. Therefore, it can be understood that the structure of this embodiment can improve the short-circuit withstand capability of the semiconductor device (3 semiconductor devices).
  • the drain current during the load short circuit if to be 1 4 0 0 0 / ⁇ 2 or less, it is possible to obtain the desired short-circuit tolerance.
  • the drain current at the time of load short-circuiting is 1400 0.88/ ⁇ 2 or less when the n-type impurity concentration of the first source region 8 a is 1.0 X 10 It is the case when it becomes 1 7 / ⁇ 3 or less. Therefore, the n- type impurity concentration of the first source region 8a is set to 1.0 1 0 1 7 / ⁇ as in the 3 semiconductor device of this embodiment. By setting the following, it becomes possible to improve the short circuit withstand capability.
  • n-type impurity concentration of the first source region 83 is too low, the resistance value of the first source region 83 becomes too large and the on-resistance ⁇ n is increased.
  • the results shown in Fig. 6 were obtained. 3 ⁇ Considering the high-speed switching operation of semiconductor devices, the on resistance ⁇ ! The following is preferable. According to the results of FIG. 6, but n-type impurity concentration of the first source region 8 a is 2. 0 X 1 0 1 6 / Rei_rei_1 goes below 3 abruptly on resistance [3 ⁇ 4_ ⁇ n increases, ⁇ If the type impurity concentration is higher, the on-resistance R on is 1.
  • the 1 ⁇ -type impurity concentration of the first source region 8 3 2.
  • the concentration of the gate-type impurities in the first source region 8 3 is 2.0 X 10 16 to 1.0 X 10 17 / ⁇ 3 .
  • ON resistance [It is possible to suppress the deterioration of the gate.
  • the 3 ⁇ 3 semiconductor device of the present embodiment is provided with a "3" section and an electric field block layer 4.
  • the 3FE section 3 and the electric field blocking layer 4 function as a saturation current suppressing layer, and the saturation current suppressing effect is exerted, resulting in low on-resistance. It is possible to achieve a structure that can maintain a low saturation current while aiming. Specifically, the following operation is performed because the stripe portion and the electric field blocking layer 4 of the Mending portion 3 are alternately and repeatedly formed.
  • the drain voltage is a voltage applied during normal operation, such as 1 to 1.5 V
  • the depletion layer extending from the electric field blocking layer 4 side to the "mending part 3" is Only the width smaller than the width of the striped part of the claw part 3 extends. Therefore, even if the depletion layer extends into the Mitsube part 3, a current path is secured. Further, since the n-type impurity concentration of the Mending part 3 is higher than that of the n ⁇ -type layer 2, the current path can be configured to have a low resistance, so that a low on-resistance can be achieved.
  • the depletion layer extending from the electric field blocking layer 4 side to the "Mending part 3" was formed into a striped shape in the "Ming part 3". It extends longer than the width of the part. Then, before the mold current dispersion layer 5, the Mitsube 3 is immediately pinched off. At this time,
  • the relationship between the drain voltage V ⁇ 1 and the width of the depletion layer is determined based on the width of the striped portion of the Mending part 3 and the n-type impurity concentration. For this reason, the width of the striped portion of the Mouth portion 3 and the gate-shaped impurity should be checked so that the “Mouth portion 3 is pinched off when the drain voltage becomes slightly higher than the drain voltage during normal operation.” Set the concentration. As a result, it is possible to pinch off the Mitsube part 3 even with a low drain voltage. In this way, when the drain voltage becomes higher than the voltage during normal operation" ⁇ 0 2020/175 157 17 (: 17 2020 /005592
  • the electric field blocking layer 4 and the electric field blocking layer 4 function as a saturation current suppressing layer and exerts a saturation current suppressing effect, a low on-resistance and a low saturation current can be achieved at the same time. It will be possible.
  • the electric field blocking layer 4 By providing the electric field blocking layer 4 so as to sandwich the Mending part 3, the striped portion of the "Minging part 3" and the electric field blocking layer 4 are alternately and repeatedly formed. It is considered as a structure. Therefore, even if the drain voltage becomes high, the extension of the depletion layer extending from the bottom to the 1-!-type layer 2 is suppressed by the field block layer 4 and the extension to the trench gate structure is prevented. You can Therefore, the electric field suppressing effect of lowering the electric field applied to the gate insulating film 12 can be exerted, and the destruction of the gate insulating film 12 can be suppressed, so that an element with high withstand voltage and high reliability can be obtained. It will be possible.
  • an n + type substrate 1 is prepared as a semiconductor substrate. And, not shown By epitaxial growth using the equipment
  • n ⁇ -type layer 2 made of 300 is formed on the main surface of the + type substrate 1.
  • a so-called epi substrate in which the n ⁇ -type layer 2 is previously grown on the main surface of the door + type substrate 1 may be used. And it consists of 3 parts on the mold layer 2.”
  • the epitaxial growth is performed by introducing a gas that serves as an n-type dopant, for example, nitrogen gas, in addition to silane and propane that serve as raw material gases of 300 parts.
  • a gas that serves as an n-type dopant for example, nitrogen gas
  • silane and propane that serve as raw material gases of 300 parts.
  • the mask 17 After arranging the mask 17 on the surface of the part 3, the mask 17 is patterned to open the region where the electric field blocking layer 4 is to be formed. Then, the electric field blocking layer 4 is formed by ion-implanting the type impurities. Then mask 17 is removed.
  • the electric field blocking layer 4 is formed here by ion implantation, the electric field blocking layer 4 may be formed by a method other than ion implantation. For example, after the anisotropic etching of the "3" part is selectively formed to form a recess at a position corresponding to the electric field blocking layer 4, a type impurity layer is epitaxially grown on the recessed part, and then the "3 part of the 3" part is formed.
  • the electric field blocking layer 4 is formed by planarizing the type impurity layer in the upper portion. In this way, the electric field blocking layer 4 can also be formed by epitaxial growth. In the case of epitaxially growing the type 300, it is sufficient to introduce a type dopant gas, for example, trimethylaluminum (hereinafter referred to as Ding 1/18), in addition to the source gas of the type 300.
  • Ding 1/18 trimethylaluminum
  • the n-type current 3 is epitaxially grown on the Mending part 3 and the electric field blocking layer 4 to form the type current spreading layer 5.
  • a mask (not shown) having an opening in the region where the mold deep layer 9 is to be formed is arranged.
  • a mold deep layer 9 is formed by ion-implanting mold impurities from above the mask.
  • the example in which the mold deep layer 9 is also formed by ion implantation is shown, but it can be formed by a method other than ion implantation.
  • a type impurity layer is epitaxially grown and the type impurity layer is planarized to form the type deep layer 9. I will do it ⁇ 2020/175 157 19 ⁇ (: 170? 2020/005592
  • a first source region 8 3 of the type base region 6 and the type source region 8 is sequentially grown epitaxially on the n-type current spreading layer 5 and the type deep layer 9 by using a ⁇ V 0 device (not shown).
  • the growth furnace is heated to a predetermined temperature through a temperature raising process, and then, first, epitaxial growth is performed by introducing a gas serving as a type dopant together with a carrier gas and a raw material gas. To form the mold base region 6.
  • the ⁇ dopant by stopping the introduction of the type dopants, to form formed the first source region 8 3.
  • the thickness of the first source region 8 3 is added by the thickness of the second source region 8 13.
  • the process time is shortened by performing the epitaxial growth of the first source region 83 while maintaining the temperature after forming the mold base region 6 without performing the temperature lowering process.
  • the first source region 8 3 can be formed by the epitaxial growth layer, and the second source region 8 13 can be formed by the ion implantation layer.
  • the mold base region 6 and the mold source region 8 can be formed with the above impurity concentration and film thickness.
  • the film thickness and the impurity concentration of each part are determined as follows.
  • the channel length is set while the impurity concentration forming the inverted channel is set when the gate voltage V 9 is applied.
  • the film thickness is defined as follows. Therefore, for the type base region 6, for example,
  • the thickness is 0.4 to 0.60! ⁇ 2020/175 157 20 (: 170? 2020/005592
  • the saturation current value is reduced and the resistance is high even when a high drain voltage V ⁇ 1 is applied when the load is short-circuited.
  • the film thickness and the n-type impurity concentration are set so as to prevent this from occurring. Therefore, for the first source region 83, for example, the n-type impurity concentration is set to 2.0 X 1016 to 1.0 X 1 X 1a/x3 and the thickness is set to 0. That is all.
  • the second source region 8 13 is a film that does not completely disappear due to a chemical reaction with the source electrode 15 while having an impurity concentration that allows the source electrode 15 to be in ohmic contact. It is set to thick. The higher the n- type impurity concentration of the second source region 8 s, the easier it is to make a talented contact.
  • the type source layer 8 may be epitaxially grown and then the type impurities may be ion-implanted to form the type coupling layer 10. In that case, the type source layer 8 may be formed. If the n- type impurity concentration is too high, the type coupling layer 10 cannot have a desired concentration. Therefore, in the present embodiment is an n-type impurity concentration of the second source region 8 spoon as example 1. 0 X 1 ⁇ 1 8 to 5.0 1 0 1 4.5 / Rei_rei_1 3.
  • the source electrode 15 is made of a plurality of metals, and the portion which makes a mechanical contact with the second source region 8 is made of, for example, I. In that case, the portion of the second source region 8 that is in contact with 1 ⁇ 1 ⁇ will be 1 ⁇ ]. 8 swallows will disappear. And since the thickness of about 1 ⁇ 1 becomes silicidation due to the silicidation reaction, it is necessary to make sure that the entire second source region (8 wells) does not disappear due to silicidation reaction. 2 The thickness of the source region 8 is set to 0.11 or more.
  • first source region 8 3 and the second source region forming the n-type source region 8 are also included.
  • the first source region 83 and the second source region ⁇ 2020/175 157 21 ⁇ (: 170? 2020 /005592
  • the film thickness of the first source region 8 3 and the film thickness of the second source region 8 3 are set within the above ranges.
  • the type base region 6 and the first source region 83 are formed by epitaxial growth, it is possible to reduce variations in the film thickness of each part. Further, in the mold base region 6 used for forming the channel region, the variation in film thickness can be reduced, so that the channel length can be accurately created. As a result, it is possible to reduce the variation in the threshold V I of the vertical type 1/103.
  • n-type impurities are added back to the type base region 6 to form both the first source region 8 3 and the second source region 8 swath. It is also possible to do so. However, in this case, it is necessary to increase the thickness of the mold base region 6 during the epitaxial growth in consideration of the thickness of the first source region 8 3 and the second source region 8 3 formed by ion implantation. ..
  • the variation in film thickness during epitaxial growth increases as the thickness of the grown film increases, but the variation in the range of ion implantation is not so large, so the thickness/variation of the mold base region 6 after ion implantation is The variation corresponds to the thickness of the epitaxially grown film.
  • the first source region 8 3 and the second source region are formed by ion implantation. Even after forming 8 13, the film thickness variation of the mold base region 6 is ⁇ 0.21.
  • the film thickness variation of the mold base region 6 is different from that of the first source region 8 3 and the second source region 8
  • the variation does not include the film thickness, but corresponds to the thickness of only the mold base region 6.
  • the film thickness variation is ⁇ 0.06 to 0.090! Therefore, by forming each part by epitaxial growth, it is possible to suppress the variation in the film thickness of the mold base region 6, and to accurately build the channel length. ⁇ 2020/175 157 22 ⁇ (: 170? 2020/005592
  • the impurity concentration does not change rapidly because the lattice constant depends on the impurity concentration.
  • the gate type source region 8 is formed on the type base region 6 as in the present embodiment, the impurity concentration does not change rapidly because the first source region 8 3 exists.
  • the high-concentration second source region 8 is formed by ion implantation instead of epitaxial growth. For this reason, when n-type dopant remains in the epitaxial growth equipment and contaminates the growth furnace, as in the case of epitaxially growing a high-concentration second source region, the n-type layer or n-type layer is formed later. It is possible to suppress the occurrence of dopant contamination. Therefore, it becomes possible to stably control the impurity concentrations of the type base region 6 and the first source region 83 formed by the epitaxial growth apparatus.
  • a mask (not shown) having an opening at the position where the mold coupling layer 10 is to be formed is arranged. Then, after ion-implanting the type impurities from above the mask, a heat treatment of 150 ° C. or more is performed for activation.
  • the element to be ion-implanted either boron (Mitsumi), aluminum (8), or both are used. As a result, the gate type source region 8 can be repelled by ion implantation of the type impurities to form the type coupling layer 10.
  • the second region 10 of the mold coupling layer 10 needs to be able to make an artificial contact with the source electrode 15. Therefore, the ion implantation is performed at a dose amount that is 2 to 10 times the type impurity concentration of the second source region 81. Regarding the dose amount, if it is twice as much as the type impurity concentration of the second source region 81, it is thought that the carrier concentration can be such that ohmic contact is made with the source electrode 15, but considering the activation rate, 2 to 10 times is preferable ⁇ 2020/175 157 23 ⁇ (: 170? 2020/005592
  • the carrier concentration of the second region 10 cc that is, the type impurity concentration of the component functioning as a carrier excluding the amount of cancellation with respect to the second source region 8 s and the non-activation of
  • it can be set to 2.0 1 ⁇ 18 to 1 ⁇ ⁇ 1 ⁇ 2 ⁇ / ⁇ 3.
  • the source electrode 15 13 is also formed in the second source region 8 13 before the second region 10 13 is formed. I have to make contact with him.
  • since a large dose causes the generation of crystal defects due to ion implantation, it is necessary to suppress the amount to a certain level.
  • the first region 103 since the first region 103 is not a portion that is in ohmic contact with the source electrode 15, it may have a lower type impurity concentration than that of the second region 10. However, here, in consideration of the activation rate, the type impurity is ion-implanted in a dose amount 2 to 10 times that of the first source region 83.
  • the total thickness of the type source region 8 into which the type impurities are implanted is not more than 0.8 from the viewpoint of the output of the ion implantation device. It is preferable to do so. In this way, the mold coupling layer 10 can be formed so as to reach the mold base region 6 even with the output of a general-purpose ion implanter, and mass productivity can be ensured. ..
  • Gate trench 11 is formed by performing anisotropic etching such as ⁇ mi ([ ⁇ 301; 6 10 ⁇ 1x11 _1 hit).
  • the mask is removed and then, for example, thermal oxidation is performed to form the gate insulating film 12, and the gate insulating film 12 covers the inner wall surface of the gate trench 11 and the surface of the n-type source region 8. .. Then, after depositing ? ⁇ I 7-3 I doped with type impurities or gate type impurities, this is etched back, and at least the gate saw 11 is left in the gate trench 11 to form the gate electrode. Forming 1 3 This completes the trench gate structure.
  • the gate trench 1 1 is formed when the trench wrench gate structure is formed due to the influence of damage at the time of ion implantation.
  • the side surface of the is inclined. Therefore, the channel mobility is reduced and the gate trench 11 is widened on the inlet side, which makes it difficult to miniaturize the device.
  • the first source region 8 3 is formed by epitaxial growth, and only the second source region 8 13 is formed by ion implantation. Therefore, the inclination of the side surface of the gate trench 11 due to the damage of the ion implantation is suppressed, and the portion in contact with the second source region 8 is rounded and inclined. Therefore, the gate trench 11 is suppressed from becoming wider on the inlet side, and the miniaturization of the device can be promoted.
  • the interlayer insulating film 14 made of, for example, an oxide film is formed so as to cover the surfaces of the gate electrode 13 and the gate insulating film 12. Further, a contact hole exposing the mold source region 8 and the mold deep layer 9 is formed in the interlayer insulating film 14 by using a mask (not shown). Then, after forming an electrode material composed of, for example, a laminated structure of a plurality of metals on the surface of the interlayer insulating film 14, the electrode material is patterned to form the source electrode 15 and the gate wiring layer. Further, the drain electrode 16 is formed on the back surface side of the gate + type substrate 1. In this way, the 3 ⁇ 3 semiconductor device according to the present embodiment is completed.
  • the n-type source region ⁇ 2020/175 157 25 ⁇ (: 170? 2020 /005592
  • Region 8 is composed of a first source region 8 3 having a relatively low concentration and a second source region 8 13 having a higher concentration. Then, the first source region 83 is formed by epitaxial growth, and the second source region 83 is formed by ion implantation. Therefore, it is possible to improve the short-circuit resistance, suppress the variation of the threshold value V I and the inclination of the side surface of the trench gate, and realize the 3 ⁇ 3 semiconductor device having a structure in which the impurity concentration can be easily controlled.
  • the present embodiment is provided with a non-doped layer as compared with the first embodiment, and is otherwise the same as the first embodiment, so only the parts different from the first embodiment will be described.
  • the non-doped layer 7 made of three silicon oxide is formed on the mold base region 6 and is formed on the three semiconductor devices.
  • the non-doped layer 7 is a layer that is not doped with impurities, or is a layer that has a low carrier concentration by being doped with both a gate type impurity and a type impurity.
  • the thickness of the non-doped layer 7 is set to 0.05 to 0.2.
  • a non-doped layer 7, nitrogen (1 ⁇ 1) n-type impurity is 1.
  • 0 X 1 0 1 6 / ⁇ 3 hereinafter such, preferably is a 1. 0 X 1 0 1 5 / ⁇ 3 or less There is.
  • the non-doped layer 7 contains 1. It is preferably 1.0 X 1 0 1 5 / ⁇ 3 or less.
  • a non-doped layer 7 is provided between the source region 8 3 and the source region. Therefore, the effect of suppressing damage to the gate insulating film 12 can be obtained.
  • This effect will be described with reference to FIGS. 9 to 11.
  • 9 to 11 show the case where the first source region 8 3 is formed so as to be in contact with the type base region 6 when the whole region of the 1... type source region 8 has a high impurity concentration.
  • the gate voltage V 9 is 20 V and the drain-source voltage ⁇ / ⁇ 13 is _ 5 ⁇ /.
  • the parasitic diode formed in the vertical type 1//103 serves as a freewheeling diode, and a freewheeling current flows through the parasitic diode. Then, the holes diffused from the mold layer side of the 1 ⁇ ! junction forming the parasitic diode to the n- type layer side are recombined with the electrons in the gate type layer.
  • Basal plane dislocations hereinafter referred to as “Mix” in the gate-shaped layer composed of the epitaxial film expand and are called single shock race tacking faults (hereinafter referred to as “3 3 3 ”). It becomes a stacking fault.
  • the electric field applied to the n -type source region 8 causes the portion of the type source region 8 that is in contact with the type base region 6 to be in contact with the type base region 6.
  • the existing carriers are accelerated by the electric field and become a hot electron. This collides with the gate insulating film 12 and causes a problem of damaging the gate insulating film 12. In particular, when the n-type impurity concentration is increased in the entire area of the gate type source region 8, this problem becomes remarkable.
  • the n-type source region 8 has the first source region 8 3 without the non-doped layer 7, the type base region 6 and the first source region 8 3 are 1 ⁇ ! Join will be constructed.
  • the n- type impurity concentration of the first source region 8 a is relatively low.
  • the electric field applied to the parts can be suppressed to some extent. That is, as shown in FIG. 10, the equipotential lines at the 1 ⁇ ! junction have a larger distance than in the case of FIG. 9, and the structure including the first source region 8 3 causes the electric field to some extent. Can be suppressed.
  • the junction is formed by the type base region 6 and the first source region 83, so that it is less than in the case of FIG.
  • the above problem can be caused by the generation of hot electrons.
  • a non-doped layer 7 is provided between the n-type source region 8 and 8 3, it is possible to receive an equipotential line by the non-doped layer 7 and weaken the electric field in the n-type source region 8. Become. Then, although an electric field is generated in the non-doped layer 7, there are almost no carriers in the non-doped layer 7. Therefore, by providing the non-doped layer 7, damage to the gate insulating film 12 due to photoelectrons during reverse conduction can be suppressed.
  • the semiconductor device according to Embodiment 3 ⁇ 3 has a non-doped layer 7 formed after forming the mold base region 6 and before forming the mold source region 8. It is manufactured by performing steps.
  • the non-doped layer 7 is formed using the epitaxial growth apparatus used for forming the mold base region 6 and the first source region 88. Specifically, after the type base region 6 is formed, the epitaxial growth is continuously performed with the introduction of the dopant gases of both the type dopant and the n-type dopant into the epitaxial growth apparatus stopped, whereby the non-doped layer is formed. Can form 7. At this time, if the non-doped layer 7 is formed while maintaining the temperature after the formation of the mold base region 6 without performing the temperature lowering process, the process time can be shortened. Further, regarding the subsequent epitaxial growth of the first source region 83, if the temperature is maintained without performing the temperature lowering process after the formation of the non-doped layer 7, the process time can be further shortened.
  • the film thickness can be set arbitrarily, but if it is too thick, the on-resistance ⁇ O becomes high. Therefore, the thickness is set to 0.05 to 0.20!. Further, it is basically preferable that the non-doped layer 7 be free of impurities, but the carrier concentration may be low. In particular, if an attempt is made to continuously form the non-doped layer 7 after the formation of the base region 6, the type impurities remaining in the atmosphere are introduced, or the nitrogen present in the atmosphere is n- type. It may be introduced as an impurity. Even in such a case, it is sufficient if the impurity concentration is low.
  • the impurities of the other conductivity type are intentionally introduced so that they are doped so that they cancel each other out.
  • the carrier concentration may be lowered.
  • the impurity concentration is the 1. 0 X 1 0 1 6 / ⁇ 3 below, when both are doped, one another By canceling each other out, the carrier concentration becomes 1. ⁇ 2020/175 157 29 ⁇ (: 170? 2020 /005592
  • the non-doped layer 7 When the non-doped layer 7 is formed, it is necessary to connect the mold coupling layer 10 to the mold base region 6 when the mold coupling layer 10 is formed.
  • the type impurities are also implanted into 7 and this part also serves as the type coupling layer 10.
  • the non-doped layer 7 is provided between the type base region 6 and the first source region 83. Therefore, the effect of suppressing the generation of photoelectrons and suppressing the damage to the gate insulating film 12 can be obtained.
  • a third embodiment will be described.
  • a method for measuring the film state of the mold layer in the first and second embodiments will be described.
  • an n-type current spreading layer 5 and the first source region 8 3 is epitaxially grown. After formation of these n-type layer, and measured the n-type impurity concentration as the film state of the n-type layer.
  • the surface electronic state of the 1-! type layer does not stabilize immediately after the epitaxial growth of the type layer, but stabilizes after a certain period of time. In order to improve the accuracy of, it is necessary to wait until a certain time has passed after epitaxial growth.
  • the 1 ⁇ ! type impurity concentration can be measured based on the measurement flow of the n type impurity concentration shown in FIG.
  • a 1 ⁇ /103 stacking process is performed.
  • the production process of 1 ⁇ /! ⁇ 3, which is referred to here, is the process of manufacturing the vertical type 1 ⁇ /1 ⁇ 3, which is used in the semiconductor device described in the first and second embodiments.
  • the measurement target layer is the 1-! type current spreading layer 5
  • the steps up to forming the electric field blocking layer 4 shown in FIG. 7 are performed.
  • the measurement target layer is the first source region 8 3 ⁇ 0 2020/175 157 30 (: 17 2020 /005592
  • Step 3110 an epitaxial growth step of the measurement target layer is performed.
  • the gate-shaped current spreading layer 5 or the first source region 83 to be measured is epitaxially grown.
  • a holding step of holding for 10 hours or more in an air atmosphere is performed as an electron stabilizing step.
  • the process proceeds to Step 3130 and the n- type impurity concentration of the measurement target layer is measured.
  • the measurement of the n- type impurity concentration in the n-type layer can be performed using a method called non-contact ⁇ 3 V concentration evaluation. As shown in Fig. 13, the wafer 20 on which the n-type layer has been formed is continuously applied with a charge by corona discharge to electrify the surface of the mold layer and then placed on the wafer 20. This is a method of measuring the n- type impurity concentration from the 0 V curve by repeating the measurement of the surface potential with the potential probe 21. This method can be used to measure the O-type impurity concentration in the measurement target layer after epitaxial growth.
  • the n-type impurity concentration gradually decreases with the elapse of time when the mold layer is simply exposed to the air atmosphere. Then, when the elapsed time reaches 10 hours or more, preferably 18 hours or more, for example, about 24 hours, the n- type impurity concentration is stabilized to be almost constant.
  • the changes in the n-type impurity concentration over time have been examined multiple times, but the impact is a concern because the contactless ⁇ V concentration evaluation will be performed each time. Therefore, the measurement by non-contact ⁇ 3 V concentration evaluation was performed as the first measurement 24 hours after the formation of the n-type layer or the second measurement 30 hours later. ⁇ 2020/175 157 31 ⁇ (: 170? 2020 /005592
  • the n- type impurity concentration of the measurement target layer is measured by the non-contact 0 V concentration evaluation, and the measurement is not performed immediately after the epitaxial growth, but as a step of electron stabilization, the atmosphere is used. The measurement is performed after carrying out the holding step of holding for 10 hours or more below. This makes it possible to measure the concentration of the gate-type impurities with high accuracy.
  • non-contact at 3 ⁇ 3 In the 3 V concentration evaluation, the presence or absence of an oxide film is optional, and the O-type impurity concentration can be measured without being affected by the presence or absence of an oxide film.
  • 1 to 1 treatment even if an oxide film was formed, it was removed so that it could be removed from the beginning even if no oxide film was formed. It is possible to measure the n- type impurity concentration based on the concentration evaluation.
  • step 3230 the n-type impurity concentration of the measurement target layer is measured by the same method as in step 3130 of FIG.
  • the time for starting the measurement of the n-type impurity concentration that is, the elapsed time after the completion of the acid cleaning step is arbitrary, and therefore the elapsed time may be short.
  • a fourth embodiment will be described.
  • the n-type layer but the ⁇ current spreading layer 5 and the first source region 8 3 has been described by way of example, Epitaki ⁇ 2020/175 157 33 ⁇ (: 170? 2020/005592
  • n ⁇ type layer 2 is epitaxially grown on the main surface of n + type substrate 1, A case of measuring the n- type impurity concentration of the mold layer 2 will be described.
  • the 1 ⁇ !-type impurity concentration can be measured based on the n- type impurity concentration measurement flow shown in FIG.
  • a 30° bulk substrate that is, an n + type substrate 1 is prepared.
  • the mold layer 2 is epitaxially grown on the main surface of the n + -type substrate 1.
  • steps 3320 and 3330 a step of measuring the O-type impurity concentration is performed after an acid cleaning step as in steps 3220 and 3230 of FIG.
  • the Mitsune portion 3 and the electric field blocking layer 4 and the n- type current spreading layer 5 are provided, and the "Mitsune portion 3 and the n- type current spreading layer 5 are the drift layers.
  • the structure is a part of the. However, this is merely an example of the configuration of the vertical 1 ⁇ /103 stacking structure, that is, the structure that does not include the JFE part 3 and the electric field blocking layer 4, the structure that does not include the n- type current spreading layer 5, Alternatively, the structure may not include both of them.
  • first region 10 3 may be formed deeper than the first source region 8 3
  • second region 10 c may be formed deeper than the second source region 8 3. Is also good.
  • the mold deep layer 9 and the mold coupling layer 10 are separately configured, but they may be composed of the same mold layer.
  • a deep trench is formed from the surface of the gate type source region 8 through the non-doped layer 7, the type base region 6 and the type current distribution layer 5 to reach the electric field blocking layer 4, and is embedded in the deep trench.
  • a type impurity is ion-implanted from the surface of the n-type source region 8 to form a type layer that reaches the electric field blocking layer 4 from the non-doped layer 7, the O-type base region 6 and the n- type current spreading layer 5. By doing so, it becomes possible to form the mold deep layer 9 and the mold connecting layer 10 by the mold layer.
  • the impurity concentration of the gate type source region 8 is different.
  • the structure in which the two regions, that is, the first source region 83 and the second source region 8 is divided has been described, but the structure may not be clearly divided. That is, the type base region 6 side of the type source region 8 has a lower impurity concentration than the surface side contacted with the source electrode 15 and the surface side is a high impurity concentration contacted with the source electrode 15 by ohmic contact. It only has to be the concentration. In other words, there may be a concentration gradient such that the first source region 8 3 and the second source region 8 are gradually increased in impurity concentration toward the source electrode 15 side.
  • the n-type impurity concentration is measured after the epitaxial growth by using the 1! type current spreading layer 5, the first source region 8 3, and the type layer. This is explained by taking 2 as an example.
  • the ion-implantation step was performed after the epitaxial growth layer was formed on the 3x bulk substrate, and then the gate-shaped current to be the measurement target layer was formed. shows a case that as to form an n-type layer such as distributed layer 5 and the first source region 8 3.
  • the epitaxial growth layer formed in the lower layer ⁇ 2020/175 157 35 ⁇ (: 170? 2020 /005592
  • the n- type impurity concentration can be measured by the non-contact 0 V concentration evaluation described above.
  • the case where the epitaxial growth layer is formed on the 30-bulk substrate, that is, the -type layer 2, which is the 30-layer to be measured, is shown.
  • the n- type impurity concentration can be measured by the above-mentioned non-contact 0 V concentration evaluation even when the epitaxial growth of the layer to be measured is directly performed on the 3 ⁇ 3 bulk substrate.
  • a vertical channel type 1 ⁇ /103 knives which is an n-channel for the first conductivity type and a mold for the second conductivity type, has been described as an example. However, it is also good as a channel-type vertical type 1 ⁇ /! Further, in the above description, the vertical type 1 ⁇ /103 photo was taken as an example of the semiconductor element, but the present disclosure can be applied to a photo of a similar structure.
  • the conductivity type of the n + type substrate 1 is only changed from the door type to the type in the above-mentioned respective embodiments, and other structures and manufacturing methods are the same as those in the above-mentioned respective embodiments Is the same as.

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Abstract

In the present invention, a source region (8) includes a first source region (8a) which is composed of an epitaxial layer that is formed on a base region (6) side, and a second source region (8b) which contacts a source electrode and is composed of an ion implanted layer that has a first conductivity type impurity concentration that is higher than that of the first source region.

Description

\¥0 2020/175157 1 卩（：17 2020 /005592 明 細 書 \¥0 2020/175 157 1 ((17 2020/005592 clarification
発明の名称 ： 炭化珪素半導体装置およびその製造方法 Title of Invention: Silicon Carbide Semiconductor Device and Manufacturing Method Thereof
関連出願への相互参照 Cross-reference to related application
[0001 ] 本出願は、 2 0 1 9年2月 2 7日に出願された日本特許出願番号 2 0 1 9 — 3 4 3 8 0号と、 2 0 2 0年 1月 2 2日に出願された日本特許出願番号 2 0 2 0 - 8 3 7 6号とに基づくもので、 ここにその記載内容が参照により組 み入れられる。 [0001] This application is filed on Feb. 27, 1921, Japanese Patent Application No. 2 0 1 9 — 3 4 3 8 0, and on Jan. 22, 20 20. Japanese Patent Application No. 20202-08367, which is incorporated by reference, the contents of which are incorporated herein by reference.
技術分野 Technical field
[0002] 本開示は、 炭化珪素 （以下、 3 丨 （3という） にて構成される1\/1〇3構造の 半導体素子を有した 3 丨 <3半導体装置およびその製造方法に関する。 [0002] The present disclosure relates to a semiconductor device having a semiconductor element having a 1\/103 structure composed of silicon carbide (hereinafter referred to as "3 (3)") <3 <3 and a manufacturing method thereof.
背景技術 Background technology
[0003] 従来より、 大電流が流せるようにチャネル密度を高く した構造として、 卜 レンチゲート構造を有する 3 丨 <3半導体装置がある。 この 3 丨 <3半導体装置 は、 门型ドリフト層の上に 型べース領域と n +型ソース領域とが順に形成さ れ、 型ソース領域の表面から 型べース領域を貫通して +型ドリフト層 に達するようにトレンチゲートが形成された構造とされる。 具体的には、 n 型ドリフト層の上に 型べース領域をエピタキシャル成長させたのち、 型 ベース領域に対して 1·!型不純物をイオン注入で打ち返すことで 型べース領 域の一部を门型に反転させ、 n +型ソース領域を形成している （例えば、 特許 文献 1参照） 。 [0003] Conventionally, as a structure having a high channel density so that a large current can flow, there is a 3<3 semiconductor device having a wrench gate structure. In this 3 <3 semiconductor device, a type base region and an n + type source region are formed in order on the gate type drift layer, and the + type source region penetrates the type base region from the surface of the type source region. The trench gate is formed so as to reach the type drift layer. Specifically, a type base region is epitaxially grown on the n-type drift layer, and then a 1! type impurity is ion-implanted into the type base region to implant a part of the type base region. Are inverted into a closed type to form an n + type source region (see, for example, Patent Document 1).
先行技術文献 Prior art documents
特許文献 Patent literature
[0004] 特許文献 1 :国際公開第 2 0 1 6 / 0 6 3 6 4 4号パンフレッ ト [0004] Patent Document 1: International Publication No. 2 0 1 6/0 6 3 6 4 4 Panfret
発明の概要 Summary of the invention
[0005] しかしながら、 n +型ソース領域の全域を高濃度の n型不純物層によって形 成しているため、 負荷短絡時の飽和電流値が大きくなり、 3 丨 <3半導体装置 の短絡耐量を得ることができない。 〇 2020/175157 2 卩（：170? 2020 /005592 [0005] However, since the entire n + -type source region is formed by the high-concentration n-type impurity layer, the saturation current value at the time of load short-circuiting becomes large, and the short-circuit withstand capability of the semiconductor device <3 <3 I can't. 〇 2020/175157 2 卩 (: 170? 2020 /005592
[0006] また、 エピタキシャル成長させるときの膜厚バラツキは、 成長させる膜厚 が厚いほど大きくなるが、 イオン注入の飛程のバラツキはあまり大きくない ため、 イオン注入後の 型べース領域の膜厚バラツキは、 エピタキシャル成 長させた膜厚に対応するバラツキとなる。 このため、 型べース領域に対し て +型ソース領域をイオン注入で形成した場合、 +型ソース領域の厚みの バラツキは少なく、 型べース領域の厚みのバラツキが大きくなる。 したが って、 閾値 V Iのバラツキを生じさせるという課題がある。 [0006] Further, the film thickness variation during epitaxial growth increases as the film thickness grown increases, but the variation in the range of ion implantation is not so large, so the film thickness of the mold base region after ion implantation is small. The variation corresponds to the thickness of the epitaxially grown film. Therefore, when the + type source region is formed by ion implantation with respect to the type base region, the variation in the thickness of the + type source region is small and the variation in the thickness of the type base region is large. Therefore, there is the problem of causing variations in the threshold V I.
[0007] また、 n +型ソース領域をイオン注入によって形成すると、 イオン注入時の ダメージの影響により、 トレンチゲートを形成したときに、 トレンチゲート の側面が傾斜した状態となる。 このため、 チャネル移動度を低下させると共 に、 トレンチ入口側においてトレンチゲートが幅広になり、 素子の微細化が 困難になるという課題がある。 When the n + type source region is formed by ion implantation, the side surface of the trench gate is inclined when the trench gate is formed due to the influence of damage at the time of ion implantation. Therefore, there is a problem that the channel mobility is lowered and the trench gate is widened at the trench entrance side, which makes it difficult to miniaturize the device.
[0008] そこで、 本発明者らは、 型べース領域だけでなく、 门+型ソース領域につ いてもエピタキシャル成長によって形成することについて検討を行った。 こ のようにすれば、 型べース領域と门 +型ソース領域それぞれに厚みのバラツ キが分配されることから、 型べース領域の厚みのバラツキを小さくするこ とが可能となる。 ところが、 门+型ソース領域をエピタキシャル成長させるに は、 エピタキシャル成長装置内に n型ドーパントガスを高濃度に導入する必 要があり、 n +型ソース領域の形成後にもエピタキシャル成長装置内に n型ド —パントが残り、 成長炉が汚染される。 これにより、 その後に 型層や门型 層を形成しようとしたときにドーパントコンタミネーシヨンが生じ、 不純物 濃度の管理が不安定になるという課題を発生させる。 [0008] Therefore, the inventors of the present invention examined formation of not only the type base region but also the gate + type source region by epitaxial growth. By doing so, the variation in thickness is distributed to each of the mold base region and the gate + type source region, so that it is possible to reduce the variation in thickness of the mold base region. However, in order to epitaxially grow the gate + type source region, it is necessary to introduce a high concentration of the n-type dopant gas into the epitaxial growth apparatus, and even after the formation of the n + type source region, the n-type dopant region is formed in the epitaxial growth apparatus. Remains and the growth reactor is contaminated. As a result, when the mold layer or the gate-shaped layer is subsequently formed, dopant contamination occurs and the control of the impurity concentration becomes unstable.
本開示は、 短絡耐量の向上、 閾値 V 1のバラツキやトレンチゲートの側面 の傾斜の抑制が図れると共に、 不純物濃度の管理を容易に行える構造の 3 丨 0半導体装置およびその製造方法を提供することを目的とする。 The present disclosure provides a 3-0 semiconductor device having a structure capable of improving the short-circuit withstand capability, suppressing the variation of the threshold V 1 and suppressing the inclination of the side surface of the trench gate, and easily controlling the impurity concentration, and a manufacturing method thereof. With the goal.
[0009] 本開示の 1つの観点における 3 丨 〇半導体装置は、 3 丨 〇からなる第 1 ま たは第 2導電型の基板と、 基板の上に形成され、 基板よりも低不純物濃度と された第 1導電型の 3 丨 〇からなるドリフト層と、 ドリフト層の上に形成さ 〇 2020/175157 3 卩（：170? 2020 /005592 [0009] A semiconductor device according to one aspect of the present disclosure is a substrate of the first or second conductivity type composed of 300, and is formed on a substrate and has an impurity concentration lower than that of the substrate. And a drift layer made of the first conductivity type 3 〇 and formed on the drift layer. 〇 2020/175157 3 (: 170? 2020/005592
れた第 2導電型の 3 丨 （3からなるベース領域と、 ベース領域の上に形成され 、 ドリフト層よりも第 1導電型不純物濃度が高くされた第 1導電型の 3 丨 〇 からなるソース領域と、 ソース領域の表面からベース領域よりも深く形成さ れたゲートトレンチ内に、 該ゲートトレンチの内壁面を覆うゲート絶縁膜と 該ゲート絶縁膜の上に配置されたゲート電極とを備えて構成され、 一方向を 長手方向として複数本がストライプ状に並べられたトレンチゲート構造と、 ゲート電極およびゲート絶縁膜を覆うと共にコンタクトホールが形成された 層間絶縁膜と、 コンタクトホールを通じて、 ソース領域にオーミック接触さ せられたソース電極と、 基板の裏面側に形成されたドレイン電極と、 を含む 半導体素子を備えている。 そして、 ソース領域は、 ベース領域側に形成され たエピタキシャル成長層によって構成されている第 1 ソース領域と、 ソース 電極に接すると共に第 1 ソース領域よりも第 1導電型不純物濃度が高くされ たイオン注入層によって構成されている第 2ソース領域と、 を有している。 Of the second conductivity type (3) (3) and a source of the first conductivity type (3) formed on the base region and having the first conductivity type impurity concentration higher than that of the drift layer. A gate insulating film covering an inner wall surface of the gate trench and a gate electrode disposed on the gate insulating film, the gate insulating film covering a region, a gate trench formed deeper than the surface of the source region and deeper than the base region. The trench gate structure is composed of a plurality of lines arranged in stripes with one direction as the longitudinal direction, the interlayer insulating film that covers the gate electrode and the gate insulating film and the contact hole is formed, and the source region through the contact hole. The semiconductor device includes a source electrode in ohmic contact and a drain electrode formed on the back surface side of the substrate, and the source region is composed of an epitaxial growth layer formed on the base region side. A first source region that is in contact with the source electrode, and a second source region that is formed of an ion-implanted layer having a higher first-conductivity-type impurity concentration than the first source region.
[0010] このように、 ソース領域を比較的低濃度とされた第 1 ソース領域とそれよ りも高濃度とされた第 2ソース領域とによって構成している。 そして、 第 1 ソース領域についてはエピタキシャル成長により形成し、 第 2ソース領域に ついてはイオン注入によって形成している。 このため、 短絡耐量の向上、 閾 値 V Iのバラツキやトレンチゲートの側面の傾斜の抑制が図れると共に、 不 純物濃度の管理を容易に行える構造の 3 丨 <3半導体装置とすることが可能と なる。 As described above, the source region is composed of the first source region having a relatively low concentration and the second source region having a higher concentration. Then, the first source region is formed by epitaxial growth, and the second source region is formed by ion implantation. For this reason, it is possible to improve the short-circuit resistance, suppress the variation of the threshold value VI and suppress the inclination of the side surface of the trench gate, and make it possible to provide a semiconductor device with a structure of 3 <3 semiconductor having a structure capable of easily managing the impurity concentration. Become.
[001 1 ] 本開示のもう 1つの観点は、 上記した本開示の 1つの観点における 3 丨 〇 半導体装置の製造方法に関するものである。 [001 1] Another aspect of the present disclosure relates to a method for manufacturing a 300 semiconductor device according to the above-described one aspect of the present disclosure.
[0012] 具体的には、 3 丨 〇からなる第 1 または第 2導電型の基板を用意すること と、 基板の上に、 基板よりも低不純物濃度の第 1導電型の 3 丨 （3からなるド リフト層を形成することと、 ドリフト層の上に、 第 2導電型の 3 丨 〇からな るべース領域を形成することと、 ベース領域の上に、 ドリフト層よりも第 1 導電型不純物濃度が高くされた第 1導電型の 3 丨 〇からなり、 ベース領域側 に配置される第 1 ソース領域と該第 1 ソース領域の上に該第 1 ソース領域よ 〇 2020/175157 4 卩（：170? 2020 /005592 [0012] Specifically, a substrate of the first or second conductivity type consisting of 300 is prepared, and a substrate of the first conductivity type having a lower impurity concentration than the substrate (from 3 Of the first conductive layer over the drift layer and the base region of the second-conductivity type 300 made on the drift layer. The first source region is formed on the first source region of the third conductivity type having a high impurity concentration, and is disposed on the base region side, and the first source region is formed on the first source region. 〇 2020/175 157 4 (: 170? 2020/005592
りも高不純物濃度とされた第 2ソース領域とを有するソース領域を形成する ことと、 ソース領域の表面からベース領域よりも深いゲートトレンチを、 一 方向を長手方向としてストライプ状に複数本形成したのち、 ゲートトレンチ の内壁面にゲート絶縁膜を形成すると共に、 ゲート絶縁膜の上にゲート電極 を形成することでトレンチゲート構造を形成することと、 ソース領域に電気 的に接続されるソース電極を形成することと、 基板の裏面側にドレイン電極 を形成することと、 を含み、 ベース領域を形成することでは、 ベース領域を エピタキシャル成長によって形成し、 ソース領域を形成することでは、 第 1 ソース領域をエピタキシャル成長によって形成したのち、 第 1 ソース領域に 対して第 1導電型不純物をイオン注入することで第 2ソース領域を形成する Forming a source region having a second source region with a higher impurity concentration, and forming a plurality of gate trenches deeper than the base region from the surface of the source region in stripes with one direction as the longitudinal direction. After that, a gate insulating film is formed on the inner wall surface of the gate trench, a trench gate structure is formed by forming a gate electrode on the gate insulating film, and a source electrode electrically connected to the source region is formed. And forming a drain electrode on the back surface side of the substrate. By forming the base region, the base region is formed by epitaxial growth, and by forming the source region, the first source region is formed. After forming by epitaxial growth, the second source region is formed by ion-implanting the first conductivity type impurity into the first source region.
[0013] このようにして、 第 1 ソース領域についてはエピタキシャル成長により形 成し、 第 2ソース領域についてはイオン注入によって形成している。 これに より、 短絡耐量の向上、 閾値 V 1のバラツキやトレンチゲートの側面の傾斜 の抑制が図れると共に、 不純物濃度の管理を容易に行える構造の 3 丨 （3半導 体装置を製造できる。 In this way, the first source region is formed by epitaxial growth, and the second source region is formed by ion implantation. As a result, the short-circuit withstand capability can be improved, variations in the threshold V 1 and the inclination of the side surface of the trench gate can be suppressed, and the 3D (3 semiconductor device) structure can be manufactured in which the impurity concentration can be easily controlled.
[0014] 本開示のさらにもう 1つの観点における 3 丨 <3半導体装置の製造方法は、 測定対象層となる 型の 3 丨 <3層をエピタキシャル成長させることと、 3 I 〇層をエピタキシャル成長させたのちに、 3 丨 〇層の表面電子を安定化させ ることと、 表面電子の安定化後に、 電荷を塗布して 3 丨 〇層の表面を帯電さ せたのち、 3 丨 〇層の表面電位を測定することによって該3 丨 〇層の n型不 純物濃度を測定することと、 を含んでいる。 [0014] According to yet another aspect of the present disclosure, a method of manufacturing a 3<3 semiconductor device includes a method of epitaxially growing 3<<3 layers of a type that is a layer to be measured, and a 3 I 0 layer after epitaxial growth. In addition, the surface electrons of the 3.0 layer are stabilized, and after stabilizing the surface electrons, a charge is applied to charge the surface of the 3.0 layer and then the surface potential of the 3.0 layer is changed. Measuring the concentration of n-type impurities in the 30 layer by measuring.
[0015] このように、 3 丨 〇層の表面電子の安定化を行ってから、 3 丨 〇層の表面 電位の測定を行うようにしている。 これにより、 3 丨 〇層の n型不純物濃度 を精度良く測定することが可能となる。 [0015] As described above, after stabilizing the surface electrons of the 300 layer, the surface potential of the 300 layer is measured. This makes it possible to accurately measure the n-type impurity concentration of the 300 layer.
[0016] なお、 各構成要素等に付された括弧付きの参照符号は、 その構成要素等と 後述する実施形態に記載の具体的な構成要素等との対応関係の _例を示すも のである。 〇 2020/175157 5 卩（：170? 2020 /005592 [0016] Note that the reference numerals in parentheses attached to the respective constituent elements and the like indicate "_" examples of the correspondence relationship between the constituent elements and the like and specific constituent elements and the like described in the embodiments described later. .. 〇 2020/175 157 5 (: 170? 2020/005592
図面の簡単な説明 Brief description of the drawings
［0017］ ［図 1］第 1実施形態にかかる 3 丨 <3半導体装置の断面図である。 [0017] [Fig. 1] Fig. 3 is a cross-sectional view of a 3<3 semiconductor device according to the first embodiment.
［図 2］図 1 に示す 3 丨 〇半導体装置の斜視断面図である。 [Fig. 2] Fig. 2 is a perspective cross-sectional view of the three semiconductor devices shown in Fig. 1.
［図 3］ 型ソース領域の全域を高濃度とした場合の電子電流密度をシミュレー シヨンにより調べた結果を示す図である。 [Fig. 3] Fig. 3 is a diagram showing the results of an electron current density simulation conducted when the concentration of the entire source region is high.
［図 4］ n型ソース領域を第 1 ソース領域および第 2ソース領域で構成した場合 の電子電流密度をシミュレーシヨンにより調べた結果を示す図である。 [Fig. 4] Fig. 4 is a diagram showing the result of examination by simulation of electron current densities when the n- type source region is composed of a first source region and a second source region.
［図 5］第 1 ソース領域の不純物濃度を変化させて、 ドレイン電流の変化をシミ ュレーシヨンにより調べた結果を示す図である。 [FIG. 5] FIG. 5 is a diagram showing the results of examining changes in drain current by simulation while changing the impurity concentration in the first source region.
［図 6］第 1 ソース領域の 型不純物濃度とオン抵抗との関係についてシミュレ —シヨンにより調べた結果を示す図である。 [Fig. 6] Fig. 6 is a diagram showing the results of a simulation study on the relationship between the on-resistance and the type impurity concentration of the first source region.
［図 7八］図 1 に示す 3 丨 <3半導体装置の製造工程を示した斜視断面図である。 ［図 78］図 7 に続く 3 丨 <3半導体装置の製造工程を示した斜視断面図である [Fig. 78] Fig. 7 is a perspective sectional view showing a manufacturing process of the semiconductor device 3<3 shown in Fig. 1. FIG. 78 is a perspective cross-sectional view showing the manufacturing process of the semiconductor device 3 <3 following FIG. 7
［図 7(：］図 7巳に続く 3 丨 <3半導体装置の製造工程を示した斜視断面図である [FIG. 7(:] is a perspective sectional view showing the manufacturing process of the semiconductor device 3 <3 following FIG.
［図 70］図 7 (3に続く 3 丨 <3半導体装置の製造工程を示した斜視断面図である [Fig. 70] Fig. 7 ( 3 3 <3 is a perspective cross-sectional view showing the manufacturing process of the semiconductor device
［図 7£］図 7 0に続く 3 丨 <3半導体装置の製造工程を示した斜視断面図である [Fig. 7£] Fig. 70 is a perspective cross-sectional view showing the manufacturing process of a semiconductor device 3 <3
［図 7ド］図 7巳に続く 3 丨 <3半導体装置の製造工程を示した斜視断面図である [FIG. 7C] is a perspective sectional view showing the manufacturing process of the semiconductor device 3 <3 following FIG.
［図 70］図 7 に続く 3 丨 <3半導体装置の製造工程を示した斜視断面図である [Fig. 70] Fig. 70 is a perspective cross-sectional view showing the manufacturing process of a semiconductor device 3 <3 following FIG.
［図 8］第 2実施形態にかかる 3 丨 <3半導体装置の断面図である。 [FIG. 8] A cross-sectional view of a 3<3 semiconductor device according to a second embodiment.
［図 9；^型ソース領域の全域を高不純物濃度とした場合について、 逆導通時の 電圧分布を調べた結果を示した図である。 [FIG. 9; FIG. 9 is a diagram showing the results of examining the voltage distribution during reverse conduction when the entire region of the ^-type source region has a high impurity concentration.
［図 10］第 1 ソース領域を 型べース領域に接するように形成した場合につい 〇 2020/175157 6 卩（：170? 2020 /005592 [Fig. 10] When the first source region is formed in contact with the mold base region, 〇 2020/175 157 6 卩 (: 170? 2020 /005592
て、 逆導通時の電圧分布を調べた結果を示した図である。 FIG. 6 is a diagram showing a result of examining a voltage distribution during reverse conduction.
［図 1 1］ノンドープ層を備えた場合について、 逆導通時の電圧分布を調べた結 果を示した図である。 [Fig. 11] Fig. 11 shows the results of examining the voltage distribution during reverse conduction in the case where the non-doped layer was provided.
［図 12］第 3実施形態で説明する n型不純物濃度の測定フローを示した図であ る。 FIG. 12 is a diagram showing a measurement flow of the n- type impurity concentration described in the third embodiment.
［図 13］第 3実施形態で説明する n型不純物濃度の測定の様子を示した斜視図 である。 FIG. 13 is a perspective view showing how to measure the n- type impurity concentration described in the third embodiment.
［図 14］ 型層をエピタキシャル成長させた後に、 大気雰囲気に曝した時間と 、 门型濃度の測定結果との関係を示した図である。 [Fig. 14] Fig. 14 is a diagram showing the relationship between the exposure time to the atmosphere after the epitaxial growth of the mold layer and the measurement result of the concentration of the gate type.
［図 15］ 1~1 処理前後の濃度評価値の関係を示した図である。 FIG. 15 is a diagram showing the relationship between the density evaluation values before and after the 1 to 1 treatments.
［図 16］第 3実施形態の他の例として説明する n型不純物濃度の測定フローを 示した図である。 FIG. 16 is a diagram showing a measurement flow of n- type impurity concentration described as another example of the third embodiment.
［図 17］第 4実施形態で説明する n型不純物濃度の測定フローを示した図であ る。 FIG. 17 is a diagram showing a measurement flow of n- type impurity concentration described in the fourth embodiment.
発明を実施するための形態 MODE FOR CARRYING OUT THE INVENTION
［0018］ 以下、 本開示の実施形態について図に基づいて説明する。 なお、 以下の各 実施形態相互において、 互いに同一もしくは均等である部分には、 同一符号 を付して説明を行う。 [0018] Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. In each of the following embodiments, the same or equivalent portions will be denoted by the same reference numerals for description.
［0019］ （第 1実施形態） [0019] (First embodiment)
第 1実施形態について説明する。 本実施形態にかかる 3 丨 <3半導体装置は 、 半導体素子として、 図 1および図 2に示すトレンチゲート構造の反転型の 縦型 1\/1〇3 巳丁が形成されたものである。 これらの図に示す縦型 1\/1〇3 巳丁は、 3 丨 <3半導体装置のうちのセル領域に形成されており、 そのセル領 域を囲むように外周耐圧構造が形成されることで 3 丨 <3半導体装置が構成さ れているが、 ここでは縦型 1\/1〇3 巳丁のみ図示してある。 なお、 以下では 、 図 1および図 2に示すように、 縦型 1\/1〇 3 巳丁の幅方向を X方向、 X方 向に対して交差する縦型1\/1〇3 巳丁の奥行方向を丫方向、 縦型1\/1〇3 巳 丁の厚み方向もしくは深さ方向、 つまり乂丫平面に対する法線方向を 方向 〇 2020/175157 7 卩（：170? 2020 /005592 The first embodiment will be described. In the 3 <3 semiconductor device according to the present embodiment, as a semiconductor element, an inverted vertical 1\/103 stacking trench gate structure shown in FIGS. 1 and 2 is formed. The vertical type 1\/ 1 0 3 mats shown in these figures are formed in the cell region of the semiconductor device of 3 <3 semiconductor devices, and the outer peripheral withstand voltage structure is formed so as to surround the cell region. 3 <3 semiconductor devices are constructed, but only the vertical type 1\/103 is shown here. In addition, in the following, as shown in Fig. 1 and Fig. 2, the vertical 1\/1○3 mending machine intersects the width direction of the vertical 1\/1○3 mending machine in the X direction and the X direction. The depth direction of the vertical direction is the thickness direction or the depth direction of the vertical 1\/1〇3 knife, that is, the direction normal to the flat surface. 〇 2020/175 157 7 卩 (: 170? 2020 /005592
として説明する。 As described below.
[0020] 図 1および図 2に示されるように、 3 丨 〇半導体装置には、 3 丨 〇からな る门+型基板 1が半導体基板として用いられている。 n+型基板 1の主表面上 に 3 丨 <3からなる n-型層 2が形成されている。 门+型基板 1は、 表面が （0 001） 3 丨面とされ、 例えば n型不純物濃度が 5. 9 1 018/〇〇^とさ れ、 厚さが 1 〇〇 とされている。 n-型層 2は、 例えば n型不純物濃度が 7. 0 1 015~2. 0 X 1 016/〇〇13とされ、 厚さが 8. 〇 とされて いる。 As shown in FIG. 1 and FIG. 2, a 3+ semiconductor device uses a ++ type substrate 1 made of 300 as a semiconductor substrate. On the main surface of the n+ type substrate 1, an n− type layer 2 of 3<3 is formed. The surface of the door + type substrate 1 is a (0 001) 3 surface, for example, the n-type impurity concentration is 5.9 1 0 18 /○^, and the thickness is 100 °. n -. -type layer 2, an n-type impurity concentration is set to 7. 0 1 0 15 ~ 2 0 X 1 0 16 / Rei_rei_1 3, the thickness is the 8 〇.
[0021] n-型層 2の上には、 3 丨 〇からなる」 巳丁部 3と電界ブロック層 4が形 成されており、 n-型層 2は、 n+型基板 1から離れた位置において」 巳丁 部 3と連結されている。 [0021] On top of the n-type layer 2, there are 3 parts.” The part 3 and the electric field blocking layer 4 are formed, and the n-type layer 2 is located away from the n+ type substrate 1. At “”, it is connected to Mitsube Department 3.
[0022] J F E丁部 3と電界ブロック層 4は、 飽和電流抑制層を構成するものであ り、 共に、 X方向に延設され、 丫方向において交互に繰り返し並べられて配 置されている。 つまり、 门+型基板 1の主表面に対する法線方向から見て、 」 巳丁部 3の少なくとも一部と電界ブロック層 4は、 それぞれ複数の短冊状 、 つまりストライプ状とされ、 それぞれが交互に並べられたレイアウトとさ れている。 [0022] The JFE section 3 and the electric field blocking layer 4 compose a saturation current suppressing layer, and both extend in the X direction and are alternately arranged in the vertical direction. In other words, when viewed from the direction normal to the main surface of the door + type substrate 1, at least a part of the Ming part 3 and the electric field blocking layer 4 are respectively formed into a plurality of strips, that is, stripes, and are alternately arranged. It is said to be a side-by-side layout.
[0023] なお、 本実施形態の場合、 」 巳丁部 3が電界ブロック層 4よりも下方ま で形成されたものとされている。 このため、 」 巳丁部 3のうちストライプ 状とされている部分は電界ブロック層 4の下方において連結した状態になっ ているが、 ストライプ状とされている各部はそれぞれ複数の電界ブロック層 4の間に配置された状態となっている。 In the case of the present embodiment, it is assumed that “” the part 3 is formed below the electric field blocking layer 4. For this reason, the striped portion of the "3" part 3 is connected below the electric field blocking layer 4, but each striped portion of each of the plurality of electric field blocking layers 4 is connected. It is in a state of being placed in between.
[0024] 」 巳丁部 3のうちストライプ状とされている部分の各部、 つまり各短冊 状の部分は、 幅が例えば〇. 25 、 形成間隔となるピッチが例えば〇. 6〜2. 〇 とされている。 また、
Figure imgf000009_0001
の厚みは、 例えば 1. 5 とされており、 n型不純物濃度は、 n-型層 2よりも高くされていて、 例 えば 5. 0 1 016~2. 0 X 1 018/〇〇13とされている。 [0024]" Each part of the striped portion of the Mending part 3, that is, each strip-shaped part has a width of, for example, 0.25, and a pitch of forming intervals is, for example, 0.6 to 2. Has been done. Also,
Figure imgf000009_0001
The thickness of the n-type layer is, for example, 1.5, and the n-type impurity concentration is set higher than that of the n-type layer 2, for example, 5.0 1 0 16 to 2.0 X 10 18 /○ there is a 1 3.
[0025] 電界ブロック層 4は、 型不純物層によって構成されている。 上記したよ 〇 2020/175157 8 卩（：170? 2020 /005592 The electric field blocking layer 4 is composed of a type impurity layer. I mentioned above 〇 2020/175 157 8 卩 (: 170? 2020 /005592
うに、 電界ブロック層 4は、 ストライプ状とされており、 ストライプ状とさ れた電界ブロック層 4の各短冊状の部分は、 幅が例えば〇. 1 5 、 厚み が例えば 1 . 4 とされている。 また、 電界ブロック層 4は、 例えば 型 不純物濃度が 3 . 0 X 1 0 1 7〜 1 .
Figure imgf000010_0001
本実施 形態の場合、 電界ブロック層 4は、 深さ方向において 型不純物濃度が一定 とされている。 また、 電界ブロック層 4は、 n -型層 2と反対側の表面が」 巳丁部 3の表面と同一平面とされている。 As described above, the electric field blocking layer 4 has a striped shape, and each strip-shaped portion of the striped electric field blocking layer 4 has a width of, for example, 0.15 and a thickness of, for example, 1.4. There is. Further, the electric field blocking layer 4 has, for example, a type impurity concentration of 3.0 X 1017 to 1.
Figure imgf000010_0001
In the case of the present embodiment, the electric field blocking layer 4 has a constant type impurity concentration in the depth direction. The surface of the electric field blocking layer 4 opposite to the n − -type layer 2 is flush with the surface of the Mending part 3.
[0026] さらに、 」 巳丁部 3および電界ブロック層 4の上には、 3 丨 〇からなる 门型電流分散層 5が形成されている。 n型電流分散層 5は、 後述するように チヤネルを通じて流れる電流が X方向に拡散できるようにする層であり、 例 えば、
Figure imgf000010_0002
型層 2よりも n型不純物濃度が高くされている。 本実施形態では、 门型電流分散層 5は、 丫方向に向けて延設されており、 n型不純物濃度が」 巳丁部 3と同じかそれよりも高くされ、 例えば厚みが〇. 5 とされて いる。 [0026] Further, on the Mending part 3 and the electric field blocking layer 4, a closed type current spreading layer 5 made of 300 is formed. The n-type current distribution layer 5 is a layer that allows the current flowing through the channel to diffuse in the X direction, as will be described later.
Figure imgf000010_0002
The n- type impurity concentration is higher than that of the mold layer 2. In the present embodiment, the gate-type current spreading layer 5 is extended in the direction of the bird's eye, and has the n-type impurity concentration equal to or higher than that of the Mitsube part 3, for example, a thickness of 0.5. Has been done.
[0027] なお、 ここでは、 ドリフト層を、 便宜的に 型層 2、
Figure imgf000010_0003
部 3および 门型電流分散層 5に分けて説明しているが、 これらは共にドリフト層を構成 する部分であり、 互いに連結されている。 [0027] Here, the drift layer is referred to as a mold layer 2 for convenience sake.
Figure imgf000010_0003
The part 3 and the gate-type current spreading layer 5 are described separately, but these are both parts that form the drift layer and are connected to each other.
[0028] n型電流分散層 5の上には 3 丨 〇からなる 型べース領域 6が形成されて いる。 また、 型べース領域 6の上には 型ソース領域 8が形成されている 。 n型ソース領域 8は、 型べース領域 6のうち n型電流分散層 5と対応す る部分の上に形成されている。 [0028] On the n-type current spreading layer 5, a type base region 6 of 300 is formed. A mold source region 8 is formed on the mold base region 6. The n- type source region 8 is formed on a portion of the type base region 6 corresponding to the n- type current spreading layer 5.
[0029] 型べース領域 6は、 電界ブロック層 4よりも厚みが薄く、 かつ、 型不 純物濃度が低くされており、 例えば 型不純物濃度が 3 X 1 〇1 7/〇 3とさ れ、 厚さが〇. 4〜〇. 6 〇!とされている。 [0029] The type base region 6 is thinner than the electric field blocking layer 4 and has a low concentration of type impurities. For example, the type impurity concentration is 3 X 1 0 1 7/0 3. It is said that the thickness is from 0.4 to 0.60!
[0030] n型ソース領域 8は、 型べース領域 6側とその反対側、 つまり素子表面 側とで〇型不純物濃度が異なった構造とされている。 具体的には、 n型ソー ス領域 8は、 型べース領域 6側に配置された第 1 ソース領域 8 3と、 素子 表面側に配置された第 2ソース領域 8匕とを有した構成とされている。 〇 2020/175157 9 卩（：170? 2020 /005592 The n-type source region 8 has a structure in which the O-type impurity concentration is different between the type base region 6 side and the opposite side, that is, the element surface side. Specifically, the n- type source region 8 includes a first source region 8 3 arranged on the side of the type base region 6 and a second source region 8 3 arranged on the device surface side. It is said that. 〇 2020/175 157 9 (: 170? 2020/005592
[0031 ] 第 1 ソース領域 8 3は、 第 2ソース領域 8 13よりも n型不純物濃度が低く されており、 エピタキシャル成長層にて構成されたもので、 本実施形態の場 合は〇型べース領域 6と接している。 第 1 ソース領域 8 3は、 例えば n型不 純物濃度が 2 . 0 X 1 0 〜 1 . 〇 X 1 〇 1ァ/〇〇1 3以下とされ、 厚みが〇.[0031] The first source region 8 3 has a lower n- type impurity concentration than the second source region 8 13 and is composed of an epitaxial growth layer. Borders area 6. The first source region 8 3, for example, n-type non-pure concentration is between 2. 0 X 1 0 ~ 1. 〇 X 1 〇 1 § / hundred 1 3 or less, a thickness 〇.
2〜〇. 5 01、 好ましくは〇. 3 〇!以上とされている。 It is set to 2 to 0. 05 01, preferably 0. 3 0! or more.
[0032] 第 2ソース領域 8 13は、 後述するソース電極 1 5とのコンタクトを取るた めの領域であり、 イオン注入層によって構成されたもので、 1·!型不純物が高 濃度とされている。 第 2ソース領域 8匕は、 例えば n型不純物濃度が 1 . 0 X 1 0 1 8 ~ 5 . 0 X 1 0 1 9/〇〇1 3とされ、 厚みが〇. 1〜〇. 2 とされ ている。 The second source region 8 13 is a region for making contact with a source electrode 15 to be described later, and is composed of an ion-implanted layer, and has a high concentration of 1·!-type impurities. There is. Second source region 8 spoon, for example n-type impurity concentration is set to 1. 0 X 1 0 1 8 ~ 5. 0 X 1 0 1 9 / Rei_rei_1 3, is the thickness 〇. 1～〇. 2 ing.
[0033] また、 型べース領域 6から下方に向けて、 具体的には」 巳丁部 3と電 界ブロック層 4の表面から 型べース領域 6の間であって、 型電流分散層 5が形成されていない部分に、 型ディープ層 9が形成されている。 本実施 形態では、 型ディープ層 9は、 」 巳丁部 3のうちのストライプ状の部分 や電界ブロック層 4の長手方向に対して交差する方向、 ここでは丫方向を長 手方向とした短冊状とされ、 X方向に複数本並べられることでストライプ状 にレイアウトされている。 この 型ディープ層 9を通じて、 型べース領域 6や電界ブロック層 4が電気的に接続されている。 型ディープ層 9の形成 ピッチは、 後述するトレンチゲート構造の形成間隔となるセルピッチと合わ せてあり、 隣り合う トレンチゲート構造の間に 型ディープ層 9が配置され るようにしてある。 [0033] In addition, from the mold base region 6 downward, specifically, between the surface of the mold part 3 and the electric field block layer 4 and the mold base region 6, the mold current distribution The mold deep layer 9 is formed in a portion where the layer 5 is not formed. In the present embodiment, the mold deep layer 9 is a strip-shaped portion in which the striped portion of the Mending part 3 and the longitudinal direction of the electric field blocking layer 4 are crossed. It is laid out in stripes by arranging multiple lines in the X direction. Through the mold deep layer 9, the mold base region 6 and the electric field blocking layer 4 are electrically connected. The formation pitch of the type deep layer 9 is matched with the cell pitch which is the formation interval of the trench gate structure described later, and the type deep layer 9 is arranged between the adjacent trench gate structures.
[0034] さらに、 型べース領域 6上のうち 型ディープ層 9と対応する位置、 換 言すれば n型ソース領域 8と異なる位置であって n型ソース領域 8を挟んで トレンチゲート構造と反対側の位置に、 型連結層 1 0が形成されている。 型連結層 1 〇は、 型べース領域 6と後述するソース電極 1 5とを連結す ることで電気的に接続するための層である。 本実施形態では、 型連結層 1 0は、 型べース領域 6側とその反対側、 つまり素子表面側とで 型不純物 濃度が異なった構造とされている。 具体的には、 型連結層 1 0は、 型べ 〇 2020/175157 10 卩（：170? 2020 /005592 Further, a trench gate structure is formed on the type base region 6 at a position corresponding to the type deep layer 9, that is, at a position different from the n-type source region 8 with the n-type source region 8 interposed therebetween. The mold connecting layer 10 is formed at a position on the opposite side. The mold connection layer 10 is a layer for electrically connecting by connecting the mold base region 6 and a source electrode 15 described later. In the present embodiment, the type coupling layer 10 has a structure in which the type impurity concentration is different between the type base region 6 side and the opposite side, that is, the element surface side. Specifically, the mold connecting layer 10 is a mold base. 〇 2020/175 157 10 卩 (: 170? 2020 /005592
—ス領域 6側に配置された第 1領域 1 03と、 素子表面側に配置された第 2 領域 1 013とを有した構成とされている。 —A first region 103 arranged on the side of the scan region 6 and a second region 1013 arranged on the side of the element surface.
[0035] 第 1領域 1 〇 3は、 第 1 ソース領域 83と同程度もしくは、 より深く構成 され、 第 2領域 1 0匕よりも 型不純物濃度が低くされていて、 型べース 領域 6と接した構造とされている。 第 1領域 1
Figure imgf000012_0001
は、 例えば 型不純物濃 度が 2. 0X 1 〇17〜 1. 0 X 1 019/〇〇13とされ、 厚みが〇. 2〜 0. 5 、 好ましくは〇. 3 以上とされている。 ただし、 本実施形態の場合 、 第 1領域 1 03を第 1 ソース領域 83へのイオン注入によって形成してい ることから、 キャリア濃度、 つまりキャリアとして機能する分の 型不純物 濃度が 2. 0X 1 〇17〜 1. 0 X 1 019/〇 3となるようにしている。 [0035] The first region 1 〇 3, the degree and the first source region 8 3 same or is configured deeper, the type impurity concentration than the second region 1 0 spoon have been lowered, the mold base over source region 6 It is said to be in contact with the structure. First area 1
Figure imgf000012_0001
Is, for example, type impurity concentration is 2 is as 0X 1 〇 17 ~ 1. 0 X 1 0 19 / Rei_rei_1 3, thickness 〇. 2 to 0.5, and is preferably a 〇. 3 above .. However, in the case of the present embodiment, since the first region 103 is formed by ion implantation into the first source region 83, the carrier concentration, that is, the type impurity concentration of the portion functioning as a carrier, is 2.0X10. 17 to 1. are set to be 0 X 1 0 19 / 〇 3.
[0036] 第 2領域 1 〇匕は、 第 2ソース領域 8匕と同程度の深さで構成され、 後述 するソース電極 1 5とのコンタクトを取るための領域であり、 型不純物が 高濃度とされている。 第 2領域 1 〇匕は、 例えば 型不純物濃度が 2. 〇 1 018〜 1. 0x 1 020/0 01 3とされ、 厚みが〇. 2〜〇. 3 〇!とされて いる。 ただし、 本実施形態の場合、 第 2領域 1 0匕を第 2ソース領域 8匕へ のイオン注入によって形成していることから、 キャリア濃度、 つまりキャリ アとして機能する分の 型不純物濃度が 2. 0 1 〇18〜 1. 0X 1 020/ 〇 013となるようにしている。 [0036] The second region 10 ⌕ is a region having a depth similar to that of the second source region 8 ⌕, and is a region for making contact with a source electrode 15 described later, and has a high concentration of type impurities. Has been done. The second region 1 〇 spoon, for example the type impurity concentration 2. is a 〇 1 018~ 1. 0x 1 020/0 01 3, thickness 〇. 2～〇. 3 〇! As being. However, in the case of the present embodiment, since the second region 10 cavities are formed by ion implantation into the second source region 8 cavities, the carrier concentration, that is, the type impurity concentration of the portion functioning as a carrier is 2. 0 1 Rei_18～ are to 1. so that 0X 1 020 / 〇 01 3.
[0037] なお、 後述するように、 本実施形態では、 n型ソース領域 8への 型不純 物のイオン注入によって 型連結層 1 〇を形成している。 その場合、 第 1領 域 1 や第 2領域 1 013の 型不純物濃度は、 型不純物のうちキャリア として機能する分の濃度のことを意味する。 型不純物のうちの一部は、 打 ち込み前の第 1 ソース領域 83に含まれている 型不純物とキャンセルされ て、 キャリアとしては機能しない。 このため、 イオン注入によって 型連結 層 1 〇を形成する場合、 活性化率を加味して、 例えば第 1 ソース領域 83や 第 2ソース領域 813の 型不純物濃度の 2〜 1 0倍のドーズ量で 型不純物 を注入すれば、 上記した 型不純物濃度が得られる。 As will be described later, in the present embodiment, the type coupling layer 10 is formed by ion implantation of type impurities into the n-type source region 8. In that case, the type impurity concentration of the first region 1 and the second region 1013 means the concentration of the type impurities that function as carriers. Some of the type impurities are canceled with the type impurities contained in the first source region 83 before the implantation and do not function as carriers. Therefore, when forming the type coupling layer 10 by ion implantation, taking into account the activation rate, for example, a dose amount that is 2 to 10 times the type impurity concentration of the first source region 8 3 and the second source region 813. By injecting the type impurities with, the above type impurity concentration can be obtained.
[0038] さらに、 n型ソース領域 8および 型べース領域 6を貫通して n型電流分 〇 2020/175157 1 1 卩（：170? 2020 /005592 [0038] Furthermore, the n- type source region 8 and the type base region 6 are penetrated and an n- type current component is 〇 2020/175 157 1 1 卩(: 170? 2020/005592
散層 5に達するように、 例えば幅が〇. 4 、 深さが 型べース領域 6と 门型ソース領域 8の合計膜厚よりも〇. 2〜〇. 4 深くされたゲートト レンチ 1 1が形成されている。 このゲートトレンチ 1 1の側面と接するよう に上述した 型べース領域 6やn型ソース領域 8が配置されている。 ゲート トレンチ 1 1は、 図 2の X方向を幅方向、 」 巳丁部 3や電界ブロック層 4 の長手方向と交差する方向、 ここでは丫方向を長手方向、 方向を深さ方向 とする短冊状のレイアウトで形成されている。 そして、 図 1および図 2には 示していないが、 ゲートトレンチ 1 1は、 複数本が X方向に等間隔に配置さ れたストライプ状とされており、 それぞれの間に 型べース領域 6や 型ソ —ス領域 8が配置されている。 また、 各ゲートトレンチ 1 1の中間位置に、 型ディープ層 9や 型連結層 1 0が配置されている。 The gate wrench is deeper than the total thickness of the base region 6 and the gate source region 8 by a depth of 0.4 to reach 0.4, for example, to reach the diffusion layer 5. Are formed. The above-mentioned type base region 6 and n-type source region 8 are arranged so as to be in contact with the side surface of the gate trench 11. The gate trench 11 has a width direction in the X direction in FIG. 2 and a direction intersecting the longitudinal direction of the Mending part 3 and the electric field block layer 4, here, a strip shape with the longitudinal direction as the longitudinal direction and the direction as the depth direction. It is formed with the layout of. Although not shown in FIGS. 1 and 2, the gate trenches 11 are in the form of stripes in which a plurality of gate trenches 11 are arranged at equal intervals in the X direction, and a type base region 6 is provided between them. A type source area 8 is placed. Further, the mold deep layer 9 and the mold coupling layer 10 are arranged at the intermediate position of each gate trench 11.
[0039] このゲートトレンチ 1 1の側面の位置において、 型べース領域 6は、 縦 型1\/1〇 3 巳丁の作動時に n型ソース領域 8と n型電流分散層 5との間を繫 ぐチャネル領域を形成する。 このチャネル領域を含むゲートトレンチ 1 1の 内壁面は、 ゲート絶縁膜 1 2で覆われている。 ゲート絶縁膜 1 2の表面には ドープド 〇 丨 7 - 3 I にて構成されたゲート電極 1 3が形成されており、 これらゲート絶縁膜 1 2およびゲート電極 1 3によってゲートトレンチ 1 1 内が埋め尽くされ、 トレンチゲート構造が構成されている。 [0039] At the position on the side surface of the gate trench 11, the type base region 6 is located between the n- type source region 8 and the n- type current spreading layer 5 during the operation of the vertical type 1\/1〇3. Form a channel region that connects The inner wall surface of the gate trench 11 including the channel region is covered with the gate insulating film 12. On the surface of the gate insulating film 12 is formed a gate electrode 13 composed of doped 〇丨7-3I, and the inside of the gate trench 11 is filled with these gate insulating film 12 and gate electrode 13. The trench gate structure is constructed.
[0040] このトレンチゲート構造は、 ゲートトレンチ 1 1の側壁がほぼ 方向と平 行とされ、 開口部の入口側において丸みを帯びて傾斜させられて、 開口幅が 底部よりも若干広くなった構造となっている。 より詳しくは、 ゲートトレン チ 1 1の側壁のうち第 1 ソース領域 8 3や 型べース領域 6および n型電流 分散層 5と接する部分についてはほぼ 方向と平行とされ、 第 2ソース領域 8匕と接する部分については丸みを帯びて傾斜した状態となっている。 [0040] In this trench gate structure, the side walls of the gate trench 11 are substantially parallel to each other, and are rounded and inclined at the entrance side of the opening so that the opening width is slightly wider than the bottom. Has become. More specifically, the part of the side wall of the gate trench 11 that is in contact with the first source region 8 3 and the type base region 6 and the n-type current spreading layer 5 is almost parallel to the direction, and the second source region 8 3 The part in contact with the swallow is rounded and inclined.
[0041 ] また、 n型ソース領域 8の表面やゲート電極 1 3の表面には、 層間絶縁膜 [0041] Further, an interlayer insulating film is formed on the surface of the n-type source region 8 and the surface of the gate electrode 13.
1 4を介してソース電極 1 5や図示しないゲート配線層などが形成されてい る。 ソース電極 1 5やゲート配線層は、 複数の金属、 例えば 丨 /八 I等に て構成されている。 そして、 複数の金属のうち少なくとも门型3 丨 （3、 具体 〇 2020/175157 12 卩（：170? 2020 /005592 A source electrode 15 and a gate wiring layer (not shown) are formed via 14. The source electrode 15 and the gate wiring layer are composed of a plurality of metals, for example, I/I. At least 3 types of metal (3, 〇 2020/175 157 12 (: 170? 2020/005592
的には n型ソース領域 8と接触する部分は、 n型 3 丨 <3とオーミック接触可 能な金属で構成されている。 また、 複数の金属のうち少なくとも 型 3 丨 〇 、 具体的には第 2領域 1 0匕と接触する部分は、 型 3 丨 <3とオーミック接 触可能な金属で構成されている。 なお、 ソース電極 1 5は、 層間絶縁膜 1 4 上に形成されることで 3 丨 〇部分と電気的に絶縁されているが、 層間絶縁膜 1 4に形成されたコンタクトホールを通じて、 型ソース領域 8および 型 ディープ層 9と電気的に接触させられている。 Specifically, the part in contact with the n-type source region 8 is composed of a metal capable of ohmic contact with n-type 3 <3. In addition, at least the part of the plurality of metals that is in contact with the mold 3, specifically the second region 10 is made of a metal that is capable of ohmic contact with the mold 3 <3. Although the source electrode 15 is formed on the interlayer insulating film 14 and is electrically insulated from the part of the source electrode 30, the source electrode 15 is formed on the interlayer insulating film 14 through the contact hole formed in the interlayer insulating film 14. 8 and the mold deep layer 9 are in electrical contact.
[0042] 一方、 n +型基板 1の裏面側には n +型基板 1 と電気的に接続されたドレイ ン電極 1 6が形成されている。 このような構造により、 チャネルタイプの 反転型のトレンチゲート構造の縦型1\/1〇3 巳丁が構成されている。 このよ うな縦型1\/1〇3 巳丁が複数セル配置されることでセル領域が構成されてい る。 そして、 このような縦型 1\/1〇3 巳丁が形成されたセル領域を囲むよう に図示しないガードリングなどによる外周耐圧構造が構成されることで 3 1 0半導体装置が構成されている。 On the other hand, a drain electrode 16 electrically connected to the n + type substrate 1 is formed on the back surface side of the n + type substrate 1. With this structure, a vertical 1/3 of a channel-type inverted trench gate structure is constructed. A cell area is constructed by arranging multiple cells of such vertical type 1/103. Then, a 3 10 semiconductor device is formed by forming an outer periphery withstand voltage structure by a guard ring or the like (not shown) so as to surround the cell region in which such a vertical type 1/103 is formed. ..
[0043] このように構成される縦型1\/1〇3 巳丁を有する 3 丨 <3半導体装置は、 例 えば、 ソース電圧 3を〇 、 ドレイン電圧 V を 1〜 1 . 5 Vとした状態 で、 ゲート電極 1 3に対して 2 0 Vのゲート電圧 V 9を印加することで動作 させられる。 すなわち、 縦型 1\/1〇3 巳丁は、 ゲート電圧 V 9が印加される ことにより、 ゲートトレンチ 1 1 に接する部分の 型べース領域 6にチャネ ル領域を形成する。 これにより、 门型ソース領域 8と n型電流分散層 5との 間が導通する。 したがって、 縦型 IV!〇 3 巳丁は、 n +型基板 1 より、 n _型 層 2と」 巳丁部 3および n型電流分散層 5にて構成されるドリフト層を通 じ、 さらにチャネル領域から 1·!型ソース領域 8を通じて、 ドレインーソース 間に電流を流すという動作を行う。 [0043] For example, a semiconductor device having a vertical type 1// 1 0 3 sets of 3 <3 semiconductor devices has a source voltage 3 of 0 and a drain voltage V of 1 to 1.5 V, for example. In this state, it is operated by applying a gate voltage V 9 of 20 V to the gate electrode 13. In other words, the vertical type 1//103 has a channel region formed in the type base region 6 which is in contact with the gate trench 11 when the gate voltage V 9 is applied. As a result, conduction is established between the gate type source region 8 and the n type current spreading layer 5. Therefore, the vertical IV!〇3 舳刳is from the n + -type substrate 1 to the n _ -type layer 2 through the drift layer composed of the 舳鈭 section 3 and the n- type current spreading layer 5 From the region through the 1! type source region 8, an operation is performed in which a current flows between the drain and the source.
[0044] また、 このような半導体装置における縦型1\/1〇3 巳丁を上アームと下ア —ムが備えられたインバータ回路等に適用すると、 縦型1\/1〇3 巳丁に内蔵 される寄生ダイオードが還流ダイオードとして働く。 具体的には、 n -型層 2 などドリフト層を構成する门型層と電界ブロック層 4や 型べース領域 6も 〇 2020/175157 13 卩（：170? 2020 /005592 [0044] Further, when the vertical type 1//1 03 ken in such a semiconductor device is applied to an inverter circuit or the like provided with an upper arm and a lower arm, the vertical type 1//1 003 The parasitic diode built into the circuit works as a freewheeling diode. Specifically, the gate-type layer forming the drift layer such as the n − -type layer 2, the electric field blocking layer 4, and the type base region 6 are also included. 〇 2020/175 157 13 卩 (: 170? 2020 /005592
しくは 型ディープ層 9を含む 型層とによる 1\1接合によって寄生ダイオ —ドが構成され、 これが還流ダイオードとして働く。 A parasitic diode is formed by a 1\1 junction with the type layer including the type deep layer 9, and this acts as a freewheeling diode.
[0045] インバータ回路等は、 直流電源を用いつつ交流モータ等の負荷に対して交 流電流を供給する際に用いられる。 例えば、 インバータ回路等は、 直流電源 に対して上アームと下アームを直列接続したプリッジ回路を複数個並列接続 し、 各プリッジ回路の上アームと下アームを交互に繰り返しオンオフさせる ことで、 負荷に対して交流電流を供給する。 The inverter circuit and the like are used when supplying an alternating current to a load such as an AC motor while using a DC power supply. For example, in an inverter circuit or the like, a plurality of bridge circuits in which an upper arm and a lower arm are connected in series are connected in parallel to a DC power supply, and the upper arm and lower arm of each bridge circuit are alternately turned on and off repeatedly to load An alternating current is supplied to it.
[0046] 具体的には、 インバータ回路等の各ブリッジ回路では、 上アームの縦型 IV! 〇 3 巳丁をオン、 下アームの縦型 1\/1〇3 巳丁をオフすることで負荷に対 して電流供給を行う。 その後、 上アームの縦型 1\/1〇3 巳丁をオフ、 下アー ムの縦型 |\/|〇3 巳丁をオンして電流供給を停止する。 また、 各アームの縦 型 1\/1〇3 巳丁のオンオフの切り替えの際には、 オフされる側の縦型 IV!〇 3 巳丁に備えられる寄生ダイオードが還流ダイオードとして働き、 還流電流 をソースードレイン間に流すという逆導通時の動作を行う。 このようにして 、 インバータ回路等による負荷の交流駆動が行われる。 [0046] Specifically, in each bridge circuit such as an inverter circuit, a load is generated by turning on the vertical IV! Current is supplied to. After that, turn off the vertical type 1\/1 03 of the upper arm and turn on the vertical type |\/|○3 of the lower arm to stop the current supply. In addition, when switching the vertical type 1//1 03 of each arm on and off, the parasitic diode provided in the vertical IV! The reverse conduction is performed by flowing the current between the source and the drain. In this way, the AC drive of the load is performed by the inverter circuit or the like.
[0047] このような動作を行うに当たり、 負荷短絡が発生すると、 例えば 6 0 0〜 [0047] In performing such an operation, if a load short circuit occurs, for example, 600 to
1 2 0 0 Vもしくはそれ以上の電圧がドレインーソース間電圧 3として ドレインに印加されることになる。 このとき、 门型ソース領域 8の全域が高 濃度の n型不純物層によって構成されていると、 負荷短絡時の飽和電流値が 大きくなり、 3 丨 〇半導体装置の短絡耐量を得ることができなくなる。 これ は、 1·!型ソース領域 8が高濃度とされていることから、 殆ど空乏化する領域 が発生せず、 型ソース領域 8の全域において電流が流れているためと考え られる。 A voltage of 120 V or higher is applied to the drain as the drain-source voltage 3. At this time, if the entire area of the gate-type source region 8 is composed of a high-concentration n-type impurity layer, the saturation current value at the time of load short-circuit becomes large, and it becomes impossible to obtain the short-circuit withstand capability of the semiconductor device. .. This is presumably because the 1! type source region 8 has a high concentration, so that a depleted region hardly occurs and the current flows in the entire region of the type source region 8.
[0048] しかしながら、 本実施形態の 3 丨 （3半導体装置では、 n型ソース領域 8を 比較的低濃度とされた第 1 ソース領域 8 3とそれよりも高濃度とされた第 2 ソース領域 8 13とによって構成していることから、 負荷短絡時の飽和電流値 を小さくすることが可能となる。 これは、 第 1 ソース領域 8 3が低濃度とさ れていることから、 第 1 ソース領域 8 3の広範囲に入り込むように空乏化が 〇 2020/175157 14 卩（：170? 2020 /005592 However, in the three semiconductor devices (three semiconductor devices of the present embodiment, the n-type source region 8 has a relatively low concentration of the first source region 8 3 and the second source region 8 has a higher concentration than that. It is possible to reduce the saturation current value when the load is short-circuited, because it is composed of 13 and 13. This is because the first source region 8 3 has a low concentration, so Depletion so that it enters the wide area of 8 3 〇 2020/175 157 14 卩 (: 170? 2020 /005592
生じ、 空乏化した部分において電流が流れなくなるためと考えられる。 この ように、 本実施形態の 3 丨 （3半導体装置によれば、 短絡耐量を向上させるこ とが可能となる。 It is considered that this is because the current no longer flows in the depleted portion. As described above, according to the three semiconductor devices (three semiconductor devices) of the present embodiment, it is possible to improve the short circuit resistance.
[0049] ここで、 シミュレーシヨンにより、 型ソース領域 8の全域を高濃度とし た場合と、 本実施形態のように第 1 ソース領域 8 3および第 2ソース領域 8 で構成した場合、 それぞれについて、 電子電流密度を調べた。 図 3および 図 4は、 それぞれの結果を示した図である。 図中ハッチングの間隔が狭い部 分ほど、 電子電流密度が高いことを示している。 また、 第 1 ソース領域 8 3 の不純物濃度を変化させて、 ドレイン電流の変化を調べた。 図 5は、 その結 果を示している。 [0049] Here, in the case where the entire area of the mold source region 8 is made to have a high concentration by simulation, and when the first source region 8 3 and the second source region 8 are formed as in the present embodiment, respectively, The electron current density was investigated. Figures 3 and 4 show the respective results. In the figure, the smaller the hatching interval, the higher the electron current density. Further, the change of the drain current was investigated by changing the impurity concentration of the first source region 83. Figure 5 shows the results.
[0050] なお、 図 3〜図 5のシミュレーシヨンでは、 ソース電圧 3を〇 、 ゲー 卜電圧 9を 2 0 、 ドレイン電圧 を 7 5〇 としている。 また、 図 3 のシミュレーシヨンでは、 门型ソース領域 8の全域の门型不純物濃度を 1 .[0050] In the simulations of Figs. 3 to 5, the source voltage 3 is 0, the gate voltage 9 is 20 and the drain voltage is 75 0. In addition, in the simulation shown in Fig. 3, the concentration of the gate-shaped impurity in the entire gate-shaped source region 8 is 1.
0 X 1 0 1 9/〇 3としている。 同様に、 図 4のシミュレーシヨンでは、 门型 ソース領域 8を第 1 ソース領域 8 3と第 2ソース領域 8 13で構成しつつ、 第 1 ソース領域 8 3の 型不純物濃度を 1 . 0 1 0 1 6/〇〇1 3とし、 第 2ソー ス領域 8 1〇の门型不純物濃度を 1 . 0 X 1 0 1 9/〇〇1 3としている。 図 5のシ ミュレーシヨンでは、 型ソース領域 8を第 1 ソース領域 8 3と第 2ソース 領域 8 13で構成しつつ、 第 2ソース領域 8 1〇の 型不純物濃度を 1 . 0 X 1
Figure imgf000016_0001
とし、 第 1 ソース領域 8 3の 型不純物濃度を変化させている。 It is set as 0 X 1 0 1 9 / 〇 3 . Similarly, in the simulation shown in FIG. 4, the gate type source region 8 is composed of the first source region 8 3 and the second source region 8 13 while the type impurity concentration of the first source region 8 3 is 1.0 1 0. and 1 6 / Rei_rei_1 3, and the门型impurity concentration of the second source region 8 1_Rei and 1. 0 X 1 0 1 9 / Rei_rei_1 3. In the simulation of FIG. 5, the type source region 8 is composed of the first source region 8 3 and the second source region 8 13 while the type impurity concentration of the second source region 8 10 is 1.0 X 1
Figure imgf000016_0001
Then, the type impurity concentration of the first source region 83 is changed.
[0051 ] 図 3に示すように、 n型ソース領域 8の全域の n型不純物濃度を高濃度と した場合、 1·!型ソース領域 8の全域において電子電流密度が高くなっている ことが判る。 これは、 门型ソース領域 8が高濃度とされていることから、 殆 ど空乏化する領域が発生せず、 〇型ソース領域 8の全域において電流が流れ ているためと考えられる。 As shown in FIG. 3, when the n- type impurity concentration in the entire region of the n- type source region 8 is high, it can be seen that the electron current density is high in the entire region of the 1-! type source region 8. .. It is considered that this is because the high concentration of the gate-type source region 8 causes almost no depletion region to occur, and the current flows in the entire region of the O-type source region 8.
[0052] —方、 図 4に示すように、 n型ソース領域 8を第 1 ソース領域 8 3および 第 2ソース領域 8 13で構成した場合、 第 1 ソース領域 8 3において、 電子電 流密度が小さくなっていることが判る。 これは、 第 1 ソース領域 8 3が低濃 〇 2020/175157 15 卩（：170? 2020 /005592 [0052] On the other hand, when the n-type source region 8 is composed of the first source region 8 3 and the second source region 8 13 as shown in FIG. 4, the electron current density in the first source region 8 3 is You can see that it is getting smaller. This is because the first source area 8 3 〇 2020/175 157 15 卩(: 170? 2020/005592
度とされていることから、 第 1 ソース領域 8 3の広範囲に入り込むように空 乏化が生じ、 空乏化した部分において電流が流れなくなるためと考えられる It is considered that depletion occurs so that it enters the wide area of the first source region 8 3 and current does not flow in the depleted portion.
［0053］ このシミュレーション結果からも、 门型ソース領域 8を第 1 ソース領域 8 [0053] Also from this simulation result, the gate-shaped source region 8 is changed to the first source region 8
3および第 2ソース領域 8 13によって構成することで、 負荷短絡時における 飽和電流値を低減できると言える。 したがって、 本実施形態の構造とするこ とで、 3 丨 （3半導体装置の短絡耐量を向上させることが可能になることが判 る。 It can be said that the saturation current value at the time of load short-circuiting can be reduced by using the third and second source regions 813. Therefore, it can be understood that the structure of this embodiment can improve the short-circuit withstand capability of the semiconductor device (3 semiconductor devices).
［0054］ また、 第 1 ソース領域 8 3については、 第 2ソース領域 8匕よりも n型不 純物濃度が低ければ良いものの、 ある程度の濃度でないと飽和電流値を所望 値まで低下させることができない。 具体的には、 負荷短絡時のドレイン電流 が 1 4 0 0 0 /〇 2以下となるようにすれば、 所望の短絡耐量を得ること ができる。 そして、 図 5に示されるように、 負荷短絡時のドレイン電流が 1 4 0 0 0八/〇 2以下となるのは、 第 1 ソース領域 8 aのn型不純物濃度が 1 . 0 X 1 0 1 7/〇 3以下となる場合である。 したがって、 本実施形態の 3 半導体装置のように、 第 1 ソース領域 8 aのn型不純物濃度を 1 . 〇 1 0 1 7/〇
Figure imgf000017_0001
以下とすることで、 短絡耐量を向上させることが可能となる。[0054] Regarding the first source region 83, it is sufficient if the n-type impurity concentration is lower than that of the second source region 8, but the saturation current value can be reduced to a desired value if the concentration is not a certain level. Can not. Specifically, the drain current during the load short circuit if to be 1 4 0 0 0 / 〇 2 or less, it is possible to obtain the desired short-circuit tolerance. Then, as shown in FIG. 5, the drain current at the time of load short-circuiting is 1400 0.88/○ 2 or less when the n-type impurity concentration of the first source region 8 a is 1.0 X 10 It is the case when it becomes 1 7 / 〇 3 or less. Therefore, the n- type impurity concentration of the first source region 8a is set to 1.0 1 0 1 7 /○ as in the 3 semiconductor device of this embodiment.
Figure imgf000017_0001
By setting the following, it becomes possible to improve the short circuit withstand capability.
［0055］ ただし、 第 1 ソース領域 8 3の n型不純物濃度が低すぎると、 第 1 ソース 領域 8 3の抵抗値が大きくなり過ぎ、 オン抵抗 〇 nを増大させることにな る。 第 1 ソース領域 8 3の 型不純物濃度とオン抵抗 〇 との関係につい て調べたところ、 図 6に示す結果となった。 3 丨 〇半導体装置の高速スイッ チング動作を鑑みると、 オン抵抗 〇 1·!については 1 .
Figure imgf000017_0002
以下であ ることが好ましい。 図 6の結果によれば、 第 1 ソース領域 8 aのn型不純物 濃度が 2 . 0 X 1 0 1 6/〇〇1 3未満になると急激にオン抵抗［¾〇 nが上昇する が、 〇型不純物濃度がそれ以上であれば、 オン抵抗 R o nを 1 .
Figure imgf000017_0003
[0055] However, if the n-type impurity concentration of the first source region 83 is too low, the resistance value of the first source region 83 becomes too large and the on-resistance 〇 n is increased. When the relationship between the type impurity concentration of the first source region 83 and the on-resistance 〇 was investigated, the results shown in Fig. 6 were obtained. 3 〇 Considering the high-speed switching operation of semiconductor devices, the on resistance 〇!
Figure imgf000017_0002
The following is preferable. According to the results of FIG. 6, but n-type impurity concentration of the first source region 8 a is 2. 0 X 1 0 1 6 / Rei_rei_1 goes below 3 abruptly on resistance [¾_〇 n increases, 〇 If the type impurity concentration is higher, the on-resistance R on is 1.
Figure imgf000017_0003
以下にできていた。 したがって、 本実施形態の 3 丨 <3半導体装置のように、 第 1 ソース領域 8 3の1^型不純物濃度を 2 . 〇 1 0 1 6/〇 3以上とするこ とで、 オン抵抗 〇门の劣化を抑制することが可能となる。 〇 2020/175157 16 卩（：170? 2020 /005592 It was done below. Thus, like the 3丨<3 semiconductor device of the present embodiment, the 1 ^ -type impurity concentration of the first source region 8 3 2. 〇 1 0 1 and 6 / 〇 3 or more and child, the on-resistance 〇门Can be suppressed. 〇 2020/175 157 16 卩 (: 170? 2020 /005592
［0056］ このように、 第 1 ソース領域 8 3の门型不純物濃度を 2 . 0 X 1 0 1 6〜 1 . 0 X 1 0 1 7/〇 3とすることで、 短絡耐量を向上させつつ、 オン抵抗［¾〇 门の劣化を抑制することが可能となる。 [0056] By thus setting the concentration of the gate-type impurities in the first source region 8 3 to be 2.0 X 10 16 to 1.0 X 10 17 /○ 3 , the short-circuit withstand capability is improved. , ON resistance [It is possible to suppress the deterioration of the gate.
［0057］ また、 本実施形態の 3 丨 <3半導体装置には、 」 巳丁部 3および電界ブロ ック層 4を備えてある。 このため、 縦型 1\/1〇3 巳丁の動作時には、 3 F E 丁部 3および電界ブロック層 4が飽和電流抑制層として機能し、 飽和電流抑 制効果を発揮することで低オン抵抗を図りつつ、 低飽和電流を維持できる構 造とすることが可能となる。 具体的には、 」 巳丁部 3のうちストライプ状 とされた部分と電界ブロック層 4とが交互に繰り返し形成された構造とされ ていることから、 次に示すような作動を行う。 [0057] In addition, the 3<3 semiconductor device of the present embodiment is provided with a "3" section and an electric field block layer 4. For this reason, when the vertical type 1//103 is in operation, the 3FE section 3 and the electric field blocking layer 4 function as a saturation current suppressing layer, and the saturation current suppressing effect is exerted, resulting in low on-resistance. It is possible to achieve a structure that can maintain a low saturation current while aiming. Specifically, the following operation is performed because the stripe portion and the electric field blocking layer 4 of the Mending portion 3 are alternately and repeatedly formed.
［0058］ まず、 ドレイン電圧 が例えば 1〜 1 . 5 Vのように通常作動時に印加 される電圧である場合には、 電界ブロック層 4側から」 巳丁部 3へ伸びる 空乏層は、 」 巳丁部 3のうちストライプ状とされた部分の幅よりも小さい 幅しか伸びない。 このため、 」 巳丁部 3内へ空乏層が伸びても電流経路が 確保される。 そして、 」 巳丁部 3の n型不純物濃度が n -型層 2よりも高く されていて、 電流経路を低抵抗に構成できるため、 低オン抵抗を図ることが 可能となる。 [0058] First, when the drain voltage is a voltage applied during normal operation, such as 1 to 1.5 V, the depletion layer extending from the electric field blocking layer 4 side to the "mending part 3" is Only the width smaller than the width of the striped part of the claw part 3 extends. Therefore, even if the depletion layer extends into the Mitsube part 3, a current path is secured. Further, since the n-type impurity concentration of the Mending part 3 is higher than that of the n − -type layer 2, the current path can be configured to have a low resistance, so that a low on-resistance can be achieved.
［0059］ また、 負荷短絡などによってドレイン電圧 が通常作動時の電圧よりも 高くなると、 電界ブロック層 4側から」 巳丁部 3へ伸びる空乏層が」 巳 丁部 3のうちストライプ状とされた部分の幅よりも伸びる。 そして、 型電 流分散層 5よりも先に」 巳丁部 3が即座にピンチオフされる。 このとき、 [0059] Also, when the drain voltage becomes higher than the voltage during normal operation due to a load short circuit, etc., the depletion layer extending from the electric field blocking layer 4 side to the "Mending part 3" was formed into a striped shape in the "Ming part 3". It extends longer than the width of the part. Then, before the mold current dispersion layer 5, the Mitsube 3 is immediately pinched off. At this time,
」 巳丁部 3のうちストライプ状とされた部分の幅および n型不純物濃度に 基づいてドレイン電圧 V ¢1と空乏層の幅との関係が決まる。 このため、 通常 作動時のドレイン電圧 よりも少し高い電圧となったときに」 巳丁部 3 がピンチオフされるように、 」 巳丁部 3のうちストライプ状とされた部分 の幅および门型不純物濃度を設定する。 これにより、 低いドレイン電圧 でも」 巳丁部 3をピンチオフすることが可能となる。 このように、 ドレイ ン電圧 が通常作動時の電圧よりも高くなったときに」 巳丁部 3が即座 \¥0 2020/175157 17 卩（：17 2020 /005592 The relationship between the drain voltage V ¢1 and the width of the depletion layer is determined based on the width of the striped portion of the Mending part 3 and the n-type impurity concentration. For this reason, the width of the striped portion of the Mouth portion 3 and the gate-shaped impurity should be checked so that the “Mouth portion 3 is pinched off when the drain voltage becomes slightly higher than the drain voltage during normal operation.” Set the concentration. As a result, it is possible to pinch off the Mitsube part 3 even with a low drain voltage. In this way, when the drain voltage becomes higher than the voltage during normal operation" \¥0 2020/175 157 17 (: 17 2020 /005592
にピンチオフされるようにすることで、 低飽和電流を維持することができ、 更に負荷短絡等による 3 丨 0半導体装置の耐量を向上することが可能となる By pinching off at low voltage, it is possible to maintain a low saturation current and further improve the withstand capability of the 3 x 0 semiconductor device due to load short circuit, etc.
[0060] このように、
Figure imgf000019_0001
よび電界ブロック層 4が飽和電流抑制層とし て機能し、 飽和電流抑制効果を発揮することで、 更に低オン抵抗と低飽和電 流を両立することができる 3 丨 <3半導体装置とすることが可能となる。 [0060] In this way,
Figure imgf000019_0001
Since the electric field blocking layer 4 and the electric field blocking layer 4 function as a saturation current suppressing layer and exerts a saturation current suppressing effect, a low on-resistance and a low saturation current can be achieved at the same time. It will be possible.
[0061 ] さらに、 」 巳丁部 3を挟み込むように電界ブロック層 4を備えることで 、 」 巳丁部 3のうちストライプ状とされた部分と電界ブロック層 4とが交 互に繰り返し形成された構造とされている。 このため、 ドレイン電圧 が 高電圧になったとしても、 下方から 1·! -型層 2に伸びてくる空乏層の伸びが電 界ブロック層 4によって抑えられ、 トレンチゲート構造に延伸することを防 ぐことができる。 したがって、 ゲート絶縁膜 1 2に掛かる電界を低下させる 電界抑制効果を発揮させられ、 ゲート絶縁膜 1 2が破壊されることを抑制で きるため、 高耐圧化で信頼性の高い素子とすることが可能となる。 そして、 このようにトレンチゲート構造への空乏層の延伸を防げるため、 ドリフト層 の一部を構成する〇 -型層 2や」 巳丁部 3の n型不純物濃度を比較的濃くす ることができ、 低オン抵抗化を図ることが可能となる。 [0061] Further, "" By providing the electric field blocking layer 4 so as to sandwich the Mending part 3, the striped portion of the "Minging part 3" and the electric field blocking layer 4 are alternately and repeatedly formed. It is considered as a structure. Therefore, even if the drain voltage becomes high, the extension of the depletion layer extending from the bottom to the 1-!-type layer 2 is suppressed by the field block layer 4 and the extension to the trench gate structure is prevented. You can Therefore, the electric field suppressing effect of lowering the electric field applied to the gate insulating film 12 can be exerted, and the destruction of the gate insulating film 12 can be suppressed, so that an element with high withstand voltage and high reliability can be obtained. It will be possible. In order to prevent the depletion layer from extending to the trench gate structure in this way, it is possible to make the n- type impurity concentration of the 〇 − type layer 2 and the ‘Ming part 3 which form part of the drift layer relatively high. Therefore, it is possible to reduce the on-resistance.
[0062] よって、 低オン抵抗かつ高信頼性の縦型1\/1〇3 巳丁を有する3 丨 （3半導 体装置とすることが可能となる。 [0062] Therefore, it becomes possible to provide a 3 x (3 semiconductor device) having a low ON resistance and a highly reliable vertical type 1/103 knives.
[0063] 次に、 本実施形態にかかる nチャネルタイプの反転型のトレンチゲート構 造の縦型|\/|〇3 巳丁を備えた 3 丨 <3半導体装置の製造方法について、 図 7 八〜図 7 1~1に示す製造工程中の断面図を参照して説明する。 [0063] Next, a method of manufacturing a semiconductor device with a vertical type of the n-channel type inverted trench gate structure according to the present embodiment |\/| It described with reference to cross-sectional views in the manufacturing process shown in to 7 1-1.
[0064] 〔図 7八に示す工程〕 [0064] [Steps shown in FIG. 78]
まず、 半導体基板として、 n +型基板 1 を用意する。 そして、 図示しない〇
Figure imgf000019_0002
装置を用いたエピタキシャル成長によりFirst, an n + type substrate 1 is prepared as a semiconductor substrate. And, not shown
Figure imgf000019_0002
By epitaxial growth using the equipment
、 门+型基板 1の主表面上に 3 丨 〇からなる n -型層 2を形成する。 このとき 、 门+型基板 1の主表面上に予め n -型層 2を成長させてある所謂エピ基板を 用いても良い。 そして、 型層 2の上に 3 丨 〇からなる」 巳丁部 3をエピ 〇 2020/175157 18 卩（：170? 2020 /005592 An n − -type layer 2 made of 300 is formed on the main surface of the + type substrate 1. At this time, a so-called epi substrate in which the n − -type layer 2 is previously grown on the main surface of the door + type substrate 1 may be used. And it consists of 3 parts on the mold layer 2.” Epi 〇 2020/175 157 18 卩 (: 170? 2020 /005592
タキシャル成長させる。 Grow taxi.
[0065] なお、 エピタキシャル成長については、 3 丨 〇の原料ガスとなるシランや プロパンに加えて、 n型ドーパントとなるガス、 例えば窒素ガスを導入する ことで行っている。 [0065] Note that the epitaxial growth is performed by introducing a gas that serves as an n-type dopant, for example, nitrogen gas, in addition to silane and propane that serve as raw material gases of 300 parts.
[0066] 〔図 7巳に示す工程〕 [0066] [Step shown in Fig. 7]
」 巳丁部 3の表面に、 マスク 1 7を配置したのち、 マスク 1 7をバター ニングして電界ブロック層 4の形成予定領域を開口させる。 そして、 型不 純物をイオン注入することで、 電界ブロック層 4を形成する。 その後、 マス ク 1 7を除去する。 After arranging the mask 17 on the surface of the part 3, the mask 17 is patterned to open the region where the electric field blocking layer 4 is to be formed. Then, the electric field blocking layer 4 is formed by ion-implanting the type impurities. Then mask 17 is removed.
[0067] なお、 ここでは、 電界ブロック層 4をイオン注入によって形成しているが 、 イオン注入以外の方法によって電界ブロック層 4を形成しても良い。 例え ば、 」 巳丁部 3を選択的に異方性エッチングして電界ブロック層 4と対応 する位置に凹部を形成し、 この上に 型不純物層をエピタキシャル成長させ たのち、 」 巳丁部 3の上に位置する部分において 型不純物層を平坦化し て電界ブロック層 4を形成する。 このように、 電界ブロック層 4をエピタキ シャル成長によって形成することもできる。 型 3 丨 〇をエピタキシャル成 長させる場合、 3 丨 〇の原料ガスに加えて、 型ドーパントとなるガス、 例 えばトリメチルアルミニウム （以下、 丁1\/1八という） を導入すれば良い。 Although the electric field blocking layer 4 is formed here by ion implantation, the electric field blocking layer 4 may be formed by a method other than ion implantation. For example, after the anisotropic etching of the "3" part is selectively formed to form a recess at a position corresponding to the electric field blocking layer 4, a type impurity layer is epitaxially grown on the recessed part, and then the "3 part of the 3" part is formed. The electric field blocking layer 4 is formed by planarizing the type impurity layer in the upper portion. In this way, the electric field blocking layer 4 can also be formed by epitaxial growth. In the case of epitaxially growing the type 300, it is sufficient to introduce a type dopant gas, for example, trimethylaluminum (hereinafter referred to as Ding 1/18), in addition to the source gas of the type 300.
[0068] 〔図 7〇に示す工程〕 [0068] [Steps shown in FIG. 70]
引き続き、 」 巳丁部 3および電界ブロック層 4の上に n型 3 丨 〇をエピ タキシャル成長させることで、 型電流分散層 5を形成する。 そして、 型 電流分散層 5の上に、 型ディープ層 9の形成予定領域が開口する図示しな いマスクを配置する。 その後、 マスクの上から 型不純物をイオン注入する ことで 型ディープ層 9を形成する。 なお、 型ディープ層 9についてもイ オン注入によって形成する例を示したが、 イオン注入以外の方法によって形 成することもできる。 例えば、 電界ブロック層 4と同様に、 n型電流分散層 5に対して凹部を形成したのち、 型不純物層をエピタキシャル成長させ、 さらに 型不純物層の平坦化を行うことで、 型ディープ層 9を形成するよ 〇 2020/175157 19 卩（：170? 2020 /005592 Then, the n-type current 3 is epitaxially grown on the Mending part 3 and the electric field blocking layer 4 to form the type current spreading layer 5. Then, on the mold current spreading layer 5, a mask (not shown) having an opening in the region where the mold deep layer 9 is to be formed is arranged. After that, a mold deep layer 9 is formed by ion-implanting mold impurities from above the mask. The example in which the mold deep layer 9 is also formed by ion implantation is shown, but it can be formed by a method other than ion implantation. For example, similar to the electric field blocking layer 4, after forming a recess in the n-type current spreading layer 5, a type impurity layer is epitaxially grown and the type impurity layer is planarized to form the type deep layer 9. I will do it 〇 2020/175 157 19 卩(: 170? 2020/005592
うにしても良い。 You can do it.
[0069] 〔図 7 0に示す工程〕 [Steps shown in FIG. 70]
図示しない〇 V 0装置を用いて、 n型電流分散層 5および 型ディープ層 9の上に 型べース領域 6および 型ソース領域 8のうちの第 1 ソース領域 8 3を順にエピタキシャル成長させる。 例えば、 同じ＜3 〇装置内において 、 昇温過程を経て成長炉内を所定温度に高温化したのち、 まずはキャリアガ スや 3 丨 〇原料ガスと共に 型ドーパントとなるガスを導入したエピタキシ ャル成長によって 型べース領域 6を形成する。 続いて、 型ドーパントの 導入を停止して门型ドーパントを導入することで、 第 1 ソース領域 8 3を形 成する。 ただし、 このときには第 1 ソース領域 8 3を第 2ソース領域 8 13の 厚み分加算した厚みとしている。 このとき、 降温過程を行うことなく、 型 ベース領域 6の形成後に温度を維持したまま第 1 ソース領域 8 3のエピタキ シャル成長させるようにすることで、 プロセス時間の短縮化を図っている。 A first source region 8 3 of the type base region 6 and the type source region 8 is sequentially grown epitaxially on the n-type current spreading layer 5 and the type deep layer 9 by using a ∘ V 0 device (not shown). For example, in the same <30 equipment, the growth furnace is heated to a predetermined temperature through a temperature raising process, and then, first, epitaxial growth is performed by introducing a gas serving as a type dopant together with a carrier gas and a raw material gas. To form the mold base region 6. Then, by introducing the门型dopant by stopping the introduction of the type dopants, to form formed the first source region 8 3. However, at this time, the thickness of the first source region 8 3 is added by the thickness of the second source region 8 13. At this time, the process time is shortened by performing the epitaxial growth of the first source region 83 while maintaining the temperature after forming the mold base region 6 without performing the temperature lowering process.
[0070] そして、 イオン注入装置を用いて、 型ソース領域 8のうちの表層部に 型不純物をイオン注入する。 これにより、 门型不純物濃度を高く した第 2ソ —ス領域 8匕を形成すると共に、 n型ソース領域 8のうち第 2ソース領域 8 の下方に位置する部分により第 1 ソース領域 8 3を構成する。 このように することで、 第 1 ソース領域 8 3についてはエピタキシャル成長層によって 構成でき、 第 2ソース領域 8 13についてはイオン注入層によって構成ができ る。 Then, a type impurity is ion-implanted into the surface layer portion of the type source region 8 using an ion implantation device. As a result, the second source region 8 having a high impurity concentration is formed, and the first source region 8 3 is formed by the portion of the n-type source region 8 located below the second source region 8. To do. By doing so, the first source region 8 3 can be formed by the epitaxial growth layer, and the second source region 8 13 can be formed by the ion implantation layer.
[0071 ] このようにして、 型べース領域 6および 型ソース領域 8を上記した不 純物濃度および膜厚で形成することができる。 ここで、 各部の膜厚や不純物 濃度については次のように決めている。 In this way, the mold base region 6 and the mold source region 8 can be formed with the above impurity concentration and film thickness. Here, the film thickness and the impurity concentration of each part are determined as follows.
[0072] まず、 型べース領域 6については、 チャネル領域が設定される部分とな ることから、 ゲート電圧 V 9の印加時に反転型チャネルを構成する不純物濃 度に設定しつつ、 チャネル長を規定する膜厚となるようにしている。 このた め、 型べース領域 6については、 例えば 型不純物濃度を
Figure imgf000021_0001
[0072] First, since the channel region is set in the type base region 6, the channel length is set while the impurity concentration forming the inverted channel is set when the gate voltage V 9 is applied. The film thickness is defined as follows. Therefore, for the type base region 6, for example,
Figure imgf000021_0001
3、 厚さを 0 . 4〜〇. 6 〇!としている。 〇 2020/175157 20 卩（：170? 2020 /005592 3. The thickness is 0.4 to 0.60! 〇 2020/175 157 20 (: 170? 2020/005592
［0073］ 门型ソース領域 8のうちの第 1 ソース領域 8 3については、 負荷短絡時に 高いドレイン電圧 V ¢1が印加された場合でも飽和電流値を小さく しつつ、 才 ン抵抗 〇门が高くなることを抑制できるように膜厚および n型不純物濃度 を設定している。 このため、 第 1 ソース領域 8 3については、 例えば n型不 純物濃度を 2 . 0 X 1 0 1 6〜 1 . 〇 X 1 〇 1ァ/〇 3とし、 厚みを〇.
Figure imgf000022_0001
以上としている。 [0073] Regarding the first source region 83 of the gate-shaped source region 8, the saturation current value is reduced and the resistance is high even when a high drain voltage V ¢1 is applied when the load is short-circuited. The film thickness and the n-type impurity concentration are set so as to prevent this from occurring. Therefore, for the first source region 83, for example, the n-type impurity concentration is set to 2.0 X 1016 to 1.0 X 1 X 1a/x3 and the thickness is set to 0.
Figure imgf000022_0001
That is all.
［0074］ 第 2ソース領域 8 13については、 ソース電極 1 5と才ーミック接触させら れる不純物濃度となるようにしつつ、 ソース電極 1 5との化学反応によって 全域が消失してしまわない程度の膜厚に設定してある。 第 2ソース領域 8匕 の n型不純物濃度については高いほど才ーミック接触させ易くなる。 しかし ながら、 本実施形態のように门型ソース領域 8をエピタキシャル成長させた のち 型不純物をイオン注入して 型連結層 1 0を形成することもあり、 そ の場合には、 门型ソース領域 8の n型不純物濃度が高すぎると、 型連結層 1 〇を所望の濃度にできない。 このため、 本実施形態の場合は、 第 2ソース 領域 8匕の n型不純物濃度を例えば 1 . 0 X 1 〇1 8〜 5 . 0 1 0 1 9/〇〇1 3 としてある。 [0074] The second source region 8 13 is a film that does not completely disappear due to a chemical reaction with the source electrode 15 while having an impurity concentration that allows the source electrode 15 to be in ohmic contact. It is set to thick. The higher the n- type impurity concentration of the second source region 8 s, the easier it is to make a talented contact. However, as in the present embodiment, the type source layer 8 may be epitaxially grown and then the type impurities may be ion-implanted to form the type coupling layer 10. In that case, the type source layer 8 may be formed. If the n- type impurity concentration is too high, the type coupling layer 10 cannot have a desired concentration. Therefore, in the present embodiment is an n-type impurity concentration of the second source region 8 spoon as example 1. 0 X 1 〇 1 8 to 5.0 1 0 1 4.5 / Rei_rei_1 3.
［0075］ また、 上記したように、 ソース電極 1 5は、 複数の金属によって構成され ており、 第 2ソース領域 8匕と才ーミック接触させられる部分は、 例えば I によって構成される。 その場合、 第 2ソース領域 8 のうち 1\1 丨 と接触さ せられる部分は 1\］ 丨 シリサイ ドとなることで才ーミック接触となるが、 シリ サイ ド化される分、 第 2ソース領域 8匕が消失することになる。 そして、 シ リサイ ド化反応によって 1\1 丨 シリサイ ドとなるのが〇. 1 程度の厚さで あることから、 シリサイ ド化反応によって第 2ソース領域 8匕が全域消失し ないように、 第 2ソース領域 8 の厚みを〇. 1 〇1以上としている。 [0075] Further, as described above, the source electrode 15 is made of a plurality of metals, and the portion which makes a mechanical contact with the second source region 8 is made of, for example, I. In that case, the portion of the second source region 8 that is in contact with 1\1丨 will be 1\]. 8 swallows will disappear. And since the thickness of about 1\1 becomes silicidation due to the silicidation reaction, it is necessary to make sure that the entire second source region (8 wells) does not disappear due to silicidation reaction. 2 The thickness of the source region 8 is set to 0.11 or more.
［0076］ また、 n型ソース領域 8を構成する第 1 ソース領域 8 3や第 2ソース領域 [0076] In addition, the first source region 8 3 and the second source region forming the n-type source region 8 are also included.
8匕を厚くすると、 ゲートトレンチ 1 1内を 〇 丨 7 - 3 Iで埋め込んだ後 にエッチバックしてゲート電極 1 3を形成する際のエッチバック加工のバラ ツキを許容することができる。 このため、 第 1 ソース領域 8 3および第 2ソ 〇 2020/175157 21 卩（：170? 2020 /005592 If the thickness of the trench is made thicker, it is possible to allow variations in the etch-back process when forming the gate electrode 13 by etching back after filling the inside of the gate trench 11 with 0 7-7 I. Therefore, the first source region 83 and the second source region 〇 2020/175 157 21 卩 (: 170? 2020 /005592
—ス領域 8 13の合計厚さを大きい値にすると良いことから、 第 1 ソース領域 8 3の膜厚や第 2ソース領域 8匕の膜厚を上記範囲としている。 Since it is preferable to make the total thickness of the source region 8 13 large, the film thickness of the first source region 8 3 and the film thickness of the second source region 8 3 are set within the above ranges.
[0077] また、 型べース領域 6および第 1 ソース領域 8 3をエピタキシャル成長 によって形成する場合、 各部の膜厚のバラツキを小さくできる。 そして、 チ ャネル領域の形成に用いられる 型べース領域 6については、 膜厚バラツキ を小さくできることにより、 チャネル長を精度良く作りこむことが可能とな る。 これにより、 縦型 1\/1〇3 巳丁の閾値 V I のバラツキを低減すること が可能となる。 Further, when the type base region 6 and the first source region 83 are formed by epitaxial growth, it is possible to reduce variations in the film thickness of each part. Further, in the mold base region 6 used for forming the channel region, the variation in film thickness can be reduced, so that the channel length can be accurately created. As a result, it is possible to reduce the variation in the threshold V I of the vertical type 1/103.
[0078] 例えば、 型べース領域 6をエピタキシャル成長させたのち、 型べース 領域 6に対して n型不純物を打ち返すことで第 1 ソース領域 8 3および第 2 ソース領域 8匕を両方共に形成することも可能である。 しかしながら、 この 場合、 エピタキシャル成長させるときの 型べース領域 6の膜厚について、 イオン注入によって形成する第 1 ソース領域 8 3および第 2ソース領域 8匕 の分の厚みを見込んで厚くする必要がある。 エピタキシャル成長させるとき の膜厚バラツキは、 成長させる膜厚が厚いほど大きくなるが、 イオン注入の 飛程のバラツキはあまり大きくないため、 イオン注入後の 型べース領域 6 の膜厚/ ラツキは、 エピタキシャル成長させた膜厚に対応するバラツキとな る。 このため、 例えば 型べース領域 6を 1 . 4 の厚みとした場合の膜 厚バラツキが土〇. 2 1 であったとすると、 イオン注入によって第 1 ソ —ス領域 8 3および第 2ソース領域 8 13を形成した後でも、 型べース領域 6の膜厚バラツキは ± 0 . 2 1 となる。 [0078] For example, after the type base region 6 is epitaxially grown, n-type impurities are added back to the type base region 6 to form both the first source region 8 3 and the second source region 8 swath. It is also possible to do so. However, in this case, it is necessary to increase the thickness of the mold base region 6 during the epitaxial growth in consideration of the thickness of the first source region 8 3 and the second source region 8 3 formed by ion implantation. .. The variation in film thickness during epitaxial growth increases as the thickness of the grown film increases, but the variation in the range of ion implantation is not so large, so the thickness/variation of the mold base region 6 after ion implantation is The variation corresponds to the thickness of the epitaxially grown film. Therefore, for example, if the thickness variation of the base region 6 is 1.4 and the soil thickness is 0.21, the first source region 8 3 and the second source region are formed by ion implantation. Even after forming 8 13, the film thickness variation of the mold base region 6 is ± 0.21.
[0079] これに対して、 本実施形態のように、 各部をエピタキシャル成長で形成す る場合、 型べース領域 6の膜厚バラツキは、 第 1 ソース領域 8 3および第 2ソース領域 8匕の膜厚分を含んだバラツキにはならず、 型べース領域 6 のみの厚みに対応したバラツキとなる。 例えば、 型べース領域 6の膜厚を 0 . 4〜〇. 6 とする場合、 膜厚バラツキが ± 0 . 0 6〜〇. 0 9 〇! となる。 このため、 各部をエピタキシャル成長によって形成することで、 型べース領域 6の膜厚バラツキを抑制でき、 チャネル長を精度良く作りこむ 〇 2020/175157 22 卩（：170? 2020 /005592 On the other hand, when each portion is formed by epitaxial growth as in the present embodiment, the film thickness variation of the mold base region 6 is different from that of the first source region 8 3 and the second source region 8 The variation does not include the film thickness, but corresponds to the thickness of only the mold base region 6. For example, when the film thickness of the mold base region 6 is 0.4 to 0.6, the film thickness variation is ±0.06 to 0.090! Therefore, by forming each part by epitaxial growth, it is possible to suppress the variation in the film thickness of the mold base region 6, and to accurately build the channel length. 〇 2020/175 157 22 卩(: 170? 2020/005592
ことができる。 be able to.
[0080] また、 エピタキシャル成長によって各部を連続的に形成する場合、 格子定 数に不純物濃度依存性があることから、 不純物濃度が急激に変化しないこと が好ましい。 これに対して、 本実施形態のように、 型べース領域 6の上に 门型ソース領域 8を形成する場合、 第 1 ソース領域 8 3が存在することから 、 不純物濃度が急激に変化しないようにできる。 Further, when each part is continuously formed by epitaxial growth, it is preferable that the impurity concentration does not change rapidly because the lattice constant depends on the impurity concentration. On the other hand, when the gate type source region 8 is formed on the type base region 6 as in the present embodiment, the impurity concentration does not change rapidly because the first source region 8 3 exists. You can
[0081 ] したがって、 不純物濃度が急激に変化する場合に生じる結晶欠陥を抑制す ることが可能となる。 Therefore, it becomes possible to suppress crystal defects that occur when the impurity concentration changes abruptly.
[0082] さらに、 高濃度となる第 2ソース領域 8 については、 エピタキシャル成 長ではなくイオン注入によって形成している。 このため、 高濃度な第 2ソー ス領域 8匕をエピタキシャル成長させる場合のように、 エピタキシャル成長 装置内に n型ドーパントが残って成長炉を汚染し、 その後に 型層や n型層 を形成したときにドーパントコンタミネーシヨンが生じることを抑制できる 。 したがって、 エピタキシャル成長装置で形成する 型べース領域 6や第 1 ソース領域 8 3の不純物濃度の管理を安定して行うことが可能となる。 Further, the high-concentration second source region 8 is formed by ion implantation instead of epitaxial growth. For this reason, when n-type dopant remains in the epitaxial growth equipment and contaminates the growth furnace, as in the case of epitaxially growing a high-concentration second source region, the n-type layer or n-type layer is formed later. It is possible to suppress the occurrence of dopant contamination. Therefore, it becomes possible to stably control the impurity concentrations of the type base region 6 and the first source region 83 formed by the epitaxial growth apparatus.
[0083] 〔図 7巳に示す工程〕 [0083] [Step shown in Fig. 7]
型ソース領域 8の上に 型連結層 1 0の形成予定位置を開口させた図示 しないマスクを配置する。 そして、 マスクの上から 型不純物をイオン注入 したのち、 活性化のために 1 5 0 0 °〇以上の熱処理を行う。 イオン注入する 元素としては、 ボロン （巳） とアルミニウム （八 丨） のいずれか一方もしく は両方を用いている。 これにより、 门型ソース領域 8を 型不純物のイオン 注入によって打ち返して 型連結層 1 0を形成することができる。 On the mold source region 8, a mask (not shown) having an opening at the position where the mold coupling layer 10 is to be formed is arranged. Then, after ion-implanting the type impurities from above the mask, a heat treatment of 150 ° C. or more is performed for activation. As the element to be ion-implanted, either boron (Mitsumi), aluminum (8), or both are used. As a result, the gate type source region 8 can be repelled by ion implantation of the type impurities to form the type coupling layer 10.
[0084] このとき、 型連結層 1 0のうちの第 2領域 1 0 については、 ソース電 極 1 5と才ーミック接触が取れるようにする必要がある。 このため、 第 2ソ —ス領域 8 1〇の 型不純物濃度の 2〜 1 0倍のドーズ量でイオン注入を行っ ている。 ドーズ量については、 第 2ソース領域 8 1〇の 型不純物濃度の 2倍 あれば、 ソース電極 1 5とオーミック接触させられる程度のキャリア濃度に できると考えられるが、 活性化率を考慮して、 2〜 1 0倍とするのが好まし 〇 2020/175157 23 卩（：170? 2020 /005592 At this time, the second region 10 of the mold coupling layer 10 needs to be able to make an artificial contact with the source electrode 15. Therefore, the ion implantation is performed at a dose amount that is 2 to 10 times the type impurity concentration of the second source region 81. Regarding the dose amount, if it is twice as much as the type impurity concentration of the second source region 81, it is thought that the carrier concentration can be such that ohmic contact is made with the source electrode 15, but considering the activation rate, 2 to 10 times is preferable 〇 2020/175 157 23 卩(: 170? 2020/005592
い。 Yes.
[0085] これにより、 第 2領域 1 0匕のキャリア濃度、 つまり第 2ソース領域 8匕 との間でキャンセルされる分や活性化していない分を除いたキャリアとして 機能する分の 型不純物濃度が例えば 2 . 0 1 〇 1 8〜 1 . 〇\ 1 〇2〇/〇 3となるようにできる。 第 2領域 1 0 13の不純物濃度が高いほどソース電極 1 5とのオーミック接触が取り易くなるが、 第 2領域 1 0匕を形成する前の 第 2ソース領域 8 13についても、 ソース電極 1 5と才ーミック接触させなけ ればならない。 また、 ドーズ量が多いとイオン注入による結晶欠陥の生成の 原因となることから、 ある程度の量に抑える必要がある。 これらを加味して 、 第 2ソース領域 8 13の n型不純物濃度と第 2領域 1 0 13の 型不純物濃度 を設定する必要がある。 このため、 第 2ソース領域 8 1〇の 型不純物濃度や 第 2領域 1 0匕のうち 型不純物濃度を例えば 1 . 0 1 〇 1 8〜 5 . 〇 X 1 0 1 9/〇 3としている。 [0085] As a result, the carrier concentration of the second region 10 cc, that is, the type impurity concentration of the component functioning as a carrier excluding the amount of cancellation with respect to the second source region 8 s and the non-activation of For example, it can be set to 2.0 1 〇 18 to 1 〇 \ 1 〇 2 〇 / 〇 3. The higher the impurity concentration of the second region 10 13 is, the easier the ohmic contact with the source electrode 15 is made. However, the source electrode 15 13 is also formed in the second source region 8 13 before the second region 10 13 is formed. I have to make contact with him. In addition, since a large dose causes the generation of crystal defects due to ion implantation, it is necessary to suppress the amount to a certain level. Taking these into consideration, it is necessary to set the n-type impurity concentration of the second source region 8 13 and the n-type impurity concentration of the second region 10 13. Therefore, we have an out-type impurity concentration of the impurity concentration of the second source region 8 1_Rei and second regions 1 0 spoon for example, 1. 0 1 〇 1 8 1-5. 〇 X 1 0 1 9 / 〇 3.
[0086] —方、 第 1領域 1 0 3については、 ソース電極 1 5と才ーミック接触させ られる部分ではないため、 第 2領域 1 0匕よりも 型不純物濃度が低くて良 い。 ただし、 ここでは、 活性化率を考慮して、 第 1 ソース領域 8 3の 2〜 1 0倍のドーズ量の 型不純物をイオン注入するようにしている。 On the other hand, since the first region 103 is not a portion that is in ohmic contact with the source electrode 15, it may have a lower type impurity concentration than that of the second region 10. However, here, in consideration of the activation rate, the type impurity is ion-implanted in a dose amount 2 to 10 times that of the first source region 83.
[0087] なお、 型連結層 1 0をイオン注入によって形成する場合、 イオン注入装 置の出力の観点より、 型不純物が注入される〇型ソース領域 8の合計膜厚 が〇. 8 以下となるようにすると好ましい。 このようにすれば、 汎用さ れているイオン注入装置の出力でも 型連結層 1 0を 型べース領域 6に達 するように形成することができ、 量産性を担保することが可能となる。 When the mold coupling layer 10 is formed by ion implantation, the total thickness of the type source region 8 into which the type impurities are implanted is not more than 0.8 from the viewpoint of the output of the ion implantation device. It is preferable to do so. In this way, the mold coupling layer 10 can be formed so as to reach the mold base region 6 even with the output of a general-purpose ion implanter, and mass productivity can be ensured. ..
[0088] 〔図 7 に示す工程〕 [0088] [Steps shown in FIG. 7]
门型ソース領域 8などの上に図示しないマスクを形成したのち、 マスクの うちのゲートトレンチ 1 1の形成予定領域を開口させる。 そして、 マスクを 用いて
Figure imgf000025_0001
丨 巳 （[^301； 6 10^1x11 _1叩） 等の異方性エッチングを行うことで、 ゲートトレンチ 1 1 を形成する。 After forming a mask (not shown) on the gate-shaped source region 8 etc., the region where the gate trench 11 is to be formed in the mask is opened. And using a mask
Figure imgf000025_0001
Gate trench 11 is formed by performing anisotropic etching such as 踨mi ([^301; 6 10^1x11 _1 hit).
[0089] 〔図 7 0に示す工程〕 〇 2020/175157 24 卩（：170? 2020 /005592 [Steps shown in FIG. 70] 〇 2020/175 157 24 卩 (: 170? 2020 /005592
その後、 マスクを除去してから例えば熱酸化を行うことによって、 ゲート 絶縁膜 1 2を形成し、 ゲート絶縁膜 1 2によってゲートトレンチ 1 1の内壁 面上および n型ソース領域 8の表面上を覆う。 そして、 型不純物もしくは 门型不純物がドープされた ?〇 I 7 - 3 I をデポジションした後、 これをエ ッチバックし、 少なくともゲートトレンチ 1 1内に 〇 丨 ソー 3 丨 を残すこ とでゲート電極 1 3を形成する。 これにより、 トレンチゲート構造が完成す る。 After that, the mask is removed and then, for example, thermal oxidation is performed to form the gate insulating film 12, and the gate insulating film 12 covers the inner wall surface of the gate trench 11 and the surface of the n-type source region 8. .. Then, after depositing ?〇 I 7-3 I doped with type impurities or gate type impurities, this is etched back, and at least the gate saw 11 is left in the gate trench 11 to form the gate electrode. Forming 1 3 This completes the trench gate structure.
[0090] このようなトレンチゲート構造を形成する際に、 门型ソース領域 8を全域 イオン注入によって形成すると、 イオン注入時のダメージの影響により、 卜 レンチゲート構造を形成したときにゲートトレンチ 1 1の側面が傾斜した状 態となる。 このため、 チャネル移動度を低下させると共に、 ゲートトレンチ 1 1が入口側において幅広になり、 素子の微細化が困難になる。 [0090] In forming such a trench gate structure, if the gate type source region 8 is formed by ion implantation all over, the gate trench 1 1 is formed when the trench wrench gate structure is formed due to the influence of damage at the time of ion implantation. The side surface of the is inclined. Therefore, the channel mobility is reduced and the gate trench 11 is widened on the inlet side, which makes it difficult to miniaturize the device.
[0091 ] しかしながら、 本実施形態では、 第 1 ソース領域 8 3をエピタキシャル成 長によって形成しており、 イオン注入によって形成しているのは第 2ソース 領域 8 13のみである。 このため、 イオン注入のダメージによるゲートトレン チ 1 1の側面の傾斜が抑制され、 概ね第 2ソース領域 8匕と接する部分だけ で丸みを帯びて傾斜した状態となる。 よって、 ゲートトレンチ 1 1が入口側 において幅広になることが抑制され、 素子の微細化も促進できる。 However, in this embodiment, the first source region 8 3 is formed by epitaxial growth, and only the second source region 8 13 is formed by ion implantation. Therefore, the inclination of the side surface of the gate trench 11 due to the damage of the ion implantation is suppressed, and the portion in contact with the second source region 8 is rounded and inclined. Therefore, the gate trench 11 is suppressed from becoming wider on the inlet side, and the miniaturization of the device can be promoted.
[0092] この後の工程については図示しないが、 以下のような工程を行う。 すなわ ち、 ゲート電極 1 3およびゲート絶縁膜 1 2の表面を覆うように、 例えば酸 化膜などによって構成される層間絶縁膜 1 4を形成する。 また、 図示しない マスクを用いて層間絶縁膜 1 4に 型ソース領域 8および 型ディープ層 9 を露出させるコンタクトホールを形成する。 そして、 層間絶縁膜 1 4の表面 上に例えば複数の金属の積層構造により構成される電極材料を形成したのち 、 電極材料をパターニングすることでソース電極 1 5やゲート配線層を形成 する。 さらに、 门+型基板 1の裏面側にドレイン電極 1 6を形成する。 このよ うにして、 本実施形態にかかる 3 丨 <3半導体装置が完成する。 Although not shown in the subsequent steps, the following steps are performed. That is, the interlayer insulating film 14 made of, for example, an oxide film is formed so as to cover the surfaces of the gate electrode 13 and the gate insulating film 12. Further, a contact hole exposing the mold source region 8 and the mold deep layer 9 is formed in the interlayer insulating film 14 by using a mask (not shown). Then, after forming an electrode material composed of, for example, a laminated structure of a plurality of metals on the surface of the interlayer insulating film 14, the electrode material is patterned to form the source electrode 15 and the gate wiring layer. Further, the drain electrode 16 is formed on the back surface side of the gate + type substrate 1. In this way, the 3<3 semiconductor device according to the present embodiment is completed.
[0093] 以上説明したように、 本実施形態の 3 丨 （3半導体装置では、 n型ソース領 〇 2020/175157 25 卩（：170? 2020 /005592 As described above, in the three semiconductor devices (three semiconductor devices, the n-type source region 〇 2020/175 157 25 卩 (: 170? 2020 /005592
域 8を比較的低濃度とされた第 1 ソース領域 8 3とそれよりも高濃度とされ た第 2ソース領域 8 13とによって構成している。 そして、 第 1 ソース領域 8 3についてはエピタキシャル成長により形成し、 第 2ソース領域 8匕につい てはイオン注入によって形成している。 このため、 短絡耐量の向上、 閾値 V Iのバラツキやトレンチゲートの側面の傾斜の抑制が図れると共に、 不純物 濃度の管理を容易に行える構造の 3 丨 <3半導体装置とすることが可能となる Region 8 is composed of a first source region 8 3 having a relatively low concentration and a second source region 8 13 having a higher concentration. Then, the first source region 83 is formed by epitaxial growth, and the second source region 83 is formed by ion implantation. Therefore, it is possible to improve the short-circuit resistance, suppress the variation of the threshold value V I and the inclination of the side surface of the trench gate, and realize the 3 <3 semiconductor device having a structure in which the impurity concentration can be easily controlled.
[0094] （第 2実施形態） (Second Embodiment)
第 2実施形態について説明する。 本実施形態は、 第 1実施形態に対してノ ンドープ層を備えるようにしたものであり、 その他については第 1実施形態 と同様であるため、 第 1実施形態と異なる部分についてのみ説明する。 The second embodiment will be described. The present embodiment is provided with a non-doped layer as compared with the first embodiment, and is otherwise the same as the first embodiment, so only the parts different from the first embodiment will be described.
[0095] 図 8に示すように、 本実施形態にかかる 3 丨 （3半導体装置では、 型べ一 ス領域 6の上に、 3 丨 〇からなるノンドープ層 7が形成されており、 その上 には n型ソース領域 8が形成された構造とされている。 As shown in FIG. 8, in the three semiconductor devices (three semiconductor devices, the non-doped layer 7 made of three silicon oxide is formed on the mold base region 6 and is formed on the three semiconductor devices. Has a structure in which an n-type source region 8 is formed.
[0096] ノンドープ層 7は、 不純物をドープしていない層、 もしくは、 门型不純物 および 型不純物を共にドープすることでキャリア濃度を低く した層である 。 ノンドープ層 7の厚みは、 〇. 0 5〜〇. 2 とされている。 ノンドー プ層 7は、 n型不純物および 型不純物が共にドープされていないのが好ま しいが、 ドープされていたとしても、 キャリア濃度が 1 . 0 1 0 1 6/〇〇1 3 以下、 好ましくは 1 . 0 X 1 0 1 5/〇 3以下とされていれば良い。 例えば、 ノンドープ層 7は、 窒素 （ 1\1） などの n型不純物が 1 . 0 X 1 0 1 6/〇 3以 下、 好ましくは 1 . 0 X 1 0 1 5/〇 3以下とされている。 またノンドープ層 7は、 アルミニウムなどの 型不純物が 1 .
Figure imgf000027_0001
好まし くは 1 . 0 X 1 0 1 5/〇 3以下とされている。 そして、 型不純物と n型不 純物の一方のみがドープされている場合には、 不純物濃度が 1 . 0 X 1 0 1 6 /〇 3以下とされ、 両方がドープされている場合には、 互いに打ち消しあう ことでキャリア濃度が 1 . 0 X 1 0 1 6/〇 3以下となっている。 The non-doped layer 7 is a layer that is not doped with impurities, or is a layer that has a low carrier concentration by being doped with both a gate type impurity and a type impurity. The thickness of the non-doped layer 7 is set to 0.05 to 0.2. Nondo flop layer 7, arbitrary preferable that n-type impurity and impurity are not both doped, even if it is doped with a carrier concentration of 1.0 1 0 1 6 / Rei_rei_1 3 or less, preferably It should be 1.0 X 1 0 1 5 / 〇 3 or less. For example, a non-doped layer 7, nitrogen (1 \ 1) n-type impurity is 1. 0 X 1 0 1 6 / 〇 3 hereinafter such, preferably is a 1. 0 X 1 0 1 5 / 〇 3 or less There is. In addition, the non-doped layer 7 contains 1.
Figure imgf000027_0001
It is preferably 1.0 X 1 0 1 5 / 〇 3 or less. When only one of type impurity and n-type non neat is doped, if the impurity concentration of 1. Is a 0 X 1 0 1 6 / 〇 3 or less, both are doped, carrier concentration is in the 1. 0 X 1 0 1 6 / 〇 3 or less by cancel each other.
[0097] このように、 本実施形態の 3 丨 （3半導体装置では、 型べース領域 6と第 〇 2020/175157 26 卩（：170? 2020 /005592 As described above, in the three semiconductor devices (three semiconductor devices of the present embodiment, 〇 2020/175 157 26 卩 (: 170? 2020 /005592
1 ソース領域 8 3との間にノンドープ層 7を備えるようにしている。 このた め、 ゲート絶縁膜 1 2へのダメージを抑制できるという効果が得られる。 こ の効果について、 図 9〜図 1 1 を参照して説明する。 なお、 図 9〜図 1 1は 、 それぞれ、 1·!型ソース領域 8の全域を高不純物濃度とした場合、 第 1 ソー ス領域 8 3を 型べース領域 6に接するように形成した場合、 ノンドープ層 7を備えた本実施形態の構造の場合について、 逆導通時の電圧分布を調べた 結果を示している。 逆導通時の条件としては、 ゲート電圧 V 9を 2 0 V、 ド レインーソ _ス間電圧 \/〇1 3を _ 5 \/としている。 1 A non-doped layer 7 is provided between the source region 8 3 and the source region. Therefore, the effect of suppressing damage to the gate insulating film 12 can be obtained. This effect will be described with reference to FIGS. 9 to 11. 9 to 11 show the case where the first source region 8 3 is formed so as to be in contact with the type base region 6 when the whole region of the 1... type source region 8 has a high impurity concentration. In the case of the structure of the present embodiment including the non-doped layer 7, the results of examining the voltage distribution during reverse conduction are shown. As conditions for reverse conduction, the gate voltage V 9 is 20 V and the drain-source voltage \/〇 13 is _ 5 \/.
[0098] 逆導通時には、 基本的には、 縦型 1\/1〇3 巳丁に形成される寄生ダイオー ドが還流ダイオードとして働き、 寄生ダイオードを通じて還流電流が流れる 。 そして、 寄生ダイオードを構成する 1\!接合の 型層側から n型層側に拡 散した正孔と门型層中の電子が再結合する。 このとき、 再結合エネルギーが 大きいために、 エピタキシャル膜で構成された门型層中の基底面転位 （以下 、 巳 〇という） が拡張してシングルショックレースタッキングフォルト （ 以下、 3 3 3 という） という積層欠陥になる。 巳 〇は線状欠陥であるた めに、 3 丨 <3半導体装置のセル領域内における占有面積が狭く、 素子動作に 及ぼす影響が殆ど無いが、 3 3 3 になると、 積層欠陥となるためにセル領 域内における占有面積が広くなり、 素子動作に及ぼす影響が大きくなる。 こ のため、 逆導通時にも積極的にゲート電圧 V 9を印加してチャネル領域を形 成し、 チャネル領域を通じても還流電流が流れるようにすれば、 還流電流を 分散して再結合エネルギーを低減できるため、 3 3 3 の発生を抑制するこ とが可能となる。 ただし、 チャネル領域を通じての還流電流の流れが発生す ることから、 型べース領域 6と 型ソース領域 8の間において、 高い電界 が掛かることになり、 ホッ トエレクトロンを生じさせ、 ゲート絶縁膜 1 2に ダメージを与えるという現象が発生する。 At the time of reverse conduction, basically, the parasitic diode formed in the vertical type 1//103 serves as a freewheeling diode, and a freewheeling current flows through the parasitic diode. Then, the holes diffused from the mold layer side of the 1\! junction forming the parasitic diode to the n- type layer side are recombined with the electrons in the gate type layer. At this time, because of the large recombination energy, basal plane dislocations (hereinafter referred to as “Mix”) in the gate-shaped layer composed of the epitaxial film expand and are called single shock race tacking faults (hereinafter referred to as “3 3 3 ”). It becomes a stacking fault. Since ∘∘ is a linear defect, 3 <3 the occupation area in the cell region of the semiconductor device is small, and it has almost no effect on the device operation, but when it is 3 33, it becomes a stacking fault. The occupied area in the cell area becomes wider and the influence on the device operation becomes larger. Therefore, if the gate voltage V 9 is positively applied during reverse conduction to form the channel region and the return current also flows through the channel region, the return current is dispersed and the recombination energy is reduced. Therefore, it is possible to suppress the generation of 3 33. However, since a reflux current flows through the channel region, a high electric field is applied between the type base region 6 and the type source region 8 to generate photoelectrons, which causes the gate insulating film. Phenomenon of causing damage to 1 2 occurs.
[0099] 具体的には、 図 9に示すように、 型べース領域 6に接するように全域高 濃度とした n型ソース領域 8を形成する場合、 逆導通時に、 1\1接合箇所に おいて電位分布が生じ、 门型ソース領域 8に高い電界が掛かる状態となる。 〇 2020/175157 27 卩（：170? 2020 /005592 [0099] Specifically, as shown in FIG. 9, when forming the n-type source region 8 having a high concentration in the entire region so as to be in contact with the type base region 6, at the time of reverse conduction, the 1\1 junction is formed. At this time, a potential distribution is generated and a high electric field is applied to the gate type source region 8. 〇 2020/175 157 27 卩 (: 170? 2020 /005592
〇型べース領域 6に接するように n型ソース領域 8を形成する場合、 n型ソ —ス領域 8に掛けられる電界によって、 型ソース領域 8のうち 型べース 領域 6と接する部分に存在するキャリアが電界によって加速され、 ホッ トエ レクトロンとなる。 これがゲート絶縁膜 1 2に衝突し、 ゲート絶縁膜 1 2に ダメージを与えるという課題を発生させる。 特に、 门型ソース領域 8の全域 において n型不純物濃度を高くすると、 この課題が顕著になる。 〇 When the n- type source region 8 is formed so as to be in contact with the type base region 6, the electric field applied to the n -type source region 8 causes the portion of the type source region 8 that is in contact with the type base region 6 to be in contact with the type base region 6. The existing carriers are accelerated by the electric field and become a hot electron. This collides with the gate insulating film 12 and causes a problem of damaging the gate insulating film 12. In particular, when the n-type impurity concentration is increased in the entire area of the gate type source region 8, this problem becomes remarkable.
[0100] —方、 ノンドープ層 7を備えていなくても、 n型ソース領域 8に第 1 ソー ス領域 8 3を備える場合、 型べース領域 6と第 1 ソース領域 8 3とによっ て 1\!接合が構成されることになる。 このように、 第 1 ソース領域 8 3を備 える場合、 ノンドープ層 7を備えていなくても、 第 1 ソース領域 8 aのn型 不純物濃度が比較的低くされていることから、 1\1接合部に掛かる電界をあ る程度抑制できる。 すなわち、 図 1 0に示されるように、 図 9の場合よりも 1\!接合部での等電位線の間隔が広くなり、 第 1 ソース領域 8 3を備えた構 造の方が電界をある程度抑制できる。 [0100] — On the other hand, if the n-type source region 8 has the first source region 8 3 without the non-doped layer 7, the type base region 6 and the first source region 8 3 are 1\! Join will be constructed. As described above, when the first source region 8 3 is provided, even if the non-doped layer 7 is not provided, the n- type impurity concentration of the first source region 8 a is relatively low. The electric field applied to the parts can be suppressed to some extent. That is, as shown in FIG. 10, the equipotential lines at the 1\! junction have a larger distance than in the case of FIG. 9, and the structure including the first source region 8 3 causes the electric field to some extent. Can be suppressed.
[0101 ] しかしながら、 ノンドープ層 7を形成しない場合には、 型べース領域 6 と第 1 ソース領域 8 3とによる 接合部が構成されることから、 図 9の場 合よりも軽減されるものの、 ホッ トエレクトロンが生成されることで、 上記 課題を発生させ得る。 [0101] However, in the case where the non-doped layer 7 is not formed, the junction is formed by the type base region 6 and the first source region 83, so that it is less than in the case of FIG. The above problem can be caused by the generation of hot electrons.
[0102] これに対して、 本実施形態のように、 型べース領域 6と第 1 ソース領域 [0102] On the other hand, as in the present embodiment, the type base region 6 and the first source region 6
8 3との間にノンドープ層 7を備えると、 図 1 1 に示すように、 ノンドープ 層 7によって等電位線を受けることができ、 n型ソース領域 8中の電界を弱 めることが可能となる。 そして、 ノンドープ層 7中に電界が発生するものの 、 ノンドープ層 7中に殆どキャリアが存在しない。 したがって、 ノンドープ 層 7を備えることにより、 逆導通時のホッ トエレクトロンによるゲート絶縁 膜 1 2のダメージを抑制することができる。 If a non-doped layer 7 is provided between the n-type source region 8 and 8 3, it is possible to receive an equipotential line by the non-doped layer 7 and weaken the electric field in the n-type source region 8. Become. Then, although an electric field is generated in the non-doped layer 7, there are almost no carriers in the non-doped layer 7. Therefore, by providing the non-doped layer 7, damage to the gate insulating film 12 due to photoelectrons during reverse conduction can be suppressed.
[0103] よって、 逆導通時に、 寄生ダイオードだけでなく積極的にチャネル領域を 通じても還流電流が流れるようにすることで 3 3 3 の発生を抑制しつつ、 ホッ トエレクトロンの生成も抑制でき、 ゲート絶縁膜 1 2にダメージを与え 〇 2020/175157 28 卩（：170? 2020 /005592 [0103] Therefore, at the time of reverse conduction, not only the parasitic diode but also the free-wheeling current is allowed to flow positively through the channel region, thereby suppressing generation of 3 3 3 and also generation of hot electrons. , Damage the gate insulating film 1 2 〇 2020/175 157 28 卩 (: 170? 2020 /005592
ることを抑制できる。 Can be suppressed.
[0104] 次に、 本実施形態の 3 丨 <3半導体装置の製造方法について説明する。 本実 施形態の 3 丨 <3半導体装置は、 第 1実施形態で説明した製造方法に加えて、 型べース領域 6の形成後、 型ソース領域 8の形成前に、 ノンドープ層 7 の形成工程を行うことで製造される。 [0104] Next, a method of manufacturing a semiconductor device according to Embodiment 3 <3 will be described. In addition to the manufacturing method described in the first embodiment, the semiconductor device according to the third embodiment has a non-doped layer 7 formed after forming the mold base region 6 and before forming the mold source region 8. It is manufactured by performing steps.
[0105] ノンドープ層 7については、 型べース領域 6や第 1 ソース領域 8 8の形 成に用いるエピタキシャル成長装置を用いて形成される。 具体的には、 型 ベース領域 6を形成したのち、 エピタキシャル成長装置内への 型ドーパン 卜と n型ドーパントの両方のドーパントガスの導入を停止した状態でエピタ キシャル成長を連続して行うことでノンドープ層 7を形成することができる 。 このとき、 降温過程を行うことなく、 型べース領域 6の形成後に温度を 維持したままノンドープ層 7の形成を行うようにすると、 プロセス時間の短 縮化が図れる。 さらに、 その後の第 1 ソース領域 8 3のエピタキシャル成長 についても、 ノンドープ層 7の形成後に降温過程を行うことなく温度を維持 したままにすると、 よりプロセス時間の短縮化が図れる。 [0105] The non-doped layer 7 is formed using the epitaxial growth apparatus used for forming the mold base region 6 and the first source region 88. Specifically, after the type base region 6 is formed, the epitaxial growth is continuously performed with the introduction of the dopant gases of both the type dopant and the n-type dopant into the epitaxial growth apparatus stopped, whereby the non-doped layer is formed. Can form 7. At this time, if the non-doped layer 7 is formed while maintaining the temperature after the formation of the mold base region 6 without performing the temperature lowering process, the process time can be shortened. Further, regarding the subsequent epitaxial growth of the first source region 83, if the temperature is maintained without performing the temperature lowering process after the formation of the non-doped layer 7, the process time can be further shortened.
[0106] ノンドープ層 7については、 任意に膜厚を設定できるが、 厚すぎるとオン 抵抗 ^〇 が高くなる。 このため、 0 . 0 5〜〇. 2 〇!の厚みとしている 。 また、 ノンドープ層 7については、 基本的には不純物が存在しないように するのが好ましいが、 キャリア濃度が低くなっていれば良い。 特に、 型べ —ス領域 6の形成後に連続してノンドープ層 7を形成しようとすると、 雰囲 気中に残留している 型不純物が導入されたり、 大気中に存在している窒素 が n型不純物として導入されることもあり得る。 このような場合であっても 不純物濃度が低ければ良い。 また、 _方の導電型の不純物が導入され得るこ とが想定される場合、 他方の導電型の不純物を意図的に導入して、 両方がド —プされるようにすることで互いに打ち消しあってキャリア濃度が低くなる ようにすればよい。 例えば、 型不純物と n型不純物の一方のみがドープさ れている場合には、 不純物濃度が 1 . 0 X 1 0 1 6/〇 3以下とされ、 両方が ドープされている場合には、 互いに打ち消しあうことでキャリア濃度が 1 . 〇 2020/175157 29 卩（：170? 2020 /005592 [0106] Regarding the non-doped layer 7, the film thickness can be set arbitrarily, but if it is too thick, the on-resistance ^O becomes high. Therefore, the thickness is set to 0.05 to 0.20!. Further, it is basically preferable that the non-doped layer 7 be free of impurities, but the carrier concentration may be low. In particular, if an attempt is made to continuously form the non-doped layer 7 after the formation of the base region 6, the type impurities remaining in the atmosphere are introduced, or the nitrogen present in the atmosphere is n- type. It may be introduced as an impurity. Even in such a case, it is sufficient if the impurity concentration is low. In addition, if it is assumed that impurities of one conductivity type can be introduced, the impurities of the other conductivity type are intentionally introduced so that they are doped so that they cancel each other out. The carrier concentration may be lowered. For example, in the case where only one type impurities and n-type impurity is doped, the impurity concentration is the 1. 0 X 1 0 1 6 / 〇 3 below, when both are doped, one another By canceling each other out, the carrier concentration becomes 1. 〇 2020/175 157 29 卩 (: 170? 2020 /005592
0 X 1 0 1 6/〇 01 3以下となるようにしている。 0 X 1 0 1 6 / 〇 01 3 or less.
[0107] なお、 ノンドープ層 7を形成する場合、 型連結層 1 0の形成の際に、 型連結層 1 〇が 型べース領域 6に接続されるようにする必要があるため、 ノンドープ層 7にも 型不純物が打ち込まれるようにし、 この部分も 型連 結層 1 0となるようにしている。 When the non-doped layer 7 is formed, it is necessary to connect the mold coupling layer 10 to the mold base region 6 when the mold coupling layer 10 is formed. The type impurities are also implanted into 7 and this part also serves as the type coupling layer 10.
[0108] 以上説明したように、 本実施形態の 3 丨 （3半導体装置では、 型べース領 域 6と第 1 ソース領域 8 3との間にノンドープ層 7を備えるようにしている 。 このため、 ホッ トエレクトロンの生成を抑制でき、 ゲート絶縁膜 1 2への ダメージを抑制できるという効果が得られる。 As described above, in the three semiconductor devices (three semiconductor devices of the present embodiment, the non-doped layer 7 is provided between the type base region 6 and the first source region 83. Therefore, the effect of suppressing the generation of photoelectrons and suppressing the damage to the gate insulating film 12 can be obtained.
[0109] （第 3実施形態） [0109] (Third Embodiment)
第 3実施形態について説明する。 本実施形態では、 第 1、 第 2実施形態に おける 型層の膜状態の測定方法について説明する。 A third embodiment will be described. In the present embodiment, a method for measuring the film state of the mold layer in the first and second embodiments will be described.
[01 10] 上記第 1、 第 2実施形態の 3 丨 〇半導体装置では、 n型層として、 n型電 流分散層 5や第 1 ソース領域 8 3をエピタキシャル成長させている。 これら の n型層の形成後に、 n型層の膜状態として n型不純物濃度の測定を行って いる。 [01 10] In the first and 3丨〇 semiconductor device of the second embodiment, as an n-type layer, an n-type current spreading layer 5 and the first source region 8 3 is epitaxially grown. After formation of these n-type layer, and measured the n-type impurity concentration as the film state of the n-type layer.
[01 1 1 ] しかしながら、 1·!型層の表面電子状態は、 型層をエピタキシャル成長さ せて直ぐには安定化せず、 ある程度時間が経過してから安定化するため、 门 型不純物濃度の測定の精度を良くするためには、 エピタキシャル成長後に所 定時間経過するまで待つ必要がある。 具体的には、 図 1 2に示す n型不純物 濃度の測定フローに基づいて、 1·!型不純物濃度の測定を行うことができる。 [01 1 1] However, the surface electronic state of the 1-! type layer does not stabilize immediately after the epitaxial growth of the type layer, but stabilizes after a certain period of time. In order to improve the accuracy of, it is necessary to wait until a certain time has passed after epitaxial growth. Specifically, the 1·! type impurity concentration can be measured based on the measurement flow of the n type impurity concentration shown in FIG.
[01 12] まず、 図 1 2のステップ 3 1 0 0に示すように、 1\/1〇3 巳丁の作成工程 を行う。 ここでいう1\/!〇3 巳丁の作成工程とは、 第 1、 第 2実施形態で説 明した 3 丨 <3半導体装置における縦型1\/1〇3 巳丁の製造工程中の n型不純 物濃度の測定対象となる〇型層 （以下、 測定対象層という） の形成工程の前 までの工程を行うことを意味している。 第 1実施形態を例に挙げると、 測定 対象層が 1·!型電流分散層 5であれば、 図 7巳に示す電界ブロック層 4を形成 するまでの工程を行うことである。 また、 測定対象層が第 1 ソース領域 8 3 \¥0 2020/175157 30 卩（：17 2020 /005592 [01 12] First, as shown in step 3100 of FIG. 12, a 1\/103 stacking process is performed. The production process of 1\/! 〇3, which is referred to here, is the process of manufacturing the vertical type 1\/1 〇3, which is used in the semiconductor device described in the first and second embodiments. This means performing the steps up to the step of forming the O-type layer (hereinafter referred to as the measurement target layer), which is the measurement target of the n-type impurity concentration. Taking the first embodiment as an example, if the measurement target layer is the 1-! type current spreading layer 5, the steps up to forming the electric field blocking layer 4 shown in FIG. 7 are performed. Also, the measurement target layer is the first source region 8 3 \¥0 2020/175 157 30 (: 17 2020 /005592
であれば、 図 7 の 型べース領域 6を形成するまでの工程を行うことであ る。 In that case, the process up to forming the mold base region 6 in FIG. 7 is performed.
[01 13] その後、 ステップ 3 1 1 0に示すように、 測定対象層のエピタキシャル成 長工程を行う。 これにより、 例えば測定対象となる门型電流分散層 5もしく は第 1 ソース領域 8 3がエピタキシャル成長させられる。 そして、 エピタキ シャル成長後に、 ステップ 3 1 2 0に示すように、 電子安定化工程として、 大気雰囲気下において 1 〇時間以上保持する保持工程を行う。 その後、 ステ ップ 3 1 3 0に進み、 測定対象層の n型不純物濃度の測定を行う。 [0113] After that, as shown in Step 3110, an epitaxial growth step of the measurement target layer is performed. As a result, for example, the gate-shaped current spreading layer 5 or the first source region 83 to be measured is epitaxially grown. Then, after the epitaxial growth, as shown in step 3120, a holding step of holding for 10 hours or more in an air atmosphere is performed as an electron stabilizing step. After that, the process proceeds to Step 3130 and the n- type impurity concentration of the measurement target layer is measured.
[01 14] n型層における n型不純物濃度の測定については、 非接触 <3 V濃度評価と いう手法を用いて行うことができる。 これは、 図 1 3のように、 n型層を形 成したウェハ 2 0にコロナ放電で電荷を連続的に塗布して 型層の表面を帯 電させた後、 ウェハ 2 0の上に配置した電位プローブ 2 1で表面電位を測定 することを繰り返し、 0 Vカーブから n型不純物濃度を測定する手法である 。 この手法を用いて、 エピタキシャル成長後の測定対象層の〇型不純物濃度 を測定することができる。 [0114] The measurement of the n- type impurity concentration in the n-type layer can be performed using a method called non-contact <3 V concentration evaluation. As shown in Fig. 13, the wafer 20 on which the n-type layer has been formed is continuously applied with a charge by corona discharge to electrify the surface of the mold layer and then placed on the wafer 20. This is a method of measuring the n- type impurity concentration from the 0 V curve by repeating the measurement of the surface potential with the potential probe 21. This method can be used to measure the O-type impurity concentration in the measurement target layer after epitaxial growth.
[01 15] ただし、 エピタキシャル成長の直後には、 測定対象層となる门型層の表面 電子状態が安定しておらず、 精度良く 1·!型不純物濃度を測定できないことが 確認された。 具体的に、 非接触〇 濃度評価の手法を用いて、 n型層のエピ タキシャル成長後の経過時間と 1·!型不純物濃度との関係について調べた。 図 1 4は、 その結果を示している。 [0115] However, immediately after the epitaxial growth, it was confirmed that the surface electron state of the gate-shaped layer, which is the measurement target layer, was not stable, and the 1! Specifically, the relationship between the elapsed time after the epitaxial growth of the n- type layer and the 1!!-type impurity concentration was investigated using a non-contact O concentration evaluation method. Figure 14 shows the results.
[01 16] 図 1 4に示すように、 型層のエピタキシャル成長後に、 大気雰囲気に曝 しただけの状態の場合、 経過時間に伴って徐々に n型不純物濃度が低下して いく。 そして、 経過時間が 1 0時間以上、 好ましくは 1 8時間以上、 例えば 2 4時間程度に達すると、 ほぼ n型不純物濃度が一定に安定した。 なお、 時 間経過に対する n型不純物濃度の変化について複数回調べているが、 その度 に非接触〇 V濃度評価を行うことになることから、 その影響が懸念される。 このため、 非接触 <3 V濃度評価による測定を、 n型層を形成してから 2 4時 間経過後に 1回目として実施した場合や 3 0時間経過後に 2回目として実施 〇 2020/175157 31 卩（：170? 2020 /005592 [0116] As shown in Fig. 14, after the epitaxial growth of the mold layer, the n-type impurity concentration gradually decreases with the elapse of time when the mold layer is simply exposed to the air atmosphere. Then, when the elapsed time reaches 10 hours or more, preferably 18 hours or more, for example, about 24 hours, the n- type impurity concentration is stabilized to be almost constant. The changes in the n-type impurity concentration over time have been examined multiple times, but the impact is a concern because the contactless 〇V concentration evaluation will be performed each time. Therefore, the measurement by non-contact <3 V concentration evaluation was performed as the first measurement 24 hours after the formation of the n-type layer or the second measurement 30 hours later. 〇 2020/175 157 31 卩 (: 170? 2020 /005592
した場合の n型不純物濃度についても確認したが、 複数回行った場合と同程 度の値になっていた。 したがって、 1·!型不純物濃度の変化の仕方は、 非接触 〇 濃度評価の実施の影響は受けないと言える。 We also confirmed the n-type impurity concentration in the case of performing, but the value was almost the same as that of performing multiple times. Therefore, it can be said that the method of changing the 1·!-type impurity concentration is not affected by the non-contact 〇 concentration evaluation.
[01 17] このように、 エピタキシャル成長の直後には、 測定対象層となる 1·!型層の 表面電子状態が安定しておらず、 n型不純物濃度が高く出てしまうため、 精 度良く |^型不純物濃度を測定することができない。 これに対して、 大気雰囲 気下において 1 0時間以上保持すれば、 測定対象層となる〇型層の表面電子 状態が安定し、 精度良く 1·!型不純物濃度を測定できる。 [0117] As described above, immediately after the epitaxial growth, the surface electron state of the 1-! type layer, which is the measurement target layer, is not stable, and the n-type impurity concentration becomes high. The ^-type impurity concentration cannot be measured. On the other hand, if it is kept in the atmosphere for 10 hours or more, the surface electron state of the O-type layer, which is the measurement target layer, becomes stable, and the 1!
[01 18] 以上のように、 非接触 0 V濃度評価によって測定対象層の n型不純物濃度 を測定しつつ、 エピタキシャル成長させた直後に測定を行うのではなく、 電 子安定化工程として、 大気雰囲気下において 1 〇時間以上保持する保持工程 を行ってから測定を行うようにしている。 これにより、 精度良く 门型不純物 濃度を測定することが可能となる。 [0118] As described above, the n- type impurity concentration of the measurement target layer is measured by the non-contact 0 V concentration evaluation, and the measurement is not performed immediately after the epitaxial growth, but as a step of electron stabilization, the atmosphere is used. The measurement is performed after carrying out the holding step of holding for 10 hours or more below. This makes it possible to measure the concentration of the gate-type impurities with high accuracy.
[01 19] ただし、 保持工程を行ってから測定対象層の n型不純物濃度を測定する場 合、 製造プロセスの長時間化を招くことになり、 ひいては製造コストを増大 させることになる。 [0119] However, if the n- type impurity concentration of the measurement target layer is measured after the holding step is performed, the manufacturing process is lengthened, and the manufacturing cost is increased.
[0120] そこで、 本発明者らは、 n型層の膜状態の測定に要する時間の短時間化す ることについて鋭意検討を行った。 その結果、 型層のエピタキシャル成長 後に表面を酸洗浄することで、 〇型不純物濃度の状態がエピタキシャル成長 後に 1 0時間以上大気雰囲気に曝した場合と同様に安定化することを見出し た。 図 1 4中に、 エピタキシャル成長後に保持工程を行うことなく酸洗浄を 行って非接触 <3 V濃度評価を行った場合の結果についても示した。 [0120] Therefore, the present inventors have earnestly studied to shorten the time required to measure the film state of the n-type layer. As a result, it was found that by acid cleaning the surface after the epitaxial growth of the mold layer, the state of the O-type impurity concentration was stabilized as in the case of being exposed to the atmosphere for 10 hours or more after the epitaxial growth. Figure 14 also shows the results of non-contact <3 V concentration evaluation by acid cleaning without a holding step after epitaxial growth.
[0121 ] n型層のエピタキシャル成長後に、 直ぐに酸洗浄を行った場合の n型不純 物濃度について確認してみると、 図 1 3の白抜き四角形で示すように、 大気 雰囲気に 2 4時間以上曝していた場合と同等の値になっていることが判る。 酸洗浄としては、 3 0 - 2 （塩酸過酸化水素水溶液） 、 3 !\/1 （硫酸過酸化 水素水溶液） 、 オゾン洗浄などを適用することができる。 酸洗浄を行った場 合、 3 丨 <3表面に酸化膜が形成されることもあるが、 酸化膜の有無について 〇 2020/175157 32 卩（：170? 2020 /005592 [0121] After confirming the n-type impurity concentration when the acid cleaning was performed immediately after the epitaxial growth of the n-type layer, as shown by the white squares in Fig. 13, it was exposed to the atmosphere for 24 hours or more. It can be seen that the value is the same as when it was. As the acid cleaning, 30-2 (hydrochloric acid/hydrogen peroxide aqueous solution), 3!\/1 (sulfuric acid/hydrogen peroxide aqueous solution), ozone cleaning or the like can be applied. When acid cleaning is performed, an oxide film may be formed on the surface of 3 <3. 〇 2020/175 157 32 卩 (: 170? 2020 /005592
は任意である。 具体的に、 酸化膜の有無の影響を調べるべく、 型層のエピ タキシャル成長後に酸洗浄を行って〇型不純物濃度を調べた場合と、 さらに その後に 1~1 処理を行ってから再度 n型不純物濃度を調べた場合とで、 n型 不純物濃度の変化を調べた。 その結果、 図 1 5に示すように、 1回目に調べ た n型不純物濃度と 2回目に調べた n型不純物濃度とで変化は無かった。 こ のことから、 3 丨 <3での非接触（3 V濃度評価において、 酸化膜の有無は任意 であり、 酸化膜の有無に影響されずに〇型不純物濃度を測定することができ ることが判る。 なお、 1~1 処理については、 仮に酸化膜が形成されていた場 合でも、 それを除去できるように実施したが、 はじめから酸化膜が形成され ていなくても、 非接触 0 V濃度評価に基づいて n型不純物濃度を測定するこ とは可能である。 Is optional. Specifically, in order to investigate the effect of the presence or absence of an oxide film, a case where acid cleaning was performed after epitaxial growth of the mold layer to check the type 0 impurity concentration, and after that, 1 to 1 treatments were performed and then the n type The change in the n-type impurity concentration was examined depending on whether the impurity concentration was examined. As a result, as shown in Fig. 15, there was no change between the n- type impurity concentration examined at the first time and the n- type impurity concentration examined at the second time. Therefore, non-contact at 3 <3 (In the 3 V concentration evaluation, the presence or absence of an oxide film is optional, and the O-type impurity concentration can be measured without being affected by the presence or absence of an oxide film. Regarding 1 to 1 treatment, even if an oxide film was formed, it was removed so that it could be removed from the beginning even if no oxide film was formed. It is possible to measure the n- type impurity concentration based on the concentration evaluation.
[0122] このように、 n型層のエピタキシャル成長後に酸洗浄を行うことで、 経過 時間が短かったとしても、 1·!型不純物濃度の変化が安定化した後の値を測定 することが可能となる。 したがって、 门型電流分散層 5や第 1 ソース領域 8 3をエピタキシャル成長させた後、 直ぐであっても、 酸洗浄を行ってから 1·! 型不純物濃度を測定することで、 精度良い測定が可能となる。 なお、 このよ うな酸洗浄を行う場合には、 上記した図 1 2に代えて、 図 1 6に示す測定フ 口一に基づいて 型不純物濃度の測定を行うことになる。 すなわち、 ステッ プ3 2 0 0、 3 2 1 0において、 図 1 2のステップ 3 1 0 0 , 3 1 1 0と同 様の工程を行ったのち、 ステップ 3 2 2 0において、 電子安定化工程として 酸洗浄工程を行う。 その後、 ステップ 3 2 3 0において、 図 1 2のステップ 3 1 3 0と同様の手法によって測定対象層の n型不純物濃度を測定する。 こ のときの n型不純物濃度の測定を開始する時間、 つまり酸洗浄工程を完了し てからの経過時間については任意であるため、 経過時間が短かったとしても 構わない。 [0122] Thus, by performing the acid cleaning after the epitaxial growth of the n-type layer, it is possible to measure the value after the change in the 1·!-type impurity concentration is stabilized, even if the elapsed time is short. Become. Therefore, even after the epitaxial growth of the gate-shaped current diffusion layer 5 and the first source region 83, accurate measurement can be performed by performing acid cleaning and then measuring the 1! Becomes When performing such an acid cleaning, the type impurity concentration is measured based on the measurement method shown in FIG. 16 instead of FIG. 12 described above. That is, in steps 3200 and 3210, the same process as steps 3100 and 3110 in Fig. 12 is performed, and then in step 3220, the electronic stabilization process is performed. As an acid cleaning step. Then, in step 3230, the n-type impurity concentration of the measurement target layer is measured by the same method as in step 3130 of FIG. At this time, the time for starting the measurement of the n-type impurity concentration, that is, the elapsed time after the completion of the acid cleaning step is arbitrary, and therefore the elapsed time may be short.
[0123] （第 4実施形態） [0123] (Fourth Embodiment)
第 4実施形態について説明する。 上記第 3実施形態では、 n型層として、 门型電流分散層 5や第 1 ソース領域 8 3を例に挙げて説明したが、 エピタキ 〇 2020/175157 33 卩（：170? 2020 /005592 A fourth embodiment will be described. In the third embodiment, the n-type layer, but the门型current spreading layer 5 and the first source region 8 3 has been described by way of example, Epitaki 〇 2020/175 157 33 卩(: 170? 2020/005592
シャル成長後に〇型不純物濃度を測定する場合について、 どのような n型層 に対しても適用できる。 ここでは、 n +型基板 1の主表面上に n -型層 2をエ ピタキシャル成長させたのちに、
Figure imgf000035_0001
型層 2の n型不純物濃度を測定する場合 について説明する。 When measuring the O-type impurity concentration after char growth, it can be applied to any n- type layer. Here, after n − type layer 2 is epitaxially grown on the main surface of n + type substrate 1,
Figure imgf000035_0001
A case of measuring the n- type impurity concentration of the mold layer 2 will be described.
[0124] n -型層 2の n型不純物濃度を測定する場合には、 図 1 7に示す n型不純物 濃度の測定フローに基づいて、 1·!型不純物濃度の測定を行うことができる。 When measuring the n- type impurity concentration of the n − -type layer 2, the 1·!-type impurity concentration can be measured based on the n- type impurity concentration measurement flow shown in FIG.
[0125] まず、 図 1 7のステップ 3 3 0 0に示すように、 3 丨 〇バルク基板、 すな わち n +型基板 1 を用意する。 続いて、 ステップ 3 3 1 0に示すように、 n + 型基板 1の主表面上に 型層 2をエピタキシャル成長させる。 そして、 ステ ップ 3 3 2 0、 3 3 3 0において、 図 1 6のステップ 3 2 2 0、 3 2 3 0と 同様に酸洗浄工程を経てから〇型不純物濃度を測定する工程を行う。 [0125] First, as shown in step 3300 of Fig. 17, a 30° bulk substrate, that is, an n + type substrate 1 is prepared. Subsequently, as shown in step 3310, the mold layer 2 is epitaxially grown on the main surface of the n + -type substrate 1. Then, in steps 3320 and 3330, a step of measuring the O-type impurity concentration is performed after an acid cleaning step as in steps 3220 and 3230 of FIG.
[0126] このようにすれば、 门+型基板 1の主表面上に n -型層 2をエピタキシャル 成長させたのちに、 n -型層 2の n型不純物濃度を測定したい場合にも、 酸洗 浄を行うことで、 エピタキシャル成長後の経過時間にかかわらず精度良く 门 型不純物濃度を測定できる。 [0126] By doing so, even if it is desired to measure the n- type impurity concentration of the n- type layer 2 after the n-type layer 2 is epitaxially grown on the main surface of the + substrate 1 By performing cleaning, the concentration of the gate-type impurities can be measured accurately regardless of the elapsed time after epitaxial growth.
[0127] (他の実施形態) [0127] (Other Embodiments)
本開示は、 上記した実施形態に準拠して記述されたが、 当該実施形態に限 定されるものではなく、 様々な変形例や均等範囲内の変形をも包含する。 カロ えて、 様々な組み合わせや形態、 さらには、 それらに一要素のみ、 それ以上 、 あるいはそれ以下、 を含む他の組み合わせや形態をも、 本開示の範疇や思 想範囲に入るものである。 Although the present disclosure has been described based on the above-described embodiment, the present disclosure is not limited to the embodiment and includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and also other combinations and forms including only one element, more or less than them, are included in the scope and the scope of the present disclosure.
[0128] ( 1 ) 例えば、 上記実施形態において、 」 巳丁部 3および電界ブロック 層 4を備えると共に n型電流分散層 5を備え、 」 巳丁部 3や n型電流分散 層 5がドリフト層の一部を構成する構造としている。 しかしながら、 これは 縦型1\/1〇3 巳丁の構成の一例を挙げたに過ぎず、 J F E丁部 3および電界 ブロック層 4を備えない構造、 n型電流分散層 5を備えない構造、 もしくは 、 これら両方を備えない構造としても良い。 [0128] (1) For example, in the above-mentioned embodiment, "" the Mitsune portion 3 and the electric field blocking layer 4 and the n- type current spreading layer 5 are provided, and the "Mitsune portion 3 and the n- type current spreading layer 5 are the drift layers. The structure is a part of the. However, this is merely an example of the configuration of the vertical 1\/103 stacking structure, that is, the structure that does not include the JFE part 3 and the electric field blocking layer 4, the structure that does not include the n- type current spreading layer 5, Alternatively, the structure may not include both of them.
[0129] ( 2 ) また、 上記実施形態で示した 3 丨 <3半導体装置を構成する各部の不 〇 2020/175157 34 卩（：170? 2020 /005592 [0129] (2) In addition, 3 <3 shown in the above embodiment <3 is not included in each part of the semiconductor device. 〇 2020/175 157 34 卩(: 170? 2020/005592
純物濃度や厚み、 幅等の各種寸法については一例を示したに過ぎない。 例え ば、 第 1領域 1 0 3が第 1 ソース領域 8 3よりも深い位置まで形成されてい たり、 第 2領域 1 0匕が第 2ソース領域 8匕よりも深い位置まで形成されて いたりしても良い。 The dimensions of pure substances, thickness, width, etc. are merely examples. For example, the first region 10 3 may be formed deeper than the first source region 8 3, or the second region 10 c may be formed deeper than the second source region 8 3. Is also good.
[0130] ( 3 ) また、 上記実施形態では、 型ディープ層 9と 型連結層 1 0を別 々に構成したが、 これらを同じ 型層によって構成しても良い。 例えば、 门 型ソース領域 8の表面からノンドープ層 7や 型べース領域 6および 型電 流分散層 5を貫通して電界ブロック層 4に達するディープトレンチを形成し 、 このディープトレンチ内に埋め込まれるように 型層を形成する。 または 、 n型ソース領域 8の表面から 型不純物をイオン注入し、 ノンドープ層 7 や〇型べース領域 6および n型電流分散層 5から電界ブロック層 4に達する 型層を形成する。 これらのようにすれば、 型層によって 型ディープ層 9と 型連結層 1 0を構成することが可能となる。 [0130] (3) In the above embodiment, the mold deep layer 9 and the mold coupling layer 10 are separately configured, but they may be composed of the same mold layer. For example, a deep trench is formed from the surface of the gate type source region 8 through the non-doped layer 7, the type base region 6 and the type current distribution layer 5 to reach the electric field blocking layer 4, and is embedded in the deep trench. To form the mold layer. Alternatively, a type impurity is ion-implanted from the surface of the n-type source region 8 to form a type layer that reaches the electric field blocking layer 4 from the non-doped layer 7, the O-type base region 6 and the n- type current spreading layer 5. By doing so, it becomes possible to form the mold deep layer 9 and the mold connecting layer 10 by the mold layer.
[0131 ] ( 4 ) また、 上記実施形態では、 门型ソース領域 8を不純物濃度が異なる [0131] (4) In the above embodiment, the impurity concentration of the gate type source region 8 is different.
2つの領域、 つまり第 1 ソース領域 8 3と第 2ソース領域 8匕とに区画する 構造について説明したが、 これらが明確に区画された構造でなくても良い。 すなわち、 型ソース領域 8のうちの 型べース領域 6側がソース電極 1 5 に接触させられる表面側よりも低不純物濃度で、 かつ、 表面側がソース電極 1 5に対してオーミック接触させられる高不純物濃度とされていれば良い。 換言すれば、 第 1 ソース領域 8 3や第 2ソース領域 8匕がソース電極 1 5側 に向かって徐々に不純物濃度が高くなるように濃度勾配があっても良い。 The structure in which the two regions, that is, the first source region 83 and the second source region 8 is divided has been described, but the structure may not be clearly divided. That is, the type base region 6 side of the type source region 8 has a lower impurity concentration than the surface side contacted with the source electrode 15 and the surface side is a high impurity concentration contacted with the source electrode 15 by ohmic contact. It only has to be the concentration. In other words, there may be a concentration gradient such that the first source region 8 3 and the second source region 8 are gradually increased in impurity concentration toward the source electrode 15 side.
[0132] ( 5 ) また、 上記第 3、 第 4実施形態では、 エピタキシャル成長後に n型 不純物濃度を測定するものとして、 1·!型電流分散層 5や第 1 ソース領域 8 3 、 さらには 型層 2を例に挙げて説明した。 [0132] (5) In the third and fourth embodiments, the n-type impurity concentration is measured after the epitaxial growth by using the 1! type current spreading layer 5, the first source region 8 3, and the type layer. This is explained by taking 2 as an example.
[0133] 具体的には、 第 3実施形態では、 前に 3 丨 〇バルク基板の上にエピタキシ ャル成長層を形成した後にイオン注入工程を行い、 その後に、 測定対象層と なる门型電流分散層 5や第 1 ソース領域 8 3などの n型層を形成するように する場合を示している。 このように、 下層に形成したエピタキシャル成長層 〇 2020/175157 35 卩（：170? 2020 /005592 [0133] Specifically, in the third embodiment, the ion-implantation step was performed after the epitaxial growth layer was formed on the 3x bulk substrate, and then the gate-shaped current to be the measurement target layer was formed. shows a case that as to form an n-type layer such as distributed layer 5 and the first source region 8 3. Thus, the epitaxial growth layer formed in the lower layer 〇 2020/175 157 35 卩 (: 170? 2020 /005592
に対してイオン注入を行ったから測定対象層となる 3 丨 〇層のエピタキシャ ル成長を行うような場合に、 上記した非接触〇 V濃度評価による n型不純物 濃度の測定を行うことができる。 When the epitaxial growth of the 3 x 0 layer, which is the measurement target layer, is performed after the ion implantation, the n- type impurity concentration can be measured by the non-contact 0 V concentration evaluation described above.
[0134] また、 第 4実施形態では、 3 丨 〇バルク基板の上に測定対象層の 3 丨 〇層 となる -型層 2をエピタキシャル成長層を形成した場合を示している。 この ように、 3 丨 <3バルク基板に対して直接測定対象層のエピタキシャル成長を 行うような場合にも、 上記した非接触 0 V濃度評価による n型不純物濃度の 測定を行うことができる。 [0134] In addition, in the fourth embodiment, the case where the epitaxial growth layer is formed on the 30-bulk substrate, that is, the -type layer 2, which is the 30-layer to be measured, is shown. In this way, the n- type impurity concentration can be measured by the above-mentioned non-contact 0 V concentration evaluation even when the epitaxial growth of the layer to be measured is directly performed on the 3 <3 bulk substrate.
[0135] ( 6 ) また、 上記実施形態では、 第 1導電型を n型、 第 2導電型を 型と した门チャネルタイプの縦型1\/1〇3 巳丁を例に挙げて説明したが、 各構成 要素の導電型を反転させた チャネルタイプの縦型1\/!〇3 巳丁としても良 い。 また、 上記説明では、 半導体素子として縦型1\/1〇3 巳丁を例に挙げて 説明したが、 同様の構造の丨 ◦巳丁に対しても本開示を適用することができ る。 门チャネルタイプの I 〇巳丁の場合、 上記各実施形態に対して n +型基板 1の導電型を门型から 型に変更するだけであり、 その他の構造や製造方法 に関しては上記各実施形態と同様である。 [0135] (6) Further, in the above-described embodiment, a vertical channel type 1\/103 knives, which is an n-channel for the first conductivity type and a mold for the second conductivity type, has been described as an example. However, it is also good as a channel-type vertical type 1\/! Further, in the above description, the vertical type 1\/103 photo was taken as an example of the semiconductor element, but the present disclosure can be applied to a photo of a similar structure. In the case of the I-channel of the door channel type, the conductivity type of the n + type substrate 1 is only changed from the door type to the type in the above-mentioned respective embodiments, and other structures and manufacturing methods are the same as those in the above-mentioned respective embodiments Is the same as.

Claims

\¥0 2020/175157 36 卩（：17 2020 /005592 請求の範囲 \¥0 2020/175 157 36 (: 17 2020/005592 Claims
[請求項 1 ] 反転型の半導体素子を備えている炭化珪素半導体装置であって、 炭化珪素からなる第 1 または第 2導電型の基板 （1） と、 前記基板の上に形成され、 前記基板よりも低不純物濃度とされた第 1導電型の炭化珪素からなるドリフト層 （2、 3、 5） と、 [Claim 1] A silicon carbide semiconductor device comprising an inversion type semiconductor element, comprising: a first or second conductivity type substrate (1) made of silicon carbide; and the substrate formed on the substrate. Drift layer (2, 3, 5) made of silicon carbide of the first conductivity type with a lower impurity concentration than
前記ドリフト層の上に形成された第 2導電型の炭化珪素からなるベ —ス領域 （6） と、 A base region (6) made of silicon carbide of the second conductivity type formed on the drift layer,
前記べース領域の上に形成され、 前記ドリフト層よりも第 1導電型 不純物濃度が高くされた第 1導電型の炭化珪素からなるソース領域 （ 8） と、 A source region (8) formed on the base region, the source region being made of silicon carbide of the first conductivity type having an impurity concentration higher than that of the drift layer;
前記ソース領域の表面から前記べース領域よりも深く形成されたゲ —卜トレンチ （1 1） 内に、 該ゲートトレンチの内壁面を覆うゲート 絶縁膜 （1 2） と該ゲート絶縁膜の上に配置されたゲート電極 （1 3 ） とを備えて構成され、 一方向を長手方向として複数本がストライプ 状に並べられたトレンチゲート構造と、 A gate insulating film (1 2) covering the inner wall surface of the gate trench and a top surface of the gate insulating film are formed in a gate trench (1 1) formed deeper than the surface of the source region and deeper than the base region. A trench gate structure in which a plurality of electrodes are arranged in stripes with one direction as a longitudinal direction,
前記ゲート電極および前記ゲート絶縁膜を覆うと共にコンタクトホ —ルが形成された層間絶縁膜 （1 4） と、 An interlayer insulating film (14) on which a contact hole is formed while covering the gate electrode and the gate insulating film,
前記コンタクトホールを通じて、 前記ソース領域に才ーミック接触 させられたソース電極 （1 5） と、 A source electrode (15) in ohmic contact with the source region through the contact hole;
前記基板の裏面側に形成されたドレイン電極 （1 6） と、 を含む前 記半導体素子を備え、 A drain electrode (16) formed on the back surface side of the substrate;
前記ソース領域は、 前記べース領域側に形成されたエピタキシャル 成長層によって構成されている第 1 ソース領域 （8 3） と、 前記ソー ス電極に接すると共に前記第 1 ソース領域よりも第 1導電型不純物濃 度が高くされたイオン注入層によって構成されている第 2ソース領域 （8匕） と、 を有している炭化珪素半導体装置。 The source region is in contact with the source electrode and has a first conductivity region higher than that of the first source region (83) formed of an epitaxial growth layer formed on the base region side. A silicon carbide semiconductor device having: a second source region (8 wells) composed of an ion-implanted layer having a high type impurity concentration.
[請求項 2] 前記第 1 ソース領域は、 厚さが〇. 2〜〇. 5 とされ、 不純物 濃度が 2 . 0 1 0 1 6 ~ 1 . 0 1 0 1 7/〇〇1 3とされ、 〇 2020/175157 37 卩（：170? 2020 /005592 [Claim 2] The first source region is thick and 〇. 2～〇. 5, the impurity concentration is set to 2. 0 1 0 1 6 to 1.0 1 0 1 7 / Rei_rei_1 3 , 〇 2020/175 157 37 卩(: 170? 2020/005592
前記第 2ソース領域は、 厚さが〇. 1 以上とされていると共に 、 第 2導電型不純物濃度が 1. 0X 1 018〜 5. 0x 1 019/0 0^ とされている請求項 1 に記載の炭化珪素半導体装置。 The second source region, as well there is a thickness 〇. 1 above, the second conductivity type impurity concentration 1. 0X 1 018~ 5. 0x 1 019 /0 0 ^ and has been being claim 1 The silicon carbide semiconductor device described.
[請求項 3] 前記べース領域と前記ソース領域との間には、 厚さが〇. 05〜〇 [Claim 3] The thickness between the base region and the source region is 0.05 to 0.
. 2 とされ、 キャリア濃度が 1. 0 1 016/〇〇13以下とされ たノンドープ層 （7） が備えられている請求項 1 または 2に記載の炭 化珪素半導体装置。 3. The silicon carbide semiconductor device according to claim 1 or 2, further comprising a non-doped layer (7) having a carrier concentration of 1.01 0 16 /○ 0 13 or less.
[請求項 4] 前記ゲートトレンチは、 前記第 2ソース領域と対応する部分におい て丸みを有して傾斜している請求項 1ないし 3のいずれか 1つに記載 の炭化珪素半導体装置。 4. The silicon carbide semiconductor device according to claim 1, wherein the gate trench is rounded and inclined at a portion corresponding to the second source region.
[請求項 5] 反転型の半導体素子を備えた炭化珪素半導体装置の製造方法であっ て、 [Claim 5] A method for manufacturing a silicon carbide semiconductor device including an inversion-type semiconductor element, comprising:
炭化珪素からなる第 1 または第 2導電型の基板 （ 1） を用意するこ とと、 Preparing a first or second conductivity type substrate (1) made of silicon carbide,
前記基板の上に、 前記基板よりも低不純物濃度の第 1導電型の炭化 珪素からなるドリフト層 （2、 3、 5） を形成することと、 Forming on the substrate a drift layer (2, 3, 5) made of a first conductivity type silicon carbide having an impurity concentration lower than that of the substrate;
前記ドリフト層の上に、 第 2導電型の炭化珪素からなるベース領域 （6） を形成することと、 Forming a base region (6) of second conductivity type silicon carbide on the drift layer;
前記べース領域の上に、 前記ドリフト層よりも第 1導電型不純物濃 度が高くされた第 1導電型の炭化珪素からなり、 前記べース領域側に 配置される第 1 ソース領域 （83） と該第 1 ソース領域の上に該第 1 ソース領域よりも高不純物濃度とされた第 2ソース領域 （813） とを 有するソース領域 （8） を形成することと、 A first source region formed on the base region, the first source region being made of first conductivity type silicon carbide having a first conductivity type impurity concentration higher than that of the drift layer; 83) and a second source region (813) having an impurity concentration higher than that of the first source region, the source region (8) being formed on the first source region.
前記ソース領域の表面から前記べース領域よりも深いゲートトレン チ （1 1） を、 一方向を長手方向としてストライプ状に複数本形成し たのち、 前記ゲートトレンチの内壁面にゲート絶縁膜 （1 2） を形成 すると共に、 前記ゲート絶縁膜の上にゲート電極 （1 3） を形成する ことでトレンチゲート構造を形成することと、 〇 2020/175157 38 卩（：170? 2020 /005592 After forming a plurality of gate trenches (11) deeper than the surface of the source region in a stripe shape with one direction being the longitudinal direction, a gate insulating film (11) is formed on the inner wall surface of the gate trench. Forming a trench gate structure by forming a gate electrode (1 3) on the gate insulating film, and forming a trench gate structure. 〇 2020/175 157 38 卩 (: 170? 2020 /005592
前記ソース領域に電気的に接続されるソース電極 （1 5） を形成す ることと、 Forming a source electrode (15) electrically connected to the source region;
前記基板の裏面側にドレイン電極 （1 6） を形成することと、 を含 み、 Forming a drain electrode (16) on the back surface side of the substrate,
前記べース領域を形成することでは、 前記べース領域をエピタキシ ャル成長によって形成し、 Forming the base region includes forming the base region by epitaxial growth,
前記ソース領域を形成することでは、 前記第 1 ソース領域をエピタ キシャル成長によって形成したのち、 前記第 1 ソース領域に対して第 1導電型不純物をイオン注入することで前記第 2ソース領域を形成す る炭化珪素半導体装置の製造方法。 In forming the source region, the first source region is formed by epitaxial growth, and then the second source region is formed by ion-implanting a first conductivity type impurity into the first source region. A method for manufacturing a silicon carbide semiconductor device.
[請求項 6] 前記べース領域を形成すること、 および、 前記ソース領域を形成す ることの間に、 炭化珪素で構成されるノンドープ層 （7） を形成する ことを含んでいる請求項 5に記載の炭化珪素半導体装置の製造方法。 6. A non-doped layer (7) composed of silicon carbide is formed between forming the base region and forming the source region. 5. A method for manufacturing a silicon carbide semiconductor device according to 5.
[請求項 7] 前記べース領域を形成することと前記ノンドープ層を形成すること とは、 同じエピタキシャル成長装置内において、 温度を維持したまま 連続的に行われる請求項 6に記載の炭化珪素半導体装置の製造方法。 7. The silicon carbide semiconductor according to claim 6, wherein the forming of the base region and the forming of the non-doped layer are continuously performed in the same epitaxial growth apparatus while maintaining a temperature. Device manufacturing method.
[請求項 8] 前記べース領域を形成することから前記第 1 ソース領域を形成する ことまでは、 同じエピタキシャル成長装置内において、 温度を維持し たまま連続的に行われる請求項 6または 7に記載の炭化挂素半導体装 置の製造方法。 [Claim 8] The process from the formation of the base region to the formation of the first source region is continuously performed in the same epitaxial growth apparatus while maintaining the temperature. A method for manufacturing the described silicon carbide semiconductor device.
[請求項 9] 測定対象層となる n型の炭化珪素層 （2、 5、 8a） をエピタキシ ャル成長させることと、 [Claim 9] epitaxially growing an n-type silicon carbide layer (2, 5, 8a) to be measured,
前記炭化珪素層をエピタキシャル成長させたのちに、 前記炭化珪素 層の表面電子を安定化させることと、 Stabilizing the surface electrons of the silicon carbide layer after epitaxially growing the silicon carbide layer;
前記表面電子の安定化後に、 電荷を塗布して前記炭化珪素層の表面 を帯電させたのち、 前記炭化珪素層の表面電位を測定することによっ て該炭化珪素層の〇型不純物濃度を測定することと、 を含む炭化珪素 半導体装置の製造方法。 〇 2020/175157 39 卩（：170? 2020 /005592 After stabilizing the surface electrons, a charge is applied to charge the surface of the silicon carbide layer, and then the surface potential of the silicon carbide layer is measured to measure the O-type impurity concentration of the silicon carbide layer. And a method for manufacturing a silicon carbide semiconductor device, comprising: 〇 2020/175 157 39 卩(: 170? 2020/005592
[請求項 10] 前記炭化珪素層の表面電子を安定化させることは、 前記炭化珪素層 を形成したのち、 大気雰囲気下において 1 0時間以上保持することで ある、 請求項 9に記載の炭化珪素半導体装置の製造方法。 10. The silicon carbide according to claim 9, wherein stabilizing the surface electrons of the silicon carbide layer is to hold the silicon carbide layer for 10 hours or more in an air atmosphere after forming the silicon carbide layer. Method of manufacturing semiconductor device.
[請求項 1 1 ] 前記炭化珪素層の表面電子を安定化させることは、 前記炭化珪素層 を形成したのち、 該炭化珪素層の表面を酸洗浄することである、 請求 項 9に記載の炭化珪素半導体装置の製造方法。 [Claim 11] Stabilizing the surface electrons of the silicon carbide layer is to form the silicon carbide layer and then acid-clean the surface of the silicon carbide layer. Method of manufacturing silicon semiconductor device.
[請求項 12] 前記酸洗浄することは、 塩酸過酸化水素水溶液、 硫酸過酸化水素水 溶液、 オゾン洗浄のいずれか 1つを用いた洗浄である、 請求項 1 1 に 記載の炭化珪素半導体装置の製造方法。 12. The silicon carbide semiconductor device according to claim 11, wherein the acid cleaning is cleaning using any one of a hydrochloric acid/hydrogen peroxide solution, a sulfuric acid/hydrogen peroxide solution, and ozone cleaning. Manufacturing method.
[請求項 13] 炭化珪素バルク基板 （1） の上に、 门型層 （2） をエピタキシャル 成長させることを含み、 [Claim 13] comprising epitaxially growing a gate layer (2) on a silicon carbide bulk substrate (1),
前記炭化珪素層の表面電子を安定化させることは、 前記〇型層を前 記炭化珪素層として、 該n型層の表面電子を安定化させることであり 前記 n型不純物濃度を測定することは、 前記 n型層の n型不純物濃 度を測定することである、 請求項 9ないし 1 2のいずれか 1つに記載 の炭化珪素半導体装置の製造方法。 Stabilizing the surface electrons of the silicon carbide layer is stabilizing the surface electrons of the n-type layer by using the O-type layer as the silicon carbide layer described above, and measuring the n-type impurity concentration is The method for manufacturing a silicon carbide semiconductor device according to claim 9, wherein the n- type impurity concentration of the n-type layer is measured.
[請求項 14] 炭化珪素バルク基板 （1） の上に、 エピタキシャル成長層 （3） を 形成することと、 [Claim 14] forming an epitaxial growth layer (3) on a silicon carbide bulk substrate (1),
前記エピタキシャル成長層に対して不純物のイオン注入を行って不 純物層 （4） を形成することと、 Forming an impurity layer (4) by ion-implanting impurities into the epitaxial growth layer;
前記エピタキシャル成長層および前記不純物層の上に、 1·!型層 （8 3） をエピタキシャル成長させることを含み、 Comprising epitaxially growing a 1! type layer (83) on the epitaxial growth layer and the impurity layer,
前記炭化珪素層の表面電子を安定化させることは、 前記〇型層を前 記炭化珪素層として、 該n型層の表面電子を安定化させることであり 前記 n型不純物濃度を測定することは、 前記 n型層の n型不純物濃 度を測定することである、 請求項 9ないし 1 2のいずれか 1つに記載 \¥0 2020/175157 40 卩（：17 2020 /005592 Stabilizing the surface electrons of the silicon carbide layer is stabilizing the surface electrons of the n-type layer by using the O-type layer as the silicon carbide layer described above, and measuring the n-type impurity concentration is Measuring the n- type impurity concentration of the n-type layer, The method according to any one of claims 9 to 12. \¥0 2020/175 157 40 卩 (: 17 2020 /005592
の炭化珪素半導体装置の製造方法。 Manufacturing method of the silicon carbide semiconductor device.
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