WO2020175157A1 - Dispositif à semi-conducteur au carbure de silicium et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur au carbure de silicium et son procédé de fabrication Download PDF

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Publication number
WO2020175157A1
WO2020175157A1 PCT/JP2020/005592 JP2020005592W WO2020175157A1 WO 2020175157 A1 WO2020175157 A1 WO 2020175157A1 JP 2020005592 W JP2020005592 W JP 2020005592W WO 2020175157 A1 WO2020175157 A1 WO 2020175157A1
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Prior art keywords
layer
type
source region
silicon carbide
impurity concentration
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PCT/JP2020/005592
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English (en)
Japanese (ja)
Inventor
竹内　有一
鈴木　克己
侑佑 山下
武寛 加藤
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株式会社デンソー
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Priority claimed from JP2020008376A external-priority patent/JP7140148B2/ja
Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Priority to CN202080016354.9A priority Critical patent/CN113498544B/zh
Priority to CN202311330705.5A priority patent/CN117276345A/zh
Publication of WO2020175157A1 publication Critical patent/WO2020175157A1/fr
Priority to US17/410,044 priority patent/US12057498B2/en

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    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/781—Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
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Definitions

  • the present disclosure relates to a semiconductor device having a semiconductor element having a 1 ⁇ /103 structure composed of silicon carbide (hereinafter referred to as "3 (3)") ⁇ 3 ⁇ 3 and a manufacturing method thereof.
  • a 3 ⁇ 3 semiconductor device having a wrench gate structure.
  • a type base region and an n + type source region are formed in order on the gate type drift layer, and the + type source region penetrates the type base region from the surface of the type source region.
  • the trench gate is formed so as to reach the type drift layer.
  • a type base region is epitaxially grown on the n-type drift layer, and then a 1! type impurity is ion-implanted into the type base region to implant a part of the type base region.
  • a 1! type impurity is ion-implanted into the type base region to implant a part of the type base region.
  • Patent Document 1 International Publication No. 2 0 1 6/0 6 3 6 4 4 Panfret
  • the film thickness variation during epitaxial growth increases as the film thickness grown increases, but the variation in the range of ion implantation is not so large, so the film thickness of the mold base region after ion implantation is small.
  • the variation corresponds to the thickness of the epitaxially grown film. Therefore, when the + type source region is formed by ion implantation with respect to the type base region, the variation in the thickness of the + type source region is small and the variation in the thickness of the type base region is large. Therefore, there is the problem of causing variations in the threshold V I.
  • the side surface of the trench gate is inclined when the trench gate is formed due to the influence of damage at the time of ion implantation. Therefore, there is a problem that the channel mobility is lowered and the trench gate is widened at the trench entrance side, which makes it difficult to miniaturize the device.
  • the inventors of the present invention examined formation of not only the type base region but also the gate + type source region by epitaxial growth. By doing so, the variation in thickness is distributed to each of the mold base region and the gate + type source region, so that it is possible to reduce the variation in thickness of the mold base region.
  • the gate + type source region it is necessary to introduce a high concentration of the n-type dopant gas into the epitaxial growth apparatus, and even after the formation of the n + type source region, the n-type dopant region is formed in the epitaxial growth apparatus. Remains and the growth reactor is contaminated. As a result, when the mold layer or the gate-shaped layer is subsequently formed, dopant contamination occurs and the control of the impurity concentration becomes unstable.
  • the present disclosure provides a 3-0 semiconductor device having a structure capable of improving the short-circuit withstand capability, suppressing the variation of the threshold V 1 and suppressing the inclination of the side surface of the trench gate, and easily controlling the impurity concentration, and a manufacturing method thereof. With the goal.
  • a semiconductor device is a substrate of the first or second conductivity type composed of 300, and is formed on a substrate and has an impurity concentration lower than that of the substrate. And a drift layer made of the first conductivity type 3 ⁇ and formed on the drift layer. ⁇ 2020/175157 3 (: 170? 2020/005592
  • the trench gate structure is composed of a plurality of lines arranged in stripes with one direction as the longitudinal direction, the interlayer insulating film that covers the gate electrode and the gate insulating film and the contact hole is formed, and the source region through the contact hole.
  • the semiconductor device includes a source electrode in ohmic contact and a drain electrode formed on the back surface side of the substrate, and the source region is composed of an epitaxial growth layer formed on the base region side.
  • the source region is composed of the first source region having a relatively low concentration and the second source region having a higher concentration. Then, the first source region is formed by epitaxial growth, and the second source region is formed by ion implantation. For this reason, it is possible to improve the short-circuit resistance, suppress the variation of the threshold value VI and suppress the inclination of the side surface of the trench gate, and make it possible to provide a semiconductor device with a structure of 3 ⁇ 3 semiconductor having a structure capable of easily managing the impurity concentration. Become.
  • Another aspect of the present disclosure relates to a method for manufacturing a 300 semiconductor device according to the above-described one aspect of the present disclosure.
  • a substrate of the first or second conductivity type consisting of 300 is prepared, and a substrate of the first conductivity type having a lower impurity concentration than the substrate (from 3 Of the first conductive layer over the drift layer and the base region of the second-conductivity type 300 made on the drift layer.
  • the first source region is formed on the first source region of the third conductivity type having a high impurity concentration, and is disposed on the base region side, and the first source region is formed on the first source region.
  • a source region having a second source region with a higher impurity concentration Forming a source region having a second source region with a higher impurity concentration, and forming a plurality of gate trenches deeper than the base region from the surface of the source region in stripes with one direction as the longitudinal direction.
  • a gate insulating film is formed on the inner wall surface of the gate trench
  • a trench gate structure is formed by forming a gate electrode on the gate insulating film, and a source electrode electrically connected to the source region is formed. And forming a drain electrode on the back surface side of the substrate.
  • the base region By forming the base region, the base region is formed by epitaxial growth, and by forming the source region, the first source region is formed.
  • the second source region is formed by ion-implanting the first conductivity type impurity into the first source region.
  • the first source region is formed by epitaxial growth, and the second source region is formed by ion implantation.
  • the short-circuit withstand capability can be improved, variations in the threshold V 1 and the inclination of the side surface of the trench gate can be suppressed, and the 3D (3 semiconductor device) structure can be manufactured in which the impurity concentration can be easily controlled.
  • a method of manufacturing a 3 ⁇ 3 semiconductor device includes a method of epitaxially growing 3 ⁇ 3 layers of a type that is a layer to be measured, and a 3 I 0 layer after epitaxial growth.
  • the surface electrons of the 3.0 layer are stabilized, and after stabilizing the surface electrons, a charge is applied to charge the surface of the 3.0 layer and then the surface potential of the 3.0 layer is changed. Measuring the concentration of n-type impurities in the 30 layer by measuring.
  • the surface potential of the 300 layer is measured. This makes it possible to accurately measure the n-type impurity concentration of the 300 layer.
  • FIG. 3 is a cross-sectional view of a 3 ⁇ 3 semiconductor device according to the first embodiment.
  • Fig. 2 is a perspective cross-sectional view of the three semiconductor devices shown in Fig. 1.
  • Fig. 3 is a diagram showing the results of an electron current density simulation conducted when the concentration of the entire source region is high.
  • Fig. 4 is a diagram showing the result of examination by simulation of electron current densities when the n- type source region is composed of a first source region and a second source region.
  • FIG. 5 is a diagram showing the results of examining changes in drain current by simulation while changing the impurity concentration in the first source region.
  • Fig. 6 is a diagram showing the results of a simulation study on the relationship between the on-resistance and the type impurity concentration of the first source region.
  • FIG. 7 is a perspective sectional view showing a manufacturing process of the semiconductor device 3 ⁇ 3 shown in Fig. 1.
  • FIG. 78 is a perspective cross-sectional view showing the manufacturing process of the semiconductor device 3 ⁇ 3 following FIG. 7
  • FIG. 7(:] is a perspective sectional view showing the manufacturing process of the semiconductor device 3 ⁇ 3 following FIG.
  • Fig. 7 ( 3 3 ⁇ 3 is a perspective cross-sectional view showing the manufacturing process of the semiconductor device
  • Fig. 70 is a perspective cross-sectional view showing the manufacturing process of a semiconductor device 3 ⁇ 3
  • FIG. 7C is a perspective sectional view showing the manufacturing process of the semiconductor device 3 ⁇ 3 following FIG.
  • Fig. 70 is a perspective cross-sectional view showing the manufacturing process of a semiconductor device 3 ⁇ 3 following FIG.
  • FIG. 8 A cross-sectional view of a 3 ⁇ 3 semiconductor device according to a second embodiment.
  • FIG. 9 is a diagram showing the results of examining the voltage distribution during reverse conduction when the entire region of the ⁇ -type source region has a high impurity concentration.
  • FIG. 6 is a diagram showing a result of examining a voltage distribution during reverse conduction.
  • Fig. 11 shows the results of examining the voltage distribution during reverse conduction in the case where the non-doped layer was provided.
  • FIG. 12 is a diagram showing a measurement flow of the n- type impurity concentration described in the third embodiment.
  • FIG. 13 is a perspective view showing how to measure the n- type impurity concentration described in the third embodiment.
  • Fig. 14 is a diagram showing the relationship between the exposure time to the atmosphere after the epitaxial growth of the mold layer and the measurement result of the concentration of the gate type.
  • FIG. 15 is a diagram showing the relationship between the density evaluation values before and after the 1 to 1 treatments.
  • FIG. 16 is a diagram showing a measurement flow of n- type impurity concentration described as another example of the third embodiment.
  • FIG. 17 is a diagram showing a measurement flow of n- type impurity concentration described in the fourth embodiment.
  • the first embodiment will be described.
  • an inverted vertical 1 ⁇ /103 stacking trench gate structure shown in FIGS. 1 and 2 is formed as a semiconductor element.
  • the vertical type 1 ⁇ / 1 0 3 mats shown in these figures are formed in the cell region of the semiconductor device of 3 ⁇ 3 semiconductor devices, and the outer peripheral withstand voltage structure is formed so as to surround the cell region.
  • 3 ⁇ 3 semiconductor devices are constructed, but only the vertical type 1 ⁇ /103 is shown here.
  • the vertical 1 ⁇ /1 ⁇ 3 mending machine intersects the width direction of the vertical 1 ⁇ /1 ⁇ 3 mending machine in the X direction and the X direction.
  • the depth direction of the vertical direction is the thickness direction or the depth direction of the vertical 1 ⁇ /1 ⁇ 3 knife, that is, the direction normal to the flat surface. ⁇ 2020/175 157 7 ⁇ (: 170? 2020 /005592
  • a 3+ semiconductor device uses a ++ type substrate 1 made of 300 as a semiconductor substrate.
  • an n ⁇ type layer 2 of 3 ⁇ 3 is formed on the main surface of the n+ type substrate 1.
  • the surface of the door + type substrate 1 is a (0 001) 3 surface, for example, the n-type impurity concentration is 5.9 1 0 18 / ⁇ , and the thickness is 100 °.
  • an n-type impurity concentration is set to 7. 0 1 0 15 ⁇ 2 0 X 1 0 16 / Rei_rei_1 3, the thickness is the 8 ⁇ .
  • n-type layer 2 On top of the n-type layer 2, there are 3 parts.” The part 3 and the electric field blocking layer 4 are formed, and the n-type layer 2 is located away from the n+ type substrate 1. At “”, it is connected to Mitsube Department 3.
  • the JFE section 3 and the electric field blocking layer 4 compose a saturation current suppressing layer, and both extend in the X direction and are alternately arranged in the vertical direction.
  • at least a part of the Ming part 3 and the electric field blocking layer 4 are respectively formed into a plurality of strips, that is, stripes, and are alternately arranged. It is said to be a side-by-side layout.
  • Each part of the striped portion of the Mending part 3, that is, each strip-shaped part has a width of, for example, 0.25, and a pitch of forming intervals is, for example, 0.6 to 2.
  • the thickness of the n-type layer is, for example, 1.5, and the n-type impurity concentration is set higher than that of the n-type layer 2, for example, 5.0 1 0 16 to 2.0 X 10 18 / ⁇ there is a 1 3.
  • the electric field blocking layer 4 is composed of a type impurity layer. I mentioned above ⁇ 2020/175 157 8 ⁇ (: 170? 2020 /005592
  • the electric field blocking layer 4 has a striped shape, and each strip-shaped portion of the striped electric field blocking layer 4 has a width of, for example, 0.15 and a thickness of, for example, 1.4. There is. Further, the electric field blocking layer 4 has, for example, a type impurity concentration of 3.0 X 1017 to 1. In the case of the present embodiment, the electric field blocking layer 4 has a constant type impurity concentration in the depth direction. The surface of the electric field blocking layer 4 opposite to the n ⁇ -type layer 2 is flush with the surface of the Mending part 3.
  • a closed type current spreading layer 5 made of 300 is formed on the Mending part 3 and the electric field blocking layer 4, a closed type current spreading layer 5 made of 300 is formed.
  • the n-type current distribution layer 5 is a layer that allows the current flowing through the channel to diffuse in the X direction, as will be described later.
  • the n- type impurity concentration is higher than that of the mold layer 2.
  • the gate-type current spreading layer 5 is extended in the direction of the bird's eye, and has the n-type impurity concentration equal to or higher than that of the Mitsube part 3, for example, a thickness of 0.5. Has been done.
  • the drift layer is referred to as a mold layer 2 for convenience sake.
  • the part 3 and the gate-type current spreading layer 5 are described separately, but these are both parts that form the drift layer and are connected to each other.
  • n-type current spreading layer 5 On the n-type current spreading layer 5, a type base region 6 of 300 is formed. A mold source region 8 is formed on the mold base region 6. The n- type source region 8 is formed on a portion of the type base region 6 corresponding to the n- type current spreading layer 5.
  • the type base region 6 is thinner than the electric field blocking layer 4 and has a low concentration of type impurities.
  • the type impurity concentration is 3 X 1 0 1 7/0 3. It is said that the thickness is from 0.4 to 0.60!
  • the n-type source region 8 has a structure in which the O-type impurity concentration is different between the type base region 6 side and the opposite side, that is, the element surface side. Specifically, the n- type source region 8 includes a first source region 8 3 arranged on the side of the type base region 6 and a second source region 8 3 arranged on the device surface side. It is said that. ⁇ 2020/175 157 9 (: 170? 2020/005592
  • the first source region 8 3 has a lower n- type impurity concentration than the second source region 8 13 and is composed of an epitaxial growth layer. Borders area 6.
  • the first source region 8 3, for example, n-type non-pure concentration is between 2. 0 X 1 0 ⁇ 1. ⁇ X 1 ⁇ 1 ⁇ / hundred 1 3 or less, a thickness ⁇ .
  • It is set to 2 to 0. 05 01, preferably 0. 3 0! or more.
  • the second source region 8 13 is a region for making contact with a source electrode 15 to be described later, and is composed of an ion-implanted layer, and has a high concentration of 1 ⁇ !-type impurities. There is. Second source region 8 spoon, for example n-type impurity concentration is set to 1. 0 X 1 0 1 8 ⁇ 5. 0 X 1 0 1 9 / Rei_rei_1 3, is the thickness ⁇ . 1 ⁇ . 2 ing.
  • the mold current distribution The mold deep layer 9 is formed in a portion where the layer 5 is not formed.
  • the mold deep layer 9 is a strip-shaped portion in which the striped portion of the Mending part 3 and the longitudinal direction of the electric field blocking layer 4 are crossed. It is laid out in stripes by arranging multiple lines in the X direction. Through the mold deep layer 9, the mold base region 6 and the electric field blocking layer 4 are electrically connected.
  • the formation pitch of the type deep layer 9 is matched with the cell pitch which is the formation interval of the trench gate structure described later, and the type deep layer 9 is arranged between the adjacent trench gate structures.
  • a trench gate structure is formed on the type base region 6 at a position corresponding to the type deep layer 9, that is, at a position different from the n-type source region 8 with the n-type source region 8 interposed therebetween.
  • the mold connecting layer 10 is formed at a position on the opposite side.
  • the mold connection layer 10 is a layer for electrically connecting by connecting the mold base region 6 and a source electrode 15 described later.
  • the type coupling layer 10 has a structure in which the type impurity concentration is different between the type base region 6 side and the opposite side, that is, the element surface side.
  • the mold connecting layer 10 is a mold base. ⁇ 2020/175 157 10 ⁇ (: 170? 2020 /005592
  • the carrier concentration that is, the type impurity concentration of the portion functioning as a carrier, is 2.0X10. 17 to 1. are set to be 0 X 1 0 19 / ⁇ 3.
  • the second region 10 ⁇ is a region having a depth similar to that of the second source region 8 ⁇ , and is a region for making contact with a source electrode 15 described later, and has a high concentration of type impurities.
  • the second region 1 ⁇ spoon, for example the type impurity concentration 2. is a ⁇ 1 018 ⁇ 1. 0x 1 020/0 01 3, thickness ⁇ . 2 ⁇ . 3 ⁇ ! As being.
  • the carrier concentration that is, the type impurity concentration of the portion functioning as a carrier is 2.
  • 0 1 Rei_18 ⁇ are to 1. so that 0X 1 020 / ⁇ 01 3.
  • the type coupling layer 10 is formed by ion implantation of type impurities into the n-type source region 8.
  • the type impurity concentration of the first region 1 and the second region 1013 means the concentration of the type impurities that function as carriers. Some of the type impurities are canceled with the type impurities contained in the first source region 83 before the implantation and do not function as carriers. Therefore, when forming the type coupling layer 10 by ion implantation, taking into account the activation rate, for example, a dose amount that is 2 to 10 times the type impurity concentration of the first source region 8 3 and the second source region 813. By injecting the type impurities with, the above type impurity concentration can be obtained.
  • n- type source region 8 and the type base region 6 are penetrated and an n- type current component is ⁇ 2020/175 157 1 1 ⁇ (: 170? 2020/005592
  • the gate wrench is deeper than the total thickness of the base region 6 and the gate source region 8 by a depth of 0.4 to reach 0.4, for example, to reach the diffusion layer 5.
  • the above-mentioned type base region 6 and n-type source region 8 are arranged so as to be in contact with the side surface of the gate trench 11.
  • the gate trench 11 has a width direction in the X direction in FIG. 2 and a direction intersecting the longitudinal direction of the Mending part 3 and the electric field block layer 4, here, a strip shape with the longitudinal direction as the longitudinal direction and the direction as the depth direction. It is formed with the layout of. Although not shown in FIGS.
  • the gate trenches 11 are in the form of stripes in which a plurality of gate trenches 11 are arranged at equal intervals in the X direction, and a type base region 6 is provided between them. A type source area 8 is placed. Further, the mold deep layer 9 and the mold coupling layer 10 are arranged at the intermediate position of each gate trench 11.
  • the type base region 6 is located between the n- type source region 8 and the n- type current spreading layer 5 during the operation of the vertical type 1 ⁇ /1 ⁇ 3.
  • Form a channel region that connects The inner wall surface of the gate trench 11 including the channel region is covered with the gate insulating film 12.
  • a gate electrode 13 composed of doped ⁇ 7-3I, and the inside of the gate trench 11 is filled with these gate insulating film 12 and gate electrode 13.
  • the trench gate structure is constructed.
  • the side walls of the gate trench 11 are substantially parallel to each other, and are rounded and inclined at the entrance side of the opening so that the opening width is slightly wider than the bottom. Has become. More specifically, the part of the side wall of the gate trench 11 that is in contact with the first source region 8 3 and the type base region 6 and the n-type current spreading layer 5 is almost parallel to the direction, and the second source region 8 3 The part in contact with the swallow is rounded and inclined.
  • an interlayer insulating film is formed on the surface of the n-type source region 8 and the surface of the gate electrode 13.
  • a source electrode 15 and a gate wiring layer are formed via 14.
  • the source electrode 15 and the gate wiring layer are composed of a plurality of metals, for example, I/I. At least 3 types of metal (3, ⁇ 2020/175 157 12 (: 170? 2020/005592
  • the part in contact with the n-type source region 8 is composed of a metal capable of ohmic contact with n-type 3 ⁇ 3.
  • at least the part of the plurality of metals that is in contact with the mold 3, specifically the second region 10 is made of a metal that is capable of ohmic contact with the mold 3 ⁇ 3.
  • the source electrode 15 is formed on the interlayer insulating film 14 and is electrically insulated from the part of the source electrode 30, the source electrode 15 is formed on the interlayer insulating film 14 through the contact hole formed in the interlayer insulating film 14. 8 and the mold deep layer 9 are in electrical contact.
  • a drain electrode 16 electrically connected to the n + type substrate 1 is formed on the back surface side of the n + type substrate 1.
  • a vertical 1/3 of a channel-type inverted trench gate structure is constructed.
  • a cell area is constructed by arranging multiple cells of such vertical type 1/103.
  • a 3 10 semiconductor device is formed by forming an outer periphery withstand voltage structure by a guard ring or the like (not shown) so as to surround the cell region in which such a vertical type 1/103 is formed. ..
  • a semiconductor device having a vertical type 1// 1 0 3 sets of 3 ⁇ 3 semiconductor devices has a source voltage 3 of 0 and a drain voltage V of 1 to 1.5 V, for example. In this state, it is operated by applying a gate voltage V 9 of 20 V to the gate electrode 13.
  • the vertical type 1//103 has a channel region formed in the type base region 6 which is in contact with the gate trench 11 when the gate voltage V 9 is applied. As a result, conduction is established between the gate type source region 8 and the n type current spreading layer 5.
  • the vertical IV! ⁇ 3 ⁇ is from the n + -type substrate 1 to the n _ -type layer 2 through the drift layer composed of the ⁇ section 3 and the n- type current spreading layer 5 From the region through the 1! type source region 8, an operation is performed in which a current flows between the drain and the source.
  • the vertical type 1//1 03 ken in such a semiconductor device is applied to an inverter circuit or the like provided with an upper arm and a lower arm
  • the vertical type 1//1 003 The parasitic diode built into the circuit works as a freewheeling diode.
  • the gate-type layer forming the drift layer such as the n ⁇ -type layer 2, the electric field blocking layer 4, and the type base region 6 are also included. ⁇ 2020/175 157 13 ⁇ (: 170? 2020 /005592
  • a parasitic diode is formed by a 1 ⁇ 1 junction with the type layer including the type deep layer 9, and this acts as a freewheeling diode.
  • the inverter circuit and the like are used when supplying an alternating current to a load such as an AC motor while using a DC power supply.
  • a load such as an AC motor
  • a DC power supply for example, in an inverter circuit or the like, a plurality of bridge circuits in which an upper arm and a lower arm are connected in series are connected in parallel to a DC power supply, and the upper arm and lower arm of each bridge circuit are alternately turned on and off repeatedly to load An alternating current is supplied to it.
  • each bridge circuit such as an inverter circuit
  • a load is generated by turning on the vertical IV! Current is supplied to. After that, turn off the vertical type 1 ⁇ /1 03 of the upper arm and turn on the vertical type
  • the parasitic diode provided in the vertical IV! The reverse conduction is performed by flowing the current between the source and the drain. In this way, the AC drive of the load is performed by the inverter circuit or the like.
  • a voltage of 120 V or higher is applied to the drain as the drain-source voltage 3.
  • the entire area of the gate-type source region 8 is composed of a high-concentration n-type impurity layer, the saturation current value at the time of load short-circuit becomes large, and it becomes impossible to obtain the short-circuit withstand capability of the semiconductor device. .. This is presumably because the 1! type source region 8 has a high concentration, so that a depleted region hardly occurs and the current flows in the entire region of the type source region 8.
  • the n-type source region 8 has a relatively low concentration of the first source region 8 3 and the second source region 8 has a higher concentration than that. It is possible to reduce the saturation current value when the load is short-circuited, because it is composed of 13 and 13. This is because the first source region 8 3 has a low concentration, so Depletion so that it enters the wide area of 8 3 ⁇ 2020/175 157 14 ⁇ (: 170? 2020 /005592
  • the source voltage 3 is 0, the gate voltage 9 is 20 and the drain voltage is 75 0.
  • the concentration of the gate-shaped impurity in the entire gate-shaped source region 8 is 1.
  • the gate type source region 8 is composed of the first source region 8 3 and the second source region 8 13 while the type impurity concentration of the first source region 8 3 is 1.0 1 0. and 1 6 / Rei_rei_1 3, and the ⁇ impurity concentration of the second source region 8 1_Rei and 1. 0 X 1 0 1 9 / Rei_rei_1 3.
  • the type source region 8 is composed of the first source region 8 3 and the second source region 8 13 while the type impurity concentration of the second source region 8 10 is 1.0 X 1 Then, the type impurity concentration of the first source region 83 is changed.
  • the electron current density in the first source region 8 3 is You can see that it is getting smaller. This is because the first source area 8 3 ⁇ 2020/175 157 15 ⁇ (: 170? 2020/005592
  • depletion occurs so that it enters the wide area of the first source region 8 3 and current does not flow in the depleted portion.
  • the saturation current value at the time of load short-circuiting can be reduced by using the third and second source regions 813. Therefore, it can be understood that the structure of this embodiment can improve the short-circuit withstand capability of the semiconductor device (3 semiconductor devices).
  • the drain current during the load short circuit if to be 1 4 0 0 0 / ⁇ 2 or less, it is possible to obtain the desired short-circuit tolerance.
  • the drain current at the time of load short-circuiting is 1400 0.88/ ⁇ 2 or less when the n-type impurity concentration of the first source region 8 a is 1.0 X 10 It is the case when it becomes 1 7 / ⁇ 3 or less. Therefore, the n- type impurity concentration of the first source region 8a is set to 1.0 1 0 1 7 / ⁇ as in the 3 semiconductor device of this embodiment. By setting the following, it becomes possible to improve the short circuit withstand capability.
  • n-type impurity concentration of the first source region 83 is too low, the resistance value of the first source region 83 becomes too large and the on-resistance ⁇ n is increased.
  • the results shown in Fig. 6 were obtained. 3 ⁇ Considering the high-speed switching operation of semiconductor devices, the on resistance ⁇ ! The following is preferable. According to the results of FIG. 6, but n-type impurity concentration of the first source region 8 a is 2. 0 X 1 0 1 6 / Rei_rei_1 goes below 3 abruptly on resistance [3 ⁇ 4_ ⁇ n increases, ⁇ If the type impurity concentration is higher, the on-resistance R on is 1.
  • the 1 ⁇ -type impurity concentration of the first source region 8 3 2.
  • the concentration of the gate-type impurities in the first source region 8 3 is 2.0 X 10 16 to 1.0 X 10 17 / ⁇ 3 .
  • ON resistance [It is possible to suppress the deterioration of the gate.
  • the 3 ⁇ 3 semiconductor device of the present embodiment is provided with a "3" section and an electric field block layer 4.
  • the 3FE section 3 and the electric field blocking layer 4 function as a saturation current suppressing layer, and the saturation current suppressing effect is exerted, resulting in low on-resistance. It is possible to achieve a structure that can maintain a low saturation current while aiming. Specifically, the following operation is performed because the stripe portion and the electric field blocking layer 4 of the Mending portion 3 are alternately and repeatedly formed.
  • the drain voltage is a voltage applied during normal operation, such as 1 to 1.5 V
  • the depletion layer extending from the electric field blocking layer 4 side to the "mending part 3" is Only the width smaller than the width of the striped part of the claw part 3 extends. Therefore, even if the depletion layer extends into the Mitsube part 3, a current path is secured. Further, since the n-type impurity concentration of the Mending part 3 is higher than that of the n ⁇ -type layer 2, the current path can be configured to have a low resistance, so that a low on-resistance can be achieved.
  • the depletion layer extending from the electric field blocking layer 4 side to the "Mending part 3" was formed into a striped shape in the "Ming part 3". It extends longer than the width of the part. Then, before the mold current dispersion layer 5, the Mitsube 3 is immediately pinched off. At this time,
  • the relationship between the drain voltage V ⁇ 1 and the width of the depletion layer is determined based on the width of the striped portion of the Mending part 3 and the n-type impurity concentration. For this reason, the width of the striped portion of the Mouth portion 3 and the gate-shaped impurity should be checked so that the “Mouth portion 3 is pinched off when the drain voltage becomes slightly higher than the drain voltage during normal operation.” Set the concentration. As a result, it is possible to pinch off the Mitsube part 3 even with a low drain voltage. In this way, when the drain voltage becomes higher than the voltage during normal operation" ⁇ 0 2020/175 157 17 (: 17 2020 /005592
  • the electric field blocking layer 4 and the electric field blocking layer 4 function as a saturation current suppressing layer and exerts a saturation current suppressing effect, a low on-resistance and a low saturation current can be achieved at the same time. It will be possible.
  • the electric field blocking layer 4 By providing the electric field blocking layer 4 so as to sandwich the Mending part 3, the striped portion of the "Minging part 3" and the electric field blocking layer 4 are alternately and repeatedly formed. It is considered as a structure. Therefore, even if the drain voltage becomes high, the extension of the depletion layer extending from the bottom to the 1-!-type layer 2 is suppressed by the field block layer 4 and the extension to the trench gate structure is prevented. You can Therefore, the electric field suppressing effect of lowering the electric field applied to the gate insulating film 12 can be exerted, and the destruction of the gate insulating film 12 can be suppressed, so that an element with high withstand voltage and high reliability can be obtained. It will be possible.
  • an n + type substrate 1 is prepared as a semiconductor substrate. And, not shown By epitaxial growth using the equipment
  • n ⁇ -type layer 2 made of 300 is formed on the main surface of the + type substrate 1.
  • a so-called epi substrate in which the n ⁇ -type layer 2 is previously grown on the main surface of the door + type substrate 1 may be used. And it consists of 3 parts on the mold layer 2.”
  • the epitaxial growth is performed by introducing a gas that serves as an n-type dopant, for example, nitrogen gas, in addition to silane and propane that serve as raw material gases of 300 parts.
  • a gas that serves as an n-type dopant for example, nitrogen gas
  • silane and propane that serve as raw material gases of 300 parts.
  • the mask 17 After arranging the mask 17 on the surface of the part 3, the mask 17 is patterned to open the region where the electric field blocking layer 4 is to be formed. Then, the electric field blocking layer 4 is formed by ion-implanting the type impurities. Then mask 17 is removed.
  • the electric field blocking layer 4 is formed here by ion implantation, the electric field blocking layer 4 may be formed by a method other than ion implantation. For example, after the anisotropic etching of the "3" part is selectively formed to form a recess at a position corresponding to the electric field blocking layer 4, a type impurity layer is epitaxially grown on the recessed part, and then the "3 part of the 3" part is formed.
  • the electric field blocking layer 4 is formed by planarizing the type impurity layer in the upper portion. In this way, the electric field blocking layer 4 can also be formed by epitaxial growth. In the case of epitaxially growing the type 300, it is sufficient to introduce a type dopant gas, for example, trimethylaluminum (hereinafter referred to as Ding 1/18), in addition to the source gas of the type 300.
  • Ding 1/18 trimethylaluminum
  • the n-type current 3 is epitaxially grown on the Mending part 3 and the electric field blocking layer 4 to form the type current spreading layer 5.
  • a mask (not shown) having an opening in the region where the mold deep layer 9 is to be formed is arranged.
  • a mold deep layer 9 is formed by ion-implanting mold impurities from above the mask.
  • the example in which the mold deep layer 9 is also formed by ion implantation is shown, but it can be formed by a method other than ion implantation.
  • a type impurity layer is epitaxially grown and the type impurity layer is planarized to form the type deep layer 9. I will do it ⁇ 2020/175 157 19 ⁇ (: 170? 2020/005592
  • a first source region 8 3 of the type base region 6 and the type source region 8 is sequentially grown epitaxially on the n-type current spreading layer 5 and the type deep layer 9 by using a ⁇ V 0 device (not shown).
  • the growth furnace is heated to a predetermined temperature through a temperature raising process, and then, first, epitaxial growth is performed by introducing a gas serving as a type dopant together with a carrier gas and a raw material gas. To form the mold base region 6.
  • the ⁇ dopant by stopping the introduction of the type dopants, to form formed the first source region 8 3.
  • the thickness of the first source region 8 3 is added by the thickness of the second source region 8 13.
  • the process time is shortened by performing the epitaxial growth of the first source region 83 while maintaining the temperature after forming the mold base region 6 without performing the temperature lowering process.
  • the first source region 8 3 can be formed by the epitaxial growth layer, and the second source region 8 13 can be formed by the ion implantation layer.
  • the mold base region 6 and the mold source region 8 can be formed with the above impurity concentration and film thickness.
  • the film thickness and the impurity concentration of each part are determined as follows.
  • the channel length is set while the impurity concentration forming the inverted channel is set when the gate voltage V 9 is applied.
  • the film thickness is defined as follows. Therefore, for the type base region 6, for example,
  • the thickness is 0.4 to 0.60! ⁇ 2020/175 157 20 (: 170? 2020/005592
  • the saturation current value is reduced and the resistance is high even when a high drain voltage V ⁇ 1 is applied when the load is short-circuited.
  • the film thickness and the n-type impurity concentration are set so as to prevent this from occurring. Therefore, for the first source region 83, for example, the n-type impurity concentration is set to 2.0 X 1016 to 1.0 X 1 X 1a/x3 and the thickness is set to 0. That is all.
  • the second source region 8 13 is a film that does not completely disappear due to a chemical reaction with the source electrode 15 while having an impurity concentration that allows the source electrode 15 to be in ohmic contact. It is set to thick. The higher the n- type impurity concentration of the second source region 8 s, the easier it is to make a talented contact.
  • the type source layer 8 may be epitaxially grown and then the type impurities may be ion-implanted to form the type coupling layer 10. In that case, the type source layer 8 may be formed. If the n- type impurity concentration is too high, the type coupling layer 10 cannot have a desired concentration. Therefore, in the present embodiment is an n-type impurity concentration of the second source region 8 spoon as example 1. 0 X 1 ⁇ 1 8 to 5.0 1 0 1 4.5 / Rei_rei_1 3.
  • the source electrode 15 is made of a plurality of metals, and the portion which makes a mechanical contact with the second source region 8 is made of, for example, I. In that case, the portion of the second source region 8 that is in contact with 1 ⁇ 1 ⁇ will be 1 ⁇ ]. 8 swallows will disappear. And since the thickness of about 1 ⁇ 1 becomes silicidation due to the silicidation reaction, it is necessary to make sure that the entire second source region (8 wells) does not disappear due to silicidation reaction. 2 The thickness of the source region 8 is set to 0.11 or more.
  • first source region 8 3 and the second source region forming the n-type source region 8 are also included.
  • the first source region 83 and the second source region ⁇ 2020/175 157 21 ⁇ (: 170? 2020 /005592
  • the film thickness of the first source region 8 3 and the film thickness of the second source region 8 3 are set within the above ranges.
  • the type base region 6 and the first source region 83 are formed by epitaxial growth, it is possible to reduce variations in the film thickness of each part. Further, in the mold base region 6 used for forming the channel region, the variation in film thickness can be reduced, so that the channel length can be accurately created. As a result, it is possible to reduce the variation in the threshold V I of the vertical type 1/103.
  • n-type impurities are added back to the type base region 6 to form both the first source region 8 3 and the second source region 8 swath. It is also possible to do so. However, in this case, it is necessary to increase the thickness of the mold base region 6 during the epitaxial growth in consideration of the thickness of the first source region 8 3 and the second source region 8 3 formed by ion implantation. ..
  • the variation in film thickness during epitaxial growth increases as the thickness of the grown film increases, but the variation in the range of ion implantation is not so large, so the thickness/variation of the mold base region 6 after ion implantation is The variation corresponds to the thickness of the epitaxially grown film.
  • the first source region 8 3 and the second source region are formed by ion implantation. Even after forming 8 13, the film thickness variation of the mold base region 6 is ⁇ 0.21.
  • the film thickness variation of the mold base region 6 is different from that of the first source region 8 3 and the second source region 8
  • the variation does not include the film thickness, but corresponds to the thickness of only the mold base region 6.
  • the film thickness variation is ⁇ 0.06 to 0.090! Therefore, by forming each part by epitaxial growth, it is possible to suppress the variation in the film thickness of the mold base region 6, and to accurately build the channel length. ⁇ 2020/175 157 22 ⁇ (: 170? 2020/005592
  • the impurity concentration does not change rapidly because the lattice constant depends on the impurity concentration.
  • the gate type source region 8 is formed on the type base region 6 as in the present embodiment, the impurity concentration does not change rapidly because the first source region 8 3 exists.
  • the high-concentration second source region 8 is formed by ion implantation instead of epitaxial growth. For this reason, when n-type dopant remains in the epitaxial growth equipment and contaminates the growth furnace, as in the case of epitaxially growing a high-concentration second source region, the n-type layer or n-type layer is formed later. It is possible to suppress the occurrence of dopant contamination. Therefore, it becomes possible to stably control the impurity concentrations of the type base region 6 and the first source region 83 formed by the epitaxial growth apparatus.
  • a mask (not shown) having an opening at the position where the mold coupling layer 10 is to be formed is arranged. Then, after ion-implanting the type impurities from above the mask, a heat treatment of 150 ° C. or more is performed for activation.
  • the element to be ion-implanted either boron (Mitsumi), aluminum (8), or both are used. As a result, the gate type source region 8 can be repelled by ion implantation of the type impurities to form the type coupling layer 10.
  • the second region 10 of the mold coupling layer 10 needs to be able to make an artificial contact with the source electrode 15. Therefore, the ion implantation is performed at a dose amount that is 2 to 10 times the type impurity concentration of the second source region 81. Regarding the dose amount, if it is twice as much as the type impurity concentration of the second source region 81, it is thought that the carrier concentration can be such that ohmic contact is made with the source electrode 15, but considering the activation rate, 2 to 10 times is preferable ⁇ 2020/175 157 23 ⁇ (: 170? 2020/005592
  • the carrier concentration of the second region 10 cc that is, the type impurity concentration of the component functioning as a carrier excluding the amount of cancellation with respect to the second source region 8 s and the non-activation of
  • it can be set to 2.0 1 ⁇ 18 to 1 ⁇ ⁇ 1 ⁇ 2 ⁇ / ⁇ 3.
  • the source electrode 15 13 is also formed in the second source region 8 13 before the second region 10 13 is formed. I have to make contact with him.
  • since a large dose causes the generation of crystal defects due to ion implantation, it is necessary to suppress the amount to a certain level.
  • the first region 103 since the first region 103 is not a portion that is in ohmic contact with the source electrode 15, it may have a lower type impurity concentration than that of the second region 10. However, here, in consideration of the activation rate, the type impurity is ion-implanted in a dose amount 2 to 10 times that of the first source region 83.
  • the total thickness of the type source region 8 into which the type impurities are implanted is not more than 0.8 from the viewpoint of the output of the ion implantation device. It is preferable to do so. In this way, the mold coupling layer 10 can be formed so as to reach the mold base region 6 even with the output of a general-purpose ion implanter, and mass productivity can be ensured. ..
  • Gate trench 11 is formed by performing anisotropic etching such as ⁇ mi ([ ⁇ 301; 6 10 ⁇ 1x11 _1 hit).
  • the mask is removed and then, for example, thermal oxidation is performed to form the gate insulating film 12, and the gate insulating film 12 covers the inner wall surface of the gate trench 11 and the surface of the n-type source region 8. .. Then, after depositing ? ⁇ I 7-3 I doped with type impurities or gate type impurities, this is etched back, and at least the gate saw 11 is left in the gate trench 11 to form the gate electrode. Forming 1 3 This completes the trench gate structure.
  • the gate trench 1 1 is formed when the trench wrench gate structure is formed due to the influence of damage at the time of ion implantation.
  • the side surface of the is inclined. Therefore, the channel mobility is reduced and the gate trench 11 is widened on the inlet side, which makes it difficult to miniaturize the device.
  • the first source region 8 3 is formed by epitaxial growth, and only the second source region 8 13 is formed by ion implantation. Therefore, the inclination of the side surface of the gate trench 11 due to the damage of the ion implantation is suppressed, and the portion in contact with the second source region 8 is rounded and inclined. Therefore, the gate trench 11 is suppressed from becoming wider on the inlet side, and the miniaturization of the device can be promoted.
  • the interlayer insulating film 14 made of, for example, an oxide film is formed so as to cover the surfaces of the gate electrode 13 and the gate insulating film 12. Further, a contact hole exposing the mold source region 8 and the mold deep layer 9 is formed in the interlayer insulating film 14 by using a mask (not shown). Then, after forming an electrode material composed of, for example, a laminated structure of a plurality of metals on the surface of the interlayer insulating film 14, the electrode material is patterned to form the source electrode 15 and the gate wiring layer. Further, the drain electrode 16 is formed on the back surface side of the gate + type substrate 1. In this way, the 3 ⁇ 3 semiconductor device according to the present embodiment is completed.
  • the n-type source region ⁇ 2020/175 157 25 ⁇ (: 170? 2020 /005592
  • Region 8 is composed of a first source region 8 3 having a relatively low concentration and a second source region 8 13 having a higher concentration. Then, the first source region 83 is formed by epitaxial growth, and the second source region 83 is formed by ion implantation. Therefore, it is possible to improve the short-circuit resistance, suppress the variation of the threshold value V I and the inclination of the side surface of the trench gate, and realize the 3 ⁇ 3 semiconductor device having a structure in which the impurity concentration can be easily controlled.
  • the present embodiment is provided with a non-doped layer as compared with the first embodiment, and is otherwise the same as the first embodiment, so only the parts different from the first embodiment will be described.
  • the non-doped layer 7 made of three silicon oxide is formed on the mold base region 6 and is formed on the three semiconductor devices.
  • the non-doped layer 7 is a layer that is not doped with impurities, or is a layer that has a low carrier concentration by being doped with both a gate type impurity and a type impurity.
  • the thickness of the non-doped layer 7 is set to 0.05 to 0.2.
  • a non-doped layer 7, nitrogen (1 ⁇ 1) n-type impurity is 1.
  • 0 X 1 0 1 6 / ⁇ 3 hereinafter such, preferably is a 1. 0 X 1 0 1 5 / ⁇ 3 or less There is.
  • the non-doped layer 7 contains 1. It is preferably 1.0 X 1 0 1 5 / ⁇ 3 or less.
  • a non-doped layer 7 is provided between the source region 8 3 and the source region. Therefore, the effect of suppressing damage to the gate insulating film 12 can be obtained.
  • This effect will be described with reference to FIGS. 9 to 11.
  • 9 to 11 show the case where the first source region 8 3 is formed so as to be in contact with the type base region 6 when the whole region of the 1... type source region 8 has a high impurity concentration.
  • the gate voltage V 9 is 20 V and the drain-source voltage ⁇ / ⁇ 13 is _ 5 ⁇ /.
  • the parasitic diode formed in the vertical type 1//103 serves as a freewheeling diode, and a freewheeling current flows through the parasitic diode. Then, the holes diffused from the mold layer side of the 1 ⁇ ! junction forming the parasitic diode to the n- type layer side are recombined with the electrons in the gate type layer.
  • Basal plane dislocations hereinafter referred to as “Mix” in the gate-shaped layer composed of the epitaxial film expand and are called single shock race tacking faults (hereinafter referred to as “3 3 3 ”). It becomes a stacking fault.
  • the electric field applied to the n -type source region 8 causes the portion of the type source region 8 that is in contact with the type base region 6 to be in contact with the type base region 6.
  • the existing carriers are accelerated by the electric field and become a hot electron. This collides with the gate insulating film 12 and causes a problem of damaging the gate insulating film 12. In particular, when the n-type impurity concentration is increased in the entire area of the gate type source region 8, this problem becomes remarkable.
  • the n-type source region 8 has the first source region 8 3 without the non-doped layer 7, the type base region 6 and the first source region 8 3 are 1 ⁇ ! Join will be constructed.
  • the n- type impurity concentration of the first source region 8 a is relatively low.
  • the electric field applied to the parts can be suppressed to some extent. That is, as shown in FIG. 10, the equipotential lines at the 1 ⁇ ! junction have a larger distance than in the case of FIG. 9, and the structure including the first source region 8 3 causes the electric field to some extent. Can be suppressed.
  • the junction is formed by the type base region 6 and the first source region 83, so that it is less than in the case of FIG.
  • the above problem can be caused by the generation of hot electrons.
  • a non-doped layer 7 is provided between the n-type source region 8 and 8 3, it is possible to receive an equipotential line by the non-doped layer 7 and weaken the electric field in the n-type source region 8. Become. Then, although an electric field is generated in the non-doped layer 7, there are almost no carriers in the non-doped layer 7. Therefore, by providing the non-doped layer 7, damage to the gate insulating film 12 due to photoelectrons during reverse conduction can be suppressed.
  • the semiconductor device according to Embodiment 3 ⁇ 3 has a non-doped layer 7 formed after forming the mold base region 6 and before forming the mold source region 8. It is manufactured by performing steps.
  • the non-doped layer 7 is formed using the epitaxial growth apparatus used for forming the mold base region 6 and the first source region 88. Specifically, after the type base region 6 is formed, the epitaxial growth is continuously performed with the introduction of the dopant gases of both the type dopant and the n-type dopant into the epitaxial growth apparatus stopped, whereby the non-doped layer is formed. Can form 7. At this time, if the non-doped layer 7 is formed while maintaining the temperature after the formation of the mold base region 6 without performing the temperature lowering process, the process time can be shortened. Further, regarding the subsequent epitaxial growth of the first source region 83, if the temperature is maintained without performing the temperature lowering process after the formation of the non-doped layer 7, the process time can be further shortened.
  • the film thickness can be set arbitrarily, but if it is too thick, the on-resistance ⁇ O becomes high. Therefore, the thickness is set to 0.05 to 0.20!. Further, it is basically preferable that the non-doped layer 7 be free of impurities, but the carrier concentration may be low. In particular, if an attempt is made to continuously form the non-doped layer 7 after the formation of the base region 6, the type impurities remaining in the atmosphere are introduced, or the nitrogen present in the atmosphere is n- type. It may be introduced as an impurity. Even in such a case, it is sufficient if the impurity concentration is low.
  • the impurities of the other conductivity type are intentionally introduced so that they are doped so that they cancel each other out.
  • the carrier concentration may be lowered.
  • the impurity concentration is the 1. 0 X 1 0 1 6 / ⁇ 3 below, when both are doped, one another By canceling each other out, the carrier concentration becomes 1. ⁇ 2020/175 157 29 ⁇ (: 170? 2020 /005592
  • the non-doped layer 7 When the non-doped layer 7 is formed, it is necessary to connect the mold coupling layer 10 to the mold base region 6 when the mold coupling layer 10 is formed.
  • the type impurities are also implanted into 7 and this part also serves as the type coupling layer 10.
  • the non-doped layer 7 is provided between the type base region 6 and the first source region 83. Therefore, the effect of suppressing the generation of photoelectrons and suppressing the damage to the gate insulating film 12 can be obtained.
  • a third embodiment will be described.
  • a method for measuring the film state of the mold layer in the first and second embodiments will be described.
  • an n-type current spreading layer 5 and the first source region 8 3 is epitaxially grown. After formation of these n-type layer, and measured the n-type impurity concentration as the film state of the n-type layer.
  • the surface electronic state of the 1-! type layer does not stabilize immediately after the epitaxial growth of the type layer, but stabilizes after a certain period of time. In order to improve the accuracy of, it is necessary to wait until a certain time has passed after epitaxial growth.
  • the 1 ⁇ ! type impurity concentration can be measured based on the measurement flow of the n type impurity concentration shown in FIG.
  • a 1 ⁇ /103 stacking process is performed.
  • the production process of 1 ⁇ /! ⁇ 3, which is referred to here, is the process of manufacturing the vertical type 1 ⁇ /1 ⁇ 3, which is used in the semiconductor device described in the first and second embodiments.
  • the measurement target layer is the 1-! type current spreading layer 5
  • the steps up to forming the electric field blocking layer 4 shown in FIG. 7 are performed.
  • the measurement target layer is the first source region 8 3 ⁇ 0 2020/175 157 30 (: 17 2020 /005592
  • Step 3110 an epitaxial growth step of the measurement target layer is performed.
  • the gate-shaped current spreading layer 5 or the first source region 83 to be measured is epitaxially grown.
  • a holding step of holding for 10 hours or more in an air atmosphere is performed as an electron stabilizing step.
  • the process proceeds to Step 3130 and the n- type impurity concentration of the measurement target layer is measured.
  • the measurement of the n- type impurity concentration in the n-type layer can be performed using a method called non-contact ⁇ 3 V concentration evaluation. As shown in Fig. 13, the wafer 20 on which the n-type layer has been formed is continuously applied with a charge by corona discharge to electrify the surface of the mold layer and then placed on the wafer 20. This is a method of measuring the n- type impurity concentration from the 0 V curve by repeating the measurement of the surface potential with the potential probe 21. This method can be used to measure the O-type impurity concentration in the measurement target layer after epitaxial growth.
  • the n-type impurity concentration gradually decreases with the elapse of time when the mold layer is simply exposed to the air atmosphere. Then, when the elapsed time reaches 10 hours or more, preferably 18 hours or more, for example, about 24 hours, the n- type impurity concentration is stabilized to be almost constant.
  • the changes in the n-type impurity concentration over time have been examined multiple times, but the impact is a concern because the contactless ⁇ V concentration evaluation will be performed each time. Therefore, the measurement by non-contact ⁇ 3 V concentration evaluation was performed as the first measurement 24 hours after the formation of the n-type layer or the second measurement 30 hours later. ⁇ 2020/175 157 31 ⁇ (: 170? 2020 /005592
  • the n- type impurity concentration of the measurement target layer is measured by the non-contact 0 V concentration evaluation, and the measurement is not performed immediately after the epitaxial growth, but as a step of electron stabilization, the atmosphere is used. The measurement is performed after carrying out the holding step of holding for 10 hours or more below. This makes it possible to measure the concentration of the gate-type impurities with high accuracy.
  • non-contact at 3 ⁇ 3 In the 3 V concentration evaluation, the presence or absence of an oxide film is optional, and the O-type impurity concentration can be measured without being affected by the presence or absence of an oxide film.
  • 1 to 1 treatment even if an oxide film was formed, it was removed so that it could be removed from the beginning even if no oxide film was formed. It is possible to measure the n- type impurity concentration based on the concentration evaluation.
  • step 3230 the n-type impurity concentration of the measurement target layer is measured by the same method as in step 3130 of FIG.
  • the time for starting the measurement of the n-type impurity concentration that is, the elapsed time after the completion of the acid cleaning step is arbitrary, and therefore the elapsed time may be short.
  • a fourth embodiment will be described.
  • the n-type layer but the ⁇ current spreading layer 5 and the first source region 8 3 has been described by way of example, Epitaki ⁇ 2020/175 157 33 ⁇ (: 170? 2020/005592
  • n ⁇ type layer 2 is epitaxially grown on the main surface of n + type substrate 1, A case of measuring the n- type impurity concentration of the mold layer 2 will be described.
  • the 1 ⁇ !-type impurity concentration can be measured based on the n- type impurity concentration measurement flow shown in FIG.
  • a 30° bulk substrate that is, an n + type substrate 1 is prepared.
  • the mold layer 2 is epitaxially grown on the main surface of the n + -type substrate 1.
  • steps 3320 and 3330 a step of measuring the O-type impurity concentration is performed after an acid cleaning step as in steps 3220 and 3230 of FIG.
  • the Mitsune portion 3 and the electric field blocking layer 4 and the n- type current spreading layer 5 are provided, and the "Mitsune portion 3 and the n- type current spreading layer 5 are the drift layers.
  • the structure is a part of the. However, this is merely an example of the configuration of the vertical 1 ⁇ /103 stacking structure, that is, the structure that does not include the JFE part 3 and the electric field blocking layer 4, the structure that does not include the n- type current spreading layer 5, Alternatively, the structure may not include both of them.
  • first region 10 3 may be formed deeper than the first source region 8 3
  • second region 10 c may be formed deeper than the second source region 8 3. Is also good.
  • the mold deep layer 9 and the mold coupling layer 10 are separately configured, but they may be composed of the same mold layer.
  • a deep trench is formed from the surface of the gate type source region 8 through the non-doped layer 7, the type base region 6 and the type current distribution layer 5 to reach the electric field blocking layer 4, and is embedded in the deep trench.
  • a type impurity is ion-implanted from the surface of the n-type source region 8 to form a type layer that reaches the electric field blocking layer 4 from the non-doped layer 7, the O-type base region 6 and the n- type current spreading layer 5. By doing so, it becomes possible to form the mold deep layer 9 and the mold connecting layer 10 by the mold layer.
  • the impurity concentration of the gate type source region 8 is different.
  • the structure in which the two regions, that is, the first source region 83 and the second source region 8 is divided has been described, but the structure may not be clearly divided. That is, the type base region 6 side of the type source region 8 has a lower impurity concentration than the surface side contacted with the source electrode 15 and the surface side is a high impurity concentration contacted with the source electrode 15 by ohmic contact. It only has to be the concentration. In other words, there may be a concentration gradient such that the first source region 8 3 and the second source region 8 are gradually increased in impurity concentration toward the source electrode 15 side.
  • the n-type impurity concentration is measured after the epitaxial growth by using the 1! type current spreading layer 5, the first source region 8 3, and the type layer. This is explained by taking 2 as an example.
  • the ion-implantation step was performed after the epitaxial growth layer was formed on the 3x bulk substrate, and then the gate-shaped current to be the measurement target layer was formed. shows a case that as to form an n-type layer such as distributed layer 5 and the first source region 8 3.
  • the epitaxial growth layer formed in the lower layer ⁇ 2020/175 157 35 ⁇ (: 170? 2020 /005592
  • the n- type impurity concentration can be measured by the non-contact 0 V concentration evaluation described above.
  • the case where the epitaxial growth layer is formed on the 30-bulk substrate, that is, the -type layer 2, which is the 30-layer to be measured, is shown.
  • the n- type impurity concentration can be measured by the above-mentioned non-contact 0 V concentration evaluation even when the epitaxial growth of the layer to be measured is directly performed on the 3 ⁇ 3 bulk substrate.
  • a vertical channel type 1 ⁇ /103 knives which is an n-channel for the first conductivity type and a mold for the second conductivity type, has been described as an example. However, it is also good as a channel-type vertical type 1 ⁇ /! Further, in the above description, the vertical type 1 ⁇ /103 photo was taken as an example of the semiconductor element, but the present disclosure can be applied to a photo of a similar structure.
  • the conductivity type of the n + type substrate 1 is only changed from the door type to the type in the above-mentioned respective embodiments, and other structures and manufacturing methods are the same as those in the above-mentioned respective embodiments Is the same as.

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Abstract

Selon la présente invention, une région de source (8) comprend une première région de source (8a) qui est composée d'une couche épitaxiale qui est formée sur un côté de région de base (6), et une seconde région de source (8b) qui est en contact avec une électrode de source et qui est composée d'une couche à implantation ionique ayant une concentration d'impuretés d'un premier type de conductivité qui est supérieure à celle de la première région de source.
PCT/JP2020/005592 2019-02-27 2020-02-13 Dispositif à semi-conducteur au carbure de silicium et son procédé de fabrication WO2020175157A1 (fr)

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Citations (5)

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WO2013172079A1 (fr) * 2012-05-15 2013-11-21 三菱電機株式会社 Dispositif à semi-conducteurs et procédé de fabrication de ce dernier
WO2014196164A1 (fr) * 2013-06-05 2014-12-11 株式会社デンソー Dispositif semi-conducteur au carbure de silicium, et procédé de fabrication de celui-ci
JP2018082114A (ja) * 2016-11-18 2018-05-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2018518063A (ja) * 2015-06-05 2018-07-05 セミラボ セミコンダクター フィジックス ラボラトリー カンパニー リミテッドＳＥＭＩＬＡＢ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｐｈｙｓｉｃｓ Ｌａｂｏｒａｔｏｒｙ Ｃｏ．，Ｌｔｄ． 一定の表面電位コロナ帯電を用いた半導体ドーピングの測定
JP2019016775A (ja) * 2017-07-07 2019-01-31 株式会社デンソー 半導体装置およびその製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013172079A1 (fr) * 2012-05-15 2013-11-21 三菱電機株式会社 Dispositif à semi-conducteurs et procédé de fabrication de ce dernier
WO2014196164A1 (fr) * 2013-06-05 2014-12-11 株式会社デンソー Dispositif semi-conducteur au carbure de silicium, et procédé de fabrication de celui-ci
JP2018518063A (ja) * 2015-06-05 2018-07-05 セミラボ セミコンダクター フィジックス ラボラトリー カンパニー リミテッドＳＥＭＩＬＡＢ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｐｈｙｓｉｃｓ Ｌａｂｏｒａｔｏｒｙ Ｃｏ．，Ｌｔｄ． 一定の表面電位コロナ帯電を用いた半導体ドーピングの測定
JP2018082114A (ja) * 2016-11-18 2018-05-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2019016775A (ja) * 2017-07-07 2019-01-31 株式会社デンソー 半導体装置およびその製造方法

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