WO2020168518A1

WO2020168518A1 - Packaging structure and preparation method therefor

Info

Publication number: WO2020168518A1
Application number: PCT/CN2019/075726
Authority: WO
Inventors: 罗立德; 郭健炜; 胡骁; 王盛平
Original assignee: 华为技术有限公司
Priority date: 2019-02-21
Filing date: 2019-02-21
Publication date: 2020-08-27
Also published as: CN113170579A

Abstract

Provided are a packaging structure and a preparation method therefor, wherein same relate to the technical field of microelectronic packaging, and are used for solving the problem that solder will penetrate through a crack on a solder resist layer after being melted. The packaging structure comprises a chip and a substrate for carrying the chip. A first surface of the substrate is covered with a first insulating layer, the substrate is provided with a first pad on an inner side of the first insulating layer, a first opening is provided in the first insulating layer, and the bottom of the first opening leads to the first pad. The substrate further comprises a first conductive stop, wherein the first conductive stop blocks the bottom of the first opening, and same is electrically connected to the first pad; and the height of the first conductive stop in the first opening is less than the depth of the first opening.

Description

Packaging structure and preparation method thereof

Technical field

This application relates to the field of microelectronic packaging technology, and in particular to a packaging structure and a preparation method thereof.

Background technique

Flip-chip technology has been widely used in the field of chip packaging due to its advantages such as reducing the chip packaging area and shortening the signal transmission path. For example: chip scale package (CSP), direct chip attached (DCA) and multi-chip module (MCM) package modules, all of which can be used Flip chip technology to achieve the purpose of packaging.

During the flip chip packaging process and reliability testing process, the temperature will vary widely. As a result, as shown in Figure 1, due to the large difference in thermal expansion coefficient or asymmetrical heating between the silicon material of the chip and the organic material of the substrate, the fluidity characteristic of the combined solder 30 after melting will cause the solder mask 10 and the solder IMC (intermetallic compound) is formed between the pads 20, and the IMC between the solder resist layer 10 and the pad 20 continues to grow in the horizontal direction (perpendicular to the thickness direction of the substrate), causing the pad 20 to be consumed. Thinning, the melted solder 30 expands along the IMC in the horizontal direction to form an undercut, which in turn causes cracks 101 on the solder resist layer 10.

As a result, the melted solder 30 will penetrate along the crack 101 and be connected to other conductive structures, which will cause a short circuit in adjacent conductive structures and affect the reliability of the entire device.

Summary of the invention

This application provides a package structure and a preparation method thereof, which are used to solve the problem that the solder will penetrate along the cracks on the solder resist after melting.

In order to achieve the above objectives, this application adopts the following technical solutions:

In a first aspect of the present application, a package structure is provided, which includes a chip and a substrate for carrying the chip. The first surface of the substrate is covered with a first insulating layer; the substrate is provided with a first pad inside the first insulating layer , The first insulating layer is provided with a first opening, and the bottom of the first opening leads to the first pad; the substrate further includes a first conductive stopper, the first conductive stopper blocks the bottom of the first opening, and the first conductive stopper It is electrically connected to the first pad; wherein the height of the first conductive block in the first opening is smaller than the depth of the first opening. In the package structure provided by the present application, the substrate is provided with a first auxiliary pad in a first opening penetrating the first insulating layer, and the first auxiliary pad blocks the bottom of the first opening. In this way, during the packaging process, the solder is connected to the first conductive block, and the melted solder hardly flows between the first insulating layer and the first pad, and between the first insulating layer and the first pad No IMC that grows in the horizontal direction will be formed, and no cracks will appear on the first insulating layer. Therefore, the problem of interconnection of adjacent conductive structures due to the flow of soldering liquid can be avoided, and the reliability of the entire device can be improved. In addition, since the first conductive stopper is electrically connected to the first pad, the first conductive stopper can also be regarded as a part of the first pad, which is equivalent to increasing the thickness of the first pad, thereby increasing the first pad. The anti-electromigration ability of the pad can improve the reliability of the package structure under stress and high power consumption after the substrate and chip of the present application are packaged. Moreover, since the height of the first conductive stopper in the first opening is smaller than the depth of the first opening, the solder can be trapped in the first opening of the first insulating layer. Therefore, the soldering capacity of the substrate can be increased to better The thermal expansion coefficient mismatch between the chip and the substrate is buffered to reduce the overall stress of the package. In addition, it can also avoid sliding misalignment during the setting of the preset solder balls and inaccurate alignment during the subsequent soldering process, resulting in false soldering and affecting the entire The problem of chip placement yield.

Optionally, the chip is a die.

Optionally, the chip is a packaging entity obtained by packaging one or more dies.

Optionally, the first surface is the surface of the substrate close to the chip. It can solve the problems existing in substrate and chip packaging.

Optionally, the substrate further includes a first conductive layer disposed inside the first insulating layer, and the first conductive layer includes a first pad.

Optionally, the first conductive stopper is also in contact with the sidewall of the first opening. It can better prevent the solder from flowing between the first pad and the first insulating layer.

Optionally, the first insulating layer is composed of a solid thermally cured dielectric polymer. The first insulating layer is composed of a solid thermosetting dielectric polymer, which can prevent the first insulating layer from affecting the formation of the first conductive block.

Optionally, the first insulating layer is one of a prepreg, a polyimide film, a polybenzoxazole film, a bismaleimide-triazine resin film, or a ceramic powder reinforced modified epoxy resin film.

Optionally, the first conductive block includes a body layer, and the material of the body layer includes copper or copper alloy. In order to maximize the electromigration resistance of the first pad, the material of the first auxiliary pad body layer is selected to include copper or copper alloy.

On this basis, optionally, the first conductive stopper further includes a protective layer located on the side of the body layer away from the first pad, the protective layer covers the body layer; the protective layer is used to prevent oxidation of the body layer. The protective layer can prevent the surface of the body layer of the first auxiliary pad from being contaminated and oxidized, so as to ensure the reliability of component welding.

Optionally, the second surface of the substrate opposite to the first surface is covered with a second insulating layer, a second pad is arranged inside the second insulating layer, a second opening is arranged on the second insulating layer, and the bottom of the second opening Lead to the second pad.

On this basis, optionally, the substrate further includes a second conductive stopper, the second conductive stopper blocks the bottom of the second opening, and the second conductive stopper is electrically connected to the second pad; wherein, the second conductive stopper The height in the second opening is smaller than the depth of the second opening. By arranging a second auxiliary pad in the second opening that penetrates the second insulating layer, and making the second auxiliary pad block the bottom of the second opening, the solder is connected to the second conductive stopper during the packaging process , The melted solder will hardly flow between the second insulating layer and the second pad, no horizontal IMC will be formed between the second insulating layer and the second pad, and no IMC will be formed on the second insulating layer. Cracks occur, thereby avoiding the problem of interconnection of adjacent conductive structures caused by the flow of the solder after melting, and improving the reliability of the entire device. In addition, since the second conductive stopper is electrically connected to the second pad, the second conductive stopper can also be regarded as a part of the second pad, which is equivalent to increasing the thickness of the second pad, thereby increasing the second The anti-electromigration ability of the pad, and the packaging structure formed by packaging the substrate and the chip of the present application can improve the reliability of the packaging structure under stress and high power consumption. Moreover, since the height of the second conductive stopper in the second opening is smaller than the depth of the second opening, the solder can sink into the second opening of the second insulating layer, which can increase the amount of soldering of the substrate to better buffer the chip The thermal expansion coefficient mismatch with the substrate reduces the overall stress of the package. It can also avoid the problem of sliding misalignment during the setting process of the preset solder balls and misalignment in the subsequent soldering process, resulting in false soldering and affecting the overall chip mounting yield.

Optionally, the substrate is a packaging substrate, and the packaging substrate further includes a redistribution layer disposed between the first pad and the second pad. In this case, when the packaging substrate is prepared, a detachable carrier is used as a carrier to produce a core-layer-less packaging substrate structure.

Optionally, the substrate is a packaging substrate, and the packaging substrate further includes: a core layer provided between the first pad and the second pad; a first redistribution layer provided between the core layer and the first pad; The second rewiring layer between the core layer and the second pad.

In a second aspect, a package structure is provided, which includes a chip and a substrate for carrying the chip. The first surface of the substrate is covered with a first insulating layer; the substrate is provided with a first pad on the inner side of the first insulating layer; The insulating layer is provided with a first opening, and the bottom of the first opening leads to the first pad; the second surface of the substrate opposite to the first surface is covered with a second insulating layer; the substrate is provided with a second insulating layer inside the second insulating layer A pad; a second opening is provided on the second insulating layer, and the bottom of the second opening leads to the second pad; the substrate also includes a first conductive stopper and a second conductive stopper; the first conductive stopper blocks the first opening The first conductive block is electrically connected to the first pad; the second conductive block blocks the bottom of the second opening, and the second conductive block is electrically connected to the second pad. By providing conductive stoppers on both surfaces of the substrate, the resistance to electromigration of the pads on both sides can be improved, and the packaging structure formed by packaging the substrate and the chip of the present application can improve the packaging structure under stress and high power consumption. Reliability.

Optionally, the height of the first conductive block in the first opening is greater than the depth of the first opening. The thickness of the first conductive block is relatively thick, which is equivalent to increasing the thickness of the first pad, which can maximize the anti-electromigration ability of the first pad.

Optionally, the height of the second conductive block in the second opening is greater than the depth of the second opening. The thickness of the second conductive block is thicker, which is equivalent to increasing the thickness of the second pad, which can maximize the anti-electromigration ability of the second pad.

In a third aspect, there is provided a package structure including a chip and a substrate for carrying the chip. The first surface of the substrate is covered with a first insulating layer; the substrate is provided with a first pad inside the first insulating layer, and the first insulating layer The layer is provided with a first opening, and the bottom of the first opening leads to the first pad; the substrate further includes a first conductive stopper, the first conductive stopper blocks the bottom of the first opening, and the first conductive stopper is connected to the first welding pad. The disc is electrically connected; wherein the first insulating layer is composed of a solid thermally cured dielectric polymer. In order to prevent the material of the first insulating layer from affecting the formation of the first conductive block, a solid thermal curing dielectric polymer material can be used instead of green oil as the material of the first insulating layer.

In a fourth aspect, a method for preparing a package structure is provided, which includes forming a chip and a substrate for carrying the chip; forming the substrate includes: forming a first conductive layer; forming a first thin film layer covering the first conductive layer by laser drilling A hole or mechanical drilling process forms a first opening on the first thin film layer to form a first insulating layer covering the first surface of the substrate; wherein the first opening exposes a part of the first conductive layer as a first pad The first conductive stopper is formed by the electroless plating process and the electroplating process, the first conductive stopper blocks the bottom of the first opening, and the first conductive stopper is electrically connected to the first pad; wherein, the first conductive stopper is in the first The height in the opening is smaller than the depth of the first opening. In the present application, a first opening is formed in the thin film layer along the thickness direction of the substrate through a laser drilling or mechanical drilling process to expose the first pad. Further, the electroless plating process and the electroplating process are used to form the first conductive stopper, and the thickness of the first conductive stopper can be adjusted as required, and the application range is wide. However, if grinding technology is used, the structure of the present invention cannot be obtained.

Optionally, forming the substrate further includes: using at least one surface treatment process among chemical tin, chemical nickel gold, chemical nickel palladium gold, and chemical silver to process the surface of the first conductive block away from the first pad. After the surface treatment of the first conductive stopper is performed, the body layer of the first conductive stopper can be protected from contamination and oxidation, so as to ensure the stability of welding of components.

Optionally, forming the substrate further includes: forming a second conductive layer located on the side of the first conductive layer away from the first surface of the substrate; forming a second thin film layer covering the second conductive layer by laser drilling or mechanical drilling process A second opening is formed in the second film layer to form a second insulating layer covering the second surface of the substrate opposite to the first surface; wherein the second opening exposes a part of the second conductive layer as a second solder Disk; a second conductive stopper is formed by an electroless plating process and an electroplating process, the second conductive stopper blocks the bottom of the second opening, and the second conductive stopper is electrically connected to the second pad; wherein, the second conductive stopper is in the first The height of the two openings is smaller than the depth of the second opening. In the present application, a second opening is formed in the second thin film layer along the thickness direction of the substrate through a laser drilling or mechanical drilling process to expose the second pad. Further, the electroless plating process and the electroplating process are used to form the second conductive stopper, and the thickness of the second conductive stopper can be adjusted as required, and the application range is wide.

In a fifth aspect, a method for preparing a package structure is provided, which includes forming a chip and a substrate for carrying the chip; forming the substrate includes: separately forming a first conductive layer and a second conductive layer stacked in a thickness direction of the substrate; A first thin film layer is formed on the surface of a conductive layer away from the second conductive layer, and a first opening is formed in the first thin film layer through a laser drilling or mechanical drilling process to form a first insulation covering the first surface of the substrate Wherein, the first opening exposes the part of the first conductive layer as the first pad; a second thin film layer is formed on the surface of the second conductive layer away from the first conductive layer, and is drilled by laser or mechanical drilling A second opening is formed on the second film layer to form a second insulating layer covering a second surface of the substrate opposite to the first surface; wherein the second opening exposes a part of the second conductive layer as a second pad; The first conductive stopper is formed by the electroless plating process and the electroplating process, the first conductive stopper blocks the bottom of the first opening, and the first conductive stopper is electrically connected to the first pad; the second conductive stopper is formed by the chemical plating process and the electroplating process Stopper, the second conductive stopper blocks the bottom of the second opening, and the second conductive stopper is electrically connected to the second pad. In the present application, a first opening penetrating through the first thin film layer and a second opening penetrating the second thin film layer along the thickness direction of the substrate are formed in the thin film layer through a laser drilling or mechanical drilling process, respectively exposing the first pad and the second solder. plate. Further, the electroless plating process and the electroplating process are used to form the first conductive stopper and the second conductive stopper, and the thickness of the first conductive stopper and the second conductive stopper can be adjusted as required, and the application range is wide. However, if grinding technology is used, the structure of the present invention cannot be obtained.

Optionally, the height of the first conductive block in the first opening is greater than the depth of the first opening.

Optionally, the height of the second conductive block in the second opening is greater than the depth of the second opening.

Description of the drawings

FIG. 1 is a schematic diagram of the structural relationship between solder and pads in a substrate provided by the prior art;

FIG. 2a is a first structural diagram of a substrate provided by an embodiment of the present invention;

2b is a second schematic diagram of the structure of a substrate provided by an embodiment of the present invention;

3 is a schematic diagram of the structural relationship between solder and pads in a substrate provided by an embodiment of the present invention;

4 is a schematic diagram of an electroless plating process step provided by an embodiment of the present invention;

5 is a schematic diagram of an electroplating process step provided by an embodiment of the present invention;

FIG. 6 is a third structural diagram of a substrate provided by an embodiment of the present invention;

FIG. 7 is a fourth structural diagram of a substrate provided by an embodiment of the present invention;

FIG. 8 is a fifth structural diagram of a substrate provided by an embodiment of the present invention;

FIG. 9 is a first flowchart of a method for preparing a substrate according to an embodiment of the present invention;

FIG. 10 is a first schematic diagram of a preparation process of a substrate provided by an embodiment of the present invention;

11a is a second schematic diagram of a preparation process of a substrate provided by an embodiment of the present invention;

11b is a third schematic diagram of a preparation process of a substrate provided by an embodiment of the present invention;

12 is a fourth schematic diagram of a preparation process of a substrate provided by an embodiment of the present invention;

13 is a second flowchart of a method for preparing a substrate according to an embodiment of the present invention;

14 is a third flowchart of a method for preparing a substrate provided by an embodiment of the present invention;

15a is a schematic diagram 1 of the preparation process of another substrate provided by an embodiment of the present invention;

15b is a second schematic diagram of the preparation process of another substrate provided by an embodiment of the present invention;

15c is a third schematic diagram of the preparation process of another substrate provided by an embodiment of the present invention;

16 is a fourth flowchart of a method for preparing a substrate provided by an embodiment of the present invention;

17 is a fifth flowchart of a method for preparing a substrate provided by an embodiment of the present invention;

18 is a sixth structural diagram of a substrate provided by an embodiment of the present invention;

FIG. 19 is a seventh structural diagram of a substrate provided by an embodiment of the present invention;

20 is a sixth flowchart of a method for preparing a substrate according to an embodiment of the present invention;

21 is a schematic diagram 1 of another substrate preparation process provided by an embodiment of the present invention;

22 is a second schematic diagram of the preparation process of still another substrate provided by an embodiment of the present invention;

FIG. 23 is a third schematic diagram of a preparation process of another substrate provided by an embodiment of the present invention;

24 is a fourth schematic diagram of the preparation process of another substrate provided by an embodiment of the present invention;

FIG. 25 is a seventh flowchart of a method for preparing a substrate according to an embodiment of the present invention.

Reference signs:

10- solder mask; 101-crack; 20-pad; 30-solder; 1-first surface; 11-first insulating layer; 111-first opening; 112-first film layer; 21-first conductive Layer; 211-first pad; 41-first conductive block; 411-metal layer; 412-copper film layer; 413-dry film; 2-second surface; 12-second insulating layer; 121-second Opening; 122-second film layer; 22-second conductive layer; 221-second pad; 42-second conductive block; 50-core layer; 51-through hole; 52-via; 53-hole plug; 60-rewiring layer; 61-first rewiring layer; 62-second rewiring layer; 63-dielectric layer; 64-metal wiring layer; 70-supporting board; 80-supporting copper foil; 90-ultra-thin copper Foil.

detailed description

Unless otherwise defined, the ABF technical terms or scientific terms used in this application shall have the usual meanings understood by those skilled in the art. The terms "first", "second" and similar words used in the specification and claims of this application do not denote any order, quantity or importance, but are only used to distinguish different components. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

The substrate is the carrier of the semiconductor chip package, and serves as a connecting body between an integrated circuit (IC) chip and a printed circuit board (PCB), and is used to realize the connection between the IC and the PCB.

The two opposite surfaces of the substrate are provided with external pins (solder balls or pads). The external pins on one surface of the substrate are connected to the IC, and the external pins on the other surface are connected to the PCB.

An example of a semiconductor packaging technology: Place the IC die on a substrate, connect all the pins on the IC to the external pins on the first surface of the substrate by flip chip technology, and then make the IC into a package. It is then connected to the PCB through external pins on the package body (external pins on the second surface of the substrate). The IC is connected to the PCB, and is connected to other devices through wires on the PCB, thereby realizing the connection between the internal chip and the external circuit.

The embodiment of the present application provides a package structure including a chip and a substrate for carrying the chip. As shown in FIG. 2a and FIG. 2b, the first surface 1 of the substrate is covered with a first insulating layer 11, and the substrate is in the first insulating layer. A first pad 211 is provided on the inner side of the layer 11, a first opening 111 is provided on the first insulating layer 11, and the bottom of the first opening 111 leads to the first pad 211.

The substrate further includes a first conductive stopper 41, the first conductive stopper 41 blocks the bottom of the first opening 111, and the first conductive stopper 41 is electrically connected to the first pad 211; wherein, the first conductive stopper 41 is in the first The height h1 in the opening is smaller than the depth h2 of the first opening.

It can be understood that the first surface 1 of the substrate is covered with the first insulating layer 11, that is, the first insulating layer 11 can be directly seen without disassembling the substrate. Based on this, the inner side of the first insulating layer 11 is the side of the first insulating layer 11 facing the inside of the substrate. Since the first opening 111 penetrates the first insulating layer 11, the first conductive stop 41 located in the first opening 111 directly contacts the first pad 211. The first surface 1 may be, for example, the surface of the substrate close to the chip.

In addition, the first conductive block 41 blocks the bottom of the first opening 111. As shown in FIG. 2b, the first conductive block 41 does not contact the side wall of the first opening 111, and only blocks the bottom of the first opening 111. can. It may also be as shown in FIG. 2 a that the first conductive stop 41 is also in contact with the side wall of the first opening 111, for example, the first conductive stop 41 is embedded in the first opening 111.

As shown in FIG. 3, the first conductive stop 41 blocks the bottom of the first opening 111. Since the solder cannot leak from the first opening 111 to the first pad 211, it can prevent the solder from melting along The sidewall of the first opening 111 flows to the first pad 211. The bottom of the first opening 111 refers to a position where the first opening 111 is close to the first pad 211.

Optionally, the material of the first insulating layer 11 is green oil (ink).

However, in an alternative embodiment of the present invention, since the height of the first conductive stop 41 at the first opening 111 is to be smaller than the depth of the first opening 111, during processing, electroplating and electroless plating are usually selected. A first conductive stop 41 is formed on the first pad 211. When electroplating and electroless plating are used to generate the first conductive stop 41, if the first insulating layer 11 made of green oil continues to be used, it is possible that foreign matter generated on the surface of the green oil may cause the plating solution to be contaminated and affect electroplating or The quality of electroless plating. In order to solve this problem, a thermocuring solid-state dielectric polymer (thermocuring solid-state dielectric polymer) material can be considered as the material of the first insulating layer 11 instead of green oil. The solid-state thermally cured dielectric polymer can be a prepreg, polyimide (PI) film, polybenzoxazole (PBO) film, bismaleimide triazine (BT) Film, ceramic powder reinforced modified epoxy resin (ajinomoto build up film, ABF) film, etc.

The material of the first conductive block 41 may include at least one of conductive materials such as copper, nickel, tin, gold, silver, copper alloy, or copper-tin alloy. The first conductive stop 41 may be formed by processes such as electroless plating and electroplating, so that the thickness of the first conductive stop 41 is smaller than the thickness of the first insulating layer 11.

Optionally, as shown in FIGS. 2 a and 2 b, the substrate includes a first conductive layer 21 arranged inside the first insulating layer 11, and the first conductive layer 21 includes a first pad 211.

It should be noted that, in the embodiments of the present application, the substrate is a packaging substrate as an example for description, but all packaging structures that require the use of pads are applicable to the present application.

In the package structure provided by the present application, the substrate is provided with a first conductive stopper 41 in the first opening 111 penetrating the first insulating layer 11, and the first conductive stopper 41 blocks the bottom of the first opening 111, as a result, During the packaging process, the solder is connected to the first conductive stop 41, and the melted solder hardly flows between the first insulating layer 11 and the first pad 211, which is between the first insulating layer 11 and the first pad 211 There will be no IMC (intermetallic compound) that grows in the horizontal direction, and no cracks will appear on the first insulating layer 11. Therefore, the problem of interconnection of adjacent conductive structures due to the flow of soldering liquid can be avoided, and the reliability of the entire device can be improved. In addition, since the first conductive stop 41 is electrically connected to the first pad 211, the first conductive stop 41 can also be regarded as a part of the first pad 211, which is equivalent to increasing the thickness of the first pad 211. Therefore, the resistance to electromigration of the first pad 211 can be improved, and after the substrate and the chip of the present application are packaged, the reliability of the package structure under stress and high power consumption can be improved. Moreover, since the height h1 of the first conductive stopper 41 in the first opening 111 is smaller than the depth h2 of the first opening 111, the solder can sink into the first opening 111 of the first insulating layer 11, and therefore, the suction of the substrate can be improved. Solder volume, to better buffer the thermal expansion coefficient mismatch between the chip and the substrate, reduce the overall stress of the package, in addition, it can also avoid the sliding misalignment during the preset solder ball setting process and the misalignment during the subsequent soldering process , Resulting in virtual soldering and affecting the overall chip mounting yield.

In order to maximize the electromigration resistance of the first pad 211, in some embodiments, the first conductive block 41 includes a body layer, and the material of the body layer includes copper or copper alloy.

In some embodiments, the first conductive block 41 includes a body layer and a protection layer, the body layer is electrically connected to the first pad 211, the protection layer is located on the side of the body layer away from the first pad 211, and the protection layer covers the body layer. . The body layer material includes copper or copper alloy, and the protective layer is used to prevent oxidation of the body layer.

Here, in order to prevent the surface of the body layer of the first conductive block 41 from being contaminated and oxidized, and to ensure the reliability of component welding, for example, chemical tin, chemical nickel-gold, chemical nickel-palladium-gold, chemical silver and other processes can be used to conduct The body layer of a conductive block 41 undergoes surface treatment to form a protective layer.

Example one

As shown in Figure 2a, a substrate for carrying chips is shown. The substrate includes a core layer 50. Along the thickness direction of the substrate, two opposite surfaces of the core layer 50 are respectively provided with a first redistribution layer 61 and a second redistribution layer. 62. On the side of the first redistribution layer 61 away from the core layer 50, a first conductive layer 21, a first insulating layer 11, and a first conductive stopper 41 are sequentially provided. A second conductive layer 22 and a second insulating layer 12 are sequentially provided on the side of the second redistribution layer 62 away from the core layer 50.

The structures of the first redistribution layer 61 and the second redistribution layer 62 are shown in FIG. 2a, and both include a multilayer dielectric layer 63 and a multilayer metal wiring layer 64 (FIG. 2a uses the first redistribution layer 61 and the second Each of the dual wiring layers 62 includes two dielectric layers 63 and two metal wiring layers 64 as an example for illustration). Among them, the metal wiring layer 64 and the dielectric layer 63 are alternately arranged, and the multilayer metal wiring layer 64 constitutes the metal circuit structure of the substrate.

To avoid short circuits, the first conductive layer 21 can be in contact with the dielectric layer 63 in the first redistribution layer 61. Similarly, the second conductive layer 22 can be in contact with the dielectric layer 63 in the second redistribution layer 62. . Of course, an insulating layer can also be provided between the first redistribution layer 61 and the first conductive layer 21. In this case, the outermost layer of the first redistribution layer 61 close to the first conductive layer 21 can be the dielectric layer 63. , May also be a metal wiring layer 64. Similarly, an insulating layer can be provided between the second redistribution layer 62 and the second conductive layer 22. In this case, the outermost layer of the second redistribution layer 62 close to the second conductive layer 22 can be the dielectric layer 63. , May also be a metal wiring layer 64.

Each dielectric layer 63 is provided with a via for electrically connecting two adjacent metal wiring layers 64, wherein the dielectric layer 63 close to the first conductive layer 21 is provided with a via for connecting the first conductive layer 21 with the The metal wiring layer 64 contacting the dielectric layer 63 is electrically connected with a via hole, and the dielectric layer 63 close to the second conductive layer 22 is provided with a metal wiring layer 64 for connecting the second conductive layer 22 and the dielectric layer 63 Vias for electrical connections.

The material of the dielectric layer 63 may be a dielectric material. For example, the dielectric layer 63 is one of a prepreg, PI film, PBO film, BT film, ABF film, and the like.

In terms of technology, the dielectric layer 63 can be formed in the following ways: first, a thin film layer formed by a pressing process (hot pressing, rolling, vacuum pressing, printing, suspension coating, etc.), and then through laser drilling and mechanical The drilling process forms via holes in the thin film layer to obtain the dielectric layer 63.

The material of the metal wiring layer 64 may be at least one of conductive materials such as copper, nickel, tin, gold, silver, copper alloy, or copper-tin alloy. The metal wiring layer 64 may be formed by a physical vapor deposition (Physical Vapor Deposition, PVD) process combined with an electroplating process, or may be formed by a patterning process.

The core layer 50 is provided with via holes, and the conductive layers located on both sides of the core layer 50 are connected through the via holes. The conductive layers located on both sides of the core layer 50 may be, for example, the first redistribution layer 61 closest to the core layer 50. The metal wiring layer 64 of the metal wiring layer 64 and the second rewiring layer 62 that is closest to the core layer 50.

Optionally, the core layer 50 is glass coated with copper foil on both sides. When preparing the core layer 50, the through hole 51 is formed in the glass by mechanical drilling or laser drilling process, and then the through hole 51 is formed along the through hole 51 through a metallization process (electroless plating, electroplating, printing, sputtering, etc.) The hole wall forms a via 52 in a circle to connect the metal wiring layer 64 on both sides of the core layer 50. To ensure the performance of the passage 52, a plugging material is filled in the hollow area enclosed by the passage 52 to form a plug 53.

The material and preparation process of the first conductive layer 21 and the second conductive layer 22 may be the same. For example, the material of the first conductive layer 21 and the second conductive layer 22 may be copper, nickel, tin, gold, silver, copper alloy or copper tin At least one of conductive materials such as alloys. The first conductive layer 21 and the second conductive layer 22 can be formed by a physical vapor deposition process combined with an electroplating process, or a patterning process can be used to form the first conductive layer 21 including a first pad 211, and the second conductive layer 22 including a second pad 221.

As shown in FIG. 2a, the first insulating layer 11 covers the first surface 1 of the substrate, the first insulating layer 11 is provided with a first opening 111, and the part of the first conductive layer 21 that overlaps the first opening 111 serves as the first垫211. The second insulating layer 12 covers the second surface 2 of the substrate. The second insulating layer 12 is provided with a second opening 121, and the part of the second conductive layer 22 that overlaps the second opening 121 serves as the second pad 221. The second surface 2 is opposite to the first surface 1.

When preparing the first insulating layer 11, a thin film layer formed on the side of the first conductive layer 21 away from the core layer 50 can be formed by a pressing process, the thin film layer completely covers the first conductive layer 21, and further by laser drilling or mechanical The drilling process respectively forms a first opening 111 (also referred to as a window in the art) that penetrates the film layer along the thickness direction of the substrate in the film layer to prepare the first insulating layer 11. Wherein, when the first insulating layer 11 is prepared, the portion of the first conductive layer 21 exposed by the first opening 111 is the aforementioned first pad 211. The preparation method of the second insulating layer 12 is the same as the preparation method of the first insulating layer 11. When the second insulating layer 12 is prepared, the portion of the second conductive layer 22 exposed by the second opening 121 is the aforementioned second pad 221.

The material of the first insulating layer 11 may be green oil, or the material of the first insulating layer 11 is a solid thermal curing dielectric polymer. When the material of the first insulating layer 11 is a solid thermosetting dielectric polymer, for example, the first insulating layer 11 is one of prepreg, polyimide film, polybenzoxazole film, BT film, ABF film, etc. Kind. The material of the second insulating layer 12 is the same as the material of the first insulating layer 11.

The first conductive stop 41 blocks the bottom of the first opening 111, the first conductive stop 41 is electrically connected to the first pad 211, and the height h1 of the first conductive stop 41 in the first opening 111 is smaller than that of the first opening 111. Depth h2. The material of the first conductive block 41 may include copper or copper alloy, for example, and the first conductive block 41 may be formed by, for example, electroless plating and electroplating processes.

As shown in FIG. 4, a process of forming the first conductive block 41 through electroless plating and electroplating is illustrated. First, a thinner metal layer 411 is formed on the surface of the first insulating layer 11 away from the core layer 50 as the seed layer of electroless plating, and then a thicker copper film layer 412 is electroplated to cover the surface of the metal layer 411 away from the second layer. The surface of an insulating layer 11 is then etched away from the copper film layer 412 and the metal layer 411 except for the area directly opposite to the first pad 211, thereby forming the first conductive block 41.

As shown in FIG. 5, another process of forming the first conductive block 41 through electroless plating and electroplating is illustrated. First, a thinner metal layer 411 is formed on the first insulating layer 11 as a seed layer for electroless plating. Then, a dry film 413 is pasted on the surface of the metal layer 411 away from the first insulating layer 11, and then the dry film 413 performs exposure, development and other processes to expose the first opening 111. After that, electroplating fills the first opening 111. Finally, the dry film 413 is peeled off, and the metal layer 411 is etched away except for the area directly opposite to the first pad 211 The portion of the metal layer 411 that is directly opposite to the first pad 211 and the electroplated filled portion form the first conductive stop 41.

Example two

The difference between the second example and the first example is: as shown in FIG. 6, the substrate further includes a second conductive stopper 42, which blocks the bottom of the second opening 121, and the second conductive stopper 42 is located on the second pad 221 is away from the core layer 50 side; the second conductive stopper 42 is electrically connected to the second pad 221, and the height h3 of the second conductive stopper 42 in the second opening 121 is smaller than the depth h4 of the second opening 121.

It can be understood that the bottom of the second opening 121 refers to a position where the second opening 121 is close to the second pad 221. In some embodiments, the second conductive stopper 42 is also in contact with the sidewall of the second opening 121.

The material of the second conductive block 42 may include copper or copper alloy, for example, and the second conductive block 42 may be formed by, for example, electroless plating and electroplating processes.

Wherein, as shown in FIG. 6, the substrate may include a second conductive layer 22 disposed inside the second insulating layer 12, and the second conductive layer 22 includes a second pad 221.

By arranging a second conductive stopper 42 in the second opening 121 penetrating the second insulating layer 12, and making the second conductive stopper 42 block the bottom of the second opening 121, in the packaging process, the solder and the first The two conductive stoppers 42 are connected, and the melted solder hardly flows between the second insulating layer 12 and the second pad 221, and no horizontal growth is formed between the second insulating layer 12 and the second pad 221 In the IMC, there will be no cracks on the second insulating layer 12, thereby avoiding the problem of interconnection of adjacent conductive structures due to the flow of solder, and improving the reliability of the entire device. In addition, since the second conductive stopper 42 is electrically connected to the second pad 221, the second conductive stopper 42 can be regarded as a part of the second pad 211, which is equivalent to increasing the thickness of the second pad 211, thereby The resistance to electromigration of the second pad 221 can be improved, and after the substrate and the chip of the present application are packaged, the reliability of the package structure under stress and high power consumption can be improved. Moreover, since the height h3 of the second conductive stopper 42 in the second opening 121 is smaller than the depth h4 of the second opening 121, the solder can sink into the second opening 121 of the second insulating layer 12, and therefore, the suction of the substrate can be improved. Soldering volume, to better buffer the thermal expansion coefficient mismatch between the chip and the substrate, reduce the overall stress of the package, in addition, it can also avoid the sliding misalignment during the preset solder ball setting process and the misalignment in the subsequent soldering process , Resulting in virtual soldering and affecting the overall chip mounting yield.

Example three

The third example is different from the first example in that: as shown in FIG. 7, the substrate does not include the core layer 50.

As shown in FIG. 7, the substrate includes a second insulating layer 12, a second conductive layer 22, a redistribution layer (RDL) 60, a first conductive layer 21, and a first insulating layer, which are sequentially stacked along the thickness direction of the substrate. The layer 11 and the first conductive block 41.

Wherein, the second insulating layer 12 is provided with a second opening 121 passing through the second insulating layer 12 in the thickness direction of the substrate, and the portion of the second conductive layer 22 overlapping the second opening 121 serves as the second pad 221. The first insulating layer 11 is provided with a first opening 111 penetrating the first insulating layer 11 in the thickness direction of the substrate, and a portion of the first conductive layer 21 that overlaps the first opening 111 serves as a first pad 211.

The first conductive block 41 blocks the bottom of the first opening 111 and is electrically connected to the first pad 211. The height h1 of the first conductive block 41 in the first opening 111 is smaller than the depth h2 of the first opening 111.

As shown in FIG. 7, the redistribution layer 60 includes a multilayer dielectric layer 63 and a multilayer metal wiring layer 64 (FIG. 7 takes the redistribution layer 60 including four dielectric layers 63 and three metal wiring layers 64 as an example for illustration ). Among them, the metal wiring layer 64 and the dielectric layer 63 are alternately arranged, and the multilayer metal wiring layer 64 constitutes the metal circuit structure of the substrate.

It can be understood that, in order to avoid short circuits, the first conductive layer 21 can be in contact with the dielectric layer 63 in the redistribution layer 60. Similarly, the second conductive layer 22 can be in contact with the dielectric layer 63 in the redistribution layer 60. contact. Of course, an insulating layer can also be provided between the redistribution layer 60 and the first conductive layer 21. In this case, the outermost layer of the redistribution layer 60 close to the first conductive layer 21 can be the dielectric layer 63 or Metal wiring layer 64. Similarly, an insulating layer can be provided between the redistribution layer 60 and the second conductive layer 22. In this case, the outermost layer of the redistribution layer 60 close to the second conductive layer 22 can be the dielectric layer 63 or Metal wiring layer 64.

Each dielectric layer 63 is provided with a via for electrically connecting two adjacent metal wiring layers 64, wherein the dielectric layer 63 close to the first conductive layer 21 is provided with a via for connecting the first conductive layer 21 with the The metal wiring layer 64 contacting the dielectric layer 63 is electrically connected to a via hole, and the dielectric layer 63 close to the second conductive layer 22 is provided with a metal wiring layer 64 for connecting the second conductive layer 22 and the dielectric layer 63 Vias for electrical connections.

In this case, when the substrate is prepared, a detachable carrier is used as a carrier to produce a core-free 50 substrate.

In this example, since the substrate does not have the core layer 50, the flexibility of the substrate is relatively high, which can be applied to a highly flexible packaging structure.

Example four

The difference between Example 4 and Example 3 is that: as shown in FIG. 8, the substrate further includes a second conductive stopper 42, which blocks the bottom of the second opening 121 and is located on the second pad 221 away from the core layer 50. On one side, the second conductive block 42 is electrically connected to the second pad 221, and the height h3 of the second conductive block 42 in the second opening 121 is smaller than the depth h4 of the second opening 121.

Example 5

Example 5 is different from Example 1 and Example 3 in that: the first conductive stopper 41 includes a body layer and a protective layer covering the body layer.

The material of the body layer is copper or copper alloy. The protective layer is obtained by performing a surface treatment process on the body layer. The material of the protective layer is related to the specific surface treatment process. The surface treatment process includes chemical tin, chemical nickel gold, chemical nickel palladium gold, chemical silver and so on.

Taking the chemical nickel-palladium-gold process to perform surface treatment on the body layer to obtain a protective layer as an example, the obtained protective layer includes a stacked nickel film layer, a palladium film layer, and a gold film layer.

By making the first conductive block 41 include a body layer and a protective layer covering the body layer, the protective layer can protect the surface of the body layer from contamination and oxidation, so as to ensure the stability of component welding.

Example 6

The sixth example is different from the second and fourth examples in that the second conductive stopper 42 includes a body layer and a protective layer covering the body layer.

The material of the body layer is copper or copper alloy. The protective layer is obtained by surface treatment of the body layer. The material of the protective layer is related to the specific surface treatment process. The surface treatment process includes chemical tin, chemical nickel gold, chemical nickel palladium gold , Chemical silver, etc.

By making the second conductive block 42 include a body layer and a protective layer covering the body layer, the surface of the body layer can be protected from contamination and oxidation, so as to ensure the stability of component welding.

It should be noted that during the packaging process of the substrate and the chip, the first solder connects the chip and the first conductive stop 41 of the substrate, and the method of forming the first solder includes pre-molded solder balls, printed solder paste and electroplated solder paste, etc. . On this basis, in the package structure, the PCB board and the second conductive block 42 can be connected by the second solder. The method of forming the second solder includes pre-molded solder balls, printing tin paste and electroplating tin paste.

An embodiment of the present application also provides a method for preparing a package structure, including forming a chip and a substrate for carrying the chip. As shown in FIG. 9, forming the substrate includes:

S10, forming a first conductive layer 21.

The first conductive layer 21 can be formed by a physical vapor deposition process combined with an electroplating process, or a patterning process. The material of the first conductive layer 21 can be copper, nickel, tin, gold, silver, copper alloy or copper-tin alloy. At least one of the materials.

Taking the substrate shown in FIG. 6 as an example, S10 may be: as shown in FIG. 10, the first conductive layer 21 is formed on the side of the first redistribution layer 61 away from the core layer 50.

S20, as shown in FIGS. 11a and 11b, a first thin film layer 112 is formed, and a first thin film layer 112 is formed in the first thin film layer 112 in the thickness direction of the substrate through a laser drilling or mechanical drilling process. The opening 111 is used to form a first insulating layer 11 covering the first surface 1 of the substrate; wherein the first opening 111 exposes a part of the first conductive layer 21 as a first pad 211.

Wherein, the material of the first film layer 112 may be a solid-state thermal curing dielectric polymer.

S30. As shown in FIG. 12, the first conductive stop 41 is formed through an electroless plating process and an electroplating process, the first conductive stop 41 blocks the bottom of the first opening 111, and the first conductive stop 41 and the first pad 211 Electrical connection; wherein the height h1 of the first conductive block 41 in the first opening 111 is smaller than the depth h2 of the first opening 111.

In the present application, a first opening 111 penetrating the first thin film layer 112 in the thickness direction of the substrate is formed in the thin film layer 112 through a laser drilling or mechanical drilling process, exposing the first pad 211. Further, the electroless plating process and the electroplating process are used to form the first conductive block 41, and the thickness of the first conductive block 41 can be adjusted as required, which has a wide range of applications. However, if the first conductive block 41 is made by grinding technology, the structure of the present invention cannot be obtained.

It can be understood that when the substrate includes the core layer 50, the film layers on both sides of the core layer 50 are simultaneously formed during the preparation process. In the embodiment of the present application, in order to highlight the formation process of the first conductive block 41, FIGS. 10-12 only illustrate the film layer related to the first conductive block 41 on the side of the core layer 50.

On this basis, optionally, as shown in FIG. 13, the preparation method of the substrate further includes:

S40, using at least one surface treatment process of chemical tin, chemical nickel gold, chemical nickel palladium gold, and chemical silver to process the surface of the first conductive block 41 away from the first pad 211.

In this case, the first conductive block 41 includes a body layer and a protective layer covering the body layer, and the body layer is subjected to surface treatment to obtain the protective layer.

After surface treatment is performed on the first conductive stop 41, the body layer of the first conductive stop 41 can be protected from contamination and oxidation, so as to ensure the stability of component welding.

On this basis, optionally, as shown in FIG. 14, the preparation method of the substrate further includes:

S50, forming a second conductive layer 22 on the side of the first conductive layer 21 away from the first surface 1 of the substrate.

Wherein, as shown in FIG. 15a, the second conductive layer 22 is prepared before the first insulating layer 11 is prepared, and the process used may be the same as the process used when preparing the first conductive layer 21.

S60, as shown in FIGS. 15b and 15c, a second thin film layer 122 is formed, and a second thin film layer 122 is formed in the second thin film layer 122 along the thickness direction of the substrate through a laser drilling or mechanical drilling process. The opening 121 is used to form a second insulating layer 12 covering the second surface of the substrate opposite to the first surface; wherein, the second opening 121 exposes a part of the second conductive layer 22 as the second pad 221.

Wherein, as shown in FIG. 15b, the second thin film layer 122 covering the second conductive layer 22 is prepared before the first conductive stop 41 is prepared, and the process used can be the same as that used when preparing the first thin film layer 112. The process is the same.

The material of the second film layer 122 may be a solid-state thermal curing dielectric polymer.

On this basis, as shown in Figure 16, the preparation method of the substrate further includes:

S70. As shown in FIG. 6, a second conductive stopper 42 is formed through an electroless plating process and an electroplating process, the second conductive stopper 42 blocks the bottom of the second opening 121, and the second conductive stopper 42 and the second pad 221 Electrical connection; wherein the height h3 of the second conductive block 42 in the second opening 121 is smaller than the depth h4 of the second opening 121.

In the present application, a laser drilling or mechanical drilling process is used to form a second opening 121 in the second thin film layer 122 in the thickness direction of the substrate to penetrate the second thin film layer 122 to expose the second pad 221. Further, an electroless plating process and an electroplating process are used to form the second conductive stopper 42, and the thickness of the second conductive stopper 42 can be adjusted as required, which has a wide range of applications.

On this basis, as shown in Figure 17, the preparation method of the substrate further includes:

S80, using at least one surface treatment process of chemical tin, chemical nickel gold, chemical nickel palladium gold, and chemical silver to process the surface of the second conductive block 42 away from the second pad 221.

In this case, the second conductive block 42 includes a body layer and a protective layer covering the body layer, and the body layer is subjected to surface treatment to obtain the protective layer.

After the surface treatment of the second conductive stopper 42 is performed, the body layer of the second conductive stopper 42 can be protected from contamination and oxidation, so as to ensure the stability of component welding.

The embodiment of the present application also provides a package structure, including a chip, and a substrate for carrying the chip. As shown in FIG. 18 and FIG. 19, the first surface 1 of the substrate is covered with a first insulating layer 11, and the substrate is in the first insulating layer. The inner side of the layer 11 is provided with a first pad 211; the first insulating layer 11 is provided with a first opening 111, and the bottom of the first opening 111 leads to the first pad 211.

The second surface 2 of the substrate opposite to the first surface 1 is covered with a second insulating layer 12. The substrate is provided with a second pad 221 inside the second insulating layer 12; a second opening 121 is provided on the second insulating layer 12, The bottom of the second opening 121 leads to the second pad 221.

The substrate further includes a first conductive block 41 and a second conductive block 42. The first conductive block 41 blocks the bottom of the first opening 111, and the first conductive block 41 is electrically connected to the first pad 211; The block 42 blocks the bottom of the second opening 121, and the second conductive block 42 is electrically connected to the second pad 221.

Optionally, as shown in FIGS. 18 and 19, the height h1 of the first conductive block 41 in the first opening 111 is greater than the depth h2 of the first opening 111.

Optionally, as shown in FIGS. 18 and 19, the height h3 of the second conductive stopper 42 in the second opening 121 is greater than the depth h4 of the second opening 121.

18 illustrates a substrate including a core layer 50, a first redistribution layer 61 is provided between the core layer 50 and the first conductive layer 21, and a second redistribution layer is provided between the core layer 50 and the second conductive layer 22 Layer 62. FIG. 19 illustrates a substrate without a core layer 50, and a redistribution layer 60 is directly arranged between the first conductive layer 21 and the second conductive layer 22. The first rewiring layer 61, the second rewiring layer 62, and the rewiring layer 60 all include a multilayer dielectric layer 63 and a multilayer metal wiring layer 64. The metal wiring layer 64 and the dielectric layer 63 are alternately arranged, and the multilayer metal wiring The layer 64 constitutes the metal circuit structure of the substrate.

By providing the first conductive stop 41 and the second conductive stop 42 on the two surfaces of the substrate, the electromigration resistance of the first pad 211 and the second pad 221 can be improved, and the substrate and the chip of the present application can be electrically connected. The connection can improve the reliability of the package structure under stress and high power consumption.

Optionally, the material of the first insulating layer 11 is a solid thermally cured dielectric polymer. For example, the first insulating layer 11 is one of a prepreg, a polyimide film, a polybenzoxazole film, a BT film, an ABF film, and the like. The material of the second insulating layer 12 is the same as the material of the first insulating layer 11.

Optionally, the first conductive block 41 includes a body layer, and the material of the body layer is copper or copper alloy. The second conductive block 42 includes a body layer, and the material of the body layer is copper or copper alloy.

Optionally, the first conductive block 41 includes a body layer and a protective layer, the body layer is electrically connected to the first pad 211, the protective layer is located on the side of the body layer away from the first pad 211, and the protective layer covers the body layer to protect The layer is used to prevent oxidation of the body layer.

The second conductive block 42 includes a body layer and a protection layer. The body layer is electrically connected to the second pad 221. The protection layer is located on the side of the body layer away from the second pad 221, and the protection layer covers the body layer. The body layer is oxidized.

It should be noted that during the packaging process of the substrate and the chip, the first solder connects the chip and the first conductive stop 41 of the substrate, and the method of forming the first solder includes printing tin paste and electroplating tin paste. On this basis, in the package structure, the PCB board and the second conductive block 42 can be connected by the second solder, and the method of forming the second solder includes printing tin paste and electroplating tin paste.

The embodiment of the present application also provides a method for preparing a package structure, including forming a chip and a substrate for carrying the chip; preparing the substrate as shown in FIG. 18 or FIG. 19, as shown in FIG. 20, the method for preparing the substrate include:

S100, respectively forming a first conductive layer 21 and a second conductive layer 22 stacked in the thickness direction of the substrate.

Taking the substrate shown in Figure 19 as an example, for example, S100 includes:

As shown in Figure 21, the copper foil layer and the support plate 70 are pressed together to fix the copper foil layer on the front and back sides of the support plate 70 respectively; the copper foil layer includes a support copper foil 80 and a support copper foil 80. The ultra-thin copper foil 90 and the supporting copper foil 80 are in contact with the supporting plate 70.

After that, a second conductive layer 22 is formed on the surface of each layer of ultra-thin copper foil 90 away from the support plate 70.

The second conductive layer 22 can be formed by a physical vapor deposition process combined with an electroplating process, or a patterning process. The material of the second conductive layer 22 can be copper, nickel, tin, gold, silver, copper alloy or copper-tin alloy. Wait.

Then, a rewiring layer 60 is formed on the surface of each second conductive layer 22 away from the support plate 70.

For example, the redistribution layer 60 can be formed by the following process: firstly, a dielectric layer 63 is laminated on the surface of the second conductive layer 22, and the dielectric layer 63 includes blind vias; on the surface of the dielectric layer 63 away from the support plate 70 The metal wiring layer 64 is formed, and in this way, the multilayer dielectric layer 63 and the metal wiring layer 64 are repeatedly formed.

After the rewiring layer 60 is formed, the first conductive layer 21 is formed on the surface of the rewiring layer 60 away from the support plate 70.

Next, as shown in FIG. 22, the ultra-thin copper foil 90 is peeled off from the supporting copper foil 80.

Two substrates can be prepared at one time through the above process. The following takes one substrate as an example for illustration, and the preparation process of the two substrates is the same.

Then, as shown in FIG. 23, the ultra-thin copper foil 90 is removed by etching.

S200. As shown in FIG. 24, a first thin film layer is formed on the surface of the first conductive layer 21 away from the second conductive layer 22, and formed in the first thin film layer through a laser drilling or mechanical drilling process along the thickness direction of the substrate. The first opening 111 of the first thin film layer is used to form a first insulating layer 11 covering the first surface 1 of the substrate; wherein, the first opening 111 exposes a part of the first conductive layer 21 as the first pad 211.

S300. As shown in FIG. 24, a second thin film layer is formed on the surface of the second conductive layer 22 away from the first conductive layer 21, and formed in the second thin film layer through a laser drilling or mechanical drilling process along the thickness direction of the substrate. The second opening 121 of the second film layer forms a second insulating layer 12 covering the second surface 2 of the substrate opposite to the first surface 1; wherein, the second opening 121 exposes a portion of the second conductive layer 22 As the second pad 221.

S400. As shown in FIG. 19, the first conductive stop 41 is formed by an electroplating process or an electroless plating process. The first conductive stop 41 blocks the bottom of the first opening 111 and the first conductive stop 41 is electrically connected to the first pad 211. connection.

S500. As shown in FIG. 19, the second conductive stopper 42 is formed by an electroplating process or an electroless plating process. The second conductive stopper 42 blocks the bottom of the second opening 121 and the second conductive stopper 42 is electrically connected to the second pad 221. connection.

In some embodiments, the height h1 of the first conductive stop 41 in the first opening 111 is greater than the depth h2 of the first opening 111.

In some embodiments, the height h3 of the second conductive stopper 42 in the second opening 121 is greater than the depth h4 of the second opening 121.

Since the first conductive stop 41 is electrically connected to the first pad 211, and the second conductive stop 42 is electrically connected to the second pad 221, the thickness of the first conductive stop 41 and the second conductive stop 42 is increased. , The thickness of the first pad 211 and the second pad 221 is increased to a certain extent, thereby improving the resistance to electromigration of the pad, and packaging the substrate and the chip of the present application can improve the stress and high power consumption of the packaging structure The reliability of the situation.

On this basis, as shown in FIG. 25, the preparation method of the substrate further includes:

S600, using at least one surface treatment process of chemical tin, chemical nickel gold, chemical nickel palladium gold, and chemical silver to process the surface of the first conductive block 41 away from the first pad 211.

S700, using at least one surface treatment process of chemical tin, chemical nickel gold, chemical nickel palladium gold, and chemical silver to process the surface of the second conductive block 42 away from the second pad 221.

In this case, both the first conductive block 41 and the second conductive block 42 include a body layer and a protective layer covering the body layer, and the protective layer is obtained after surface treatment of the body layer.

After surface treatment is performed on the first conductive stop 41 and the second conductive stop 42, the body layer of the first conductive stop 41 and the second conductive stop 42 can be protected from contamination and oxidation, so as to ensure the stability of the welding of components Sex.

The embodiment of the present application also provides a package structure, including a chip and a substrate for carrying the chip, as shown in FIG. 2a, FIG. 2b, FIG. 6, FIG. 7, FIG. 8, FIG. 18, and FIG. The surface 1 is covered with a first insulating layer 11, the substrate is provided with a first pad 211 inside the first insulating layer 11; a first opening 111 is provided on the first insulating layer 11, and the bottom of the first opening 111 leads to the first Pad 211; wherein, the first insulating layer 11 is composed of a solid thermally cured dielectric polymer.

The substrate further includes a first conductive stopper 41, the first conductive stopper 41 blocks the bottom of the first opening 111, and the first conductive stopper 41 is electrically connected to the first pad 211.

Optionally, the height h1 of the first conductive block 41 in the first opening 111 is greater than the depth h2 of the first opening 111.

Optionally, the height h1 of the first conductive block 41 in the first opening 111 is equal to the depth h2 of the first opening 111.

Optionally, the height h1 of the first conductive block 41 in the first opening 111 is smaller than the depth h2 of the first opening 111.

In order to prevent the material of the first insulating layer 11 from affecting the formation of the first conductive block 41, in the embodiment of the present application, a solid thermosetting dielectric polymer material is used instead of green oil as the material of the first insulating layer 11. For example, during processing, electroplating and electroless plating processes are selected to generate the first conductive stop 41 on the first pad 211. When electroplating and electroless plating are used to generate the first conductive stop 41, if the first insulating layer 11 made of green oil continues to be used, the plating solution may be contaminated due to foreign matter generated on the surface of the green oil, which affects electroplating or chemical plating. The quality of plating.

Optionally, the first insulating layer 11 is one of a prepreg, a polyimide film, a polybenzoxazole film, a bismaleimide-triazine resin film, and a ceramic powder reinforced modified epoxy resin film .

Optionally, as shown in FIGS. 6, 8, 18 and 19, the second surface 2 of the substrate opposite to the first surface 1 is covered with a second insulating layer 12, and the substrate is provided with The second pad 221; the second insulating layer 12 is provided with a second opening 121, and the bottom of the second opening 121 leads to the second pad 221; wherein the second insulating layer 12 is made of a solid thermally cured dielectric polymer.

The substrate further includes a second conductive stopper 42, the second conductive stopper 42 blocks the bottom of the second opening 121, and the second conductive stopper 42 is electrically connected to the second pad 221.

Optionally, the height h3 of the second conductive block 42 in the second opening 121 is greater than the depth h4 of the second opening 121.

Optionally, the height h3 of the second conductive block 42 in the second opening 121 is equal to the depth h4 of the second opening 121.

Optionally, the height h3 of the second conductive block 42 in the second opening 121 is smaller than the depth h4 of the second opening 121.

In order to avoid the material of the second insulating layer 12 from affecting the formation of the second conductive block 42, in the embodiment of the present application, a solid thermosetting dielectric polymer material is used instead of green oil as the material of the second insulating layer 12.

Optionally, the second insulating layer 12 is one of a prepreg, a polyimide film, a polybenzoxazole film, a bismaleimide-triazine resin film, and a ceramic powder reinforced modified epoxy resin film .

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention. It should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

A packaging structure comprising a chip and a substrate for carrying the chip, characterized in that the first surface of the substrate is covered with a first insulating layer;

The substrate is provided with a first pad on the inner side of the first insulating layer, a first opening is provided on the first insulating layer, and the bottom of the first opening leads to the first pad;

The substrate further includes a first conductive stopper, the first conductive stopper blocks the bottom of the first opening, and the first conductive stopper is electrically connected to the first pad;

Wherein, the height of the first conductive block in the first opening is smaller than the depth of the first opening.
The package structure of claim 1, wherein the first surface is a surface of the substrate close to the chip.
The package structure according to claim 1 or 2, wherein the substrate further comprises a first conductive layer disposed inside the first insulating layer, and the first conductive layer includes the first pad.
The package structure according to any one of claims 1 to 3, wherein the first conductive stopper is also in contact with the sidewall of the first opening.
The package structure according to any one of claims 1 to 4, wherein the first insulating layer is composed of a solid thermal curing dielectric polymer.
The package structure according to any one of claims 1-5, wherein the first insulating layer is a prepreg, a polyimide film, a polybenzoxazole film, a bismaleimide-triazine Resin film or ceramic powder reinforced modified epoxy resin film.
The package structure according to any one of claims 1 to 6, wherein the first conductive stopper comprises a body layer, and a material of the body layer comprises copper or copper alloy.
The package structure according to claim 7, wherein the first conductive stopper further comprises a protective layer located on a side of the body layer away from the first pad, the protective layer covering the body layer ; The protective layer is used to prevent oxidation of the body layer.
The package structure according to any one of claims 1-8, wherein the second surface of the substrate opposite to the first surface is covered with a second insulating layer, and the inside of the second insulating layer is provided with The second pad;

A second opening is provided on the second insulating layer, and the bottom of the second opening leads to the second pad.
The package structure according to claim 9, wherein the substrate further comprises a second conductive stopper, the second conductive stopper blocks the bottom of the second opening, and the second conductive stopper is in contact with the The second pad is electrically connected;

Wherein, the height of the second conductive block in the second opening is smaller than the depth of the second opening.
9. The packaging structure of claim 9, wherein the substrate is a packaging substrate, and the packaging substrate further comprises a redistribution layer disposed between the first pad and the second pad.
The package structure according to claim 9, wherein the substrate is a package substrate, and the package substrate further comprises:

A core layer provided between the first pad and the second pad;

A first rewiring layer provided between the core layer and the first pad;

A second rewiring layer provided between the core layer and the second pad.
A package structure comprising a chip and a substrate for carrying the chip, wherein the first surface of the substrate is covered with a first insulating layer; the substrate is provided with A first pad; a first opening is provided on the first insulating layer, and the bottom of the first opening leads to the first pad;

The second surface of the substrate opposite to the first surface is covered with a second insulating layer; the substrate is provided with a second pad inside the second insulating layer; and the second insulating layer is provided with a Two openings, the bottom of the second opening leads to the second pad;

The substrate further includes a first conductive stopper and a second conductive stopper; the first conductive stopper blocks the bottom of the first opening, and the first conductive stopper is electrically connected to the first pad; The second conductive stopper blocks the bottom of the second opening, and the second conductive stopper is electrically connected to the second pad.
The package structure according to claim 13, wherein the height of the first conductive block in the first opening is greater than the depth of the first opening;

and / or,

The height of the second conductive block in the second opening is greater than the depth of the second opening.
A method for preparing a package structure includes forming a chip and a substrate for carrying the chip; characterized in that, forming the substrate includes:

Forming a first conductive layer;

A first thin film layer covering the first conductive layer is formed, and a first opening is formed on the first thin film layer through a laser drilling or mechanical drilling process to form a first film covering the first surface of the substrate An insulating layer; wherein the first opening exposes a part of the first conductive layer as a first pad;

A first conductive stopper is formed by an electroless plating process and an electroplating process, the first conductive stopper blocks the bottom of the first opening, and the first conductive stopper is electrically connected to the first pad; wherein The height of the first conductive block in the first opening is smaller than the depth of the first opening.
The preparation method according to claim 15, wherein forming the substrate further comprises:

At least one surface treatment process of chemical tin, chemical nickel gold, chemical nickel palladium gold, chemical silver is used to process the surface of the first conductive block away from the first pad.
The preparation method according to claim 15, wherein forming the substrate further comprises:

Forming a second conductive layer on the side of the first conductive layer away from the first surface of the substrate;

A second thin film layer covering the second conductive layer is formed, and a second opening is formed on the second thin film layer through a laser drilling or mechanical drilling process to form a covering on the substrate opposite to the first surface The second insulating layer on the second surface of the second surface; wherein the second opening exposes a part of the second conductive layer as a second pad;

A second conductive stopper is formed through an electroless plating process and an electroplating process, the second conductive stopper blocks the bottom of the second opening, and the second conductive stopper is electrically connected to the second pad; wherein, The height of the second conductive block in the second opening is smaller than the depth of the second opening.
A method for preparing a package structure includes forming a chip and a substrate for carrying the chip; characterized in that, forming the substrate includes:

Respectively forming a first conductive layer and a second conductive layer stacked along the thickness direction of the substrate;

A first thin film layer is formed on the surface of the first conductive layer away from the second conductive layer, and a first opening is formed on the first thin film layer by a laser drilling or mechanical drilling process to form a cover on the surface A first insulating layer on the first surface of the substrate; wherein the first opening exposes a part of the first conductive layer as a first pad;

A second thin film layer is formed on the surface of the second conductive layer away from the first conductive layer, and a second opening is formed on the second thin film layer through a laser drilling or mechanical drilling process to form a covering on the surface A second insulating layer on a second surface of the substrate opposite to the first surface; wherein the second opening exposes a part of the second conductive layer as a second pad;

Forming a first conductive stopper through an electroless plating process and an electroplating process, the first conductive stopper blocks the bottom of the first opening, and the first conductive stopper is electrically connected to the first pad;

A second conductive stopper is formed through an electroless plating process and an electroplating process, the second conductive stopper blocks the bottom of the second opening, and the second conductive stopper is electrically connected to the second pad.
The manufacturing method according to claim 18, wherein the height of the first conductive block in the first opening is greater than the depth of the first opening;

and / or,

The height of the second conductive block in the second opening is greater than the depth of the second opening.
A packaging structure comprising a chip and a substrate for carrying the chip, characterized in that the first surface of the substrate is covered with a first insulating layer;

The substrate is provided with a first pad on the inner side of the first insulating layer, a first opening is provided on the first insulating layer, and the bottom of the first opening leads to the first pad;

The substrate further includes a first conductive stopper, the first conductive stopper blocks the bottom of the first opening, and the first conductive stopper is electrically connected to the first pad;

Wherein, the first insulating layer is composed of a solid thermal curing dielectric polymer.
The package structure of claim 20, wherein the first insulating layer is a prepreg, polyimide film, polybenzoxazole film, bismaleimide-triazine resin film, or ceramic powder One of the reinforced modified epoxy resin films.