WO2020155217A1 - 驱动方法、显示面板和驱动电路 - Google Patents

驱动方法、显示面板和驱动电路 Download PDF

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WO2020155217A1
WO2020155217A1 PCT/CN2019/075516 CN2019075516W WO2020155217A1 WO 2020155217 A1 WO2020155217 A1 WO 2020155217A1 CN 2019075516 W CN2019075516 W CN 2019075516W WO 2020155217 A1 WO2020155217 A1 WO 2020155217A1
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Prior art keywords
pixel
gate line
gate
time
low level
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English (en)
French (fr)
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单剑锋
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HKC Co Ltd
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HKC Co Ltd
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Priority to US16/461,369 priority Critical patent/US11386862B2/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • This application relates to the field of display technology, and in particular to a driving method, a display panel, and a driving circuit.
  • Flat panel displays include Thin Film Transistor-Liquid Crystal Display (TFT-LCD) and Organic Light-Emitting Diode (OLED) displays.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • the thin film transistor liquid crystal display refracts the light from the backlight module to produce a picture by controlling the rotation direction of the liquid crystal molecules, and has many advantages such as thin body, power saving, and no radiation.
  • the organic light emitting diode display is made of organic electroluminescent diodes, and has many advantages such as self-luminescence, short response time, high definition and contrast, flexible display and large-area full-color display.
  • the present application provides a driving method, a display panel, and a driving circuit that can solve the flicker of the display screen.
  • the present application also discloses a driving method applied to a display panel.
  • the display panel includes a plurality of data lines, a plurality of gate lines, and a plurality of pixels.
  • the gate lines and the data lines are formed alternately.
  • Each pixel is driven by a corresponding data line and a gate line, and each pixel includes a corresponding pixel electrode;
  • the driving method includes a step of outputting a gate driving signal to a gate line corresponding to the display panel;
  • one signal period of the gate drive signal includes a sustain time, an open time, and a first pull-down time adjacent to the open time; the gate drive signal is at the first low level during the sustain time; The gate drive signal is at a high level during the on time; the gate drive signal is at a second low level during the first pull-down time; the voltage value of the second low level is lower than the first Low level voltage value.
  • the first pull-down time is before the turn-on time
  • one signal period of the gate drive signal further includes a second pull-down time after the turn-on time
  • the gate drive signal is at the second pull-down time
  • the time is the third low level
  • the voltage value of the third low level is lower than the voltage value of the first low level.
  • the first pull-down time and the open time period are equal.
  • the first pull-down time and the turn-on time duration are equal; when the gate drive signal of the previous gate line corresponds to the turn-on time, the gate drive signal of the current gate line Corresponds to the first pull-down time.
  • the opening time and the second pull-down time duration are equal.
  • the turn-on time and the second pull-down time period are equal; when the gate drive signal of the previous gate line corresponds to the second pull-down time, the gate drive signal of the current gate line corresponds to the Open time.
  • the voltage value of the second low level is equal to the voltage value of the third low level.
  • each pixel includes a pixel electrode, the same gate line connects two adjacent pixels to form a pixel group, and the pixel group includes a first pixel and a second pixel connected to different data lines;
  • the pixel electrode of the first pixel of the pixel group overlaps the previous gate line to form a first overlap region; the area of the first overlap region is S1, and the first overlap of the first pixel
  • the storage capacitor formed by overlapping the region and the previous gate line is Cst1, the pixel capacitance of the first pixel is Clc1, and the parasitic capacitance formed by the pixel electrode of the first pixel and the current gate line is Cgs1;
  • the pixel electrode of the second pixel of the pixel group overlaps the next gate line to form a second overlap region; the area of the second overlap region is S2, and the second overlap region of the second pixel
  • the storage capacitance formed by overlapping with the next gate line is Cst2, the pixel capacitance of the second pixel is Clc2, and the parasitic capacitance formed by the pixel electrode of the second pixel and the current gate line is Cgs2;
  • the voltage value of the third low level is V'GL
  • the voltage value of the high level is VGH
  • the voltage value of the second low level is VGL;
  • Cst2 (VGH-VGL)*Cgs2/ (VGL-V'GL).
  • the application also discloses a display panel using the above driving method, wherein the display panel includes a plurality of data lines, a plurality of gate lines and a plurality of pixels, and the gate lines and the data lines are interlaced with each other Formed, a plurality of pixels are respectively driven by corresponding data lines and gate lines, and each pixel includes a corresponding pixel electrode; the same gate line connects two adjacent pixels to form a pixel group, and the pixel group includes The first pixel and the second pixel connected by different data lines; wherein the pixel electrode of the first pixel of the pixel group overlaps with the previous gate line to form a first overlapping area; the second pixel of the pixel group The pixel electrode overlaps the next gate line to form a second overlap area.
  • the gate line includes a main gate line and an auxiliary gate line that are connected to each other, and the main gate line is perpendicular to the auxiliary gate line.
  • the auxiliary gate line includes a first auxiliary gate line and a second auxiliary gate line, and the first auxiliary gate line and the second auxiliary gate line are arranged in parallel.
  • the gate line includes a main gate line and an auxiliary gate line that are connected to each other, the main gate line and the data line are intersected, and the auxiliary gate line is parallel to the data line Set up.
  • a first safety distance is set between the auxiliary gate line and the pixel electrode of the first pixel corresponding to the current main gate line and between the pixel electrode of the second pixel corresponding to the previous main gate line .
  • a second safety distance is provided between the auxiliary gate line and the corresponding data line.
  • the pixel electrode of the second pixel corresponding to the first auxiliary gate line and the previous gate line forms a first overlapping area
  • the second auxiliary gate line corresponds to the next gate line
  • the pixel electrode of the first pixel forms a second overlapping area
  • the area of the first overlapping area is S1
  • the area of the second overlapping area is S2.
  • the present application also discloses a driving circuit that drives the display panel as described above, and the driving circuit includes a gate driving circuit that outputs a gate driving signal to the gate line corresponding to the display panel; wherein One signal period of the gate drive signal output by the gate drive circuit includes: a sustain time, an open time, and a first pull-down time adjacent to the open time; the gate drive signal is the first during the sustain time Low level; the gate drive signal is at a high level during the on time; the gate drive signal is at a second low level during the first pull-down time; the voltage value of the second low level is lower than The voltage value of the first low level.
  • the first pull-down time is before the turn-on time
  • one signal period of the gate drive signal further includes a second pull-down time after the turn-on time
  • the gate drive signal is at the second pull-down time
  • the time is the third low level
  • the voltage value of the third low level is lower than the voltage value of the first low level.
  • a period of each gate driving signal of the present application includes three time periods, namely the maintenance time, the turn-on time and the first down time. Pull-down time, the first pull-down time is adjacent to the turn-on time, the gate drive signal is the first low level during the maintenance time, the high level during the open time, and the second low level during the pull-down time. There is a parasitic capacitance Cgs between the line and the pixel electrode.
  • the gate voltage changes through the parasitic capacitance Cgs to redistribute the charge of the liquid crystal capacitance and storage capacitor of the pixel, so that the charged voltage of the original pixel is reversed.
  • the voltage value of the second low level during the first pull-down time is less than the voltage value of the first low level during the sustain time, and the first pull-down time is used to adjust the pixel electrode and the gate line
  • the reverse voltage generated by the parasitic capacitance between them can reduce or even eliminate the flicker problem.
  • FIG. 1 is an enlarged schematic diagram of a pixel of a display panel according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of a pixel structure circuit of an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a driving waveform with only one pull-down time according to an embodiment of the present application
  • FIG. 4 is a schematic diagram of a driving waveform with two pull-down times according to an embodiment of the present application
  • FIG. 5 is a schematic diagram of a driving waveform of another embodiment of the present application.
  • FIG. 6 is a schematic diagram of a pixel structure of another embodiment of the present application.
  • FIG. 7 is a schematic diagram of a driving circuit of another embodiment of the present application.
  • FIG. 8 is a schematic diagram of a display device according to another embodiment of the present application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating relative importance or implicitly indicating the number of indicated technical features. Therefore, unless otherwise specified, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features; “plurality” means two or more.
  • the term “comprising” and any variations thereof means non-exclusive inclusion, and one or more other features, integers, steps, operations, units, components, and/or combinations thereof may be present or added.
  • connection should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection , It can also be electrical connection; it can be directly connected, it can also be indirectly connected through an intermediate medium, or the internal connection of two components.
  • connection should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection , It can also be electrical connection; it can be directly connected, it can also be indirectly connected through an intermediate medium, or the internal connection of two components.
  • this embodiment discloses a driving method applied to a display panel 110.
  • the display panel 110 includes a plurality of data lines 130, a plurality of gate lines 140, and a plurality of pixels 150.
  • the gate line 130 and the data line 140 are interlaced with each other, a plurality of pixels 150 are driven by the corresponding data line 130 and the gate line 140, and each pixel 150 includes a corresponding pixel electrode;
  • the driving method includes a step of outputting a gate driving signal to a gate line corresponding to the display panel 110;
  • one signal period of the gate drive signal includes the sustain time, the turn-on time, and the first pull-down time adjacent to the turn-on time; referring to FIG. 3, the gate drive signal is the first low level during the sustain time; The time is high level; during the first pull-down time, it is the second low level; the second low level is lower than the first low level.
  • one cycle of each gate drive signal includes three time periods, namely the sustain time, the turn-on time, and the first pull-down time.
  • the first pull-down time is adjacent to the turn-on time, and the gate drive signal is maintaining The time is the first low level, the open time is the high level, and the pull-down time is the second low level.
  • the gate voltage changes through the parasitic capacitance Cgs to redistribute the charge of the liquid crystal capacitance and the storage capacitor of the pixel, so that the charged voltage of the original pixel 150 has a kickback phenomenon.
  • the first pull-down time The voltage value of the second low level within is smaller than the voltage value of the first low level during the sustain time.
  • the gap between the pixel electrode and the gate line 140 is adjusted during the first pull-down time.
  • the reverse voltage generated by the generated parasitic capacitance reduces or even eliminates the flicker problem.
  • the first pull-down time is before the turn-on time; one signal period of the gate drive signal also includes a second pull-down time after the turn-on time; the gate drive signal is at the second pull-down time
  • the time is the third low level; the voltage value of the third low level is lower than the voltage value of the first low level.
  • the parasitic capacitance has a redistribution effect on the charge of the liquid crystal capacitance and the storage capacitor of the pixel, so that the charged voltage of the original pixel 150 is reversed, the gate drive signal is a high level signal during the on time, and the first pull down time And the second pull-down time is a low-level signal, and the voltage value of the low level is less than the voltage value of the low level during the maintenance time.
  • the low level during the two pull-down time is mainly to pull down the reverse voltage. It can better solve or even eliminate the flicker problem of the display screen caused by the reverse voltage generated by the parasitic capacitance.
  • the first pull-down time and the turn-on time duration are equal; when the gate drive signal of the previous gate line 140 corresponds to the turn-on time, the gate drive signal of the current gate line 140 corresponds to the first down time. Pull time.
  • the first pull-down time is equal to the turn-on time.
  • the gate drive signal of the previous gate line 140 corresponds to the turn-on time
  • the current gate drive signal of the gate line 140 corresponds to the first pull-down time.
  • the duration is not equal, the correspondence cannot be achieved, causing confusion, and a correct loop cannot be formed, resulting in abnormal display of the display panel 110.
  • the turn-on time and the second pull-down time are equal; when the gate drive signal of the previous gate line 140 corresponds to the second pull-down time, the gate drive signal of the current gate line 140 corresponds to the turn-on time Inside.
  • the voltage value of the second low level is equal to the voltage value of the third low level.
  • the voltage value of the second low level is equal to the voltage value of the third low level, and the voltage of the second low level.
  • the value and the voltage value of the third low level are both used to adjust the kickback phenomenon, form a more accurate loop, and reduce or even eliminate the impact of kickback.
  • each pixel 150 includes a pixel electrode, and the same gate line 140 connects two adjacent pixels 150 to form a pixel group 160.
  • the pixel group 160 includes first pixels 161 connected to different data lines 130. And the second pixel 162;
  • the pixel electrode of the first pixel 161 of the pixel group 160 overlaps with the previous gate line 140 to form a first overlap region 170; the first overlap region 170 of the first pixel 161 overlaps with the previous gate line 140 to form a memory
  • the capacitance is Cst1
  • the pixel capacitance of the first pixel 161 is Clc1
  • the parasitic capacitance formed by the pixel electrode of the first pixel 161 and the current gate line is Cgs1;
  • the voltage value of the first low level and the third low level is V’GL
  • the voltage value of the high level is VGH
  • the voltage value of the second low level is VGL
  • ⁇ V’1 (VGH-V’GL)*Cgs1/(Cgs+Cst+Clc)
  • ⁇ V”1 (V’GL-VGH)*Cst1/(Cgs+Cst+Clc)
  • ⁇ V’2 (V’GL-VGL)*Cgs1/(Cgs+Cst+Clc)
  • ⁇ V”2 (VGH-V’GL)*Cst1/(Cgs+Cst+Clc)
  • each pixel 150 includes a pixel electrode, and the same gate line 140 connects two adjacent pixels 150 to form a pixel group 160.
  • the pixel group 160 includes data lines different from those 130 connected first pixel 161 and second pixel 162;
  • the pixel electrode of the second pixel 162 of the pixel group 160 overlaps the next gate line 140 to form a second overlap region 180;
  • the storage capacitor formed by overlapping the second overlap region 180 of the second pixel 162 with the next gate line 140 is Cst2, the pixel capacitance of the second pixel 162 is Clc2, and the parasitic capacitance formed by the pixel electrode of the second pixel 162 and the current gate line Is Cgs2;
  • the voltage value of the first low level and the third low level is V’GL
  • the voltage value of the high level is VGH
  • the voltage value of the second low level is VGL
  • ⁇ V’1 (VGH-V’GL)*Cgs2/(Cgs+Cst+Clc)
  • ⁇ V”1 (V’GL-VGL)*Cst2/(Cgs+Cst+Clc)
  • At3, ⁇ V2 (V’GL-VGL)*Cgs2/(Cgs+Cst+Clc)
  • a display panel 110 using the above-mentioned driving method including a plurality of data lines 130, a plurality of gate lines 140, and a plurality of pixels 150.
  • the gate line 130 and the data line 140 are interlaced with each other, and a plurality of pixels 150 are driven by the corresponding data line 130 and the gate line 140, each pixel 150 includes a corresponding pixel electrode; the same gate line 140 connects two adjacent
  • Each pixel 150 is a pixel group 160, and the pixel group 160 includes a first pixel 161 and a second pixel 162 connected to different data lines 130;
  • the pixel electrode of the first pixel 161 of the pixel group 160 overlaps with the previous gate line 140 to form a first overlap area 170; the pixel electrode of the second pixel 162 of the pixel group 160 overlaps with the next gate line 140 to form The second overlap area 180.
  • the two pixels 150 in the pixel group 160 respectively correspond to different data lines 130, which can better ensure the data driving voltage of each pixel 150, and prevent the load of the pixel electrode itself from causing the data voltage to decrease.
  • the pixel electrodes of the different pixels 150 in the group 160 overlap with the previous gate line 140 and the next gate line 140 to form two different storage capacitors.
  • Increasing the storage capacitor can reduce the pixel electrode and the gate line 140.
  • the influence of parasitic capacitance can reduce or even eliminate the redistribution effect of parasitic capacitance on the liquid crystal capacitance and storage capacitance, which causes the display panel 110 to produce flicker. It can also reduce the aperture ratio, increase the penetration rate of liquid crystal molecules, and achieve a large viewing role. .
  • the gate line 140 includes a main gate line 141 and an auxiliary gate line 142 that are mutually conductive and perpendicular to each other, and the auxiliary gate line 142 includes a first auxiliary gate line 1421 and a second auxiliary gate line 1422, the first sub-gate line 1421 and the pixel electrode of the second pixel 162 corresponding to the previous gate line 140 form a first overlap region 170, and the second sub-gate line 1422 corresponds to the first pixel electrode of the next gate line 140
  • the pixel electrode of the pixel 161 forms a second overlapping region 180, and the auxiliary gate line and the pixel electrode of the first pixel corresponding to the current main gate line and the pixel electrode of the second pixel corresponding to the previous main gate line are both A first safety distance is provided, and a second safety distance is provided between the auxiliary gate line and the corresponding data line.
  • the auxiliary gate line 142 extending from the main gate line 141 forms an overlapping area with the pixel group 160.
  • the auxiliary gate line 142 can have the effect of shielding the electric field.
  • the first auxiliary gate and the second auxiliary gate The line and the data line are arranged in parallel, and a safety distance is set, which reduces the electric field formed between the pixel electrode and the data line 130, and also prevents the pixel electrode and the main gate line 141 from generating strong parasitic capacitance.
  • a driving circuit drives all the display panels 110 as described above, and the driving circuit includes:
  • the gate driving circuit 121 outputs a gate driving signal to the gate line corresponding to the display panel 110;
  • one signal period of the gate driving signal output by the gate driving circuit 121 includes: the sustain time, the turn-on time, and the first pull-down time adjacent to the turn-on time; the gate driving signal is the first low during the sustain time Level; high level during the open time; second low level during the first pull-down time; the voltage value of the second low level is lower than the voltage value of the first low level.
  • the driving circuit 120 is used to drive the display panel 110, and the gate driving circuit 121 in the driving circuit 120 outputs a signal to the corresponding gate line of the display panel 110, outputs a corresponding signal to turn on the corresponding gate line, and the gate drive
  • the signal cycle is divided into three time periods, which output different levels respectively. Because of the influence of the reverse voltage caused by the parasitic capacitance generated by the pixel electrode and the gate line 140, the voltage pull-down time is set in different time periods to form a correct loop , Solve the flicker problem caused by reverse voltage.
  • a display device 100 including the above-mentioned display panel 110 and the driving circuit 120.
  • the technical solution of this application can be widely used in various display panels, such as TN-type display panels (the full name is Twisted Nematic, that is, twisted nematic panels), IPS-type display panels (In-Plane Switching, plane switching), VA-type displays Panel (Vertical Alignment, vertical alignment technology), MVA type display panel (Multi-domain Vertical Alignment, multi-quadrant vertical alignment technology), of course, can also be other types of display panels, such as organic light-emitting diodes , Referred to as OLED display panel), all of the above solutions are applicable.
  • TN-type display panels the full name is Twisted Nematic, that is, twisted nematic panels
  • IPS-type display panels In-Plane Switching, plane switching
  • VA-type displays Panel Very Alignment, vertical alignment technology
  • MVA type display panel Multi-domain Vertical Alignment, multi-quadrant vertical alignment technology
  • OLED display panel organic light-emitting diodes

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Abstract

一种驱动方法、显示面板（110）和驱动电路（120），驱动方法应用于显示面板（110），包括输出栅极驱动信号给显示面板（110）对应的栅极线（140）的步骤，栅极驱动信号的一个信号周期包括维持时间、打开时间和与打开时间相邻的第一下拉时间；栅极驱动信号在维持时间内为第一低电平；在打开时间内为高电平；在第一下拉时间内为第二低电平；第二低电平低于第一低电平。

Description

驱动方法、显示面板和驱动电路
本申请要求于2019年1月30日提交中国专利局，申请号为CN201910089130.X，发明名称为“一种驱动方法、显示面板和驱动电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种驱动方法、显示面板和驱动电路。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着科技的发展和进步，平板显示器由于具备机身薄、省电和辐射低等热点而成为显示器的主流产品，得到了广泛应用。平板显示器包括薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)和有机发光二极管(Organic Light-Emitting Diode，OLED)显示器等。其中，薄膜晶体管液晶显示器通过控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面，具有机身薄、省电、无辐射等众多优点。而有机发光二极管显示器是利用有机电致发光二极管制成，具有自发光、响应时间短、清晰度与对比度高、可实现柔性显示与大面积全色显示等诸多优点。
在液晶显示器的使用中，显示画面的清晰度以及稳定性是我们一直在解决的重要问题，画面常受到驱动电压的影响，导致产生一些闪烁,此类现象亟待解决。
技术解决方案
为实现上述目的，本申请提供了能够解决显示画面闪烁的一种驱动方法、显示面板和驱动电路。
本申请还公开了一种驱动方法，应用于显示面板，所述显示面板包括多条数据线、多条栅极线和多个像素，所述栅极线和所述数据线互相交错形成，多个像素分别由对应的数据线和栅极线驱动，所述每个像素包括对应的像素电极；
所述驱动方法包括输出栅极驱动信号给所述显示面板对应的栅极线的步骤；
其中，所述栅极驱动信号的一个信号周期包括维持时间、打开时间和与打开时间相邻的第一下拉时间；所述栅极驱动信号在维持时间内为第一低电平；所述栅极驱动信号在打开时 间内为高电平；所述栅极驱动信号在第一下拉时间内为第二低电平；所述第二低电平的电压值低于所述的第一低电平的电压值。
可选的，所述第一下拉时间位于所述打开时间之前，所述栅极驱动信号的一个信号周期还包括位于打开时间之后的第二下拉时间；所述栅极驱动信号在第二下拉时间内为第三低电平；所述第三低电平的电压值低于所述的第一低电平的电压值。
可选的，所述第一下拉时间和所述打开时间时长相等。
可选的，所述第一下拉时间和所述打开时间时长相等；在上一栅极线的栅极驱动信号对应于所述打开时间时，所述的当前栅极线的栅极驱动信号对应于第一下拉时间内。
可选的，所述打开时间和所述第二下拉时间时长相等。
可选的，所述打开时间和所述第二下拉时间时长相等；在上一栅极线的栅极驱动信号对应于第二下拉时间时，当前栅极线的栅极驱动信号对应于所述打开时间。
可选的，所述第二低电平的电压值和所述第三低电平的电压值相等。
可选的，所述每个像素包括一个像素电极，同一栅极线连接相邻的两个像素为一像素组，所述像素组包括与不同的数据线连接的第一像素和第二像素；
可选的，所述像素组的第一像素的像素电极与上一栅极线重叠，形成第一重叠区；所述第一重叠区的面积为S1，，所述第一像素的第一重叠区与上一栅极线重叠形成的存储电容为Cst1，所述第一像素的像素电容为Clc1，所述第一像素的像素电极与当前栅线形成的寄生电容为Cgs1；所述第一低电平和所述第三低电平的电压值为V’GL，所述高电平的电压值为VGH，所述第二低电平的电压值为VGL；Cst1＝(VGH-VGL)*Cgs1/(VGL-V’GL)。
可选的，所述像素组的第二像素的像素电极与下一栅极线重叠，形成第二重叠区；所述第二重叠区的面积为S2，所述第二像素的第二重叠区与下一栅极线重叠形成的存储电容为Cst2，所述第二像素的像素电容为Clc2，所述第二像素的像素电极与当前栅线形成的寄生电容为Cgs2；所述第一低电平和所述第三低电平的电压值为V’GL，所述高电平的电压值为VGH，所述第二低电平的电压值为VGL；Cst2＝(VGH-VGL)*Cgs2/(VGL-V’GL)。
本申请还公开了一种使用了上述驱动方法的显示面板，其中，所述显示面板包括多条数据线、多条栅极线和多个像素，所述栅极线和所述数据线互相交错形成，多个像素分别由对应的数据线和栅极线驱动，所述每个像素包括对应的像素电极；同一栅极线连接相邻的两个像素为一个像素组，所述像素组包括与不同的数据线连接的第一像素和第二像素；其中，所述像素组的第一像素的像素电极与上一栅极线重叠，形成第一重叠区；所述像素组的第二像素的像素电极与下一栅极线重叠，形成第二重叠区。
可选的，所述栅极线包括互相导通的主栅极线和辅栅极线，所述主栅极线与辅栅极线垂直。
可选的，所述辅栅极线包括第一辅栅极线和第二辅栅极线，所述第一辅栅极线和所述第二辅栅极线平行设置。
可选的，所述栅极线包括相互导通的主栅极线和辅栅极线，所述主栅极线与所述数据线交叉设置，所述辅栅极线与所述数据线平行设置。
可选的，所述辅栅极线与当前主栅极线对应的第一像素的像素电极之间以及上一主栅极线对应的第二像素的像素电极之间都设有第一安全距离。
可选的，所述辅栅极线与对应的数据线之间设有第二安全距离。
可选的，所述第一辅栅极线与上一栅极线对应的第二像素的像素电极形成第一重叠区，所述第二辅栅极线与所述下一栅极线对应的第一像素的像素电极形成第二重叠区。
可选的，所述第一重叠区的面积为S1，所述第二重叠区的面积为S2。
本申请还公开了一种驱动电路，所述驱动电路驱动如上所述的显示面板，所述驱动电路包括：栅极驱动电路，输出栅极驱动信号给所述显示面板对应的栅极线；其中，所述栅极驱动电路输出的栅极驱动信号的一个信号周期包括：维持时间、打开时间和与打开时间相邻的第一下拉时间；所述栅极驱动信号在维持时间内为第一低电平；所述栅极驱动信号在打开时间为高电平；所述栅极驱动信号在第一下拉时间内为第二低电平；所述第二低电平的电压值低于所述的第一低电平的电压值。
可选的，所述第一下拉时间位于所述打开时间之前，所述栅极驱动信号的一个信号周期还包括位于打开时间之后的第二下拉时间；所述栅极驱动信号在第二下拉时间内为第三低电平；所述第三低电平的电压值低于所述的第一低电平的电压值。
相对于栅极驱动信号在一个周期时间内保持相同电平信号输入的方案来说，本申请每个栅极驱动信号的一个周期包括三个时间段，分别是维持时间，打开时间和第一下拉时间，第一下拉时间与打开时间相邻，栅极驱动信号在维持时间内是第一低电平，打开时间内为高电平，下拉时间内为第二低电平，由于栅极线跟像素电极存在寄生电容Cgs，当像素充电后元件关闭时，栅极电压的变化透过寄生电容Cgs对于画素的液晶电容及储存电容电荷产生再分配作用，使得原像素充电后的电压产生反向(kickback)的现象，第一下拉时间内的第二低电平的电压值小于维持时间内的第一低电平的电压值，第一下拉时间用于调节像素电极和栅极线之间产生的寄生电容所产生的反向电压,减少甚至消除闪烁问题的产生。
附图说明
图所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳 动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请的一实施例的一种显示面板的像素放大的示意图；
图2是本申请的一实施例的像素结构电路的示意图；
图3是本申请的一实施例的一种只有一个下拉时间的驱动波形的示意图；
图4是本申请的一实施例的具有两个下拉时间的的驱动波形的示意图；
图5是本申请的另一实施例的一种驱动波形的示意图；
图6是本申请的另一实施例的像素结构的示意图；
图7是本申请的另一实施例的驱动电路的示意图；
图8是本申请的另一实施例的显示装置的示意图。
具体实施方式
下需要理解的是，这里所使用的术语、公开的具体结构和功能细节，仅仅是为了描述具体实施例，是代表性的，但是本申请可以通过许多替换形式来具体实现，不应被解释成仅受限于这里所阐述的实施例。
在本申请的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示相对重要性，或者隐含指明所指示的技术特征的数量。由此，除非另有说明，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征；“多个”的含义是两个或两个以上。术语“包括”及其任何变形，意为不排他的包含，可能存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
另外，“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系的术语，是基于附图所示的方位或相对位置关系描述的，仅是为了便于描述本申请的简化描述，而不是指示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，或是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
下面参考附图和可选的实施例对本申请作进一步说明。
参考图1至图5，本实施例公开了一种驱动方法，应用于显示面板110，如图1所示，显示面板110包括多条数据线130、多条栅极线140和多个像素150，栅极线130和数据线140互相交错，多个像素150分别由对应的数据线130和栅极线140驱动，每个像素150包括对应的像素电极；
驱动方法包括输出栅极驱动信号给显示面板110对应的栅极线的步骤；
其中，栅极驱动信号的一个信号周期包括维持时间、打开时间和与打开时间相邻的第一下拉时间；参考图3，栅极驱动信号在维持时间内为第一低电平；在打开时间为高电平；在第一下拉时间内为第二低电平；第二低电平低于的第一低电平。
本方案中，每个栅极驱动信号的一个周期包括三个时间段，分别是维持时间，打开时间和第一下拉时间，第一下拉时间与打开时间相邻，栅极驱动信号在维持时间内是第一低电平，打开时间内为高电平，下拉时间内为第二低电平，参考图2所示，由于栅极线140跟像素电极存在寄生电容Cgs，当像素150充电后元件关闭时，栅极电压的变化通过寄生电容Cgs对于画素的液晶电容及储存电容电荷产生再分配作用，使得原像素150充电后的电压产生反向(kickback)的现象，第一下拉时间内的第二低电平的电压值小于维持时间内的第一低电平的电压值，为了拉低反向电压的值，在第一下拉时间内调节像素电极和栅极线140之间产生的寄生电容所产生的反向电压，减少甚至消除闪烁问题的产生。
在一实施例中，参考图4所示，第一下拉时间位于打开时间之前；栅极驱动信号的一个信号周期还包括位于打开时间之后的第二下拉时间；栅极驱动信号在第二下拉时间内为第三低电平；第三低电平的电压值低于的第一低电平的电压值。
本方案中，寄生电容对于画素的液晶电容及储存电容电荷产生再分配作用，使得原像素150充电后的电压产生反向，打开时间内栅极驱动信号为高电平信号，第一下拉时间和第二下拉时间内为低电平信号，且该低电平的电压值都小于维持时间内的低电平的电压值，两个下拉时间内的低电平主要是拉低反向电压，可以更好的解决甚至消除寄生电容产生的反向电压给显示画面的闪烁问题。
在一实施例中，第一下拉时间和打开时间时长相等；在上一栅极线140的栅极驱动信号对应于打开时间时，当前栅极线140的栅极驱动信号对应于第一下拉时间内。
本方案中，第一下拉时间和打开时间时长相等，在上一栅极线140的栅驱动信号对应与打开时间时，当前的栅极线140的栅驱动信号刚好对应与第一下拉时间内，若时长不相等，则无法实现对应，造成混乱，不能形成正确的回路，导致显示面板110显示异常。
在一实施例中，打开时间和第二下拉时间时长相等；在上一栅极线140的栅极驱动信号对应于第二下拉时间时，当前栅极线140的栅极驱动信号对应于打开时间内。
本方案中，在上一栅极线140的栅极驱动信号对应于第二下拉时间时，当前栅极线140的栅极驱动信号对应于打开时间内，保证打开时间和第二下拉时间时长相等，这样才能实现各栅极线140之间的相互对应，形成正确的回路。
在一实施例中，第二低电平的电压值和第三低电平的电压值相等。
本方案中，寄生电容的电压产生的再分配，导致出现电压反向的问题，影响画面，第二 低电平的电压值与第三低电平的电压值相等，第二低电平的电压值和第三低电平的电压值都是用以调节kickback现象，形成更加准确的回路，减轻甚至消除kickback的影响。
在一实施例中，每个像素150包括一个像素电极，同一栅极线140连接相邻的两个像素150为一像素组160，像素组160包括与不同的数据线130连接的第一像素161和第二像素162；
其中，像素组160的第一像素161的像素电极与上一栅极线140重叠，形成第一重叠区170；第一像素161的第一重叠区170与上一栅极线140重叠形成的存储电容为Cst1，第一像素161的像素电容为Clc1，第一像素161的像素电极与当前栅线形成的寄生电容为Cgs1；
第一低电平和第三低电平的电压值为V’GL，高电平的电压值为VGH，第二低电平的电压值为VGL；
Cst1＝(VGH-VGL)*Cgs1/(VGL-V’GL)
本方案中，参考附图4，可知
At①,，Vpixel＝Vdata
At②,，ΔV1＝ΔV’1+ΔV”1
ΔV’1＝(VGH-V’GL)*Cgs1/(Cgs+Cst+Clc)
ΔV”1＝(V’GL-VGH)*Cst1/(Cgs+Cst+Clc)
At③，ΔV2＝ΔV’2+ΔV”2
ΔV’2＝(V’GL-VGL)*Cgs1/(Cgs+Cst+Clc)
ΔV”2＝(VGH-V’GL)*Cst1/(Cgs+Cst+Clc)
At④，ΔV3＝(V’GL-VGL)*Cst1/(Cgs+Cst+Clc)
为了减少kickback造成闪烁，设置，Cst1＝(VGH-VGL)*Cgs1/(VGL-V’GL)，形成正确的回路，消除反向电压的影响，避免出现闪烁。
在一实施例中，参考附图1所示，每个像素150包括一个像素电极，同一栅极线140连接相邻的两个像素150为一像素组160，像素组160包括与不同的数据线130连接的第一像素161和第二像素162；
参考附图6所示，像素组160的第二像素162的像素电极与下一栅极线140重叠，形成第二重叠区180；
第二像素162的第二重叠区180与下一栅极线140重叠形成的存储电容为Cst2，第二像素162的像素电容为Clc2，第二像素162的像素电极与当前栅线形成的寄生电容为Cgs2；
第一低电平和第三低电平的电压值为V’GL，高电平的电压值为VGH，第二低电平的电压值为VGL；
Cst2＝(VGH-VGL)*Cgs2/(VGL-V’GL)
本方案中，参考附图5所示，
At①，Vpixel＝Vdata
At②，ΔV1＝ΔV’1+ΔV”1
ΔV’1＝(VGH-V’GL)*Cgs2/(Cgs+Cst+Clc)
ΔV”1＝(V’GL-VGL)*Cst2/(Cgs+Cst+Clc)
At③，ΔV2＝(V’GL-VGL)*Cgs2/(Cgs+Cst+Clc)
为了减少kickback造成闪烁，设置，Cst2＝(VGH-VGL)*Cgs1/(VGL-V’GL)，同样能形成正确的回路，消除反向电压的影响，避免出现闪烁。
如图1和图6所示，作为本申请的另一实施例，公开了一种使用了上述驱动方法的显示面板110，包括多条数据线130、多条栅极线140和多个像素150，栅极线130和数据线140互相交错，多个像素150分别由对应的数据线130和栅极线140驱动，每个像素150包括对应的像素电极；同一栅极线140连接相邻的两个像素150为一个像素组160，像素组160包括与不同的数据线130连接的第一像素161和第二像素162；
其中，像素组160的第一像素161的像素电极与上一栅极线140重叠，形成第一重叠区170；像素组160的第二像素162的像素电极与下一栅极线140重叠，形成第二重叠区180。
本方案中，像素组160内的两个像素150分别对应不同的数据线130，能够更好保证每个像素150的数据驱动电压的大小，防止像素电极本身的负载导致数据电压的降低，另外像素组160内的不同像素150的像素电极分别与上一栅极线140和下一栅极线140重叠，形成两个不同的存储电容，加大存储电容，可以减少像素电极与栅极线140产生的寄生电容的影响，减少甚至消除寄生电容对液晶电容和存储电容的再分配作用而导致显示面板110产生闪烁的问题，还可以降低开口率，提高液晶分子的穿透率，实现大视角色偏。
在一实施例中，栅极线140包括互相导通且相互垂直的主栅极线141和辅栅极线142，辅栅极线142包括第一辅栅极线1421和第二辅栅极线1422，第一辅栅极线1421与上一栅极线140对应的第二像素162的像素电极形成第一重叠区170，第二辅栅极线1422与下一栅极线140对应的第一像素161的像素电极形成第二重叠区180，辅栅极线与当前主栅极线对应的第一像素的像素电极之间以及上一主栅极线对应的第二像素的像素电极之间都设有第一安全距离，辅栅极线与对应的数据线之间设有第二安全距离。
本方案中，由主栅极线141延伸出来的辅栅极线142与像素组160形成重叠区，辅栅极线142可以具备屏蔽电场的效果，第一辅栅极想和第二辅栅极线与数据线平行设置，且设置了安全距离，减少了电场形成于像素电极与数据线130之间，另外也防止像素电极与主栅极线141产生较强的寄生电容。
如图4和图7所示，作为本申请的另一实施例，公开了一种驱动电路，驱动电路驱动如 上所有的显示面板110，驱动电路包括：
栅极驱动电路121，输出栅极驱动信号给显示面板110对应的栅极线；
其中，栅极驱动电路121输出的栅极驱动信号的一个信号周期包括：维持时间、打开时间和与打开时间相邻的第一下拉时间；的栅极驱动信号在维持时间内为第一低电平；在打开时间为高电平；在第一下拉时间内为第二低电平；第二低电平的电压值低于第一低电平的电压值。
本方案中，驱动电路120用于驱动显示面板110，驱动电路120中的栅极驱动电路121输出信号给显示面板110对应的栅极线，输出相应的信号开启对应的栅极线，栅极驱动信号周期分为三个时间段，分别输出不同的电平，因为受到像素电极与栅极线140产生的寄生电容所带来的反向电压影响，不同时间段设置电压下拉时间，形成正确的回路，解决反向电压带来的闪烁问题。
如图8所示，作为本申请的另一实施例，公开了一种显示装置100，包括上述的显示面板110及驱动电路120。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。
本申请的技术方案可以广泛用于各种显示面板，如TN型显示面板(全称为Twisted Nematic，即扭曲向列型面板)、IPS型显示面板(In-Plane Switching，平面转换)、VA型显示面板(Vertical Alignment，垂直配向技术)、MVA型显示面板(Multi-domain Vertical Alignment，多象限垂直配向技术)，当然，也可以是其他类型的显示面板，如有机发光显示面板(organic light-emitting diode，简称OLED显示面板)，均可适用上述方案。
以上内容是结合具体的优选实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (20)

  1. 一种驱动方法，应用于显示面板，所述显示面板包括：
    多条数据线；
    多条栅极线，所述栅极线和所述数据线互相交错；以及
    多个像素，分别由对应的数据线和栅极线驱动，所述每个像素包括对应的像素电极；
    所述驱动方法包括输出栅极驱动信号给所述显示面板对应的栅极线的步骤；
    其中，所述栅极驱动信号的一个信号周期包括维持时间、打开时间和与打开时间相邻的第一下拉时间；所述栅极驱动信号在维持时间内为第一低电平；所述栅极驱动信号在打开时间内为高电平；所述栅极驱动信号在第一下拉时间内为第二低电平；所述第二低电平的电压值低于所述的第一低电平的电压值。
  2. 如权利要求1所述的一种驱动方法，其中，所述第一下拉时间位于所述打开时间之前，所述栅极驱动信号的一个信号周期还包括位于打开时间之后的第二下拉时间；所述栅极驱动信号在第二下拉时间内为第三低电平；所述第三低电平的电压值低于所述的第一低电平的电压值。
  3. 如权利要求2所述的一种驱动方法，其中，所述第一下拉时间和所述打开时间时长相等。
  4. 如权利要求3所述的一种驱动方法，其中，在上一栅极线的栅极驱动信号对应于所述打开时间时，所述的当前栅极线的栅极驱动信号对应于第一下拉时间内。
  5. 如权利要求4所述的一种驱动方法，其中，所述打开时间和所述第二下拉时间时长相等。
  6. 如权利要求4所述的一种驱动方法，其中，在上一栅极线的栅极驱动信号对应于第二下拉时间时，当前栅极线的栅极驱动信号对应于所述打开时间。
  7. 如权利要求2所述的一种驱动方法，其中，所述第二低电平的电压值和所述第三低电平的电压值相等。
  8. 如权利要求5所述的一种驱动方法，其中，所述每个像素包括一个像素电极，同一栅极线连接相邻的两个像素为一像素组，所述像素组包括与不同的数据线连接的第一像素和第二像素。
  9. 如权利要求8所述的一种驱动方法，其中，所述像素组的第一像素的像素电极与上一栅极线重叠，形成第一重叠区；所述第一重叠区的面积为S1，所述第一像素的第一重叠区与上一栅极线重叠形成的存储电容为Cst1，所述第一像素的像素电容为Clc1，所述第一像素的像素电极与当前栅线形成的寄生电容为Cgs1；
    所述第一低电平和所述第三低电平的电压值为V’GL，所述高电平的电压值为VGH，所述第二低电平的电压值为VGL；
    Cst1＝(VGH-VGL)*Cgs1/(VGL-V’GL)。
  10. 如权利要求9所述的一种驱动方法，其中，所述像素组的第二像素的像素电极与下一栅极线重叠，形成第二重叠区；所述第二重叠区的面积为S2，所述第二像素的第二重叠区与下一栅极线重叠形成的存储电容为Cst2，所述第二像素的像素电容为Clc2，所述第二像素的像素电极与当前栅线形成的寄生电容为Cgs2；
    所述第一低电平和所述第三低电平的电压值为V’GL，所述高电平的电压值为VGH，所述第二低电平的电压值为VGL；
    Cst2＝(VGH-VGL)*Cgs2/(VGL-V’GL)。
  11. 一种显示面板，包括：
    多条数据线；
    多条栅极线，所述栅极线与所述数据线互相交错；以及
    多个像素，分别由对应的数据线和栅极线驱动，所述每个像素包括对应的像素电极；同一栅极线连接相邻的两个像素为一个像素组，所述像素组包括与不同的数据线连接的第一像素和第二像素；
    其中，所述像素组的第一像素的像素电极与上一栅极线重叠，形成第一重叠区；所述像素组的第二像素的像素电极与下一栅极线重叠，形成第二重叠区。
  12. 如权利要求11所述的一种显示面板，其中，所述栅极线包括互相导通的主栅极线和辅栅极线，所述主栅极线与辅栅极线垂直。
  13. 如权利要求12所述的一种显示面板，其中，所述辅栅极线包括第一辅栅极线和第二辅栅极线，所述第一辅栅极线和所述第二辅栅极线平行设置。
  14. 如权利要求12所述的一种显示面板，其中，所述栅极线包括相互导通的主栅极线和辅栅极线，所述主栅极线与所述数据线交叉设置，所述辅栅极线与所述数据线平行设置。
  15. 如权利要求14所述的一种显示面板，其中，所述辅栅极线与当前主栅极线对应的第一像素的像素电极之间以及上一主栅极线对应的第二像素的像素电极之间都设有第一安全距离。
  16. 如权利要求14所述的一种显示面板，其中，所述辅栅极线与对应的数据线之间设有第二安全距离。
  17. 如权利要求13所述的一种显示面板，其中，所述第一辅栅极线与上一栅极线对应的第二像素的像素电极形成第一重叠区，所述第二辅栅极线与所述下一栅极线对应的第一像素的像素电极形成第二重叠区。
  18. 如权利要求11所述的一种显示面板，其中，所述第一重叠区的面积为S1，所述第二重叠区的面积为S2。
  19. 一种驱动电路，所述驱动电路驱动所述显示面板，所述显示面板包括：
    多条数据线；
    多条栅极线，所述栅极线与所述数据线互相交错；以及
    多个像素，分别由对应的数据线和栅极线驱动，所述每个像素包括对应的像素电极；
    同一栅极线连接相邻的两个像素为一个像素组，所述像素组包括与不同的数据线连接的第一像素和第二像素；
    其中，所述像素组的第一像素的像素电极与上一栅极线重叠，形成第一重叠区；所述像素组的第二像素的像素电极与下一栅极线重叠，形成第二重叠区；
    所述驱动电路包括：
    栅极驱动电路，输出栅极驱动信号给所述显示面板对应的栅极线；
    其中，所述栅极驱动电路输出的栅极驱动信号的一个信号周期包括：维持时间、打开时间和与打开时间相邻的第一下拉时间；所述栅极驱动信号在维持时间内为第一低电平；所述栅极驱动信号在打开时间为高电平；所述栅极驱动信号在第一下拉时间内为第二低电平；所述第二低电平的电压值低于所述的第一低电平的电压值。
  20. 如权利要求19所述的一种驱动电路，其中，所述第一下拉时间位于所述打开时间之前，所述栅极驱动信号的一个信号周期还包括位于打开时间之后的第二下拉时间；所述栅极驱动信号在第二下拉时间内为第三低电平；所述第三低电平的电压值低于所述的第一低电平的电压值。
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