WO2020147084A1

WO2020147084A1 - Chip packaging structure and electronic device

Info

Publication number: WO2020147084A1
Application number: PCT/CN2019/072224
Authority: WO
Inventors: 张童龙; 蒋尚轩; 赵南; 郭健炜; 胡骁
Original assignee: 华为技术有限公司
Priority date: 2019-01-17
Filing date: 2019-01-17
Publication date: 2020-07-23
Also published as: CN112997305B; CN112997305A

Abstract

Disclosed are a chip packaging structure (01) and an electronic device, wherein the chip packaging structure (01) is used for solving the problem of warping during the process of packaging a larger-sized packaging substrate. The chip packaging structure (01) comprises a first packaging substrate (11), a semiconductor device (20), a plurality of first connecting members (41) and a plurality of second connecting members (42), wherein the first packaging substrate (11) has upper and lower surfaces arranged opposite each other; the semiconductor device (20) is located at the upper surface of the first packaging substrate (11), and is electrically connected to the first packaging substrate (11); an adapter assembly (30) is electrically connected to a PCB, and the adapter assembly (30) is located at the lower surface of the first packaging substrate (11), and comprises at least one second packaging substrate (12); and the plurality of first connecting members (41) are arranged at the lower surface of the first packaging substrate (11), and are used for electrically connecting the first packaging substrate (11) to the adapter assembly (30).

Description

Chip packaging structure, electronic equipment

Technical field

This application relates to a chip packaging structure, in particular to a chip packaging structure and electronic equipment.

Background technique

With the rapid development of wireless communications, automotive electronics and other consumer electronic products, electronic devices are developing in the direction of multi-function. Based on this, in the prior art, when manufacturing the above-mentioned electronic device, the chip is usually packaged and then integrated, and the integrated components are arranged in the above-mentioned electronic device.

With the continuous increase of chip functions, the input/output (I/O) pins of the chip continue to increase, which further increases the size of the package substrate used to carry the chip. In this case, a larger-sized package substrate is prone to warpage (warpage), which will have a greater negative impact on the surface mount technology (SMT) and reduce the quality of the SMT process. In addition, the increase in the above-mentioned warping phenomenon will also cause the problem of reduced reliability of the board level (BL) solder joints.

Summary of the invention

The embodiments of the present invention provide a chip packaging structure and electronic equipment, which are used to solve the problem of warpage and board-level solder joint reliability during packaging of a larger-size packaging substrate.

In order to achieve the foregoing objectives, the following technical solutions are adopted in the embodiments of the present application:

In one aspect of the embodiments of the present application, a chip packaging structure is provided. The chip packaging structure includes: a first packaging substrate, a semiconductor device, a plurality of first connectors, and a plurality of second connectors. Wherein, the first packaging substrate has upper and lower surfaces arranged oppositely. The semiconductor device is located on the upper surface of the first packaging substrate and is electrically connected to the first packaging substrate. The transfer component is electrically connected to the PCB, and the transfer component is located on the lower surface of the first packaging substrate and includes at least one second packaging substrate. A plurality of first connecting members are arranged on the lower surface of the first packaging substrate and used for electrically connecting the first packaging substrate and the adapter assembly. By disposing the above-mentioned second packaging substrate between the first packaging substrate and the PCB, the distance between the first packaging substrate and the PCB can be increased without increasing the size of the first connector, thereby making the first packaging substrate The stress with the PCB is buffered. In this case, it is possible to reduce the probability of warpage caused by the large stress between the first packaging substrate and the PCB during the packaging process of the larger-size packaging substrate, thereby improving the quality of the SMT process and the board-level welding Reliability of points.

In some embodiments of the present application, the transfer assembly includes at least two stacked second packaging substrates. In addition, the adapter assembly further includes a plurality of third connecting members. The third connecting member is located between two adjacent second packaging substrates and is used to electrically connect two adjacent second packaging substrates. In this way, while meeting the requirements of the external design and size of the chip packaging structure, by increasing the number of second packaging substrates in the transfer assembly, the distance between the first packaging substrate and the PCB can be further increased, so as to relieve the first The purpose of the stress between the package substrate and the PCB.

In some embodiments of the present application, the thermal expansion coefficients of at least two stacked second packaging substrates in the transition assembly are the same.

In some embodiments of the present application, along the direction from the first packaging substrate to the printed circuit board, the thermal expansion coefficients of the at least two stacked second packaging substrates in the transition assembly increase sequentially.

In some embodiments of the present application, the chip package structure includes at least two interconnecting components side by side. Different transition components are electrically connected to the lower surface of the first packaging substrate in different areas. In addition, any two adjacent transfer components have the same number of second packaging substrates. There is a gap between two adjacent second packaging substrates in different transfer assemblies. In this way, the size of each second packaging substrate is reduced compared to the second packaging substrate with the same size as the second packaging substrate, which can effectively reduce the occurrence of each second packaging substrate in the SMT process. The chance of warping.

In some embodiments of the present application, the thermal expansion coefficient of the second packaging substrate is greater than the thermal expansion coefficient of the first packaging substrate, and is smaller than the thermal expansion coefficient of the printed circuit board. In summary, by arranging the second packaging substrate between the first packaging substrate and the second packaging substrate, the distance between the first packaging substrate and the PCB can be increased without increasing the size of the first connector. In addition, since the CTE of the second packaging substrate is located between the CTE of the first packaging substrate and the CTE of the PCB, the difference in CTE between the first packaging substrate and the second packaging substrate is small, and the difference between the second packaging substrate and the PCB The CTE difference is small. In this case, there is less stress between the first packaging substrate and the second packaging substrate. There is less stress between the second packaging substrate and the PCB. Therefore, under the action of the second packaging substrate, the stress between the first packaging substrate and the PCB is buffered. When the first packaging substrate is mounted on the second packaging substrate through the SMT process, since the stress between the first packaging substrate and the second packaging substrate is small, the warpage of the first packaging substrate is reduced to a certain extent ease. In addition, when the second packaging substrate is mounted on the PCB through the SMT process, since the stress between the second packaging substrate and the PCB is small, the warpage of the second packaging substrate is also relieved to a certain extent. In this way, the tolerance to package warpage in the SMT process is effectively improved. Or, after the SMT process is completed, in the process of entering the temperature cycle test, since the stress between the first packaging substrate and the second packaging substrate is small, the first connections arranged on the lower surface of the first packaging substrate will be reduced. The chance of cracking. In addition, in the above-mentioned temperature cycling test process, since the stress between the second packaging substrate and the PCB is relatively small, the probability of cracking of the second connectors arranged on the lower surface of the second packaging substrate is reduced. To achieve the purpose of improving the quality of the chip packaging structure.

In some embodiments of the present application, the second packaging substrate includes at least one layer of insulating carrier, and metal wiring on and on the lower surface of the insulating carrier. In addition, the insulating carrier board is provided with via holes, and the via holes are used to electrically connect the metal wiring on the insulating carrier board and the lower surface. The second packaging substrate having the above structure can relieve the stress between the first packaging substrate and the PCB. There is no need to adjust the size, shape, number of pins, pitch, and length of the chip package structure.

In some embodiments of the present application, the chip packaging structure further includes a plurality of second connecting members arranged on the lower surface of the adapter assembly for electrically connecting the adapter assembly with the printed circuit board. A first connecting piece is electrically connected to a second connecting piece through a through hole on the insulating carrier board. In this way, the arrangement of the metal wiring in the second packaging substrate can be simplified, thereby achieving the purpose of simplifying the manufacturing process of the second packaging substrate.

In some embodiments of the present application, the upper and lower surfaces of the insulating carrier board include effective areas and ineffective areas. The metal wiring is located in the effective area. In addition, the second packaging substrate further includes a metal film covering the inactive area; the metal film is disconnected from the metal wiring. In this way, by providing the metal film on the second packaging substrate, the CTE of the second packaging substrate can be increased.

In some embodiments of the present application, the metal film and the metal wiring are made of the same material, so as to achieve the purpose of simplifying the manufacturing process of the second packaging substrate.

In some embodiments of the present application, the first connecting member and the second connecting member are solder balls or bumps.

In some embodiments of the present application, the semiconductor device includes a bare chip and a plurality of fourth connectors. The above-mentioned multiple fourth connecting members are arranged on the active surface of the bare chip and are used to electrically connect the bare chip with the first packaging substrate. In this case, the semiconductor device is a single bare chip sealed structure. In some other embodiments, the semiconductor device may also be a chip entity obtained by packaging one or more bare chips.

In some embodiments of the present application, the semiconductor device includes at least two bare chips, an interposer board, multiple fourth connectors, and multiple fifth connectors. Among them, the transfer board is used to carry at least two bare chips. A plurality of fourth connecting members are arranged on the active surface of the bare chip and are used for electrically connecting at least two bare chips with the adapter board. A plurality of fifth connecting members are arranged on the lower surface of the transfer board and are used for electrically connecting the transfer board and the first packaging substrate.

In some embodiments of the present application, the chip packaging structure further includes a heat dissipation glue bonding glue, a heat dissipation cover, and a primer. Wherein, the heat dissipation adhesive bonding adhesive covers the semiconductor device. The heat dissipation cover covers the heat dissipation glue bonding glue and is in contact with the first packaging substrate. The primer is arranged between the semiconductor device and the first packaging substrate, and between the first packaging substrate and the second packaging substrate adjacent to the first packaging substrate.

Another aspect of the embodiments of the present application provides an electronic device including any chip packaging structure described above. The transfer component in the chip packaging structure is electrically connected with the printed circuit board. The above-mentioned electronic device has the same technical effect as the electronic device provided in the foregoing embodiment, and will not be repeated here.

BRIEF DESCRIPTION

FIG. 1 is a schematic diagram of a chip packaging structure provided by some embodiments of the application;

2 is a schematic diagram of the stress gradient between a package substrate and a PCB provided by some embodiments of the application;

FIG. 3 is a schematic diagram of the package substrate warping in the structure shown in FIG. 2;

4 is a schematic diagram of a structure of the second packaging substrate in FIG. 1;

5 is a schematic diagram of another structure of the second packaging substrate in FIG. 1;

FIG. 6 is a schematic diagram of another stress gradient between a package substrate and a PCB provided by some embodiments of the application;

FIG. 7 is a schematic diagram of the package substrate warping in the structure shown in FIG. 6;

FIG. 8 is a schematic diagram of a chip packaging structure provided by some embodiments of the application;

FIG. 9 is a schematic diagram of another structure of the second packaging substrate in FIG. 1;

FIG. 10 is a schematic diagram of a chip packaging structure provided by some embodiments of the application;

FIG. 11 is a schematic diagram of a chip packaging structure provided by some embodiments of the application;

FIG. 12 is a schematic diagram of a chip packaging structure provided by some embodiments of the application;

FIG. 13 is a schematic diagram of a chip packaging structure provided by some embodiments of the application;

14a, FIG. 14b, FIG. 14c, and FIG. 14d are schematic structural diagrams of various stages corresponding to a manufacturing method of a chip package structure provided by some embodiments of the application;

15a, 15b, and 15c are schematic diagrams of various stages corresponding to the manufacturing method of another chip packaging structure provided by some embodiments of the application;

16a, FIG. 16b, and FIG. 16c are schematic diagrams of various stages corresponding to the manufacturing method of another chip packaging structure provided by some embodiments of the application.

Reference mark:

01-Chip packaging structure; 11-first packaging substrate; 12-second packaging substrate; 100-insulating carrier board; 101-metal wiring; 102-via; 103-adhesive layer; 104-metal film; 110- Active area; 111-inactive area; 20-semiconductor device; 201-bare chip; 30-transition component; 41-first connector; 42-second connector; 43-third connector; 44-fourth Connecting piece; 45-Fifth connecting piece; 50- Heat-dissipating glue bonding glue; 51- Heat-dissipating cover; 52- Bottom glue; 60- Adapter plate.

detailed description

The following describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments.

Herein, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise stated, "plurality" means two or more.

In addition, in this article, the azimuth terms such as "upper" and "lower" are defined with respect to the schematic placement of the display panel in the drawings. It should be understood that these directional terms are relative concepts, and they are used for relative For the description and clarification, it can be changed correspondingly according to the change in the orientation of the display panel.

The embodiment of the present application provides a chip packaging structure 01, as shown in FIG. 1, including: a first packaging substrate 11 and a semiconductor device 20.

Wherein, the first packaging substrate 11 has an upper surface A1 and a lower surface A2 which are oppositely arranged. The upper surface A1 of the first packaging substrate 11 is used to carry the semiconductor device 20.

Based on this, the aforementioned semiconductor device 20 is located on the upper surface A1 of the first packaging substrate 11 and is electrically connected to the first packaging substrate 11.

A circuit structure composed of metal wiring is provided in the first package substrate 11. The above circuit structure can enable the first package substrate 11 to adjust the size, shape, pin number, pitch, length, etc. of the chip package structure 01, thereby enabling the chip package structure 01 to be easily integrated with a printed circuit board (PCB) Match.

In this case, when the circuit structure formed by the metal wiring in the first packaging substrate 11 is prepared according to design requirements, the coefficient of thermal expansion (CTE) of the first packaging substrate 11 is a fixed value.

In addition, after the PCB is prepared according to the setting requirements, the CTE of the PCB is also a fixed value. In addition, the difference between the CTE of the first packaging substrate 11 and the CTE of the PCB is relatively large. For example, the CTE of the first packaging substrate 11 is 12-14 ppm/°C, and the CTE of the PCB can reach 17-20 ppm/°C.

In this case, during the SMT process, if the first packaging substrate 11 is directly mounted on the PCB. As shown in FIG. 2, the distance H between the first packaging substrate 11 and the PCB is relatively small.

At this time, it can be seen from the stress gradient that a relatively large stress will be generated between the first packaging substrate 11 and the PCB, so that during the SMT process, the solder balls or bumps on the lower surface of the first packaging substrate 11 may melt Under this condition, the first package substrate 11 with a larger one-side size (for example, 75 mm) will cause larger warpage as shown in FIG. 3.

Or, after the SMT process is completed and in the process of the warm cycle test, the greater stress generated between the first packaging substrate 11 and the PCB will cause a mismatch between the first packaging substrate 11 and the PCB ( miss match), which in turn causes the solder balls or bumps disposed on the lower surface of the first package substrate 11 to crack. The quality of the chip package structure 01 is reduced.

In order to solve the above-mentioned problem, as shown in FIG. 1, the chip packaging structure 01 provided by the embodiment of the present application further includes an adapter assembly 30 and a plurality of first connectors 41.

The above-mentioned adapter assembly 30 is located on the lower surface of the first packaging substrate 11. Moreover, the above-mentioned adapter assembly 30 includes at least one second packaging substrate 12 as shown in FIG. 4 or FIG. 5.

In some embodiments of the present application, as shown in FIG. 4, the above-mentioned second packaging substrate 12 may include a layer of insulating carrier 100 and metal wiring 101 located on the upper and lower surfaces of the insulating carrier 100.

The above-mentioned insulating carrier board 100 is provided with via holes 102. The via 102 is used to electrically connect the metal wiring 101 on the upper and lower surfaces of the insulating carrier 100.

Alternatively, in other embodiments of the present application, as shown in FIG. 5, the above-mentioned second packaging substrate 12 may include a multilayer insulating carrier 100 with metal wiring 101 on the upper and lower surfaces. An adhesive layer 103 is provided between two adjacent insulating carrier boards 100.

For the convenience of examples, the following descriptions are made by taking as an example the second packaging substrate 12 adopts the insulating carrier board 100 with metal wiring 101 on the upper and lower surfaces of a single layer as shown in FIG. 2.

In addition, the above-mentioned multiple first connecting members 41 are arranged on the lower surface of the first packaging substrate 11 for electrically connecting the first packaging substrate 11 and the adapter assembly 30.

The present application does not limit the manner in which the adapter assembly 30 is electrically connected to the PCB. For example, a pin for electrically connecting with the PCB may be provided on the adapter assembly 30.

Alternatively, the transfer assembly 30 may be electrically connected to the PCB by means of wired bonding.

Alternatively, the transfer assembly 30 can also be mounted on the PCB using the SMT process. In this case, the aforementioned chip package structure 01 further includes a plurality of second connectors 42. The plurality of second connecting members 42 are arranged on the lower surface of the adapter assembly 30 for electrically connecting the adapter assembly 30 and the PCB.

In this way, the above-mentioned adapter assembly 30 electrically connects the first package substrate 11 and the PCB through the multiple first connectors 41 and the multiple second connectors 42, so that the signals of the semiconductor device 20 can pass through the first package in turn. The substrate 11 and the second packaging substrate 12 are then transferred to the PCB.

The first connecting member 41 and the second connecting member 42 may be solder balls or bumps.

Wherein, the material constituting the solder ball may be a solder material (solder), and the solder ball may be called a solder ball. The material constituting the above-mentioned bumps may be low temperature (less than 200°C) solder.

In this way, by disposing the second packaging substrate 12 between the first packaging substrate 11 and the PCB, it is possible to make the first packaging substrate 11 and the first packaging substrate 11 and the PCB not increase the size of the first connector 41 as shown in FIG. The spacing H between PCBs is increased, so that the stress gradient shown in FIG. 6 shows that the stress between the first packaging substrate 11 and the PCB is buffered. In this case, it is possible to reduce the probability of the above-mentioned warping phenomenon caused by the greater stress between the first packaging substrate 11 and the PCB during the packaging process of the larger-size packaging substrate, thereby improving the quality and the board of the SMT process. Reliability of grade solder joints.

On this basis, when the thickness of the second packaging substrate 12 is relatively large, the CTE of the second packaging substrate 12 can be defined, so that the second packaging substrate 12 can reduce the gap between the first packaging substrate 11 and the PCB. Stress.

For example, in the embodiment of the present application, the CTE of the above-mentioned second packaging substrate 12 is greater than the CTE of the first packaging substrate 11 and smaller than the CTE of the PCB. That is, the CTE of the second packaging substrate 12 is located between the CTE of the first packaging substrate 11 and the CTE of the PCB.

For example, when the CTE of the first packaging substrate 11 is 12 ppm/°C and the CTE of the PCB is 20 ppm/°C, the CTE of the second packaging substrate 12 may be 16 ppm/°C.

In this case, it can be known from the stress gradient that there is a relatively small stress between the first packaging substrate 11 and the second packaging substrate 12. There is less stress between the second packaging substrate 12 and the PCB. Thus, under the action of the second packaging substrate 12, the stress between the first packaging substrate 11 and the PCB is buffered.

In this way, when the first packaging substrate 11 is mounted on the second packaging substrate 12 through the SMT process, since the stress between the first packaging substrate 11 and the second packaging substrate 12 is small, the first packaging substrate 11 is The warpage phenomenon, as shown in Figure 7, has been relieved to a certain extent. In addition, when the second packaging substrate 12 is mounted on the PCB through the SMT process, since the stress between the second packaging substrate 12 and the PCB is relatively small, the second packaging substrate 12 may be warped as shown in FIG. Get a certain relief. In this way, the tolerance to package warpage in the SMT process is effectively improved.

Or, after the SMT process is completed, in the process of entering the temperature cycle test, since the stress between the first packaging substrate 11 and the second packaging substrate 12 is relatively small, the arrangement on the lower surface A2 of the first packaging substrate 11 will be reduced. The probability that the first connecting member 41 will crack. In addition, in the above-mentioned temperature cycling test process, since the stress between the second packaging substrate 12 and the PCB is relatively small, the probability of cracking of the second connectors 42 arranged on the lower surface of the second packaging substrate 12 is reduced. To achieve the purpose of improving the quality of the chip packaging structure 01.

On this basis, it can be known from the above that the purpose of the second packaging substrate 12 in the adapter assembly 30 is to relieve the stress between the first packaging substrate 11 and the PCB. There is no need to adjust the size, shape, number of pins, pitch, and length of the chip package structure 01.

Based on this, as shown in FIG. 4 or FIG. 5, in the embodiment of the present application, the via hole 102 in the second packaging substrate 12 may penetrate all the insulating carrier boards 100 in the second packaging substrate 12.

In this case, as shown in FIG. 6, a first connector 41 is electrically connected to a second connector 42 through a through hole 102 on the insulating carrier board 100. In this way, the arrangement of the metal wiring 102 in the second packaging substrate 12 can be simplified, thereby achieving the purpose of simplifying the manufacturing process of the second packaging substrate 12.

The above is an example of the chip packaging structure 01 having an adapter assembly 30 and the one adapter assembly 30 having a second packaging substrate 12 to illustrate the structure of the chip packaging structure 01. Hereinafter, other structures of the chip package structure 01 having the above-mentioned at least one adapter assembly 30 are described as examples.

Example one

In this example, as shown in FIG. 8, the above-mentioned transfer assembly 30 includes at least two stacked second packaging substrates, for example, a second packaging substrate 12a and a second packaging substrate 12b.

On this basis, the above-mentioned adapter assembly 30 further includes a plurality of third connectors 43. The aforementioned third connecting member 43 may be a solder ball or a solder bump.

The plurality of third connecting members 43 are located between two adjacent second packaging substrates, and are used to electrically connect two adjacent second packaging substrates. For example, the aforementioned plurality of third connecting members 43 are arranged on the surface of the lower surface (facing the second packaging substrate 12b) of the second packaging substrate 12a, and are electrically connected to the second packaging substrate 12b.

In this way, while meeting the requirements of the external design and size of the chip packaging structure 01, by increasing the number of the second packaging substrates 12 in the adapter assembly 30, the distance between the first packaging substrate 11 and the PCB can be further increased. The purpose of alleviating the stress between the first packaging substrate 11 and the PCB is achieved.

In some embodiments of the present application, the CTE of the plurality of second packaging substrates 12 in the transfer assembly 30 may be the same.

Alternatively, in other embodiments of the present application, as shown in FIG. 8, along the direction (Z direction) from the first packaging substrate 11 to the PCB, the CTEs of the multiple second packaging substrates 12 in the transition assembly 30 may be sequentially Increment.

For example, in FIG. 8, when the CTE of the first packaging substrate 11 is 12 ppm/°C and the CTE of the PCB is 20 ppm/°C, the CTE of the second packaging substrate 12a is 14/°C, and the CTE of the second packaging substrate 12b is 16ppm/℃.

In the present application, the CTE of the plurality of second packaging substrates 12 in the transition assembly 30 will not be described one by one, as long as it can be ensured that the CTE of any second packaging substrate 12 in the transition assembly 30 is located in the first It suffices to be between the CTE of the package substrate 11 and the CTE of the PCB.

The method of adjusting the CTE of the second packaging substrate 12 will be described below.

In some embodiments of the present application, as shown in FIG. 9, the upper and lower surfaces of the insulating carrier 100 in the second packaging substrate 12 include an effective area 110 and an ineffective area 111.

It should be noted that the effective area 110 is an area on the second packaging substrate 12 for signal transmission. The inactive area 111 is an area on the second packaging substrate 12 that does not require signal transmission.

In this case, the aforementioned metal wiring 101 is located in the effective area 110.

In addition, the above-mentioned second packaging substrate 12 further includes a metal film 104 covering the ineffective area 111.

The metal film 104 is disconnected from the metal wiring 101 in the effective area 110, so that the metal wiring 101 cannot be electrically connected to the metal film 104.

In this way, by providing the above-mentioned metal film 104 on the second packaging substrate 12, the CTE of the second packaging substrate 12 can be increased.

In this case, when the second packaging substrate 12 needs to have a large CTE, the above-mentioned metal film 104 can be provided in all the inactive regions 111 on the upper and lower surfaces of the insulating carrier 100 in the second packaging substrate 12 .

Alternatively, when the second packaging substrate 12 needs to have a smaller CTE, the above-mentioned metal film 104 may be provided in the second packaging substrate 12 in the partially inactive regions 111 on the upper and lower surfaces of the insulating carrier 100.

In order to simplify the manufacturing process of the second packaging substrate 12, the metal film 104 may be made of the same material as the metal wiring 101. In this case, in the process of manufacturing the second packaging substrate 12, the copper foil covering the upper and lower surfaces of the insulating carrier 100 may be patterned, and the metal film 104 and the metal wiring 101 described above can be formed at the same time.

Alternatively, in the case of meeting the requirements of the external design dimension of the chip packaging structure 01, the thickness of the insulating carrier 100 can be increased to achieve the purpose of increasing the CTE of the second packaging substrate 12.

The material constituting the insulating carrier board 100 may be polypropylene (PP) or ABF (Ajinomoto Build-up Film).

Example two

In the embodiment of the present application, the aforementioned chip packaging structure 01, as shown in FIG. 10 or FIG. 11, includes at least two side-by-side switching components, for example, a switching component 30a and a switching component 30b.

The above-mentioned different adapter components are electrically connected to the lower surface of the first packaging substrate 11 in different areas. For example, the transition component 30a is electrically connected to the left half area of the lower surface of the first packaging substrate 11, and the transition component 30b is electrically connected to the right half area of the lower surface of the first packaging substrate 11.

Any two adjacent transfer components have the same number of second packaging substrates 12.

For example, as shown in FIG. 10, the transfer assembly 30a has a second packaging substrate 12a, and the transfer assembly 30b has a second packaging substrate 12b.

Or, for another example, as shown in FIG. 11, the adapter assembly 30 a has two stacked second packaging substrates 12. The transfer assembly 30b has two stacked second packaging substrates 12. In this case, in the process of manufacturing any one of the second packaging substrates 12 in the transfer assembly 30a and any one of the second packaging substrates 12 in the transfer assembly 30b, the specifications (for example, along the perpendicular to the PCB bearing surface The same insulating carrier 100 with the same thickness in the direction of φ) makes the manufacturing process of the adapter assembly 30a and the adapter assembly 30b simpler and easier to operate.

At this time, any one of the second packaging substrates 12 in the transfer assembly 30a and any one of the second packaging substrates 12 in the transfer assembly 30b have the same thickness. On this basis, when the number of second packaging substrates 12 in the adapter assembly 30a is the same as the number of the second packaging substrates 12 in the adapter assembly 30b, the adapter assembly 30a and the adapter assembly 30b are opposite to the first The supporting effect of the packaging substrate 11 is the same or approximately the same, so that the force on the first packaging substrate 11 is more uniform, so as to further reduce the probability of warping of the first packaging substrate 11. On this basis, there is a gap between two adjacent second packaging substrates located in different transition components. For example, in FIG. 10, there is a gap G between the second packaging substrate 12a in the transfer assembly 30a and the second packaging substrate 12b in the transfer assembly 30b.

In this case, in the chip packaging structure 01, the lower surface of the first packaging substrate 12 may be electrically connected to a plurality of second packaging substrates 12 on the same horizontal plane through a plurality of first connectors 41. In addition, the plurality of second packaging substrates 12 on the same horizontal plane are disconnected from each other.

As a result, the size of each second packaging substrate 12 in FIG. 9 and FIG. 10 is reduced compared to the second packaging substrate 12 having the same size as the second packaging substrate 11, thereby effectively reducing the size of each second packaging substrate 12 The second package substrate 12 has a probability of warping during the SMT process.

On this basis, for any chip packaging structure in the above example 1 and example 2, the semiconductor device 20 in the chip packaging structure 01, as shown in FIG. 12, may include at least one die 201 And a plurality of fourth connecting members 44.

Among them, the above-mentioned multiple fourth connecting members 44 are arranged on the active surface of the bare chip 201 and are used to electrically connect the bare chip 201 with the first packaging substrate 11.

It should be noted that the above-mentioned active surface of the bare chip 201 refers to the surface on which the circuit structure is provided on the bare chip 201. In addition, in the embodiment of the present invention, a flip chip method is taken as an example to introduce the connection method of the bare chip 201 in the chip packaging structure. In an actual product, the bare chip 201 can also be connected by wire bonding ( Wired bonding) and other methods are fixed and electrically connected to the first packaging substrate 11.

Alternatively, as shown in FIG. 13, the aforementioned semiconductor device 20 includes at least two bare chips. For example, bare chip 201a and bare chip 201b.

In addition, the aforementioned semiconductor device 20 further includes an interposer 60, a plurality of fourth connecting members 44 and a plurality of fifth connecting members 45. The fourth connecting member 44 and the fifth connecting member 45 may be solder bumps.

Wherein, the adapter board 60 is used to carry the above-mentioned at least two bare chips. A plurality of fourth connecting members 44 are arranged on the active surface of the bare chip, and are used to electrically connect the at least two bare chips with the adapter board 60.

In addition, a plurality of fifth connecting members 45 are arranged on the lower surface (the side surface facing the first packaging substrate 11) of the interposer board 60 for electrically connecting the interposer board 60 and the first packaging substrate 11.

In this case, the above-mentioned at least two bare chips can transmit signals to the first package carrier 11 through an adapter board 60.

On this basis, the aforementioned chip packaging structure 01, as shown in FIG. 12, further includes a heat dissipation glue bonding glue 50, a heat dissipation cover 51 and a primer 52.

The aforementioned heat-dissipating glue bonding glue 50 covers the semiconductor device 20 so that the bare chip 201 in the semiconductor device 20 can be wrapped.

The heat dissipation cover 51 covers the heat dissipation adhesive bonding glue 50 and is in contact with the first packaging substrate 11.

The primer 52 is disposed between the semiconductor device 20 and the first packaging substrate 11 and between the first packaging substrate 11 and the second packaging substrate 12 adjacent to the first packaging substrate 11.

In addition, the aforementioned primer 52 may also be provided between the second packaging substrate 12 and the PCB.

Hereinafter, taking the chip packaging structure 01 shown in FIG. 12 as an example, the manufacturing process of the chip packaging structure 01 will be described as an example.

Example three

In this example, the manufacturing process of the chip package structure 01 includes:

First, the bare chip 201 is obtained through a chip dicing process.

Then, as shown in FIG. 14a, a plurality of fourth connectors 44 are arranged on the active surface of the bare chip 201.

Next, through the chip mounting process, as shown in FIG. 14a, the bare chip 201 is mounted on the upper surface of the first packaging substrate 11.

Then, the plurality of fourth connecting members 44 are soldered to the upper surface of the first packaging substrate 11 through a reflow soldering process.

Next, using a primer filling process, a primer 52 is filled between the bare chip 201 and the first packaging substrate 11.

Next, the heat dissipation adhesive bonding glue 50 is coated, so that the heat dissipation adhesive bonding glue 50 can wrap the bare chip 201.

Next, the heat dissipation cover 51 is implanted to cover the heat dissipation glue bonding glue 50 with the heat dissipation cover 51.

Then, a plurality of first connectors 41 are arranged on the lower surface of the first package substrate 11 through a ball grid array (BGA) planting process. This completes the structure shown in Figure 14a.

On this basis, as shown in FIG. 14b, the structure shown in FIG. 14a is disposed on the upper surface of the second packaging substrate 12 by using the SMT process.

Then, a plurality of first connecting members 41 are soldered on the second packaging substrate 12 through a reflow soldering process.

Next, as shown in FIG. 14c, a second primer filling process is used to fill the primer 52 between the first packaging substrate 11 and the second packaging substrate 12.

Next, as shown in FIG. 14d, a second BGA ball planting process is adopted to arrange a plurality of second connecting members 42 on the lower surface of the second packaging substrate 12. This completes the structure shown in Figure 14d.

Then, using the SMT process, the structure shown in FIG. 14d is placed on the PCB, and the reflow soldering process is performed on the plurality of second connectors 42 so that the plurality of second connectors 42 are soldered on the PCB. Thus, the structure of the chip package structure 01 shown in FIG. 12 is completed.

It should be noted that the above-mentioned manufacturing process is described by taking the above-mentioned plurality of first connecting members 41 and the plurality of second connecting members 42 manufactured by the BGA ball planting process, and respectively performing the reflow soldering process as an example.

In some other embodiments of the present application, the same reflow soldering process may be used for the multiple first connecting members 41 and the multiple second connecting members 42 manufactured by the BGA ball planting process. In this case, it is necessary to fill the primer 52 between the first packaging substrate 11 and the second packaging substrate 12 after the above-mentioned reflow process is completed.

Example 4

First, as shown in FIG. 15a, a BGA ball planting process is used to arrange a plurality of second connecting members 42 on the lower surface of the second packaging substrate 12.

Next, as shown in FIG. 15b, the structure shown in FIG. 15a is placed on the PCB through the SMT process. Then, the plurality of second connectors 42 are soldered on the PCB through a reflow soldering process.

Next, the structure shown in FIG. 14a is mounted on the upper surface of the second substrate 12 through an SMT process, and a plurality of first connectors 41 are soldered on the upper surface of the second packaging substrate 12 through a reflow process. . Thus, the structure shown in Fig. 15c is formed.

It should be noted that the manufacturing method of the structure shown in FIG. 14a is the same as the method in Example 3, and will not be repeated here.

Next, as shown in the above, the primer filling process is used to fill the primer 52 between the first packaging substrate 11 and the second packaging substrate 12, and between the second packaging substrate 12 and the PCB, so as to form as shown in FIG.的chip package structure 01.

Example 5

First, as shown in FIG. 16a, a BGA ball planting process is used to arrange a plurality of first connecting members 41 on the lower surface of the first packaging substrate 11.

Then, as shown in FIG. 16b, the SMT process is used to mount the structure shown in FIG. 16a on the upper surface of the second package substrate 12, and through a reflow process, the multiple first connectors 41 are soldered to the second package On the substrate 12.

Next, the structure shown in FIG. 14a is mounted on the upper surface of the second substrate 12 through an SMT process, and a plurality of first connectors 41 are soldered to the upper surface of the second packaging substrate 12 through a reflow process. In addition, by using the BGA ball planting process, a plurality of second connecting members 42 are arranged on the lower surface of the second packaging substrate 12. Thus, the structure shown in Fig. 16c is formed.

Then, using the SMT process, the structure of FIG. 16c is mounted on the upper surface of the PCB, and the plurality of second connectors 42 are soldered on the PCB through a reflow soldering process.

Finally, using a primer filling process, primer 52 is filled between the first packaging substrate 11 and the second packaging substrate 12, and between the second packaging substrate 12 and the PCB, thereby forming a chip packaging structure 01 as shown in FIG. 12 .

The embodiment of the present application provides an electronic device, including a PCB, and any chip packaging structure 01 described above. It can be seen from the above that the second connector 42 in the chip package structure 01 is electrically connected to the PCB. The above-mentioned electronic device has the same technical effect as the chip package structure 01 provided in the foregoing embodiment. I won't repeat them here.

The above are only the specific embodiments of the present invention, but the scope of protection of the present invention is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present invention. It should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

A chip packaging structure, characterized in that it comprises:

The first packaging substrate has upper and lower surfaces arranged oppositely;

A semiconductor device located on the upper surface of the first packaging substrate and electrically connected to the first packaging substrate;

An adapter component for electrical connection with a printed circuit board, the adapter component is located on the lower surface of the first packaging substrate and includes at least one second packaging substrate;

A plurality of first connecting members are arranged on the lower surface of the first packaging substrate and used for electrically connecting the first packaging substrate and the at least one second packaging substrate.
4. The chip packaging structure of claim 1, wherein the adapter assembly comprises at least two stacked second packaging substrates;

The adapter assembly further includes a plurality of third connecting members;

The third connecting member is located between two adjacent second packaging substrates, and is used to electrically connect two adjacent second packaging substrates.
3. The chip packaging structure according to claim 2, wherein the thermal expansion coefficients of at least two stacked second packaging substrates in the transition assembly are the same.
The chip packaging structure of claim 2, wherein along the direction from the first packaging substrate to the printed circuit board, at least two of the second packaging substrates stacked in the adapter assembly are The coefficient of thermal expansion increases sequentially.
The chip packaging structure according to any one of claims 1 to 4, wherein the chip packaging structure comprises at least two adapter components side by side; different adapter components are electrically connected to the lower surface of the first packaging substrate. Different connected areas;

Any two adjacent transition components have the same number of second packaging substrates;

There is a gap between two adjacent second packaging substrates located in different transfer assemblies.
The chip packaging structure according to any one of claims 1 to 5, wherein:

The thermal expansion coefficient of the second packaging substrate is greater than the thermal expansion coefficient of the first packaging substrate, and is smaller than the thermal expansion coefficient of the printed circuit board.
The chip packaging structure according to any one of claims 1 to 6, wherein the second packaging substrate comprises at least one layer of insulating carrier, and metal wiring on the lower surface of the insulating carrier;

The insulating carrier board is provided with a via hole, and the via hole is used to electrically connect the metal wiring on the lower surface of the insulating carrier board.
7. The chip packaging structure of claim 7, wherein the chip packaging structure further comprises a plurality of second connecting members arranged on the lower surface of the adapter assembly for connecting the adapter assembly with Printed circuit board electrical connection;

One of the first connectors is electrically connected to one of the second connectors through the through holes on the insulating carrier board.
8. The chip packaging structure according to claim 7, wherein the upper and lower surfaces of the insulating carrier board include an effective area and an ineffective area;

The metal wiring is located in the effective area;

The second packaging substrate further includes a metal film covering the inactive area; the metal film is disconnected from the metal wiring.
9. The chip packaging structure of claim 9, wherein the metal film and the metal wiring are made of the same material.
8. The chip packaging structure of claim 8, wherein the second connecting member is a solder ball or a bump.
4. The chip packaging structure of claim 1, wherein the semiconductor device comprises:

Bare chip

A plurality of fourth connecting members are arranged on the active surface of the bare chip and are used to electrically connect the bare chip and the first packaging substrate.
4. The chip packaging structure of claim 1, wherein the semiconductor device comprises:

At least two bare chips;

An adapter board for carrying the at least two bare chips;

A plurality of fourth connecting members arranged on the active surface of the bare chip and used to electrically connect the at least two bare chips with the adapter board;

A plurality of fifth connecting members are arranged on the lower surface of the transfer board and are used for electrically connecting the transfer board and the first packaging substrate.
4. The chip packaging structure of claim 1, wherein the chip packaging structure further comprises:

Heat-dissipating glue bonding glue, covering the semiconductor device;

A heat dissipation cover, covering the heat dissipation glue bonding glue and contacting the first packaging substrate;

The primer is arranged between the semiconductor device and the first packaging substrate, and between the first packaging substrate and the second packaging substrate adjacent to the first packaging substrate.
4. The chip packaging structure of claim 1, wherein the first connecting member is a solder ball or a bump.
An electronic device, characterized by comprising a printed circuit board, and the chip packaging structure according to any one of claims 1-15;

The switching component in the chip packaging structure is electrically connected with the printed circuit board.