WO2020140734A1 - 一种用于光放大器在线升级程序的方法和装置 - Google Patents

一种用于光放大器在线升级程序的方法和装置 Download PDF

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Publication number
WO2020140734A1
WO2020140734A1 PCT/CN2019/125254 CN2019125254W WO2020140734A1 WO 2020140734 A1 WO2020140734 A1 WO 2020140734A1 CN 2019125254 W CN2019125254 W CN 2019125254W WO 2020140734 A1 WO2020140734 A1 WO 2020140734A1
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Prior art keywords
microprocessor
programmable logic
upgrade
program
digital
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PCT/CN2019/125254
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English (en)
French (fr)
Inventor
于龙
罗旋
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武汉光迅科技股份有限公司
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Priority to EP19906802.4A priority Critical patent/EP3907834A4/en
Priority to US17/419,536 priority patent/US20220113955A1/en
Publication of WO2020140734A1 publication Critical patent/WO2020140734A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S3/00—Lasers, i.e. devices using stimulated emission of electromagnetic radiation in the infrared, visible or ultraviolet wave range
    • H01S3/10—Controlling the intensity, frequency, phase, polarisation or direction of the emitted radiation, e.g. switching, gating, modulating or demodulating
    • H01S3/10007—Controlling the intensity, frequency, phase, polarisation or direction of the emitted radiation, e.g. switching, gating, modulating or demodulating in optical amplifiers
    • H01S3/10015—Controlling the intensity, frequency, phase, polarisation or direction of the emitted radiation, e.g. switching, gating, modulating or demodulating in optical amplifiers by monitoring or controlling, e.g. attenuating, the input signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/29—Repeaters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S3/00—Lasers, i.e. devices using stimulated emission of electromagnetic radiation in the infrared, visible or ultraviolet wave range
    • H01S3/05—Construction or shape of optical resonators; Accommodation of active medium therein; Shape of active medium
    • H01S3/06—Construction or shape of active medium
    • H01S3/063—Waveguide lasers, i.e. whereby the dimensions of the waveguide are of the order of the light wavelength
    • H01S3/067—Fibre lasers
    • H01S3/06754—Fibre amplifiers

Definitions

  • the invention relates to the technical field of optical communication, in particular to a method and device for an online upgrade program of an optical amplifier.
  • control program of the optical amplifier is basically running on the microprocessor (Microcontroller Unit, abbreviated as MCU) and programmable logic device (Field-Programmable Gate Array, abbreviated as FPGA), but when the upgrade is already in the work of the transmission network
  • MCU Microcontroller Unit
  • FPGA Field-Programmable Gate Array
  • the amplifier program often interrupts the existing optical fiber communication service and cannot guarantee the continuous operation of the optical communication service, thereby affecting the stability and reliability of the entire optical communication system.
  • the microprocessor When the microprocessor receives the upgrade instruction and the upgrade code, it saves the upgrade code and sends the upgrade instruction to the programmable logic device;
  • the last saved upgrade code is loaded, and the last saved working state and parameters are sent to the programmable logic device;
  • the programmable logic device switches the working state of the digital-analog conversion circuit according to the received working state and parameters, so that the initial state of this operation is the same as the working state before the upgrade code is loaded.
  • the method further includes:
  • the microprocessor If it is powered on, the microprocessor sends the default working state and parameters to the programmable logic device, so that the programmable logic device controls the digital-to-analog conversion circuit to switch from the non-light state to the default working state ;
  • the microprocessor sends the last saved working state and parameters to the programmable logic device, so that the programmable logic device controls the digital-to-analog conversion circuit to switch to the last working state.
  • the microprocessor judges the loading mode through static random access memory, specifically:
  • the static random access memory stores data dynamically updated when the microprocessor is running. After the microprocessor loads the upgrade code saved last time, it reads the preset address space of the static random access memory. Data, and analyze the regularity of the data;
  • the read data is a random number, it is judged that the load is power-on load; if the read data has a preset rule, it is judged that the load is continuous light load.
  • the upgrade code received by the microprocessor is divided into multiple frames, each frame contains a check bit, and the program of the microprocessor and the programmable logic device includes a CRC check of the total package; then After receiving the upgrade code, the microprocessor performs verification, and when each frame of the upgrade code is verified correctly, and the CRC check of each packet is correct, an upgrade instruction is sent to the programmable logic device.
  • the upgrade code is stored in a program memory
  • the address space of the program memory includes a BOOTLOADER area, a program selection partition, a first partition, a second partition, and a golden partition; wherein, the microprocessor selects from the BOOTLOADER The partition starts to run the program, the first partition and the second partition alternately save the latest upgrade code, the program selects the partition to update according to the partition currently holding the upgrade code, the golden partition is the default partition of the optical amplifier, Used when the upgrade fails.
  • the digital-to-analog conversion circuit is a serial interface, including chip select, clock interface, and one data line; or the digital-to-analog conversion circuit is a parallel interface, including chip select, clock interface, and multiple data lines; wherein , The analog voltage of the digital-to-analog conversion circuit is controlled by controlling the corresponding chip select and clock interface, thereby achieving control of the digital-to-analog conversion circuit.
  • the present invention also provides an apparatus for online upgrade of an optical amplifier, which is used to complete the method for online upgrade of an optical amplifier described in the first aspect, which includes a microprocessor 1 and a programmable logic device 2.
  • Program memory 3 and digital-to-analog conversion circuit 4, the microprocessor 1 is in communication with the programmable logic device 2 and the program memory 3, respectively, the programmable logic device 2 and the digital-to-analog conversion circuit 4 Communication connection;
  • the microprocessor 1 is used to receive upgrade instructions and upgrade codes and interact with the program memory 3; the program memory 3 is used to store upgrade codes and the working state and parameters of the optical amplifier; the programmable logic The device 2 is used to control the digital-to-analog conversion circuit 4 according to the upgrade instruction, working status and parameters; the digital-to-analog conversion circuit 4 is used to convert the control digital signal output from the programmable logic device 2 to an analog voltage.
  • a static random access memory 5 is further included.
  • the static random access memory 5 is in communication with the microprocessor 1 for storing data that is dynamically updated when the microprocessor 1 is running, thereby enabling the The microprocessor 1 determines the loading mode; wherein, the loading mode is divided into power-on loading and constant light loading.
  • a pump laser control system 6 and/or a tunable optical attenuator control system 7 is further included.
  • the pump laser control system 6 is connected to the digital-to-analog conversion circuit 4 and is used for controlling the digital-to-analog conversion circuit. 4
  • the analog voltage output adjusts the current of the pump laser, and then adjusts the output light size;
  • the tunable optical attenuator control system 7 is connected to the digital-to-analog conversion circuit 4 for adjusting the attenuation value of the tunable optical attenuator according to the analog voltage output by the digital-to-analog conversion circuit 4.
  • a passive optical system 8 is further included.
  • the passive optical system 8 is connected to the pump laser control system 6 for coupling the input light and the pump light of the pump laser to a gain medium to realize The magnification of the input light.
  • the invention Based on the control of the traditional optical amplifier, the invention combines the characteristics of the microprocessor and the programmable logic device itself, and uses the programmable logic device and the digital-to-analog conversion characteristics to perform special control during the upgrade.
  • the FPGA The digital-to-analog conversion circuit can be stopped.
  • the MCU saves the current working state and parameters.
  • the FPGA can switch from the last saved working state to enter the normal working state to complete the smooth transition of the business and ensure The business of optical amplifiers is not interrupted, thereby improving the stability and reliability of the entire optical communication system.
  • FIG. 1 is a schematic diagram of a transmission network system provided by an embodiment of the present invention.
  • FIG. 2 is a diagram of an apparatus for an online upgrade program of an optical amplifier provided by an embodiment of the present invention
  • FIG. 3 is a flowchart of a method for an online upgrade program of an optical amplifier according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of the FLASH address space provided by an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a specific working process for an online upgrade program of an optical amplifier provided by an embodiment of the present invention
  • FIG. 6 is a schematic diagram of a processing flow after an MCU receives an upgrade command according to an embodiment of the present invention
  • FIG. 7 is a schematic flowchart of the MCU provided by the embodiment of the present invention after loading a new program
  • FIG. 8 is a schematic diagram of a processing flow after an FPGA receives an upgrade command according to an embodiment of the present invention
  • FIG. 9 is a schematic flowchart of the FPGA after loading a new program according to an embodiment of the present invention.
  • the symbol “/” means to have two functions at the same time
  • the symbol “A and/or B” means that the combination between the front and rear objects connected by the symbol includes “A”, “ B", “A and B” three cases.
  • a typical transmission network system is simplified as shown in FIG. 1 and includes an optical amplifier 201, a data center unit 202, an optical cross-connect equipment unit 203, a gateway unit 204, a switching center unit 205, and an optical fiber connection line 206.
  • an optical amplifier 201 In order to increase the transmission distance and improve the signal-to-noise ratio, a plurality of optical amplifiers 201 are placed in the middle of the optical fiber connection line 206. The performance of the optical amplifier directly determines the quality of the optical communication service in the transmission network. Therefore, when upgrading the optical amplifier program, it is an essential requirement not to interrupt the optical communication service.
  • an embodiment of the present invention provides a method for an online upgrade program of an optical amplifier, which uses the apparatus shown in FIG. 2 and includes a microprocessor (MCU) 1, a programmable logic device (FPGA) 2, Program memory (FLASH) 3. Digital-to-analog converter (DAC) 4 and static random access memory (Static Random Access Memory, SRAM) 5, the microprocessor 1 communicates
  • the interface a communicates with a computer or a network management system, and communicates with the programmable logic device 2 through an on-board bus interface b, and the programmable logic device 2 communicates with the digital-to-analog conversion circuit 4.
  • the method refers to FIG. 3 and specifically includes the following steps:
  • Step 301 When the microprocessor receives the upgrade instruction and the upgrade code, it saves the upgrade code and sends the upgrade instruction to the programmable logic device.
  • the optical amplifier After power-on, the optical amplifier enters the normal working state.
  • the microprocessor 1 communicates with the computer or the network management system through the communication interface a, and then continuously receives data and commands; after receiving the upgrade instruction, The microprocessor 1 receives the upgrade code, writes the upgrade code to the program memory 3, and sends an upgrade instruction to the programmable logic device 2 through the on-board bus interface b.
  • the upgrade code includes an MCU program upgrade code and an FPGA program upgrade code, so as to complete the program upgrade of the microprocessor 1 and the programmable logic device 2 together.
  • step 302 the programmable logic device stops the operation of the digital-analog conversion circuit after receiving the upgrade instruction, and sends a response back to the microprocessor so that the microprocessor can save the current working state and parameters.
  • the programmable logic device 2 receives the commands and parameters of the microprocessor 1 through the on-board bus interface b, and then controls the digital-to-analog conversion circuit 4 to ensure the normal operation and operation of the optical amplifier.
  • the programmable logic device 2 receives the upgrade instruction from the microprocessor 1, on the one hand, the working state and parameters of the optical amplifier remain unchanged, and the operation of the digital-to-analog conversion circuit 4 is stopped, so that the digital
  • the analog conversion circuit 4 keeps the current state unchanged, that is, the analog signal voltage does not change, so that the optical amplifier enters the continuous light holding state; on the other hand, the current working state and parameters of the optical amplifier are passed to the microprocessor 1, and a reply is sent back
  • the command causes the microprocessor 1 to save the current working state and parameters in the program memory 3.
  • Step 303 After restarting, the microprocessor loads the last saved upgrade code, and sends the last saved working state and parameters to the programmable logic device.
  • the microprocessor 1 restarts, and runs a new program from the address 0 of the program memory 3, that is, loads the latest upgrade code stored in the program memory 3, and during the loading process, the digital-to-analog conversion circuit 4 has been in the state of stopping updating, and the optical communication service has not been interrupted; after running the new code, the microprocessor 1 reads the last saved working state and parameters from the program memory 3, and through the on-board bus interface b The programmable logic device 2 sends the last saved working state and parameters.
  • Step 304 The programmable logic device switches the working state of the digital-to-analog conversion circuit according to the received working state and parameters, so that the initial state of this operation is the same as the working state before loading the upgrade code.
  • the programmable logic device 2 After receiving the last saved working state and parameters passed from the microprocessor 1, the programmable logic device 2 switches from the last working state to enter the normal working state, that is, the data
  • the digital signal of the analog conversion circuit 4 is set as the last saved data, so that the initial state of this operation is the same as the last saved working state, and then the last saved working state is switched to the normal working state, so that the business can be completed Smooth transition.
  • the invention Based on the traditional optical amplifier control, the invention combines the characteristics of the microprocessor and the programmable logic device itself.
  • the FPGA can stop the digital-analog conversion circuit and the MCU saves the current working state and parameters.
  • the FPGA can switch according to the last saved working state and parameters, so that the initial state of this operation is the same as the previous working state, to ensure that the optical amplifier business is not interrupted, complete the smooth transition of the business, and thus improve the entire Stability and reliability of optical communication systems.
  • the static random access memory 5 may be used to determine the loading mode in advance, that is, the current loading mode Whether it is power-on loading or continuous light-loading; if it is power-on loading, the optical amplifier is in the dark state at this time, there is no need to consider whether to interrupt the service, the system executes from zero, specifically: the microprocessor 1 will default the working state and The parameters are sent to the programmable logic device 2 so that the programmable logic device 2 controls the digital-to-analog conversion circuit 4 to switch from the non-light state to the default working state, so that the optical amplifier enters normal operation; if it is Continuous light loading, the microprocessor sends the last saved working state and parameters to the programmable logic device, so that the programmable logic device controls the digital-to-analog conversion circuit to switch to the last working state first, and then After entering the normal working state, step 304 is executed.
  • the default working state is
  • step 302 after the microprocessor 1 saves the current working state and parameters to the program memory 3, it writes data to the preset address space of the static random access memory 5 to make the static
  • the random access memory 5 stores data dynamically updated when the microprocessor operates.
  • step 303 after loading the upgrade code saved last time, the microprocessor reads the data of the preset address space of the static random access memory 5, and applies the characteristics of the SRAM itself and the law of the algorithm to the data Perform an analysis to determine the loading mode; if the read data is a random number, the current load is determined to be powered on; if the read data has a preset rule, the current load is determined to be continuous light loading.
  • the internal data of the static random access memory 5 is lost after the power is turned off, so the internal data is a random number after the power is turned off and then on.
  • the microprocessor 1 reads the preset address space for the first time In the case of data, the data is randomly distributed; thereafter, the microprocessor 1 writes regular data. When reloading and running, the read data is regular data. At this time, it can be determined as constant light loading.
  • the preset address space is not uniquely limited, and it is sufficient to ensure that this space is not used by other system applications; it is assumed that the preset address space in the SRAM is between 1000 and 1100, if the address 1000 is written with 1, the address 1001 Write 2, and so on, there is a law of adding 1 to the address space and 1 to the data, or if the data in the first 50 address spaces is 0x55 and the last 50 spaces are 0xaa, etc., there is also a certain regularity, it can be determined as Constant light loading.
  • the upgrade code received by the microprocessor 1 through the communication interface a is divided into multiple frames, each frame contains a check bit, which can improve the transmission of each frame. The reliability is better adapted to the transmission of multiple communication protocols.
  • the programs of the microprocessor 1 and the programmable logic device 2 include a CRC check of the total package, and then the integrity of the data package can be guaranteed by the check.
  • the microprocessor 1 performs verification after receiving the upgrade code, including verifying each frame of the upgrade code and CRC checking of the data packet, when each frame of the upgrade code is verified correctly , And when the CRC check of each packet is correct, the microprocessor 1 sends an upgrade instruction to the programmable logic device 2; when there is a check error in the upgrade code, the microprocessor 1 continues to pass The communication interface a receives new instructions and data until the verification is successful.
  • the address space of the program memory 3 is first divided into a BOOTLOADE area, a program selection partition, and a software partition, and the software partition is further divided into a first partition, a second partition, and a golden partition.
  • the system when the system is powered on or reset, it usually executes from address 0, and this address is usually arranged as the BOOTLOADER program of the system, that is, the microprocessor 1 starts running the program from the BOOTLOADER area; the golden partition
  • the default partition of the optical amplifier which is only used when the upgrade fails, or when the first partition and the second partition are damaged; the first partition and the second partition alternately save the corresponding latest upgrade code ,
  • the program selection partition is updated according to the partition where the upgrade code is currently saved; when the upgrade fails, the program selection partition is not updated, and the code is rolled back to the program state before the upgrade to ensure the normal use of the optical amplifier.
  • the programs in the BOOTLOADER area and the golden partition will not be upgraded online, to ensure that the programs can still be upgraded online in extreme cases, improving product reliability.
  • the program selects the partition, the first partition, and the second partition, and there is a risk of failure in writing.
  • the BOOTLOADER area and the golden partition will not change, that is, these two partitions will not have a write operation, the mechanism is roughly as follows: the BOOTLOADER area and the golden partition are both valid content at the factory, and the first partition is also valid content, And the program selects the partition to write 1 (indicating that the first partition saves the code at this time); when upgrading once, the second partition writes valid content first, and then the program selects the partition to write 2 (indicating that the second partition saves code at this time) ; Upgrade again, the first partition writes valid content, the program selects the partition to write 1, and so on; when the program selects the partition to write failed, such as 100, then the golden partition works , And then the system can be guaranteed to run normally and can be upgraded again.
  • the address space of the program memory 3 except the BOOTLOADE area, the program selection partition, and the software partition also includes a firmware partition, which is also divided into a first partition, a second partition, and a golden partition; the software partition is used to write MCU program upgrade codes, and the firmware partition is used to write FPGA programs Upgrade code.
  • the function of each partition in the firmware partition is similar to that of the software partition, and reference may be made to the above introduction, which will not be repeated here.
  • the digital-to-analog conversion circuit 4 may be a serial interface or a parallel interface, and the programmable logic device 2 controls the size of the analog voltage of the digital-to-analog conversion circuit 4 through a digital interface to ensure the upgrade Continuous light during the process.
  • the digital-to-analog conversion circuit 4 when the digital-to-analog conversion circuit 4 is a serial interface, it includes chip select, clock interface, and one data line; when the digital-to-analog conversion circuit 4 is a parallel interface, it includes chip select, clock interface, and multiple channels Data cable.
  • the programmable logic device 2 controls the analog voltage of the digital-to-analog conversion circuit 4 by controlling the corresponding chip select and clock interface:
  • the chip select signal and the clock level are set to inactive levels, thereby stopping the operation of the digital-to-analog conversion circuit 4 so that the analog voltage of the digital-to-analog conversion circuit 4 is no longer updated and maintained Fixed;
  • the chip select signal and the clock level are set to At the same level before the upgrade code is loaded, the working state of the digital-to-analog conversion circuit 4 is switched, so that the optical amplifier outputs light continuously, keeping the state unchanged.
  • the upgrade method described in the embodiments of the present invention may be used for various optical amplifiers, such as Raman fiber amplifiers, erbium-doped fiber amplifiers, ytterbium-doped fiber amplifiers, hybrid fiber amplifiers, and high-power fiber amplifiers.
  • the MCU program and the FPGA program are upgraded together.
  • the system also supports the independent upgrade of the MCU program and the FPGA program.
  • the upgrade time can be saved to a certain extent. To reduce risks and increase efficiency.
  • the MCU when receiving the upgrade instruction, the MCU receives the corresponding MCU program upgrade code, and verifies each frame of the upgrade code separately. After the verification is correct, it is written to FLASH (the first partition or Second partition); Then, the CRC check of the data packet is performed.
  • the program in the FLASH is set according to the programming address of the upgrade code to select the partition, and the upgrade command is sent to the FPGA; when the FPGA returns a reply
  • the MCU saves the current working state and parameters in FLASH, and writes data to the preset address space of SRAM; the specific process can refer to FIG. 6.
  • the second step is to load a new program: restart the MCU, start the program from the BOOTLOADE area of FLASH, and then select the partition according to the program to determine the current interval to save the upgrade code, and load the latest program from the corresponding interval, such as the program selection
  • the partition is currently marked 1
  • the latest program is loaded from the first partition; at the same time, the MCU reads the SRAM preset address space data to determine the current loading mode, and then indicates the loading mode to the FPGA; if it is powered on, the MCU Send the default working state and parameters to the FPGA. If the light is continuously loaded, the MCU reads the last saved working state and parameters from FLASH and sends them to the FPGA; for the specific process, please refer to Figure 7.
  • the FPGA stops the DAC operation and controls the analog signal voltage of the DAC to remain unchanged, thereby maintaining the working state and parameters unchanged, and at the same time the FPGA will work on the optical amplifier
  • the state and parameters are saved and passed to the MCU, and a reply signal is sent back, waiting for reload; the specific process can refer to Figure 8.
  • the second step is to load the new program: the MCU loads the FPGA program upgrade code from the corresponding FLASH partition and passes it to the FPGA; the FPGA reads the loading mode from the MCU. If it is powered on and loaded, the FPGA receives the MCU. Default working state and parameters, the initial digital signal of the DAC is set to 0, the FPGA switches from the zero state to the normal working state; if it is constant light loading, the FPGA receives the last saved working state and parameters passed by the MCU, The initial digital signal of the DAC is set as the last saved data, and the FPGA switches from the last saved working state to the normal working state; the specific process can refer to FIG. 9.
  • the present invention has the following beneficial effects: without adding or changing any hardware circuit of the optical amplifier, through system design optimization, using programmable logic devices and digital-to-analog conversion characteristics, in Special control is performed during the upgrade, so that the fiber communication service is not interrupted during the program update and upgrade, and the economic benefit is significantly improved; the full use of the device characteristics of the existing static random access memory of the optical amplifier, combined with a simple algorithm, can be judged to be powered on Loading and continuous light loading provide the basis for discriminating the online upgrade of the entire device; careful arrangement of the program memory address space division reduces the upgrade risk, improves the reliability of the optical amplifier, and extends product vitality.
  • an embodiment of the present invention also provides an apparatus for an online upgrade program of an optical amplifier, which can be used to implement the method of Embodiment 1.
  • the apparatus includes a microprocessor 1, a programmable logic device 2, a program memory 3, and a digital-to-analog conversion circuit 4;
  • the microprocessor 1 is used to receive upgrade instructions and upgrade codes, and the program memory 3 is used For storing the upgrade code and the working state and parameters of the optical amplifier;
  • the programmable logic device 2 is used to control the digital-analog conversion circuit 4 according to the upgrade instruction and the working state and parameters, and the digital-analog conversion circuit 4 It is used to convert the control digital signal output by the programmable logic device 2 into an analog voltage.
  • the microprocessor 1 communicates with a computer or a network management system through a communication interface a, and communicates with the programmable logic device 2 through an on-board bus interface b, so that the microprocessor 1 can receive an upgrade command through the communication interface a And the upgrade codes of the MCU program and the FPGA program, and perform information interaction with the programmable logic device 2 through the on-board bus interface b, and at the same time program the data and/or parameters to be saved into the program memory 3.
  • the programmable logic device 2 is communicatively connected to the digital-to-analog conversion circuit 4, and the programmable logic device 2 receives commands and parameters of the microprocessor 1 through an on-board bus interface b, and then can be processed according to the microprocessing
  • the commands and parameters transmitted by the controller 1 control the digital-to-analog conversion circuit 4 to ensure that the optical transmission service of the amplifier is continuous.
  • the invention Based on the control of the traditional optical amplifier, the invention combines the characteristics of the microprocessor and the programmable logic device itself, and uses the programmable logic device and the digital-to-analog conversion characteristics through the system design without adding or changing the optical amplifier hardware circuit. Optimization, special control during the upgrade, to achieve the effect of not interrupting the optical fiber communication service during the program upgrade, complete the smooth transition of the business, and thereby improve the stability and reliability of the entire optical communication system.
  • the optical amplifier may be any one of Raman fiber amplifier, erbium-doped fiber amplifier, ytterbium-doped fiber amplifier, hybrid fiber amplifier and high-power fiber amplifier, which is not limited.
  • the device may further include a static random access memory 5.
  • the static random access memory 5 is in communication with the microprocessor 1 and is used to save the dynamic update of the microprocessor 1 during operation.
  • the data in turn, enables the microprocessor 1 to determine the loading mode; wherein, the loading mode is divided into power-on loading and constant light loading.
  • the microprocessor 1 writes data to the preset address space of the static random access memory 5 in advance, and then reads the data of the preset address space of the static random access memory 5 and applies the characteristics of the SRAM itself and The algorithm analyzes the regularity of the data to determine the loading mode.
  • the internal data of the static random access memory 5 Since the internal data of the static random access memory 5 will be lost after power off, the internal data is a random number after power off and then on, when the microprocessor 1 reads the data in the preset address space for the first time The data is randomly distributed; thereafter, the microprocessor 1 writes regular data, and when reloaded, the read data is regular data. Therefore, if the data read by the microprocessor 1 is a random number, it is determined that the current load is a power-on load; if the read data has regularity, the current load is determined to be a constant light load.
  • the present invention makes full use of the device characteristics of the existing static random access memory of the optical amplifier, combined with a simple algorithm, can judge the power-on loading and the continuous light loading, and provide a basis for the online upgrade of the entire device.
  • the device further includes a pump laser control system 6 and/or a tunable optical attenuator control system 7.
  • the pump laser control system 6 is connected to the digital-to-analog conversion circuit 4 for The analog voltage output from the digital-to-analog conversion circuit 4 adjusts the current of the pump laser, thereby adjusting the output light size;
  • the tunable optical attenuator control system 7 is connected to the digital-to-analog conversion circuit 4 for The analog voltage output by the conversion circuit 4 adjusts the attenuation value of the tunable optical attenuator.
  • the device further includes a passive optical system 8, which is connected to the pump laser control system 6 for coupling the input light and the pump light of the pump laser to a gain medium to realize Amplification of input light; wherein, the passive optical system 8 can also include optical devices such as isolators and filters to achieve various indicators of optical performance.
  • a passive optical system 8 which is connected to the pump laser control system 6 for coupling the input light and the pump light of the pump laser to a gain medium to realize Amplification of input light; wherein, the passive optical system 8 can also include optical devices such as isolators and filters to achieve various indicators of optical performance.
  • the core is the control of the pump laser and tunable optical attenuator.
  • the input light and the pump light can be coupled to the erbium-doped fiber through a coupler.
  • the erbium ion in the erbium fiber is in an excited state under the excitation of the pump light.
  • the signal photon passes through
  • the stimulated radiation effect occurs in the interaction of erbium ions in the erbium-doped fiber.
  • the metastable Er3+ ion transitions to the ground state in the form of stimulated radiation and generates photons that are exactly the same as the photons in the incident signal light. Zoom in.
  • the size of the pump light can be adjusted, thereby adjusting the output light.
  • the attenuation value of the tunable optical attenuator can also be adjusted.
  • the digital-to-analog conversion circuit 4 may be a serial interface or a parallel interface, and the programmable logic device 2 controls the size of the analog voltage of the digital-to-analog conversion circuit 4 through a digital interface to ensure the upgrade Continuous light during the process.
  • the digital-to-analog conversion circuit 4 when the digital-to-analog conversion circuit 4 is a serial interface, it includes chip select, clock interface, and one data line; when the digital-to-analog conversion circuit 4 is a parallel interface, it includes chip select, clock interface, and multiple channels Data cable.
  • the programmable logic device 2 sets the chip select signal and the clock level by controlling the corresponding chip select and clock interfaces, and then controls the analog voltage of the digital-to-analog conversion circuit 4 to make the digital-to-analog conversion circuit 4
  • the analog voltage of is no longer updated, remains fixed, and the optical amplifier outputs constant light, keeping the state unchanged.
  • the address space of the program memory 3 is first divided into a BOOTLOADE area, a program selection partition, and a software partition, and the software partition is further divided into a first partition, a second partition, and a golden partition.
  • the microprocessor 1 starts running the program from the BOOTLOADER area, and the golden partition is the default partition of the optical amplifier, which is only used when the upgrade fails, or when the first partition and the second partition are damaged Use; the first partition and the second partition alternately save the corresponding latest upgrade code, the program selection partition is updated according to the partition where the upgrade code is currently saved; when the upgrade fails, the program selection partition is not updated, The code is rolled back to the state of the program before the upgrade to ensure that the optical amplifier continues to be used normally.
  • the programs in the BOOTLOADER area and the golden partition will not be upgraded online, to ensure that the programs can still be upgraded online in extreme cases, thereby improving product reliability.
  • the address space of the program memory 3 further includes a firmware partition, and the firmware partition is also divided into a first partition, a second partition, and a golden partition; the software partition is used for When writing the MCU program upgrade code, the firmware partition is used to write the FPGA program upgrade code, and the functions of each partition in the firmware partition are similar to those of the software partition.
  • the present invention has the following beneficial effects: without adding or changing any hardware circuit of the optical amplifier, through system design optimization, using programmable logic devices and digital-to-analog conversion characteristics, special control is performed during upgrade , To achieve uninterrupted optical fiber communication services during program updates and upgrades, and significantly improve economic efficiency; make full use of the device characteristics of the existing static random access memory of the optical amplifier, combined with a simple algorithm to determine power-on loading and continuous light loading, Provide a basis for discriminating the online upgrade of the entire device; make detailed arrangements for the division of the program memory address space, reduce the upgrade risk, improve the reliability of the optical amplifier, and extend the product vitality.

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Abstract

一种用于光放大器在线升级程序的方法，当发送升级程序命令时，微处理器（1）同时接收微处理器（1）和可编程逻辑器件（2）的升级程序并保存在程序存储器（3），同时向可编程逻辑器件（2）发送升级指令；可编程逻辑器件（2）根据相应的指令，停止数模转换电路（4）工作，保持当前的状态不变；微处理器（1）加载新的微处理器（1）和可编程逻辑器件（2）代码过程中数模转换电路（4）一直处于停止更新状态；微处理器（1）和可编程逻辑器件（2）运行新代码后，读取上次保存的数据，并从上次的工作状态起始做切换，进入正常工作状态。还包括一种用于执行光放大器在线升级程序的方法的装置。在传统光放大器控制基础上，结合微处理器（1）和可编程逻辑器件（2）本身的特点，保证光放大器业务不中断，完成业务的平滑过渡，进而提升了整个光通信系统的稳定性与可靠性。

Description

一种用于光放大器在线升级程序的方法和装置 【技术领域】
本发明涉及光通信技术领域，具体涉及一种用于光放大器在线升级程序的方法和装置。
【背景技术】
光放大器是光通信网络中的关键模块之一，主要是在光纤通信线路中，实现光信号放大，光放大器性能直接决定着传输网中光通信业务的质量。当光放大器应用在骨干网络时，由于工程实际需求或者设计存在问题，通常需要对程序升级并运行新的程序。这时就需要不能中断光通信业务，即在输入光等外界环境变量没有变化的情况下，使光放大器实现程序平滑升级，光放大器在程序更新之后继续保持原有的工作状态，同时输出光信号不变，实现光放大器平稳切换。
目前，光放大器的控制程序基本是在微处理器(Microcontroller Unit，简写为MCU)和可编程逻辑器件(Field－Programmable Gate Array，简写为FPGA)运行，然而当升级已处于传输网络工作中的光放大器程序时，往往会中断已有的光纤通信业务，无法保证光通信业务的连续工作，进而影响整个光通信系统的稳定性与可靠性。
鉴于此，克服上述现有技术所存在的缺陷是本技术领域亟待解决的问题。
【发明内容】
本发明需要解决的技术问题是：
当升级已处于传输网络工作中的光放大器程序时，往往会中断已有的 光纤通信业务，无法保证光通信业务的连续工作，进而影响整个光通信系统的稳定性与可靠性。
本发明通过如下技术方案达到上述目的：
第一方面，本发明提供了一种用于光放大器在线升级程序的方法，包括：
当微处理器接收到升级指令和升级代码时，将所述升级代码保存，并向可编程逻辑器件发送升级指令；
可编程逻辑器件接收到升级指令后停止数模转换电路工作，并向所述微处理器回送应答，使所述微处理器保存当前工作状态和参数；
所述微处理器重新启动后加载上次保存的升级代码，并将上次保存的工作状态和参数发送给所述可编程逻辑器件；
所述可编程逻辑器件根据接收到的工作状态和参数，对数模转换电路的工作状态进行切换，使本次运行的初始状态与加载升级代码前的工作状态相同。
优选的，所述微处理器重新启动并加载上次保存的升级代码之后，所述方法还包括：
判断本次加载模式为上电加载还是不断光加载；
如果是上电加载，则所述微处理器将缺省工作状态和参数发送给所述可编程逻辑器件，使所述可编程逻辑器件控制数模转换电路从无光状态切换到缺省工作状态；
如果是不断光加载，则所述微处理器将上次保存的工作状态和参数发送给所述可编程逻辑器件，使所述可编程逻辑器件控制数模转换电路切换到上次工作状态。
优选的，所述微处理器通过静态随机存取存储器来判断加载模式，具体为：
所述静态随机存取存储器中保存有所述微处理器运行时动态更新的数 据，所述微处理器加载上次保存的升级代码后，读取所述静态随机存取存储器预设地址空间的数据，并对数据的规律性进行分析；
如果读取的数据为随机数，则判断本次加载为上电加载；如果读取的数据具有预设规律，则判断本次加载为不断光加载。
优选的，所述微处理器接收的升级代码被分成多帧，每帧均包含校验位，且所述微处理器和所述可编程逻辑器件的程序内含总包的CRC校验；则所述微处理器接收到升级代码后进行校验，当所述升级代码的每帧均校验正确，且各包的CRC校验正确时，向可编程逻辑器件发送升级指令。
优选的，所述升级代码保存在程序存储器内，所述程序存储器的地址空间包括BOOTLOADER区、程序选择分区、第一分区、第二分区和黄金分区；其中，所述微处理器从所述BOOTLOADER分区开始运行程序，所述第一分区和所述第二分区交替保存最新的升级代码，所述程序选择分区根据当前保存升级代码的分区进行更新，所述黄金分区为光放大器的缺省分区，在升级失败时使用。
优选的，所述数模转换电路为串行接口，包括片选、时钟接口和1路数据线；或者所述数模转换电路为并行接口，包括片选、时钟接口和多路数据线；其中，所述通过控制相应的片选和时钟接口控制所述数模转换电路的模拟电压大小，进而实现对所述数模转换电路的控制。
第二方面，本发明还提供了一种用于光放大器在线升级程序的装置，用于完成第一方面所述的用于光放大器在线升级程序的方法，包括微处理器1、可编程逻辑器件2、程序存储器3和数模转换电路4，所述微处理器1分别与所述可编程逻辑器件2和所述程序存储器3通信连接，所述可编程逻辑器件2与所述数模转换电路4通信连接；
其中，所述微处理器1用于接收升级指令和升级代码，并与所述程序存储器3交互；所述程序存储器3用于存储升级代码以及光放大器的工作状态和参数；所述可编程逻辑器件2用于根据升级指令以及工作状态和参 数，控制所述数模转换电路4；所述数模转换电路4用于将所述可编程逻辑器件2输出的控制数字信号转为模拟电压。
优选的，还包括静态随机存取存储器5，所述静态随机存取存储器5与所述微处理器1通信连接，用于保存所述微处理器1运行时动态更新的数据，进而使所述微处理器1判断加载模式；其中，所述加载模式分为上电加载和不断光加载。
优选的，还包括泵浦激光器控制系统6和/或可调谐光衰减器控制系统7，所述泵浦激光器控制系统6与所述数模转换电路4连接，用于根据所述数模转换电路4输出的模拟电压调节泵浦激光器的电流，进而调节输出光大小；
所述可调谐光衰减器控制系统7与所述数模转换电路4连接，用于根据所述数模转换电路4输出的模拟电压调节可调谐光衰减器的衰减值大小。
优选的，还包括无源光学系统8，所述无源光学系统8与所述泵浦激光器控制系统6连接，用于将输入光和所述泵浦激光器的泵浦光耦合到增益介质，实现输入光的放大。
与现有技术相比，本发明的有益效果是：
本发明在传统光放大器控制基础上，结合微处理器和可编程逻辑器件本身的特点，利用可编程逻辑器件和数模转换特性，在升级时进行特殊控制，当需要升级光放大器程序时，FPGA可停止数模转换电路工作，MCU将当前的工作状态和参数保存，当加载新程序时，FPGA可从上次保存的工作状态起始做切换，进入正常工作状态，完成业务的平滑过渡，保证光放大器业务不中断，进而提升了整个光通信系统的稳定性与可靠性。
【附图说明】
为了更清楚地说明本发明实施例的技术方案，下面将对本发明实施例中所需要使用的附图作简单地介绍。显而易见地，下面所描述的附图仅仅 是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种传输网系统的示意图；
图2为本发明实施例提供的一种用于光放大器在线升级程序的装置图；
图3为本发明实施例提供的一种用于光放大器在线升级程序的方法流程图；
图4为本发明实施例提供的FLASH地址空间的划分示意图；
图5为本发明实施例提供的一种用于光放大器在线升级程序的具体工作流程示意图；
图6为本发明实施例提供的MCU接收升级命令后的处理流程示意图；
图7为本发明实施例提供的MCU加载新程序后的流程示意图；
图8为本发明实施例提供的FPGA接收升级命令后的处理流程示意图；
图9为本发明实施例提供的FPGA加载新程序后的流程示意图。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
在本发明各实施例中，符号“/”表示同时具有两种功能的含义，而对于符号“A和/或B”则表明由该符号连接的前后对象之间的组合包括“A”、“B”、“A和B”三种情况。
此外，下面所描述的本发明各个实施方式中所涉及到的技术特征只要彼此之间未构成冲突就可以相互组合。下面就参考附图和实施例结合来详细说明本发明。
实施例1：
典型的传输网系统简化后如图1所示，包括光放大器201、数据中心单 元202、光交叉设备单元203、网关单元204、交换中心单元205以及光纤连接线206。其中，为了增加传输距离、提高信噪比，所述光纤连接线206中间放置有多个光放大器201。而光放大器的性能直接决定着传输网中光通信业务的质量，因此，升级光放大器程序时，不中断光通信业务是一个必备的要求。
为解决上述问题，本发明实施例提供了一种用于光放大器在线升级程序的方法，采用如图2所示的装置，包括微处理器(MCU)1、可编程逻辑器件(FPGA)2、程序存储器(FLASH)3、数模转换电路(digital-to-analog converter，简写为DAC)4和静态随机存取存储器(Static Random Access Memory，简写为SRAM)5，所述微处理器1通过通信接口a与计算机或者网管系统通信，通过板内总线接口b与所述可编程逻辑器件2通信，所述可编程逻辑器件2与所述数模转换电路4通信连接。通过上述装置，所述方法参考图3，具体包括以下步骤：
步骤301，当微处理器接收到升级指令和升级代码时，将所述升级代码保存，并向可编程逻辑器件发送升级指令。
上电后，光放大器进入正常工作状态，在正常工作过程中，所述微处理器1通过所述通信接口a与计算机或者网管系统通信，进而不断接收数据和命令；当接收到升级指令后，所述微处理器1接收升级代码，将所述升级代码烧写至所述程序存储器3，并通过板内总线接口b向所述可编程逻辑器件2发送升级指令。其中，所述升级代码包括MCU程序升级代码和FPGA程序升级代码，以便完成所述微处理器1和所述可编程逻辑器件2的程序共同升级。
步骤302，可编程逻辑器件接收到升级指令后停止数模转换电路工作，并向所述微处理器回送应答，使所述微处理器保存当前工作状态和参数。
所述可编程逻辑器件2通过板内总线接口b接收所述微处理器1的命令和参数，进而控制所述数模转化电路4，保证光放大器的正常运行和工作。 当所述可编程逻辑器件2接收到所述微处理器1传递来的升级指令后，一方面保持光放大器的工作状态和参数不变，停止所述数模转化电路4工作，使所述数模转换电路4保持当前的状态不变，即模拟信号电压不变，使光放大器进入不断光保持状态；另一方面将光放大器当前的工作状态和参数传递给所述微处理器1，回送应答命令，使所述微处理器1将当前的工作状态和参数保存至所述程序存储器3中。
步骤303，所述微处理器重新启动后加载上次保存的升级代码，并将上次保存的工作状态和参数发送给所述可编程逻辑器件。
所述微处理器1重新启动，并从所述程序存储器3的地址0运行新的程序，即加载所述程序存储器3中保存的最新的升级代码，在加载过程中，所述数模转换电路4一直处于停止更新状态，光通信业务没有中断；运行新代码后，所述微处理器1从所述程序存储器3中读取上次保存的工作状态和参数，并通过板内总线接口b向所述可编程逻辑器件2发送上次保存的工作状态和参数。
步骤304，所述可编程逻辑器件根据接收到的工作状态和参数，对数模转换电路的工作状态进行切换，使本次运行的初始状态与加载升级代码前的工作状态相同。
所述可编程逻辑器件2接收到所述微处理器1传递来的上次保存的工作状态和参数后，从上次的工作状态起始做切换，进入正常工作状态，也就是将所述数模转换电路4的数字信号定为上次保存的数据，使本次运行的初始状态与上次保存的工作状态相同，再从上次保存的工作状态切换到正常工作状态，从而可完成业务的平滑过渡。
本发明在传统光放大器控制基础上，结合微处理器和可编程逻辑器件本身的特点，当需要升级光放大器程序时，FPGA可停止数模转换电路工作，MCU将当前的工作状态和参数保存，当加载升级代码后FPGA可根据上次保存的工作状态和参数进行切换，使本次运行的初始状态与之前的工作状 态相同，保证光放大器业务不中断，完成业务的平滑过渡，进而提升了整个光通信系统的稳定性与可靠性。
其中，在所述步骤303中，所述微处理器1重新启动并加载上次保存的升级代码之后，还可预先通过所述静态随机存取存储器5来判断加载模式，即判断本次加载模式为上电加载还是不断光加载；如果是上电加载，此时光放大器为无光状态，则无需考虑是否中断业务，系统从零执行，具体为：所述微处理器1将缺省工作状态和参数发送给所述可编程逻辑器件2，使所述可编程逻辑器件2控制所述数模转换电路4从无光状态开始切换，切换到缺省工作状态，使光放大器进入正常运行；如果是不断光加载，则所述微处理器将上次保存的工作状态和参数发送给所述可编程逻辑器件，使所述可编程逻辑器件控制数模转换电路首先切换到上次工作状态，然后再进入正常工作状态，即执行所述步骤304。其中，所述缺省工作状态为默认工作状态，可根据实际需要预先设置并存储在所述程序存储器3中。加载模式的判断具体如下：
在所述步骤302中，所述微处理器1将当前工作状态和参数保存至所述程序存储器3后，向所述静态随机存取存储器5的预设地址空间写入数据，使所述静态随机存取存储器5中保存有所述微处理器运行时动态更新的数据。在所述步骤303中，所述微处理器加载上次保存的升级代码后，读取所述静态随机存取存储器5预设地址空间的数据，并应用SRAM本身的特性和算法对数据的规律性进行分析，进而判断加载模式；如果读取的数据为随机数，则判断本次加载为上电加载；如果读取的数据具有预设规律，则判断本次加载为不断光加载。这是因为所述静态随机存取存储器5在断电后内部数据全部丢失，所以断电再上电后内部数据为随机数，当所述微处理器1第一次读取预设地址空间的数据时，数据随机分布；此后所述微处理器1写入规律数据，当重新加载运行时，读取的数据为规律数据，此时可判定为不断光加载。其中，所述预设地址空间并不唯一限定，保证 这段空间没有被其他系统应用使用即可；假设SRAM内的预设地址空间在1000～1100之间，若地址1000写入1，地址1001写入2，以此类推，存在地址空间加1，数据加1的规律，或者若前50个地址空间数据为0x55，后50个空间为0xaa等，也存在一定的规律性，则可判定为不断光加载。
结合本发明实施例，还存在一种优选的实现方案，所述微处理器1通过所述通信接口a接收的升级代码被分成多帧，每帧均包含校验位，可提升每一帧传输的可靠性，更好地适应多种通信协议的传输。同时，所述微处理器1和所述可编程逻辑器件2的程序内含总包的CRC校验，进而可通过校验保证数据包的完整性。具体为，所述微处理器1接收到升级代码后进行校验，包括对升级代码的每帧分别进行校验以及对数据包的CRC校验，当所述升级代码的每帧均校验正确，且各包的CRC校验正确时，所述微处理器1再向所述可编程逻辑器件2发送升级指令；当所述升级代码存在校验错误时，则所述微处理器1继续通过通信接口a接收新的指令和数据，直至校验成功。
结合本发明实施例，还存在一种优选的实现方案，通过对所述程序存储器3的地址空间进行合理划分，来降低升级失败的风险。如图4所示，所述程序存储器3的地址空间首先划分为BOOTLOADE区、程序选择分区和软件分区，所述软件分区又划分为第一分区、第二分区和黄金分区。其中，系统在上电或复位时通常都是从地址0开始执行，这个地址处安排的通常就是系统的BOOTLOADER程序，即所述微处理器1从所述BOOTLOADER区开始运行程序；所述黄金分区为光放大器的缺省分区，只有在升级失败时使用，或者所述第一分区和所述第二分区损坏时使用；所述第一分区和所述第二分区交替保存对应的最新的升级代码，所述程序选择分区根据当前保存升级代码的分区进行更新；当升级失败时，所述程序选择分区不更新，代码回滚到升级前的程序状态，保证光放大器继续正常使用。其中，所述BOOTLOADER区和所述黄金分区的程序均不会在线 升级，保证在极端情况下程序仍可在线升级，提升产品可靠性。
具体来讲，所述微处理器1接收到升级代码时，在FLASH中有三个区间需要写入操作：程序选择分区、第一分区和第二分区，且写入都存在失败的风险，所述BOOTLOADER区和黄金分区不会更改，即这两个分区不会有写入操作，机理大致如下：在出厂时所述BOOTLOADER区和所述黄金分区都为有效内容，第一分区也为有效内容，且程序选择分区写1(表示此时第一分区保存代码)；当升级一次，首先所述第二分区写入有效内容，然后所述程序选择分区写2(表示此时第二分区保存代码)；再升级一次，所述第一分区写入有效内容，所述程序选择分区写1，依此类推；当所述程序选择分区写入失败，譬如为100，则此时所述黄金分区起作用，进而能保证系统正常运行且可以再次升级。
进一步参考图4，为区分保存所述微处理器1的程序升级代码以及所述可编程逻辑器件2的程序升级代码，所述程序存储器3的地址空间除BOOTLOADE区、程序选择分区和软件分区外，还包括固件分区，所述固件分区也同样划分为第一分区、第二分区和黄金分区；所述软件分区用于写入MCU程序升级代码，而所述固件分区则用于写入FPGA程序升级代码。所述固件分区内各个分区的作用与所述软件分区的类似，可参考上述介绍，此处不再赘述。通过合理的地址空间划分，降低了光放大器程序升级失败的风险，确保了光放大器的正常工作。
在本发明实施例中，所述数模转换电路4可为串行接口或者并行接口，所述可编程逻辑器件2通过数字接口控制所述数模转换电路4的模拟电压的大小，保证在升级过程中不断光。其中，当所述数模转换电路4为串行接口时，包括片选、时钟接口和1路数据线；当所述数模转换电路4为并行接口时，包括片选、时钟接口和多路数据线。所述可编程逻辑器件2通过控制相应的片选和时钟接口，控制所述数模转换电路4的模拟电压大小：在所述步骤302中，当所述可编程逻辑器件2接收到升级指令后，通过控 制片选和时钟接口，将片选信号和时钟电平设置为无效电平，从而停止所述数模转换电路4工作，使所述数模转换电路4的模拟电压不再更新，保持固定不变；在所述步骤304中，当所述可编程逻辑器件2接收到上次保存的工作状态和参数后，通过控制片选和时钟接口，将片选信号和时钟电平设置为与加载升级代码前同样的电平，完成所述数模转换电路4的工作状态切换，使光放大器输出不断光，保持状态不变。
结合上述介绍，光放大器在线升级程序的完整流程可参考图5，并总结如下：首先更新程序到FLASH，保存当前动作状态和参数，然后是新程序的加载，如果是不断光加载，则先切换到上次工作状态，然后在此基础上进入正常工作状态，实现光通信业务的平滑过渡。
本发明实施例所述的升级方法可用于多种光放大器，比如拉曼光纤放大器、掺铒光纤放大器、掺镱光纤放大器、混合光纤放大器和高功率光纤放大器等。在上面介绍的升级方法中，MCU程序和FPGA程序是共同升级的，同时，系统还支持MCU程序和FPGA程序各自的独立升级，在需要单独升级的应用场景中，可在一定程度上节省升级时间，降低风险和提高效率。
具体到所述微处理器1，MCU程序单独升级的方法可概括为以下两大步：
第一步，当接收到升级指令时，MCU接收对应的MCU程序升级代码，并对升级代码的每一帧分别进行校验，校验正确后烧写至FLASH(软件分区中的第一分区或第二分区)；然后进行数据包的CRC检验，当各包的CRC校验正确时，根据升级代码的烧写地址置位FLASH中的程序选择分区，并向FPGA发送升级命令；当FPGA回送应答之后，MCU将当前的工作状态和参数保存在FLASH中，并向SRAM的预设地址空间写入数据；具体流程可参考图6。
第二步，加载新程序：MCU重新启动，从FLASH的BOOTLOADE区 开始运行程序，然后根据所述程序选择分区确定当前保存升级代码的区间，并从相应的区间加载最新程序，比如所述程序选择分区当前标记1，则从第一分区加载最新程序；同时MCU读取SRAM预设地址空间数据，用于判断本次加载模式，进而向FPGA指示本次加载模式；如果是上电加载，则MCU发送缺省工作状态和参数给FPGA，如果是不断光加载，则MCU从FLASH读取上次保存的工作状态和参数，并发送给FPGA；具体流程可参考图7。
具体到所述可编程逻辑器件2，FPGA程序单独升级的方法可概括为以下两大步：
第一步，FPGA在正常运行中接收到MCU传递来的升级命令后，FPGA停止DAC工作，控制DAC的模拟信号电压不变，进而保持工作状态和参数不变，同时FPGA将光放大器当前的工作状态和参数保存并传递给MCU，回送应答信号，等待重新加载；具体流程可参考图8。
第二步，加载新程序：MCU从相应的FLASH分区加载FPGA程序升级代码，并传递给FPGA；FPGA从MCU处读取本次的加载模式，如果是上电加载，则FPGA接收由MCU传递来的缺省工作状态和参数，将DAC的初始数字信号置为0，FPGA从零状态切换到正常工作状态；如果是不断光加载，则FPGA接收MCU传递来的上次保存的工作状态和参数，将DAC的初始数字信号定为上次保存的数据，FPGA从上次保存的工作状态切换到正常工作状态；具体流程可参考图9。
通过上述介绍可知，与现有技术相比，本发明存在以下有益效果：在不增加和更改光放大器任何硬件电路的情况下，通过系统设计优化，利用可编程逻辑器件和数模转换特性，在升级时进行特殊控制，达到在程序更新和升级时不中断光纤通信业务，显著提升经济效益；充分利用光放大器已有的静态随机存取存储器的器件特性，结合简单的算法，即可判断上电加载和不断光加载，为整个装置的在线升级提供判别基础；对程序存储器 地址空间划分进行细致安排，降低升级风险，提升了光放大器的可靠性，延伸产品生命力。
实施例2：
在上述实施例1的基础上，本发明实施例还提供了一种用于光放大器在线升级程序的装置，可用于实现实施例1的所述方法。参考图2，所述装置包括微处理器1、可编程逻辑器件2、程序存储器3和数模转换电路4；所述微处理器1用于接收升级指令和升级代码，所述程序存储器3用于存储升级代码以及光放大器的工作状态和参数；所述可编程逻辑器件2用于根据升级指令以及工作状态和参数，实现对所述数模转换电路4的控制，所述数模转换电路4用于将所述可编程逻辑器件2输出的控制数字信号转为模拟电压。
其中，所述微处理器1通过通信接口a与计算机或者网管系统通信，通过板内总线接口b与所述可编程逻辑器件2通信，使得所述微处理器1可通过通信接口a接收升级命令以及MCU程序和FPGA程序的升级代码，并通过板内总线接口b与所述可编程逻辑器件2进行信息交互，同时将需要保存的数据和/或参数烧写至所述程序存储器3。所述可编程逻辑器件2与所述数模转换电路4通信连接，所述可编程逻辑器件2通过板内总线接口b接收所述微处理器1的命令和参数，进而可根据所述微处理器1传递来的命令和参数，控制所述数模转化电路4，保证放大器光传输业务不断光。
本发明在传统光放大器控制基础上，结合微处理器和可编程逻辑器件本身的特点，在不增加和更改光放大器硬件电路的情况下，利用可编程逻辑器件和数模转换特性，通过系统设计优化，在升级时进行特殊控制，达到在程序升级时不中断光纤通信业务的效果，完成业务的平滑过渡，进而提升了整个光通信系统的稳定性与可靠性。
其中，所述光放大器可为拉曼光纤放大器、掺铒光纤放大器、掺镱光 纤放大器、混合光纤放大器和高功率光纤放大器中的任意一种，并不唯一限定。
继续参考图2，所述装置还可包括静态随机存取存储器5，所述静态随机存取存储器5与所述微处理器1通信连接，用于保存所述微处理器1运行时动态更新的数据，进而使所述微处理器1判断加载模式；其中，所述加载模式分为上电加载和不断光加载。所述微处理器1预先向所述静态随机存取存储器5的预设地址空间写入数据，后续读取所述静态随机存取存储器5预设地址空间的数据，并应用SRAM本身的特性和算法对数据的规律性进行分析，进而判断加载模式。由于所述静态随机存取存储器5在断电后内部数据会全部丢失，断电再上电后内部数据为随机数，当所述微处理器1第一次读取预设地址空间的数据时，数据随机分布；此后所述微处理器1写入规律数据，当重新加载运行时，读取的数据便为规律数据。因此，如果所述微处理器1读取的数据为随机数，则判断本次加载为上电加载；如果读取的数据具有规律性，则判断本次加载为不断光加载。本发明充分利用光放大器已有的静态随机存取存储器的器件特性，结合简单的算法，即可判断上电加载和不断光加载，为整个装置的在线升级提供判别基础。
继续参考图2，所述装置还包括泵浦激光器控制系统6和/或可调谐光衰减器控制系统7，所述泵浦激光器控制系统6与所述数模转换电路4连接，用于根据所述数模转换电路4输出的模拟电压调节泵浦激光器的电流，进而调节输出光大小；所述可调谐光衰减器控制系统7与所述数模转换电路4连接，用于根据所述数模转换电路4输出的模拟电压调节可调谐光衰减器的衰减值大小。所述装置还包括无源光学系统8，所述无源光学系统8与所述泵浦激光器控制系统6连接，用于将输入光和所述泵浦激光器的泵浦光耦合到增益介质，实现输入光的放大；其中，所述无源光学系统8还可内置隔离器、滤波器等光学器件，以实现光学性能的各种指标。
对于光学系统，核心是泵浦激光器和可调谐光衰减器的控制。以掺铒光纤放大器为例，输入光和泵浦光可通过耦合器耦合到掺铒光纤，铒纤中的铒离子在泵浦光激励下处于激发态，当输入信号光时，信号光子通过与掺铒光纤的铒离子相互作用发生受激辐射效应，亚稳态的Er3+离子以受激辐射的方式跃迁到基态，并产生和入射信号光中的光子完全相同的光子，从而实现对输入信号光的放大。通过调整所述数模转换电路4输出电压的大小，即可调整泵浦光的大小，进而调节输出光。另一方面，通过调整所述数模转换电路4输出电压的大小，还可调节可调谐光衰减器的衰减值，所述泵浦激光器控制系统6和所述可调谐光衰减器控制系统7共同决定了系统光的输出大小和放大倍数。
在本发明实施例中，所述数模转换电路4可为串行接口或者并行接口，所述可编程逻辑器件2通过数字接口控制所述数模转换电路4的模拟电压的大小，保证在升级过程中不断光。其中，当所述数模转换电路4为串行接口时，包括片选、时钟接口和1路数据线；当所述数模转换电路4为并行接口时，包括片选、时钟接口和多路数据线。所述可编程逻辑器件2通过控制相应的片选和时钟接口，对片选信号和时钟电平进行设置，进而控制所述数模转换电路4的模拟电压大小，使所述数模转换电路4的模拟电压不再更新，保持固定不变，光放大器输出不断光，保持状态不变。
结合本发明实施例，还存在一种优选的实现方案，通过对所述程序存储器3的地址空间进行合理划分，来降低升级失败的风险。如图4所示，所述程序存储器3的地址空间首先划分为BOOTLOADE区、程序选择分区和软件分区，所述软件分区又划分为第一分区、第二分区和黄金分区。其中，所述微处理器1从所述BOOTLOADER区开始运行程序，所述黄金分区为光放大器的缺省分区，只有在升级失败时使用，或者所述第一分区和所述第二分区损坏时使用；所述第一分区和所述第二分区交替保存对应的最新的升级代码，所述程序选择分区根据当前保存升级代码的分区进行更 新；当升级失败时，所述程序选择分区不更新，代码回滚到升级前的程序状态，保证光放大器继续正常使用。其中，所述BOOTLOADER区和所述黄金分区的程序均不会在线升级，保证在极端情况下程序仍可在线升级，提升产品可靠性。为区分保存MCU程序升级代码以及FPGA程序升级代码，所述程序存储器3的地址空间还包括固件分区，所述固件分区也同样划分为第一分区、第二分区和黄金分区；所述软件分区用于写入MCU程序升级代码，而所述固件分区则用于写入FPGA程序升级代码，且所述固件分区内各个分区的作用与所述软件分区的类似。通过合理的地址空间划分，降低了光放大器程序升级失败的风险，确保了光放大器的正常工作。
其中，对于各结构的具体应用可参考实施例1中的相关介绍，此处不再赘述。与现有技术相比，本发明存在以下有益效果：在不增加和更改光放大器任何硬件电路的情况下，通过系统设计优化，利用可编程逻辑器件和数模转换特性，在升级时进行特殊控制，达到在程序更新和升级时不中断光纤通信业务，显著提升经济效益；充分利用光放大器已有的静态随机存取存储器的器件特性，结合简单的算法即可判断上电加载和不断光加载，为整个装置的在线升级提供判别基础；对程序存储器地址空间划分进行细致安排，降低升级风险，提升了光放大器的可靠性，延伸产品生命力。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种用于光放大器在线升级程序的方法，其特征在于，包括：
    当微处理器接收到升级指令和升级代码时，将所述升级代码保存，并向可编程逻辑器件发送升级指令；
    可编程逻辑器件接收到升级指令后停止数模转换电路工作，并向所述微处理器回送应答，使所述微处理器保存当前工作状态和参数；
    所述微处理器重新启动后加载上次保存的升级代码，并将上次保存的工作状态和参数发送给所述可编程逻辑器件；
    所述可编程逻辑器件根据接收到的工作状态和参数，对数模转换电路的工作状态进行切换，使本次运行的初始状态与加载升级代码前的工作状态相同。
  2. 根据权利要求1所述的用于光放大器在线升级程序的方法，其特征在于，所述微处理器重新启动并加载上次保存的升级代码之后，所述方法还包括：
    判断本次加载模式为上电加载还是不断光加载；
    如果是上电加载，则所述微处理器将缺省工作状态和参数发送给所述可编程逻辑器件，使所述可编程逻辑器件控制数模转换电路从无光状态切换到缺省工作状态；
    如果是不断光加载，则所述微处理器将上次保存的工作状态和参数发送给所述可编程逻辑器件，使所述可编程逻辑器件控制数模转换电路切换到上次工作状态。
  3. 根据权利要求2所述的用于光放大器在线升级程序的方法，其特征在于，所述微处理器通过静态随机存取存储器来判断加载模式，具体为：
    所述静态随机存取存储器中保存有所述微处理器运行时动态更新的数据，所述微处理器加载上次保存的升级代码后，读取所述静态随机存取存储器预设地址空间的数据，并对数据的规律性进行分析；
    如果读取的数据为随机数，则判断本次加载为上电加载；如果读取的数据 具有预设规律，则判断本次加载为不断光加载。
  4. 根据权利要求1所述的用于光放大器在线升级程序的方法，其特征在于，所述微处理器接收的升级代码被分成多帧，每帧均包含校验位，且所述微处理器和所述可编程逻辑器件的程序内含总包的CRC校验；则所述微处理器接收到升级代码后进行校验，当所述升级代码的每帧均校验正确，且各包的CRC校验正确时，向可编程逻辑器件发送升级指令。
  5. 根据权利要求1-4任一所述的用于光放大器在线升级程序的方法，其特征在于，所述升级代码保存在程序存储器内，所述程序存储器的地址空间包括BOOTLOADER区、程序选择分区、第一分区、第二分区和黄金分区；其中，所述微处理器从所述BOOTLOADER分区开始运行程序，所述第一分区和所述第二分区交替保存最新的升级代码，所述程序选择分区根据当前保存升级代码的分区进行更新，所述黄金分区为光放大器的缺省分区，在升级失败时使用。
  6. 根据权利要求1-4任一所述的用于光放大器在线升级程序的装置，其特征在于，所述数模转换电路为串行接口，包括片选、时钟接口和1路数据线；或者所述数模转换电路为并行接口，包括片选、时钟接口和多路数据线；其中，所述通过控制相应的片选和时钟接口控制所述数模转换电路的模拟电压大小，进而实现对所述数模转换电路的控制。
  7. 一种用于光放大器在线升级程序的装置，其特征在于，包括微处理器(1)、可编程逻辑器件(2)、程序存储器(3)和数模转换电路(4)，所述微处理器(1)分别与所述可编程逻辑器件(2)和所述程序存储器(3)通信连接，所述可编程逻辑器件(2)与所述数模转换电路(4)通信连接；
    其中，所述微处理器(1)用于接收升级指令和升级代码，并与所述程序存储器(3)交互；所述程序存储器(3)用于存储升级代码以及光放大器的工作 状态和参数；所述可编程逻辑器件(2)用于根据升级指令以及工作状态和参数，控制所述数模转换电路(4)；所述数模转换电路(4)用于将所述可编程逻辑器件(2)输出的控制数字信号转为模拟电压。
  8. 根据权利要求7所述的用于光放大器在线升级程序的装置，其特征在于，还包括静态随机存取存储器(5)，所述静态随机存取存储器(5)与所述微处理器(1)通信连接，用于保存所述微处理器(1)运行时动态更新的数据，进而使所述微处理器(1)判断加载模式；其中，所述加载模式分为上电加载和不断光加载。
  9. 根据权利要求7所述的用于光放大器在线升级程序的装置，其特征在于，还包括泵浦激光器控制系统(6)和/或可调谐光衰减器控制系统(7)，所述泵浦激光器控制系统(6)与所述数模转换电路(4)连接，用于根据所述数模转换电路(4)输出的模拟电压调节泵浦激光器的电流，进而调节输出光大小；
    所述可调谐光衰减器控制系统(7)与所述数模转换电路(4)连接，用于根据所述数模转换电路(4)输出的模拟电压调节可调谐光衰减器的衰减值大小。
  10. 根据权利要求9所述的用于光放大器在线升级程序的装置，其特征在于，还包括无源光学系统(8)，所述无源光学系统(8)与所述泵浦激光器控制系统(6)连接，用于将输入光和所述泵浦激光器的泵浦光耦合到增益介质，实现输入光的放大。
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