WO2020140362A1 - 基于fpga应用于水声定位实现可重配置和多输出的实时处理系统及方法 - Google Patents

基于fpga应用于水声定位实现可重配置和多输出的实时处理系统及方法 Download PDF

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WO2020140362A1
WO2020140362A1 PCT/CN2019/086533 CN2019086533W WO2020140362A1 WO 2020140362 A1 WO2020140362 A1 WO 2020140362A1 CN 2019086533 W CN2019086533 W CN 2019086533W WO 2020140362 A1 WO2020140362 A1 WO 2020140362A1
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correlation
real
output
parallel
group
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English (en)
French (fr)
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洪峰
冯海泓
黄敏燕
陈�峰
李钉云
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中国科学院声学研究所东海研究站
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Priority to US17/256,672 priority Critical patent/US12019136B2/en
Publication of WO2020140362A1 publication Critical patent/WO2020140362A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S1/00—Beacons or beacon systems transmitting signals having a characteristic or characteristics capable of being detected by non-directional receivers and defining directions, positions, or position lines fixed relatively to the beacon transmitters; Receivers co-operating therewith
    • G01S1/72—Beacons or beacon systems transmitting signals having a characteristic or characteristics capable of being detected by non-directional receivers and defining directions, positions, or position lines fixed relatively to the beacon transmitters; Receivers co-operating therewith using ultrasonic, sonic or infrasonic waves
    • G01S1/76—Systems for determining direction or position line
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S3/00—Direction-finders for determining the direction from which infrasonic, sonic, ultrasonic, or electromagnetic waves, or particle emission, not having a directional significance, are being received
    • G01S3/80—Direction-finders for determining the direction from which infrasonic, sonic, ultrasonic, or electromagnetic waves, or particle emission, not having a directional significance, are being received using ultrasonic, sonic or infrasonic waves
    • G01S3/86—Direction-finders for determining the direction from which infrasonic, sonic, ultrasonic, or electromagnetic waves, or particle emission, not having a directional significance, are being received using ultrasonic, sonic or infrasonic waves with means for eliminating undesired waves, e.g. disturbing noises
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
    • G01S15/006—Theoretical aspects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
    • G01S15/02—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems using reflection of acoustic waves
    • G01S15/06—Systems determining the position data of a target
    • G01S15/46—Indirect determination of position data
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
    • G01S15/88—Sonar systems specially adapted for specific applications
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/21—Pc I-O input output
    • G05B2219/21109—Field programmable gate array, fpga as I-O module

Definitions

  • the invention relates to the field of underwater acoustic signal processing, in particular to the field of underwater acoustic localization and navigation real-time processing, in particular to a real-time processing system and method for implementing reconfigurable and multi-output based on FPGA applied to underwater acoustic localization.
  • Real-time related processing technology is a very common technology in underwater acoustic positioning and navigation, and has very important application value.
  • the correlator is designed to have sample automatic Reconfigurable performance is very necessary.
  • the research is based on field programmable logic array (Field ProgrammableGateArray, FPGA) design with parallel high performance
  • Field ProgrammableGateArray, FPGA field programmable logic array
  • the existing commonly used real-time related processing methods for FPGA-based underwater acoustic positioning and navigation the sample information is deterministic, cannot be automatically transmitted and configured through multiple interfaces, and lacks versatility; in addition, it is difficult to achieve when processing
  • the versatile parallel computing is greatly affected by the changes in the number of channels and the number of targets, so that the logic design needs to be modified frequently.
  • the related multiple outputs are not formed into data outputs, and a collaborative processing mechanism cannot be formed. Therefore, whether it is from the perspective of general-purpose, real-time or noise resistance of real-time correlation processing, the general FPGA-based real-time correlation processing method is poor in performance.
  • the purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art and provide a FPGA-based application to underwater acoustic positioning for real-time processing of reconfiguration and multi-output that meets the requirements of real-time, versatility and noise resistance of the navigation process System and method.
  • the FPGA-based application of the present invention to the real-time processing system for underwater acoustic localization to achieve reconfiguration and multi-output and its method are as follows:
  • Multi-interface control and command analysis module used to automatically complete the transmission of sample information and command analysis
  • the sample management finite state machine is connected to the multi-interface control and command parsing module to calculate related data and complete the splitting, flipping and writing of samples;
  • the parallel related processor group is connected with the sample management finite state machine and is used to complete high-performance processing work for multiple targets in parallel;
  • the multi-output data former is connected to the parallel related processor group, and is used to realize the data formation of the multi-output result at the same time, and output the flag signal to the outside.
  • the multi-interface control and command parsing module includes:
  • Controller group used to receive commands and sample information of each interface
  • Multi-interface command configuration parser connected to the controller group, used to parse processing commands and sample information, and transmit them to the sample management finite state machine at the same time. After the command is triggered, the sample information is overwritten after processing .
  • the multi-interface control and command parsing module writes the sample information into the flash memory to realize automatic reading and automatic configuration under restart or command parsing operation.
  • the sample management finite state machine includes:
  • Configuration control finite state machine connected to the multi-interface command configuration parser, used to calculate the expected number of relevant points, the number of parallel channels required, and the number of zero-filling of sub-relevant computing units;
  • the sample storage RAM unit including the real RAM subunit group and the imaginary RAM subunit group, are connected to the parallel related processor group for splitting and flipping the sample information and writing into the real RAM subunits, respectively Group and imaginary part RAM subunit group, the real part RAM subunit group is used to store real part data, and the imaginary part RAM subunit group is used to store imaginary part data.
  • the parallel related processor group includes:
  • a delay controller connected to the sample storage RAM unit, is used to delay control of multiple signals respectively;
  • the multi-channel correlation calculation subunit group is connected with the delay controller and is used to complete the calculation of the real and imaginary parts of the data in parallel;
  • the correlation signal synthesis unit is connected to the multi-channel correlation calculation sub-unit group, and is used to accumulate the real part and the imaginary part separately, and perform a comprehensive operation on the correlation sub-signal.
  • the multi-output data shaper includes:
  • the calculation output unit is connected to the parallel correlation processor group, and is used to calculate and output correlation energy results, correlation energy results after time gain compensation, normalized correlation coefficient results, correlation delay results, and correlation phases result;
  • the data forming unit is connected to the calculation output unit, and is used for storing each output result in the data forming memory, and outputting the flag signal to the outside.
  • the multi-interface control and command analysis module completes the reconfiguration of real-time related processing samples
  • the sample management finite state machine calculates the number of expected correlation points, the number of parallel channels required, and the zero-filling number of sub-correlation calculation units to complete sample splitting, flipping, and writing;
  • the parallel related processor group performs high-performance related processing for multiple targets and multiple targets in parallel;
  • the multi-output data shaper completes the multi-output data results through the correlation energy results, normalized correlation coefficient results, correlation delay results, and correlation phase results after time gain compensation.
  • the sample management finite state machine includes a configuration control finite state machine and a sample storage RAM unit.
  • the sample storage RAM unit includes a real RAM subunit group and an imaginary RAM subunit group. (2) Specifically including the following steps:
  • the configuration controls the finite state machine to calculate the number of expected correlation points, the number of parallel channels required, and the number of sub-correlation calculation units to fill zeros;
  • the sample storage RAM unit splits, reverses, and writes the samples into the real RAM subunit group and the imaginary RAM subunit group.
  • the step (3) specifically includes the following steps:
  • the multi-channel correlation calculation subunit group performs the calculation of the real and imaginary parts of the data in parallel
  • the related signal synthesis unit performs a comprehensive operation on related sub-signals.
  • the real-time processing system and method for realizing reconfiguration and multi-output based on FPGA applied to underwater acoustic localization of the present invention are adopted, so that high-speed parallel related processing is realized under multiple array elements and multiple targets in the entire implementation process, Solve the problems of real-time, versatility and noise resistance, and effectively achieve high performance. It can be automatically transmitted and configured through multiple interfaces, and it is versatile; it realizes versatile parallel computing during processing, and is not affected by changes in the number of channels and the number of targets. It forms related multiple outputs into data outputs and forms a collaborative processing mechanism. It has obvious innovation and improvement in the general-purpose, real-time and noise resistance of real-time correlation processing.
  • FIG. 1 is a schematic structural diagram of a real-time processing system based on FPGA applied to underwater acoustic localization to realize reconfiguration and multi-output.
  • FIG. 2 is a schematic structural view of a multi-interface control and command parsing module of a real-time processing system based on FPGA applied to underwater acoustic localization to realize reconfiguration and multi-output.
  • FIG. 3 is a schematic structural diagram of a sample management finite state machine of a real-time processing system based on FPGA applied to underwater acoustic localization to realize reconfiguration and multi-output.
  • FIG. 4 is a schematic structural diagram of related calculations in a related calculation subunit group of a real-time processing system for real-time processing that can be reconfigured and multi-output based on FPGA applied to underwater acoustic localization of the present invention.
  • FIG. 5 is a schematic structural diagram of basic calculation of related calculation subunits in a related calculation subunit group of a real-time processing system for realizing reconfigurable and multi-output based on FPGA applied to underwater acoustic localization of the present invention.
  • FIG. 6 is a schematic structural view of a multi-output calculation and data former of a real-time processing system based on FPGA applied to underwater acoustic localization to realize reconfiguration and multi-output.
  • FIG. 7 is a schematic diagram of energy-distance attenuation curve of a real-time processing system based on FPGA applied to underwater acoustic localization to realize reconfiguration and multi-output.
  • FIG. 8 is a schematic diagram of the time gain compensation-distance attenuation curve of the FPGA-based application of the underwater acoustic localization real-time processing system to realize reconfiguration and multi-output.
  • FIG. 9 is a schematic flow chart of a method for realizing real-time processing control of reconfiguration and multi-output applied to underwater acoustic positioning based on FPGA of the present invention.
  • the FPGA-based application of the present invention to a real-time processing system for underwater acoustic positioning to realize reconfiguration and multi-output, wherein the system includes:
  • Multi-interface control and command analysis module used to automatically complete the transmission of sample information and command analysis
  • the sample management finite state machine is connected to the multi-interface control and command parsing module to calculate related data and complete the splitting, flipping and writing of samples;
  • the parallel related processor group is connected with the sample management finite state machine and is used to complete high-performance processing work for multiple targets in parallel;
  • the multi-output data former is connected to the parallel related processor group, and is used to realize the data formation of the multi-output result at the same time, and output the flag signal to the outside.
  • the multi-interface control and command parsing module includes:
  • Controller group used to receive commands and sample information of each interface
  • Multi-interface command configuration parser connected to the controller group, used to parse processing commands and sample information, and transmit them to the sample management finite state machine at the same time. After the command is triggered, the sample information is overwritten after processing .
  • the multi-interface control and command parsing module writes the sample information into the flash memory to realize automatic reading and automatic configuration under restart or command parsing operation.
  • the sample management finite state machine includes:
  • Configuration control finite state machine connected to the multi-interface command configuration parser, used to calculate the expected number of relevant points, the number of parallel channels required, and the number of zero-filling of sub-relevant computing units;
  • the sample storage RAM unit including the real RAM subunit group and the imaginary RAM subunit group, are connected to the parallel related processor group for splitting and flipping the sample information and writing into the real RAM subunits, respectively Group and imaginary part RAM subunit group, the real part RAM subunit group is used to store real part data, and the imaginary part RAM subunit group is used to store imaginary part data.
  • the parallel related processor group includes:
  • a delay controller connected to the sample storage RAM unit, is used to delay control of multiple signals respectively;
  • the multi-channel correlation calculation subunit group is connected with the delay controller and is used to complete the calculation of the real and imaginary parts of the data in parallel;
  • the correlation signal synthesis unit is connected to the multi-channel correlation calculation sub-unit group, and is used to accumulate the real part and the imaginary part separately, and perform a comprehensive operation on the correlation sub-signal.
  • the multi-output data former includes:
  • the calculation output unit is connected to the parallel correlation processor group, and is used to calculate and output correlation energy results, correlation energy results after time gain compensation, normalized correlation coefficient results, correlation delay results, and correlation phases result;
  • the data forming unit is connected to the calculation output unit, and is used for storing each output result in the data forming memory, and outputting the flag signal to the outside.
  • the real-time processing control method based on the above system for implementing FPGA-based reconfigurable and multi-output for underwater acoustic localization includes the following steps:
  • the multi-interface control and command analysis module completes the reconfiguration of real-time related processing samples
  • the sample management finite state machine calculates the number of expected correlation points, the number of parallel channels required, and the zero-filling number of sub-correlation calculation units to complete sample splitting, flipping, and writing;
  • the configuration controls the finite state machine to calculate the number of expected correlation points, the number of parallel channels required, and the number of sub-correlation calculation units to fill zeros;
  • the sample storage RAM unit splits, reverses and writes the samples into the real RAM subunit group and the imaginary RAM subunit group;
  • the parallel related processor group performs high-performance related processing for multiple targets and multiple targets in parallel;
  • the multi-channel correlation calculation subunit group performs the calculation of the real and imaginary parts of the data in parallel
  • the related signal synthesis unit performs a comprehensive operation on related sub-signals
  • the multi-output data shaper completes the multi-output data results through the correlation energy results, normalized correlation coefficient results, correlation delay results, and correlation phase results after time gain compensation.
  • the present invention discloses an FPGA-based high-performance multi-output reconfigurable real-time correlation processing method for underwater acoustic localization.
  • the method includes: using multi-interface control to complete real-time correlation processing samples Reconfiguration; use the sample management finite state machine to calculate the number of expected correlation points, the number of parallel channels required, and the zero-filling of sub-correlation calculation units to complete sample splitting, flipping, and writing; parallelization using highly resource-efficient parallel correlation processor groups Complete high-performance correlation processing for multiple targets of multiple array elements; use the correlation energy results after time gain compensation, normalized correlation coefficient results, and correlation delay-phase results to form multiple output data results.
  • the invention also discloses a reconfigurable and multi-output real-time related processing device for underwater acoustic positioning based on FPGA.
  • the device includes:
  • Multi-interface control and command parsing unit used to complete the automatic transmission of sample information and command parsing of the multi-interface control and command parsing unit
  • the sample management finite state machine is used to calculate the number of expected correlation points, the required number of parallel channels, and the number of sub-correlation calculation units to fill in zeros, to complete sample splitting, flipping and writing;
  • the multi-output data shaper is used to complete the simultaneous output of the calculation of the multi-output data result based on the correlation energy result, normalized correlation coefficient result, and correlation delay-phase result after time gain compensation.
  • Multi-interface control and command parsing unit which directly parses the command and sample information for subsequent units, and writes the data into FLASH at the same time when receiving the sample information; it can be automatically read from FLASH every time it is restarted or command parsing Take and implement automatic configuration.
  • the command parsing unit can be processed at the same time. After being triggered by the command, the sample information of each interface processor can be overwritten by "or" processing.
  • Sample management finite state machine specifically used to calculate the number of expected related points, the number of parallel channels required, and the zero-filling of sub-related calculation units, complete sample splitting, flipping, and writing, including: automatically calculating the expected related points and required according to rules The number of parallel channels and zero-filling of sub-related calculation units; automatically split, flip and write the samples into the real RAM subunit group and imaginary RAM subunit group;
  • Highly resource-saving parallel related processor group used to complete high-performance related processing for multiple targets of multiple arrays in parallel, including: delay control of multiple signals separately; use highly resource-saving resources to complete the calculation of parallel related processor groups , That is, using a logical resource including a first-in queue (First Input, First Output, FIFO), a cache RAM, a sample storage RAM, a multiply-accumulate basic unit, and related processing controllers to complete the real part
  • a logical resource including a first-in queue (First Input, First Output, FIFO), a cache RAM, a sample storage RAM, a multiply-accumulate basic unit, and related processing controllers to complete the real part
  • FIFO First Input, First Output
  • cache RAM a cache RAM
  • sample storage RAM a sample storage RAM
  • multiply-accumulate basic unit a multiply-accumulate basic unit
  • the multi-output data shaper is characterized by using the correlation energy result after time gain compensation, the normalized correlation coefficient result and the correlation delay-phase result to form a multi-output data result, including: finding the square of the real part and the square of the imaginary part And add to obtain the relevant energy result; based on the spherical wave attenuation or plane wave attenuation, and the corresponding frequency absorption attenuation, combined with the sound source level, transducer sensitivity, receiver gain and other related system parameters, calculate the energy-distance attenuation curve and Time gain compensation-distance attenuation curve; calculate the correlation energy and signal eigen energy, calculate the normalized correlation coefficient result; use the delay result to obtain the sampling frequency and the number of points; the correlation phase result can be calculated using the CORDIC algorithm Relevant phase results; use RAM and control state machine to realize the data formation of multi-output results, and output flag signals to the outside.
  • Methods include:
  • sample management finite state machine uses the sample management finite state machine to calculate the number of expected correlation points, the number of parallel channels required, and the zero-filling of the sub-correlation calculation unit to complete sample splitting, flipping, and writing;
  • Multi-output data results are simultaneously output using correlation energy results, normalized correlation coefficient results, and correlation delay-phase results after time gain compensation.
  • the multi-interface control is used to complete the real-time related processing sample reconfiguration, including: the parsed command and sample information are directly used for subsequent units, and the data is simultaneously written into FLASH when receiving the sample information; each restart or command analysis Can be automatically read from FLASH and achieve automatic configuration.
  • sample management finite state machine uses the sample management finite state machine to calculate the number of expected correlation points, the number of parallel channels required, and the zero-filling of sub-correlation calculation units to complete sample splitting, flipping, and writing, including: automatically calculating the number of expected correlation points and required parallel channels according to rules The number and sub-correlation calculation unit are filled with zeros; the sample is automatically split, flipped and written into the real RAM subunit group and the imaginary RAM subunit group;
  • the logical resources inside complete the calculation of the real part, and use the equivalent resources to complete the calculation of the imaginary part; use the pipeline structure to save resources. After multi-stage pipeline calculation, obtain the cumulative results of the real part and the imaginary part, that is, the relevant sub-signals for comprehensive operation ;
  • Multi-output data results are formed by using the correlation energy results after time gain compensation, the normalized correlation coefficient results and the correlation delay-phase results, including: summing the square of the real part and the square of the imaginary part to obtain the correlation energy result; Calculate energy-distance attenuation curve and time gain compensation-distance attenuation curve based on spherical wave attenuation or plane wave attenuation, and corresponding frequency absorption attenuation, combined with relevant system parameters such as sound source level, transducer sensitivity, receiver gain, etc.; Energy and signal intrinsic energy, calculate the normalized correlation coefficient result; use the delay result to obtain the sampling frequency and the number of points; the correlation phase result can be obtained by using the coordinate rotation digital calculation method (Coordinate Rotation Digital Computer (CORDIC) algorithm) Results, related phase results; use RAM and control state machine to realize the data formation of multiple output results, and output the flag signal to the outside.
  • CORDIC Coordinat Rotation Digital Computer
  • Embodiments of the present invention provide a FPGA-based high-performance multi-output reconfigurable real-time correlation processing method for underwater acoustic positioning, including:
  • the multi-interface controller mainly includes a serial controller, an Ethernet controller, a synchronous serial interface (SPORT) controller of a digital signal processor (DSP), and a flash memory (Flash) Memory, Flash) sample write and read controllers and other interface controllers;
  • SPORT synchronous serial interface
  • DSP digital signal processor
  • Flash flash memory
  • the command parsing unit can be performed simultaneously, and sample information of each interface processor can be overwritten after being triggered by the command;
  • the data when receiving the sample information, the data can be written into the Flash, and it can be automatically read from it every time it is restarted or parsed by command and realize automatic configuration.
  • the sample management finite state machine is responsible for managing the commands and data obtained by the multi-interface control and command parsing unit:
  • the sample management finite state machine after receiving the command, temporarily stores 2N sets of sample information of N targets, including N sets of signal real parts and N sets of sample imaginary parts, in the sample RAM storage unit;
  • the sample management finite state machine is automatically divided into N groups of sample information by the configuration control finite state machine, and each group of sample information is split into Nc group of sub-sample information, which is reversed, and then the real part and the virtual The unit is written into the real RAM subunit group and the imaginary RAM subunit group, respectively.
  • the parallel correlation processor group simultaneously completes M array elements (that is, M channels of AD signals) and N targets, that is, MN channels of high-performance related processing:
  • the single-channel high-performance correlation processing includes a signal delay controller, a multi-channel correlation calculation subunit group, and a correlation signal synthesis unit.
  • the result output also includes the output correlation energy result, the correlation energy result after time gain compensation, the normalization correlation coefficient result, as well as the correlation delay result and correlation phase result; the data shaper concatenates each output result according to the format and stores it in the data to form The memory generates a flag signal after completion.
  • An embodiment of the present invention provides an FPGA-based high-performance multi-output reconfigurable real-time related processing method and device for underwater acoustic positioning, which first uses a multi-interface control and command parsing unit to obtain commands and parse out multiple sets of sample information On the one hand, the parsed commands and sample information are directly used by subsequent units; on the other hand, the data can be written into the Flash when receiving the sample information, and it can be automatically read from each restart or after command analysis And achieve automatic configuration; the sample management finite state machine is responsible for managing the commands and data obtained by the multi-interface control and command parsing unit, automatically splitting the multi-channel sample information sequentially, and writing the real part and the imaginary part into the real part RAM subunit group respectively And the imaginary part of the RAM subunit group; then parallel related processor group, simultaneously run the signal delay controller, multi-channel correlation calculation subunit group and related signal synthesis unit, complete in parallel for M array elements (that is, M channel AD signal), N targets, namely MN high-performance correlation processing; finally, output
  • FIG. 9 is an implementation flow of a FPGA-based high-performance multi-output reconfigurable real-time correlation processing method for underwater acoustic positioning provided by an embodiment of the present invention
  • a schematic diagram, as shown in FIG. 9, this embodiment provides an FPGA-based high-performance multi-output reconfigurable real-time correlation processing method for underwater acoustic localization.
  • the method includes:
  • Step 101 First use a multi-interface control and command parsing unit to obtain commands and parse out multiple sets of sample information;
  • this step includes: the parsed command and sample information are directly used by subsequent units at the same time; when receiving the sample information, the data can be written into the Flash, and each time it is restarted or parsed by the command, it can be automatically read and Realize automatic configuration.
  • Step 102 the sample management finite state machine is responsible for managing the commands and data obtained by the multi-interface control and command parsing unit;
  • this step includes: completing command parsing and obtaining commands and data; calculating the expected number of relevant points, the number of parallel channels required, and the number of sub-relevant calculation units filled with zeros; sample splitting, flipping, and writing to the real RAM subunit group and The imaginary part RAM subunit group.
  • Step A1 Complete command analysis and obtain commands and data
  • the multiple commands and data obtained by the multi-interface process the multi-interface commands with a logical relationship of "or", and trigger data acquisition.
  • FLASH automatically reads the initialization commands and data, that is, CMD FLASH to drive; subsequent, when t>t 0 , based on subsequent commands such as serial commands CMD UART , Ethernet command CMD ETH , DSP command CMD SPORT, and other commands CMD OTHER to cover.
  • means seeking or calculating.
  • Step A2 Calculate the number of expected correlation points, the number of parallel channels required, and the number of zero-filling of the sub-correlation calculation unit;
  • N Ch-max is determined according to the ratio of 60% of the total number of FPGA resources divided by the single correlation computing resource in the autocorrelation computing unit.
  • the zero-filling number of the sub-correlation calculation unit is:
  • N pd N mux ⁇ N d -N total ......(7)
  • Step A3 The sample is split, reversed and written into the real RAM subunit group and the imaginary RAM subunit group;
  • the multi-channel sample information is automatically split sequentially, and the real and imaginary parts are written into the real RAM subunit group and the imaginary RAM subunit group, respectively.
  • Step 103 the calculation of the parallel correlation processor group is realized, and the M targets (that is, M channels of AD signals) and N targets, that is, MN channels of high-performance correlation processing are completed in parallel.
  • this step includes: completing signal delay control; correlation calculation subunit group calculation; and synthesis of correlation subsignals.
  • Step B1 Complete signal delay control
  • the signal s(n) is divided into N MUX channels, respectively delayed, and input to the relevant subunit group.
  • the first input is the original signal s(n)
  • the first output s 1 (n) s(nN d )
  • the second input is the output of the first path, that is, s 1 (n)
  • the last input is The last output is
  • Step B2 Completing the calculation of the relevant calculation subunit group
  • Step B2 mainly completes the calculation of the subunits of (10)(11), and the calculation structure is shown in FIG. 5
  • the calculation of the real and imaginary parts of the subunit each includes a first-in-first-out queue (First Input, First Output, FIFO), a buffer RAM, a sample storage RAM, a multiply-accumulate basic unit, and related processing controllers.
  • a first-in-first-out queue First Input, First Output, FIFO
  • a buffer RAM buffer RAM
  • sample storage RAM sample storage RAM
  • multiply-accumulate basic unit and related processing controllers.
  • Step B3 Complete relevant sub-signals for synthesis
  • Step 104 the calculation of the correlation energy result, the correlation energy result after time gain compensation, the normalized correlation coefficient result, and the correlation delay result and correlation phase result are calculated as multiple output results, and each output result is formatted according to the format via the data former Splicing and storing the data to form a memory, the flag signal is generated after completion, and then output.
  • this step includes: calculating the correlation energy result; calculating the correlation energy result after time gain compensation; calculating the normalized correlation coefficient result; calculating the correlation delay result and correlation phase result; data formation and output.
  • Step C1 Calculate the relevant energy results
  • Step C2 Calculate the relevant energy result after time gain compensation
  • the energy-distance attenuation curve is calculated as shown in Figure 7, and the time gain compensation -The distance attenuation curve is shown in Figure 8.
  • Step C3 Calculate the normalized correlation coefficient result
  • Step C4 Calculate the correlation delay result and correlation phase result
  • the delay result is obtained by combining the sampling frequency and the number of points; the relevant phase result can be obtained by the CORDIC algorithm.
  • Step C5 Data is formed and output.
  • the real-time processing system and method for realizing reconfiguration and multi-output based on FPGA applied to underwater acoustic localization of the present invention are adopted, so that high-speed parallel related processing is realized under multiple array elements and multiple targets in the entire implementation process Solve the problems of real-time, versatility and noise resistance, and effectively achieve high performance. It can be automatically transmitted and configured through multiple interfaces, and it is versatile; it realizes versatile parallel computing during processing, and is not affected by changes in the number of channels and the number of targets. It forms related multiple outputs into data outputs and forms a collaborative processing mechanism. It has obvious innovation and improvement in the general-purpose, real-time and noise resistance of real-time correlation processing.

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Abstract

一种基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统，包括多接口控制及命令解析模块，用于自动化地完成样本信息的传输及命令解析；样本管理有限状态机，用于计算相关数据，并完成样本的拆分、翻转和写入；并行相关处理器组，用于并行完成针对多个目标的高性能处理工作；多输出数据形成器，用于同时实现多输出结果的数据形成，并向外输出标志位信号。还涉及一种实现基于FPGA的应用于水声定位的可重配置和多输出的实时处理控制方法。采用了这种系统和方法，使得整个实现过程中在多个阵元、多个目标下，实现高速并行的相关处理，解决实时性、通用性以及抗噪性方面的问题，有效地实现高性能相关。

Description

基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统及方法
相关申请的交叉引用
本申请主张2019年1月4日提交的申请号为201910007523.1的中国发明专利申请的优先权，其内容通过引用的方式并入本申请中。
技术领域
本发明涉及水声信号处理领域，尤其涉及水声定位导航实时处理领域，具体是指一种基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统及其方法。
背景技术
实时相关处理技术是水声定位导航中的一种非常常见的技术，具有非常重要的应用价值。在涉及水声实时信号处理的应用中，特别是水声定位导航等应用中，常需要利用不同频段、不同体制的信号实现多通道、多目标的检测，因此，将相关器设计成具有样本自动可重配置性能是十分必要的。此外，考虑到不同场合下检测信号形式及信号长度的多变性会使常见的相关器无法完成计算，因此，研究基于现场可编程逻辑阵列(Field Programmable Gate Array，FPGA)设计具有并行高性能的可扩展的通用型相关器亦是必要的。最后，因水下物理环境较为复杂，存在着多途现象、传输衰减及吸收衰减的情况，为保证较好的检测性能，将包括相关结果、时间增益补偿相关结果和归一化相关结果等多种结果同时输出并完成数据形成，实现协同处理，亦具有重要意义。
目前，现有的常用的用于基于FPGA的水声定位导航的实时相关处理方法，样本的信息是确定的，无法通过多接口自动传输、自动配置，缺乏通用性；另外，在处理时难以实现通用性的并行计算，受通道数、目标数变化的影响很大，致使逻辑设计需要频繁修改；最后，在后续处理中，未将相关的多输出形成数据输出，无法形成协同处理机制。因此，无论是从实时相关处理的通用型、实时性或是抗噪性的角度，一般的基于FPGA的实时相关处理方法在性能上欠佳。
发明内容
本发明的目的是克服了上述现有技术的缺点，提供了一种满足导航过程的实时性、通用性、抗噪性要求的基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统及其方 法。
为了实现上述目的，本发明的基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统及其方法如下：
该基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统，其主要特点是，所述的系统包括：
多接口控制及命令解析模块，用于自动化地完成样本信息的传输及命令解析；
样本管理有限状态机，与所述的多接口控制及命令解析模块相连接，用于计算相关数据，并完成样本的拆分、翻转和写入；
并行相关处理器组，与所述的样本管理有限状态机相连接，用于并行完成针对多个目标的高性能处理工作；
多输出数据形成器，与所述的并行相关处理器组相连接，用于同时实现多输出结果的数据形成，并向外输出标志位信号。
较佳地，所述的多接口控制及命令解析模块包括：
控制器组，用于接收各个接口的命令和样本信息；
多接口命令配置解析器，与所述的控制器组相连接，用于解析处理命令及样本信息，并同时传输给所述的样本管理有限状态机，命令触发后的样本信息经过处理后互相覆盖。
较佳地，所述的多接口控制及命令解析模块将样本信息写入闪存，实现在重启或命令解析操作下自动读取并自动配置。
较佳地，所述的样本管理有限状态机包括：
配置控制有限状态机，与所述的多接口命令配置解析器相连接，用于计算期望相关点数、所需的并行通道数和子相关计算单元填零数；
样本存储RAM单元，包括实部RAM子单元组和虚部RAM子单元组，均与所述的并行相关处理器组相连接，用于将样本信息拆分翻转并分别写入实部RAM子单元组及虚部RAM子单元组，所述的实部RAM子单元组用于存储实部数据，所述的虚部RAM子单元组用于存储虚部数据。
较佳地，所述的并行相关处理器组包括：
延迟控制器，与所述的样本存储RAM单元相连接，用于对多路信号分别延迟控制；
多路相关计算子单元组，与所述的延迟控制器相连接，用于并行完成数据的实部和虚部计算；
相关信号综合单元，与所述的多路相关计算子单元组相连接，用于对实部和虚部分别累加计算，并对相关子信号进行综合运算。
较佳地，所述的多输出数据形成器包括：
计算输出单元，与所述的并行相关处理器组相连接，用于计算并多输出相关能量结果、时间增益补偿后的相关能量结果、归一化相关系数结果，以及相关时延结果、相关相位结果；
数据形成单元，与所述的计算输出单元相连接，用于将各输出结果存入数据形成存储器，并向外输出标志位信号。
该基于上述系统实现基于FPGA的应用于水声定位的可重配置和多输出的实时处理控制方法，其主要特点是，所述的方法包括以下步骤：
(1)所述的多接口控制及命令解析模块完成实时相关处理样本的重配置；
(2)所述的样本管理有限状态机计算期望相关点数、所需的并行通道数和子相关计算单元填零数，完成样本拆分、翻转及写入；
(3)所述的并行相关处理器组并行完成针对多阵元多个目标的高性能相关处理；
(4)所述的多输出数据形成器通过时间增益补偿后的相关能量结果、归一化相关系数结果、相关时延结果和相关相位结果完成多输出数据结果。
较佳地，所述的样本管理有限状态机包括配置控制有限状态机和样本存储RAM单元，所述的样本存储RAM单元包括实部RAM子单元组和虚部RAM子单元组，所述的步骤(2)具体包括以下步骤：
(2.1)所述的配置控制有限状态机完成命令解析并获得命令及数据；
(2.2)所述的配置控制有限状态机计算期望相关点数、所需的并行通道数和子相关计算单元填零数；
(2.3)样本存储RAM单元将样本拆分、翻转并写入实部RAM子单元组及虚部RAM子单元组。
较佳地，所述的步骤(3)具体包括以下步骤：
(3.1)所述的延迟控制器完成信号延迟控制；
(3.2)所述的多路相关计算子单元组并行完成数据的实部和虚部计算；
(3.3)所述的相关信号综合单元对相关子信号进行综合运算。
采用了本发明的基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统及其方法，使得整个实现过程中在多个阵元、多个目标下，实现高速并行的相关处理，解决实时 性、通用性以及抗噪性方面的问题，有效地实现高性能相关。可通过多接口自动传输、自动配置，具有通用性；在处理时实现通用性的并行计算，不受受通道数、目标数变化的影响，将相关的多输出形成数据输出，形成协同处理机制，在实时相关处理的通用型、实时性和抗噪性上具有较为明显的创新改进。
附图说明
图1为本发明的基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统的结构示意图。
图2为本发明的基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统的多接口控制及命令解析模块的结构示意图。
图3为本发明的基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统的样本管理有限状态机的结构示意图。
图4为本发明的基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统的相关计算子单元组中相关计算的结构示意图。
图5为本发明的基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统的相关计算子单元组中的相关计算子单元基本计算的结构示意图。
图6为本发明的基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统的多输出计算及数据形成器的结构示意图。
图7为本发明的基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统的能量-距离衰减曲线示意图。
图8为本发明的基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统的时间增益补偿-距离衰减曲线示意图。
图9为本发明的实现基于FPGA的应用于水声定位的可重配置和多输出的实时处理控制方法的流程示意图。
具体实施方式
为了能够更清楚地描述本发明的技术内容，下面结合具体实施例来进行进一步的描述。
本发明的该基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统，其中，所述的系统包括：
多接口控制及命令解析模块，用于自动化地完成样本信息的传输及命令解析；
样本管理有限状态机，与所述的多接口控制及命令解析模块相连接，用于计算相关数据，并完成样本的拆分、翻转和写入；
并行相关处理器组，与所述的样本管理有限状态机相连接，用于并行完成针对多个目标的高性能处理工作；
多输出数据形成器，与所述的并行相关处理器组相连接，用于同时实现多输出结果的数据形成，并向外输出标志位信号。
作为本发明的优选实施方式，所述的多接口控制及命令解析模块包括：
控制器组，用于接收各个接口的命令和样本信息；
多接口命令配置解析器，与所述的控制器组相连接，用于解析处理命令及样本信息，并同时传输给所述的样本管理有限状态机，命令触发后的样本信息经过处理后互相覆盖。
作为本发明的优选实施方式，所述的多接口控制及命令解析模块将样本信息写入闪存，实现在重启或命令解析操作下自动读取并自动配置。
作为本发明的优选实施方式，所述的样本管理有限状态机包括：
配置控制有限状态机，与所述的多接口命令配置解析器相连接，用于计算期望相关点数、所需的并行通道数和子相关计算单元填零数；
样本存储RAM单元，包括实部RAM子单元组和虚部RAM子单元组，均与所述的并行相关处理器组相连接，用于将样本信息拆分翻转并分别写入实部RAM子单元组及虚部RAM子单元组，所述的实部RAM子单元组用于存储实部数据，所述的虚部RAM子单元组用于存储虚部数据。
作为本发明的优选实施方式，所述的并行相关处理器组包括：
延迟控制器，与所述的样本存储RAM单元相连接，用于对多路信号分别延迟控制；
多路相关计算子单元组，与所述的延迟控制器相连接，用于并行完成数据的实部和虚部计算；
相关信号综合单元，与所述的多路相关计算子单元组相连接，用于对实部和虚部分别累加计算，并对相关子信号进行综合运算。
作为本发明的优选实施方式，所述的多输出数据形成器包括：
计算输出单元，与所述的并行相关处理器组相连接，用于计算并多输出相关能量结果、时间增益补偿后的相关能量结果、归一化相关系数结果，以及相关时延结果、相关相位结果；
数据形成单元，与所述的计算输出单元相连接，用于将各输出结果存入数据形成存储器，并向外输出标志位信号。
该基于上述系统实现基于FPGA的应用于水声定位的可重配置和多输出的实时处理控制方法，其中包括以下步骤：
(1)所述的多接口控制及命令解析模块完成实时相关处理样本的重配置；
(2)所述的样本管理有限状态机计算期望相关点数、所需的并行通道数和子相关计算单元填零数，完成样本拆分、翻转及写入；
(2.1)所述的配置控制有限状态机完成命令解析并获得命令及数据；
(2.2)所述的配置控制有限状态机计算期望相关点数、所需的并行通道数和子相关计算单元填零数；
(2.3)样本存储RAM单元将样本拆分、翻转并写入实部RAM子单元组及虚部RAM子单元组；
(3)所述的并行相关处理器组并行完成针对多阵元多个目标的高性能相关处理；
(3.1)所述的延迟控制器完成信号延迟控制；
(3.2)所述的多路相关计算子单元组并行完成数据的实部和虚部计算；
(3.3)所述的相关信号综合单元对相关子信号进行综合运算；
(4)所述的多输出数据形成器通过时间增益补偿后的相关能量结果、归一化相关系数结果、相关时延结果和相关相位结果完成多输出数据结果。
本发明的具体实施方式中，本发明公开了一种基于FPGA的应用于水声定位的高性能多输出可重配置的实时相关处理方法，所述方法包括：利用多接口控制完成实时相关处理样本的重配置；利用样本管理有限状态机计算期望相关点数、所需的并行通道数和子相关计算单元填零数，完成样本拆分、翻转及写入；利用高度节约资源的并行相关处理器组并行完成针对多阵元多个目标的高性能相关处理；利用时间增益补偿后的相关能量结果、归一化相关系数结果及相关时延-相位结果形成多输出数据结果。本发明同时还公开了一种基于FPGA的应用于水声定位的可重配置和多输出的实时相关处理装置。
装置包括：
多接口控制及命令解析单元，用于完成对多接口控制及命令解析单元自动化地完成样本信息的传输及命令解析；
样本管理有限状态机，用于计算期望相关点数、所需的并行通道数和子相关计算单元填 零数，完成样本拆分、翻转及写入；
高度节约资源的并行相关处理器组，用于并行完成针对多阵元多个目标的高性能相关处理；
多输出数据形成器，用于完成基于时间增益补偿后的相关能量结果、归一化相关系数结果及相关时延-相位结果形成多输出数据结果的计算的同时输出。
多接口控制及命令解析单元，将解析出的命令及样本信息同时直接供后续单元使用，并且在接收样本信息时将数据同时写入FLASH之中；每次重启或命令解析均可自动从FLASH读取并实现自动配置。命令解析单元，均可同时进行处理，经由命令触发后各接口处理器样本信息可以经过“或”的处理互相覆盖。
样本管理有限状态机，具体用于计算期望相关点数、所需的并行通道数和子相关计算单元填零数，完成样本拆分、翻转及写入，包括：自动根据规则计算期望相关点数、所需的并行通道数和子相关计算单元填零数；自动将样本拆分、翻转并写入实部RAM子单元组及虚部RAM子单元组；
高度节约资源的并行相关处理器组，用于并行完成针对多阵元多个目标的高性能相关处理，包括：对多路信号分别延迟控制；利用高度节约的资源完成并行相关处理器组的计算，即利用包括1个先出队列(First Input First Output，FIFO)，1个缓存RAM，1个样本存储RAM，一个乘-累加基本单元，以及相关处理控制器在内的逻辑资源完成实部的计算，利用等同的资源完成虚部的计算；利用流水线结构节约资源，经过多级流水计算后，获得实部、虚部分别累加结果，即相关子信号进行综合运算。
多输出数据形成器，其特征在于，利用时间增益补偿后的相关能量结果、归一化相关系数结果及相关时延-相位结果形成多输出数据结果，包括：将实部平方和虚部平方求和相加，求得相关能量结果；基于球面波衰减或者平面波衰减，以及相应频率的吸收衰减，结合声源级、换能器灵敏度、接收机增益等相关系统参数，计算能量-距离衰减曲线以及时间增益补偿-距离衰减曲线；计算相关能量和信号本征能量，计算归一化相关系数结果；利用时延结果结合采样频率及点数获得；相关相位结果可采用CORDIC算法获得计算相关时延结果、相关相位结果；利用RAM及控制状态机实现多输出结果的数据形成，并向外输出标志位信号。
方法包括：
利用多接口控制完成实时相关处理样本的重配置；
利用样本管理有限状态机计算期望相关点数、所需的并行通道数和子相关计算单元填零 数，完成样本拆分、翻转及写入；
利用高度节约资源的并行相关处理器组并行完成针对多阵元多个目标的高性能相关处理；
利用时间增益补偿后的相关能量结果、归一化相关系数结果及相关时延-相位结果形成多输出数据结果同时输出。
利用多接口控制完成实时相关处理样本的重配置，包括：将解析出的命令及样本信息同时直接供后续单元使用，在接收样本信息时将数据同时写入FLASH之中；每次重启或命令解析均可自动从FLASH读取并实现自动配置。
利用样本管理有限状态机计算期望相关点数、所需的并行通道数和子相关计算单元填零数，完成样本拆分、翻转及写入，包括：自动根据规则计算期望相关点数、所需的并行通道数和子相关计算单元填零数；自动将样本拆分、翻转并写入实部RAM子单元组及虚部RAM子单元组；
利用高度节约资源的并行相关处理器组并行完成针对多阵元多个目标的高性能相关处理，包括：对多路信号分别延迟控制；利用高度节约的资源完成并行相关处理器组的计算，即利用包括1个先出队列(First Input First Output，FIFO)，1个缓存随机存取存储器(Random Access Memory，RAM)，1个样本存储RAM，一个乘-累加基本单元，以及相关处理控制器在内的逻辑资源完成实部的计算，利用等同的资源完成虚部的计算；利用流水线结构节约资源，经过多级流水计算后，获得实部、虚部分别累加结果，即相关子信号进行综合运算；
利用时间增益补偿后的相关能量结果、归一化相关系数结果及相关时延-相位结果形成多输出数据结果，包括：将实部平方和虚部平方求和相加，求得相关能量结果；基于球面波衰减或者平面波衰减，以及相应频率的吸收衰减，结合声源级、换能器灵敏度、接收机增益等相关系统参数，计算能量-距离衰减曲线以及时间增益补偿-距离衰减曲线；计算相关能量和信号本征能量，计算归一化相关系数结果；利用时延结果结合采样频率及点数获得；相关相位结果可采用坐标旋转数字计算方法(Coordinate Rotation Digital Computer，CORDIC)算法获得计算相关时延结果、相关相位结果；利用RAM及控制状态机实现多输出结果的数据形成，并向外输出标志位信号。
本发明实施例提供一种基于FPGA的应用于水声定位的高性能多输出可重配置的实时相关处理方法，包括：
利用多接口控制及命令解析单元自动化地完成样本信息的传输及命令解析：
上述方案中，所述多接口控制器主要包括串口控制器、以太网控制器、数字信号处理器(Digital Signal Processor，DSP)的同步串行接口(Synchronous serial PORTs，SPORT)控制器、闪存(Flash Memory，Flash)样本写入及读取控制器以及其他接口控制器；
上述方案中，所述命令解析单元可同时进行，经由命令触发后各接口处理器样本信息可以互相覆盖；
一方面，将解析出的命令及样本信息同时直接供后续单元使用；
另一方面，在接收样本信息时将数据可写入Flash之中，每次重启或经命令解析均可自动从中读取并实现自动配置。
由样本管理有限状态机负责管理多接口控制及命令解析单元获得的命令及数据：
上述方案中，所述样本管理有限状态机接收命令后将N个目标的2N组样本信息，包括N组信号实部以及N组样本虚部暂存于样本RAM存储单元；
上述方案中，所述样本管理有限状态机再由配置控制有限状态机将N组样本信息自动依次拆分，每组样本信息拆成Nc组子样本信息，并进行翻转，再将实部与虚部分别写入实部RAM子单元组及虚部RAM子单元组。
并行相关处理器组同时完成针对M个阵元(即M路AD信号)、N个目标，即MN路高性能相关处理：
上述方案中，所述单路高性能相关处理包括信号延迟控制器、多路相关计算子单元组以及相关信号综合单元。
结果输出同时包括输出相关能量结果、时间增益补偿后的相关能量结果、归一化相关系数结果，以及相关时延结果、相关相位结果；数据形成器将各输出结果按照格式拼接并存入数据形成存储器，完成后产生标志信号。
本发明实施例提供的一种基于FPGA的应用于水声定位的高性能多输出可重配置的实时相关处理方法和装置，先利用多接口控制及命令解析单元获取命令并解析出多组样本信息，一方面，将解析出的命令及样本信息同时直接供后续单元使用；另一方面，在接收样本信息时将数据可写入Flash之中，每次重启或经命令解析均可自动从中读取并实现自动配置；样本管理有限状态机负责管理多接口控制及命令解析单元获得的命令及数据，将多路样本信息自动依次拆分，并实部与虚部分别写入实部RAM子单元组及虚部RAM子单元组；然后并行相关处理器组，同时运行信号延迟控制器、多路相关计算子单元组以及相关信号综合单元，并行完成针对M个阵元(即M路AD信号)、N个目标，即MN路高性能相关处理；最后， 将输出相关能量结果、时间增益补偿后的相关能量结果、归一化相关系数结果，以及相关时延结果、相关相位结果作为多输出结果，经由数据形成器将各输出结果按照格式拼接并存入数据形成存储器，完成后产生标志信号。如此，可使得整个实现过程中在多个阵元、多个目标下，实现高速并行的相关处理，解决实时性、通用性以及抗噪性方面的问题，有效地实现高性能相关。
下面结合附图和实施例对本发明作进一步的详细说明，图9为本发明实施例提供的一种基于FPGA的应用于水声定位的高性能多输出可重配置的实时相关处理方法的实现流程示意图，如图9所示，本实施例提供一种基于FPGA的应用于水声定位的高性能多输出可重配置的实时相关处理方法，所述方法包括：
步骤101，先利用多接口控制及命令解析单元获取命令并解析出多组样本信息；
具体的，本步骤包括：将解析出的命令及样本信息同时直接供后续单元使用；在接收样本信息时将数据可写入Flash之中，每次重启或经命令解析均可自动从中读取并实现自动配置。
步骤102，样本管理有限状态机负责管理多接口控制及命令解析单元获得的命令及数据；
具体的，本步骤包括：完成命令解析并获得命令及数据；计算期望相关点数、所需的并行通道数和子相关计算单元填零数；样本拆分、翻转并写入实部RAM子单元组及虚部RAM子单元组。
步骤A1：完成命令解析并获得命令及数据；
多接口获得的多个命令及数据，将多接口命令以“或”为逻辑关系作处理，并触发数据获取。上电时，即t＝t 0时，总以FLASH自动读取的为初始化命令及数据，即CMD FLASH进行驱动；后续，即t＞t 0时，则基于后续的命令如串口命令CMD UART、以太网命令CMD ETH、DSP命令CMD SPORT以及其他命令CMD OTHER进行覆盖。
简单地，系统命令可以综合为：
Figure PCTCN2019086533-appb-000001
其中，||表示求或计算。
步骤A2：计算期望相关点数、所需的并行通道数和子相关计算单元填零数；
假设AD最大采样频率为f s，待检测信号脉宽设为T d，则期望总相关点数为
N total＝f sT d    ……(2)
假设FPGA的处理快时钟为f clk，单次最大计算相关点数为
Figure PCTCN2019086533-appb-000002
则所需的并行通道数为：
Figure PCTCN2019086533-appb-000003
其中，
Figure PCTCN2019086533-appb-000004
代表向上取整，N Ch-max依据FPGA总资源数的60％除以自相关计算单元中的单次相关计算资源比值决定。
由此，取子相关计算单元的单次计算的有效的相关点数为：
Figure PCTCN2019086533-appb-000005
其中，单次计算的实际相关点数为：
N d≤N max    ……(6)
子相关计算单元填零数为：
N pd＝N mux·N d-N total    ……(7)
步骤A3：样本拆分、翻转并写入实部RAM子单元组及虚部RAM子单元组；
将多路样本信息自动依次拆分，并将实部与虚部分别写入实部RAM子单元组及虚部RAM子单元组。
这里，记目标C所对应的整样本实部和虚部分别为r C(n)和i C(n)，则各并行计算子单元所需样本分别拆分为
Figure PCTCN2019086533-appb-000006
…和
Figure PCTCN2019086533-appb-000007
以及
Figure PCTCN2019086533-appb-000008
…和
Figure PCTCN2019086533-appb-000009
再将其翻转，记为
Figure PCTCN2019086533-appb-000010
…和
Figure PCTCN2019086533-appb-000011
以及
Figure PCTCN2019086533-appb-000012
…和
Figure PCTCN2019086533-appb-000013
然后将样本补零，记为
Figure PCTCN2019086533-appb-000014
…和
Figure PCTCN2019086533-appb-000015
以及
Figure PCTCN2019086533-appb-000016
…和
Figure PCTCN2019086533-appb-000017
最后，将拆分、翻转和补零后的样本其按顺序自动写入实部及虚部RAM单元。
步骤103，实现并行相关处理器组的计算，并行完成针对M个阵元(即M路AD信号)、N个目标，即MN路高性能相关处理。
具体的，本步骤包括：完成信号延迟控制；相关计算子单元组计算；相关子信号进行综 合。
步骤B1：完成信号延迟控制；
将信号s(n)分为N MUX路，分别进行延迟，并输入给相关子单元组。其中，第一路输入为原始信号s(n)，第一路输出s 1(n)＝s(n-N d)；第二路输入为第一路的输出，即s 1(n)，第二路输出为s 1(n)＝s(n-2N d)；依次递推；最后一路输入为
Figure PCTCN2019086533-appb-000018
最后一路输出为
Figure PCTCN2019086533-appb-000019
步骤B2：完成相关计算子单元组计算；
假设信号能量的标准计算为：
Figure PCTCN2019086533-appb-000020
相关处理并行计算为：
Figure PCTCN2019086533-appb-000021
这里，
Figure PCTCN2019086533-appb-000022
Figure PCTCN2019086533-appb-000023
步骤B2主要完成(10)(11)的子单元计算，计算结构采用图5所示
其中，该子单元实虚部计算各包括1个先出队列(First Input First Output，FIFO)，1个缓存RAM，1个样本存储RAM，一个乘-累加基本单元，以及相关处理控制器。该结构极大地节约了资源，为大规模并行化提供了保证。
步骤B3：完成相关子信号进行综合；
完成(9)中的平方运算，并利用流水线结构节约资源，经过
Figure PCTCN2019086533-appb-000024
级流水计算后，获得实部、虚部结果。
步骤104，完成相关能量结果、时间增益补偿后的相关能量结果、归一化相关系数结果，以及相关时延结果、相关相位结果作为多输出结果的计算，经由数据形成器将各输出结果按照格式拼接并存入数据形成存储器，完成后产生标志信号，再输出。
具体的，本步骤包括：计算相关能量结果；计算时间增益补偿后的相关能量结果；计算 归一化相关系数结果；计算相关时延结果、相关相位结果；数据形成并输出。
步骤C1：计算相关能量结果；
利用(9)将实部平方和虚部平方求和相加，求得相关能量结果。
步骤C2：计算时间增益补偿后的相关能量结果；
根据基于球面波衰减或者平面波衰减，以及相应频率的吸收衰减，结合声源级、换能器灵敏度、接收机增益等相关系统参数，计算能量-距离衰减曲线如图7所示，以及时间增益补偿-距离衰减曲线如图8所示。
步骤C3：计算归一化相关系数结果；
根据(12)可求得归一化相关系数结果
Figure PCTCN2019086533-appb-000025
其中ρ(x)的范围为
Figure PCTCN2019086533-appb-000026
步骤C4：计算相关时延结果、相关相位结果；
时延结果结合采样频率及点数获得；相关相位结果可采用CORDIC算法获得。
步骤C5：数据形成并输出。
实现多输出结果的数据形成，并向外输出标志位信号。
采用了本发明的基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统及其方法，使得整个实现过程中在多个阵元、多个目标下，实现高速并行的相关处理，解决实时性、通用性以及抗噪性方面的问题，有效地实现高性能相关。可通过多接口自动传输、自动配置，具有通用性；在处理时实现通用性的并行计算，不受受通道数、目标数变化的影响，将相关的多输出形成数据输出，形成协同处理机制，在实时相关处理的通用型、实时性和抗噪性上具有较为明显的创新改进。
在此说明书中，本发明已参照其特定的实施例作了描述。但是，很显然仍可以作出各种修改和变换而不背离本发明的精神和范围。因此，说明书和附图应被认为是说明性的而非限制性的。

Claims (9)

  1. 一种基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统，其特征在于，所述的系统包括：
    多接口控制及命令解析模块，用于自动化地完成样本信息的传输及命令解析；
    样本管理有限状态机，与所述的多接口控制及命令解析模块相连接，用于计算相关数据，并完成样本的拆分、翻转和写入；
    并行相关处理器组，与所述的样本管理有限状态机相连接，用于并行完成针对多个目标的高性能处理工作；
    多输出数据形成器，与所述的并行相关处理器组相连接，用于同时实现多输出结果的数据形成，并向外输出标志位信号。
  2. 根据权利要求1所述的基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统，其特征在于，所述的多接口控制及命令解析模块包括：
    控制器组，用于接收各个接口的命令和样本信息；
    多接口命令配置解析器，与所述的控制器组相连接，用于解析处理命令及样本信息，并同时传输给所述的样本管理有限状态机，命令触发后的样本信息经过处理后互相覆盖。
  3. 根据权利要求2所述的基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统，其特征在于，所述的多接口控制及命令解析模块将样本信息写入闪存，实现在重启或命令解析操作下自动读取并自动配置。
  4. 根据权利要求1所述的基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统，其特征在于，所述的样本管理有限状态机包括：
    配置控制有限状态机，与所述的多接口命令配置解析器相连接，用于计算期望相关点数、所需的并行通道数和子相关计算单元填零数；
    样本存储RAM单元，包括实部RAM子单元组和虚部RAM子单元组，均与所述的并行相关处理器组相连接，用于将样本信息拆分翻转并分别写入实部RAM子单元组及虚部RAM子单元组，所述的实部RAM子单元组用于存储实部数据，所述的虚部RAM子单元组用于存储虚部数据。
  5. 根据权利要求1所述的基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统，其特征在于，所述的并行相关处理器组包括：
    延迟控制器，与所述的样本存储RAM单元相连接，用于对多路信号分别延迟控制；
    多路相关计算子单元组，与所述的延迟控制器相连接，用于并行完成数据的实部和虚部计算；
    相关信号综合单元，与所述的多路相关计算子单元组相连接，用于对实部和虚部分别累加计算，并对相关子信号进行综合运算。
  6. 根据权利要求1所述的基于FPGA应用于水声定位实现可重配置和多输出的实时处理系统，其特征在于，所述的多输出数据形成器包括：
    计算输出单元，与所述的并行相关处理器组相连接，用于计算并多输出相关能量结果、时间增益补偿后的相关能量结果、归一化相关系数结果，以及相关时延结果、相关相位结果；
    数据形成单元，与所述的计算输出单元相连接，用于将各输出结果存入数据形成存储器，并向外输出标志位信号。
  7. 一种利用权利要求1所述的系统实现基于FPGA的应用于水声定位的可重配置和多输出的实时处理控制方法，其特征在于，所述的方法包括以下步骤：
    (1)所述的多接口控制及命令解析模块完成实时相关处理样本的重配置；
    (2)所述的样本管理有限状态机计算期望相关点数、所需的并行通道数和子相关计算单元填零数，完成样本拆分、翻转及写入；
    (3)所述的并行相关处理器组并行完成针对多阵元多个目标的高性能相关处理；
    (4)所述的多输出数据形成器通过时间增益补偿后的相关能量结果、归一化相关系数结果、相关时延结果和相关相位结果完成多输出数据结果。
  8. 根据权利要求7所述的实现基于FPGA的应用于水声定位的可重配置和多输出的实时处理控制方法，其特征在于，所述的样本管理有限状态机包括配置控制有限状态机和样本存储RAM单元，所述的样本存储RAM单元包括实部RAM子单元组和虚部RAM子单元组，所述的步骤(2)具体包括以下步骤：
    (2.1)所述的配置控制有限状态机完成命令解析并获得命令及数据；
    (2.2)所述的配置控制有限状态机计算期望相关点数、所需的并行通道数和子相关计算单元填零数；
    (2.3)样本存储RAM单元将样本拆分、翻转并写入实部RAM子单元组及虚部RAM子单元组。
  9. 根据权利要求8所述的实现基于FPGA的应用于水声定位的可重配置和多输出的实时处理控制方法，其特征在于，所述的并行相关处理器组包括延迟控制器、多路相关计算子单 元组和相关信号综合单元，所述的步骤(3)具体包括以下步骤：
    (3.1)所述的延迟控制器完成信号延迟控制；
    (3.2)所述的多路相关计算子单元组并行完成数据的实部和虚部计算；
    (3.3)所述的相关信号综合单元对相关子信号进行综合运算。
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