WO2020135406A1 - 影像解码装置与方法 - Google Patents

影像解码装置与方法 Download PDF

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Publication number
WO2020135406A1
WO2020135406A1 PCT/CN2019/127869 CN2019127869W WO2020135406A1 WO 2020135406 A1 WO2020135406 A1 WO 2020135406A1 CN 2019127869 W CN2019127869 W CN 2019127869W WO 2020135406 A1 WO2020135406 A1 WO 2020135406A1
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pixel data
temporary storage
picture
decoded picture
storage block
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PCT/CN2019/127869
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English (en)
French (fr)
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孙明勇
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厦门星宸科技有限公司
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    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
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    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H04N19/58—Motion compensation with long-term prediction, i.e. the reference frame for a current frame not being the temporally closest one
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    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H04N19/426—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements using memory downsizing methods
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    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/43—Hardware specially adapted for motion estimation or compensation
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    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
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    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/103—Selection of coding mode or of prediction mode
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    • H04N19/136—Incoming video signal characteristics or properties
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    • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
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Definitions

  • the invention relates to image decoding technology, in particular to an image decoding device and method.
  • the video codec can compress or decompress the digital film to be more efficient in transmission.
  • many current coding technologies such as H.264, H.265, or HEVC image coding and decoding standards
  • motion estimation and motion compensation techniques are used, and the images within the reference period are encoded to effectively record and compress the dynamic images.
  • the pictures being decoded must also be temporarily stored as the decoding progresses.
  • an object of the present invention is to provide an image decoding device and method to improve the existing technology.
  • An object of the present invention is to provide an image decoding device and method that enables reference frames required for image decoding and generated decoded frames to share temporary storage blocks in a memory module, effectively reducing memory usage.
  • the invention includes a video decoding method, which includes: reading control information in a video stream; reading a plurality of video stream packets in the video stream according to the control information; at least according to the control information, enabling the decoding circuit to select from The first temporary storage block of the memory module reads the corresponding pixel data in the first reference frame and/or the second temporary storage block reads the corresponding pixel data in the second reference frame; According to the corresponding pixel data in the first reference picture and/or the corresponding pixel data in the second reference picture to generate pixel data of the decoded picture; during decoding, the pixel data of the decoded picture is transferred to the post-processing circuit And store the pixel data of the decoded picture to one of the first temporary storage block and the second temporary storage block according to the control information.
  • the invention also includes an image decoding device, including: a memory module, a decoding circuit, a post-processing circuit and a processing circuit.
  • the processing circuit is electrically coupled to the memory module, the post-processing circuit and the decoding circuit, and is configured to execute software and firmware executable instructions to execute the image decoding method.
  • the image decoding method includes: at least according to the control information, the decoding circuit is selectively The first temporary storage block of the memory module reads the corresponding pixel data in the first reference frame and/or the second temporary storage block reads the corresponding pixel data in the second reference frame; According to the corresponding pixel data in the first reference picture and/or the corresponding pixel data in the second reference picture to generate pixel data of the decoded picture; during decoding, the pixel data of the decoded picture is transferred to the post-processing circuit And store the pixel data of the decoded picture to one of the first temporary storage block and the second temporary storage block according to the control information.
  • the present invention includes an image decoding method, including: reading and decoding control information in an image stream; reading a plurality of image stream packets in the image stream according to the control information; at least according to the control information, the first A temporary storage block reads the corresponding pixel data in at least one first reference frame, wherein the storage content of the first temporary storage block is stored in sequence, and the storage content includes the maximum motion vector search range frame and sequence in front of the sequence
  • the first reference picture afterwards; decode according to the video stream packet and the corresponding pixel data in the first reference picture to generate pixel data of the decoded picture; and when decoding, transmit the pixel data of the decoded picture to
  • the post-processing circuit performs post-processing, and according to the control information, causes the decoding circuit to store the pixel data of the decoded picture line by line in the first temporary storage block, and replaces the stored content in the first temporary storage block sequentially in order Save content.
  • the invention also includes an image decoding device, including: a memory module, a decoding circuit, a post-processing circuit and a processing circuit.
  • the processing circuit is electrically coupled to the memory module, the post-processing circuit and the decoding circuit, and is configured to execute software and firmware executable instructions to execute the image decoding method.
  • the image decoding method includes: reading and decoding control information in the image stream; According to the control information, the decoding circuit reads a plurality of video stream packets in the video stream; at least according to the control information, causes the decoding circuit to read the corresponding at least one first reference frame from the first temporary storage block of the memory module Pixel data, where the storage content of the first temporary storage block is stored in sequence, and the storage content includes the largest motion vector search range picture in the order and the first reference picture in the order; enables the decoding circuit to pack according to the video stream , And decoding according to the corresponding pixel data in the first reference picture to generate pixel data of the decoded picture; and during decoding, the pixel data of the decoded picture is sent to a post-processing circuit for post-processing, and the decoding is performed according to the control information
  • the pixel data of the circuit stores the decoded picture line by line in the first temporary storage block, and replaces the stored content in order starting from the first stored content in the first temporary storage block.
  • FIG. 1 shows a block diagram of an image decoding device according to an embodiment of the invention
  • FIG. 2 shows a flowchart of an image decoding method according to an embodiment of the invention.
  • 3A to 3C show schematic diagrams of the first temporary storage block according to an embodiment of the invention.
  • An object of the present invention is to provide an image decoding device and method, so that when decoding, the memory can be more efficient in terms of the storage mechanism for reference pictures and decoded pictures, and achieve the effect of saving space.
  • FIG. 1 is a block diagram of an image decoding device 100 according to an embodiment of the invention.
  • the image decoding device 100 receives an image stream (Element Stream; ES), and performs decoding and post-processing according to the image stream packet and control information in the image stream ES, generates and outputs a decoded image DOI, and causes the display module (not shown) ) To display the decoded image DOI.
  • the video decoding device 100 includes at least a memory controller 150, a memory module 110, a decoding circuit 120, a post-processing circuit 130, and a processing circuit 140.
  • the memory module 110 can also be an independent component connected to the image decoding device 100 through an interface.
  • the memory module 110 is connected to the decoding circuit 120, the post-processing circuit 130, and the processing circuit 140 through the memory controller 150.
  • the memory module 110 has different blocks to store different data required for image decoding, at least including the video stream ES block, one or more short-range reference picture blocks, one or more long-range reference picture blocks, and an EOI Block.
  • the memory module 110 may be implemented by a faster memory, such as, but not limited to, double data rate synchronous dynamic random access memory (double data synchronous dynamic random access memory; DDR SDRAM).
  • the image decoding device 100 may further include a memory controller 150.
  • the memory controller 150 may be implemented by, for example, but not limited to, a memory interface unit (MIU).
  • MIU memory interface unit
  • Other circuit modules in the image decoding device 100 such as the decoding circuit 120, the post-processing circuit 130, and the processing circuit 140, can access the memory module 110 through the memory controller 150 to store data in the memory module 110, or The data is read from the memory module 110.
  • the decoding circuit 120 is used to decode according to required data, such as but not limited to reference pictures and video stream packets, and gradually store the decoded pixels to the memory bank and send to the post-processing circuit 130 to generate a decoded picture DI.
  • the decoder can perform the decoding process according to, for example, but not limited to, H.264 or H.265 encoding standards.
  • the post-processing circuit 130 is used to post-process the decoded image DI, such as but not limited to scaling, image quality processing, or format conversion, to generate an output decoded image DOI.
  • the processing circuit 140 is electrically coupled to the memory module 110, the post-processing circuit 120, and the decoding circuit 130.
  • the processing circuit 140 may be composed of one or more microprocessors or a video stream analysis circuit, and execute software and firmware executable instructions 141 to execute the functions of the video decoding device 100.
  • the processing circuit 140 may retrieve software and firmware executable instructions 141 from a storage module (not shown) included in the image decoding device 100, and the software and firmware executable instructions 141 include, for example but not limited to, video streaming control information
  • the firmware/driver of hardware modules such as decoding, post-processing circuit 120 and decoding circuit 130 and other related instructions for operating and controlling the hardware modules such as post-processing circuit 120 and decoding circuit 130, after further operation and control
  • the hardware modules such as the processing circuit 120 and the decoding circuit 130 achieve the aforementioned decoding and post-processing of the video stream ES, and generate an output decoded video DOI.
  • the decoding circuit 120, the post-processing circuit 130, and the processing circuit 140 exchange required control information during video stream decoding and video post-processing.
  • FIG. 2 is a flowchart of an image decoding method 200 according to an embodiment of the invention.
  • the image decoding method 200 can be applied to the image decoding device 100 shown in FIG. 1.
  • An embodiment of the image decoding method 200 is shown in FIG. 2 and includes the following steps.
  • step S210 the processing circuit 140 reads and decodes the control information in the video stream ES.
  • the control information can be used to identify whether the packet belongs to a short-range reference frame (Short Term Reference Frame; STRF) or a long-range reference frame (Long Term Reference Frame; LTRF ), and the parameters used for decoding, etc.
  • STRF Short Term Reference Frame
  • LTRF Long Term Reference Frame
  • the video stream ES is temporarily stored in the video stream packet temporary storage block 112 in the memory module 110.
  • the processing circuit 140 and the decoding circuit 120 can read the video stream packet temporary storage block 112 through the memory controller 150, and obtain the control information and the video stream packets (ESPackets) in the video stream ES.
  • ESPackets video stream packets
  • step S220 Based on the control information, the decoding circuit 120 reads the video stream packet in the video stream ES.
  • the video stream ES includes video stream packets in addition to the control information.
  • the control information in the video stream ES includes encoding-related information
  • the video stream packet is the actual video data.
  • the processing circuit 140 can know the packet to be decoded and the picture to be referenced according to the control information, and control the decoding circuit 120 to read the video stream packet in the video stream ES through the memory controller 150.
  • step S230 at least according to the control information, the decoding circuit 120 selectively reads the corresponding pixel data in the first reference frame SF and/or the second temporary storage block 116 from the first temporary storage block 114 of the memory module 110 Read the corresponding pixel data in the second reference picture LF.
  • the decoding circuit 120 may also selectively perform the above-mentioned reading operation according to the control information and the content of the video stream packet.
  • the stored content of the first temporary storage block 114 includes at least the first reference picture SF.
  • the first reference picture SF is a short-range reference picture. Taking the current decoded picture as the Nth picture in timing, for example, the first reference picture SF may be the N-1th picture, that is, the decoded picture before the decoding is completed.
  • the stored content of the second temporary storage block 116 includes at least the second reference picture LF.
  • the second reference picture LF is a long-range reference picture. Taking the current decoded picture as the Nth picture in timing, for example, the second reference picture LF may be the N-5th picture, not the previous decoded picture.
  • the decoding circuit 120 will read the required reference data according to the needs of each current decoded picture, it may read the short-range reference picture and the long-range reference picture, or it may only read one of the short-range reference picture and the long-range reference picture, or may No need to read any reference picture.
  • the current decoded picture will share the first temporary storage block 114 with the previous decoded picture, and the current decoded picture will gradually cover the previous decoded picture, but At least the previous decoded picture block required for decoding the current picture needs to be reserved.
  • the video stream included in the video stream ES has a screen height of H, and a screen width of W, and the size of the video screen is H ⁇ W, and the maximum search for motion vectors between screens is set as the standard for encoding and decoding When the number of lines is V, the size of the maximum motion vector search range screen is V ⁇ W.
  • the size of the first temporary storage block 114 is H ⁇ W+V ⁇ W, and the first temporary storage block 114 may be a ring buffer memory (Ring Buffer) design, however, the invention is not limited to this . If the current decoded picture is also a long-range reference picture, the current decoded picture will share the second temporary block 116 with the previous decoded picture, and the remaining operations are the same as the short-range reference picture sharing the first temporary block 114, which will not be repeated here.
  • step S240 control the decoding circuit 120 to decode the corresponding pixel data in the first reference frame SF and/or the corresponding pixel data in the second reference frame LF according to the video stream packet to generate a decoded frame DI pixel data.
  • the decoding circuit 120 will sequentially decode the video stream packets in the video stream ES according to the video codec standard, such as H.264 or H.265, and store the decoded pixels to the memory
  • the module 110 is sent to the post-processing circuit 130 until decoding of the current picture is completed to generate a decoded picture DI.
  • the decoding circuit 120 needs to selectively refer to the pixel data of the first reference frame SF and/or the pixel data of the second reference frame LF according to the control signal and the video stream packet data.
  • step S250 while decoding, the decoding circuit 120 is controlled to sequentially transfer the decoded pixel data in the decoded picture DI to the post-processing circuit 130 for post-processing, and according to the control information, decode the decoded pixels in the decoded picture DI The data is sequentially stored in the first temporary storage block 114 or the second temporary storage block 116.
  • the decoded picture DI is a short-range reference picture
  • the decoded pixels in the decoded picture DI are sequentially stored in the first temporary block 114
  • the decoded picture DI is a long-range reference picture
  • the decoded picture DI The pixels decoded in the middle are sequentially stored in the second temporary block 116.
  • the first temporary storage area is not limited to storing short-range reference pictures
  • the second temporary storage area is not limited to storing long-range reference pictures, which can be adjusted by the system according to requirements. Configuration.
  • the output decoded picture DOI generated by post-processing by the post-processing circuit 130 is used for display by an external display device.
  • the decoding circuit 120 reads the pixel data of the first reference picture SF in the first temporary storage block 114 through the memory controller 150 and passes through the memory controller 150 stores the pixel data of the generated decoded picture DI into the first temporary storage block 114.
  • the decoding circuit 120 when the current picture decoding needs to refer to the first reference picture SF, the size of the required maximum motion vector search range MF is V ⁇ W, and the decoding circuit 120 The generated decoded picture DI must be stored from the V ⁇ W position before the first reference picture SF in the first temporary storage block 114.
  • the decoded picture DI generated by the decoding circuit 120 preferentially replaces the content of the original maximum motion vector search range picture MF1. Then, after the maximum motion vector search range picture MF1 of size V ⁇ W is replaced, the decoding circuit 120 will then replace the first reference picture SF of the first part until all the data of the decoded picture DI are generated and Until the storage is finished.
  • the first temporary storage block 114 can gradually replace the stored content of the first temporary storage block 114 through the above-described decoded picture DI, so that the first reference frame SF and the decoded picture DI share the first temporary storage block 114.
  • the decoding circuit 120 needs the motion vector information when decoding, it is necessary to reserve at least the range of the first reference image SF that matches the maximum motion vector search, so that the last block of the decoded picture DI can still refer to the first
  • the decoding circuit 120 decodes the reference video SF.
  • the size of the maximum motion vector search range that is, the size of V
  • the size of V can be determined according to needs.
  • the decoding circuit 120 reads the second reference picture LF in the second temporary storage block 116 through the memory controller 150, and the generated decoded picture DI through the memory controller 150 The pixels are stored in the second temporary block 116.
  • the access operation of the second temporary storage block 116 is the same as the access operation of the aforementioned first temporary storage block 114, and is not repeated here.
  • FIGS. 3A to 3C are schematic diagrams of the first temporary storage block 114 according to an embodiment of the invention.
  • the first temporary storage block 114 stores the first reference image SF and the maximum motion vector search range frame MF1.
  • the decoding circuit 120 will start reading from the starting position of the first reference image SF and store the decoded picture DI from the starting position of the maximum motion vector search range picture MF1 after decoding.
  • the reading of the first reference image SF can be performed in the following manner.
  • the address offset of the start position of the first reference image SF relative to the start position of the first temporary storage block 114 can be recorded as the reference picture start address offset Stoff by the processing circuit 140.
  • the processing circuit 140 can retrieve the start address offset Mboff of the picture block corresponding to the corresponding reference picture block RB in the first reference picture SF through the control information.
  • the processing circuit 140 further adds the frame block start address offset Mboff and the reference frame start address offset Stoff, and divides it by the size of the first temporary block 114 (H ⁇ W+V ⁇ W), To get a remainder R1.
  • the remainder R1 (Mboff+Stoff)mod(H ⁇ W+V ⁇ W).
  • the processing circuit 140 calculates the read start address (IA+R1) of the first temporary storage block 114 after adding the remainder to the temporary storage block start address IA of the memory module 110, and causes the decoding circuit 120 to read Take the starting address to read the required reference picture block RB.
  • the storage of the decoded picture DI can be performed in the following manner.
  • the address offset of the start position relative to the start position of the first temporary storage block 114 can be recorded by the processing circuit 140 as the decoded picture start address offset Nfoff.
  • the offset of the decoded picture block included in the decoded picture DI relative to the start position of the decoded picture DI can be determined by the processing circuit 140 as the decoded picture block start address offset MBoff.
  • the processing circuit 140 further adds the decoded picture block start address offset MBoff and the decoded picture start address offset Nfoff, and divides it by the size of the first temporary storage block 114 to obtain a remainder R2.
  • the remainder R2 (MBoff+Nfoff)mod(H ⁇ W+V ⁇ W).
  • the decoded picture DI has not been stored to exceed the size of the maximum motion vector search range picture MF1
  • the result of the addition of the decoded picture block start address offset MBoff and the decoded picture start address offset Nfoff The size of the first temporary storage block 114 will not be exceeded, and the remainder R2 will be the same as the result of the addition.
  • the processing circuit 140 calculates the storage start address (IA+R2) of the first temporary storage block 114 after adding the remainder to the temporary storage block start address IA of the memory module 110, and causes the decoding circuit 120 to store The start address stores the decoded picture block DB.
  • the processing circuit 140 can calculate the real storage start address (IA+R2) of the first temporary storage block 114 after adding the remainder to the temporary storage block start address IA of the memory module 110, and The decoding circuit 120 stores the decoded picture block according to the storage start address.
  • the processing circuit 140 will store from the beginning of the first temporary storage block 114 to replace the original first reference picture SF.
  • the stored Nth decoded picture DI will be used as the new first reference picture SF, and is divided into two parts in the first temporary storage block 114 .
  • the timing of the first part is earlier, and is equivalent to the maximum motion vector search range screen MF1 in FIG. 3A.
  • the timing of the second part is later, but the address in the first temporary storage block 114 is earlier than the first part because it is stored from the start address, and is equivalent to a part of the first reference frame SF in FIG. 3A.
  • the other part of the first reference picture SF in FIG. 3A becomes the new maximum motion vector search range picture MF1.
  • the decoding circuit 120 will perform the above address calculation and start reading from the starting position of the first reference image SF in FIG. 3B. After decoding, the above address calculation is performed, and the decoded picture DI is stored from the beginning of the maximum motion vector search range picture MF1 in FIG. 3B.
  • the stored N+1th decoded picture DI will be used as the new first reference picture SF.
  • the remaining first reference picture SF becomes the new maximum motion vector search range picture MF1.
  • the image decoding device 100 of the present invention can effectively make the first reference frame SF and the decoded frame DI share the same temporary storage block through the above-mentioned cyclic storage mechanism.
  • the cyclic storage of the first temporary storage block 114 can be achieved by means of a circular buffer, or can also be achieved by setting a memory management unit.
  • the decoding circuit 120 can simultaneously transmit the decoded picture DI to the post-processing circuit 130 for post-processing, and there is no need to store the decoded picture DI for the post-processing circuit 130 to access. Therefore, the above mechanism of the present case can achieve the purpose of saving memory access bandwidth.
  • the decoding circuit 120 may first compress the generated decoded picture DI, and then store the compressed decoded picture DI into the first temporary storage block 114. Therefore, the size of the first temporary storage block 114 can be further reduced, and the memory usage is further saved.
  • the first temporary storage block 114 storing the short-range reference picture (first reference picture SF) is taken as an example for description.
  • the second temporary block 116 configured to store the long-range reference picture (second reference picture LF) may also have the aforementioned circular buffer mechanism to make the second long-range reference picture the second The reference picture LF and the decoded picture DI share the same temporary storage block.
  • the processing circuit 140 may determine whether the decoded picture DI generated by the current decoding is to be stored in the first temporary block 114 corresponding to the short-range reference picture or to the long-range reference picture.
  • the second temporary storage block 116 replaces the stored content through the aforementioned mechanism. Therefore, the operation mechanism of the second temporary storage block 116 will not be repeated here.
  • the first temporary storage block 114 stores a short-range reference picture as an example for description. In other embodiments, the first temporary storage block 114 may store multiple short-range reference pictures, so that the decoding circuit 120 decodes according to the multiple short-range reference pictures.
  • the decoding mechanism that simultaneously refers to the short-range reference picture and the long-range reference picture is described.
  • the decoding circuit 120 may also decode by referring to the short-range reference picture only.
  • the image decoding device and method in the present invention can make the reference picture required for image decoding and the generated decoded picture share the temporary storage block in the memory module, effectively reducing the memory usage.

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Abstract

本发明包含一种影像解码装置与方法，方法包含：读取和解码影像串流中的控制信息；根据控制信息读取影像串流中的影像串流封包；至少根据控制信息，自存储器模块的第一暂存区块读取第一参考画面中的对应像素数据，其中第一暂存区块的储存内容依顺序储存；根据影像串流封包以及根据第一参考画面中的对应像素数据进行解码，以产生解码画面的像素数据；以及于进行解码时，将解码画面的像素数据传送至后处理电路进行后处理，并根据控制信息将解码画面的像素数据储存至第一暂存区块，以自第一暂存区块中顺序最前的储存内容起始依序取代储存内容。

Description

影像解码装置与方法
本申请要求享有2018年12月25日提交的名称为“影像解码装置与方法”的中国专利申请CN201811593362.0的优先权，其全部内容通过引用并入本文中。
技术领域
本发明是关于影像解码技术，尤其是关于一种影像解码装置与方法。
背景技术
影像编解码器能够对数字影片进行压缩或者解压缩，以在传输上更有效率。在许多现行的编码技术中，例如：H.264、H.265或HEVC等影像编解码标准，是采用移动估计和移动补偿技术，参考时段内的画面进行编码，有效地记录动态影像并进行压缩，节省传输及储存的数据量。因此，在影像解码器一端，需要能够储存多个编码时序上相关的参考画面，以根据参考画面处理正在进行解码的画面。并且，正在进行解码的画面，也必须随着解码的过程进行暂时储存。
然而，参考画面及解码画面均需要储存于存储器中。如果对于储存的机制没有更有效率的设计，将容易对于存储器空间的使用造成浪费。
发明内容
鉴于现有技术的问题，本发明的一目的在于提供一种影像解码装置与方法，以改善现有技术。
本发明的一目的在于提供一种影像解码装置与方法，可使影像解码所需的参考画面以及所产生的解码画面共享存储器模块中的暂存区块，有效降低存储器的使用量。
本发明包含一种影像解码方法，包含：读取影像串流中的控制信息；根据控制信息读取影像串流中的多个影像串流封包；至少根据控制信息，使解码电路选择性地自存储器模块的第一暂存区块读取第一参考画面中的对应像素数据及/或第二暂存区块读取第二参考画面中的对应像素数据；根据影像串流封包，以及选择性地根据第一参考画面中的对应像素数据及/或第二参考画面中的对应像素数据进行解码，以产生解码画面的像素数据；于 进行解码时，将解码画面的像素数据传送至后处理电路，并根据控制信息将解码画面的像素数据储存至第一暂存区块和第二暂存区块的其中之一。
本发明另包含一种影像解码装置，包含：存储器模块、解码电路、后处理电路以及处理电路。处理电路电性耦接于存储器模块、后处理电路以及解码电路，并配置以执行软固件可执行指令，以执行影像解码方法，影像解码方法包含：至少根据控制信息，使解码电路选择性地自存储器模块的第一暂存区块读取第一参考画面中的对应像素数据及/或第二暂存区块读取第二参考画面中的对应像素数据；根据影像串流封包，以及选择性地根据第一参考画面中的对应像素数据及/或第二参考画面中的对应像素数据进行解码，以产生解码画面的像素数据；于进行解码时，将解码画面的像素数据传送至后处理电路，并根据控制信息将解码画面的像素数据储存至第一暂存区块和第二暂存区块的其中之一。
本发明包含一种影像解码方法，包含：读取和解码影像串流中的控制信息；根据控制信息读取影像串流中的多个影像串流封包；至少根据控制信息，自存储器模块的第一暂存区块读取至少一第一参考画面中的对应像素数据，其中第一暂存区块的储存内容是依顺序储存，且储存内容包含顺序在前的最大移动向量搜寻范围画面以及顺序在后的第一参考画面；根据影像串流封包，以及根据第一参考画面中的对应像素数据进行解码，以产生解码画面的像素数据；以及于进行解码时，将解码画面的像素数据传送至后处理电路进行后处理，并根据控制信息使解码电路将解码画面的像素数据逐行储存至第一暂存区块，以自第一暂存区块中顺序最前的储存内容起始依序取代储存内容。
本发明另包含一种影像解码装置，包含：存储器模块、解码电路、后处理电路以及处理电路。处理电路电性耦接于存储器模块、后处理电路以及解码电路，并配置以执行软固件可执行指令，以执行影像解码方法，影像解码方法包含：读取和解码影像串流中的控制信息；根据控制信息，使解码电路读取影像串流中的多个影像串流封包；至少根据控制信息，使解码电路自存储器模块的第一暂存区块读取至少一第一参考画面中的对应像素数据，其中第一暂存区块的储存内容是依顺序储存，且储存内容包含顺序在前的最大移动向量搜寻范围画面以及顺序在后的第一参考画面；使解码电路根据影像串流封包，以及根据第一参考画面中的对应像素数据进行解码，以产生解码画面的像素数据；以及于进行解码时，将解码画面的像素数据传送至后处理电路进行后处理，并根据控制信息使解码电路的像素数据将解码画面逐行储存至第一暂存区块，以自第一暂存区块中顺序最前的储存内容起始依序取代储存内容。
有关本发明的特征、实作与功效，现在配合图式作较佳实施例详细说明如下。
附图说明
图1显示本发明的一实施例中，影像解码装置的方块图；
图2显示本发明的一实施例中，一种影像解码方法的流程图；以及
图3A至图3C显示本发明一实施例中，第一暂存区块的示意图。
其中，附图标记：
100 影像解码装置
110 存储器模块
112 影像串流封包暂存区块
114 第一暂存区块
116 第二暂存区块
118 显示暂存器
120 解码电路
130 后处理电路
140 处理电路
141 软固件可执行指令
150 存储器控制器
200 影像解码方法
DB 解码画面区块
DI 解码画面
DOI 输出解码影像
ES 影像串流
LF 第二参考画面
MBoff 解码画面区块起始地址偏移量
Mboff 画面区块起始地址偏移量
MF1 最大移动向量搜寻范围画面
MF2 最大移动向量搜寻范围画面
Nfoff 解码画面起始地址偏移量
RB 参考画面区块
SF 第一参考画面
Stoff 参考画面起始地址偏移量
S210～S260 步骤
具体实施方式
以下结合附图和具体实施例对本发明进行详细描述，但不作为对本发明的限定。
本发明的一目的在于提供一种影像解码装置与方法，以在进行解码时，使存储器在对于参考画面以及解码画面的储存机制上，能够更有效率，达到节省空间的功效。
请参照图1。图1为本发明的一实施例中，影像解码装置100的方块图。影像解码装置100接收影像串流(Element Stream；ES)，并根据影像串流ES中的影像串流封包以及控制信息进行解码以及后处理，产生输出解码影像DOI，并使显示模块(未绘示)得以将解码影像DOI进行显示。
影像解码装置100至少包含存储器控制器150、存储器模块110、解码电路120、后处理电路130以及处理电路140。其中存储器模块110亦可为独立元件通过接口和影像解码装置100连接。
于一实施例中，存储器模块110通过存储器控制器150与解码电路120、后处理电路130以及处理电路140连接。存储器模块110具有不同的区块，以储存影像解码所需的不同数据，至少包含影像串流ES区块、一或多个短程参考画面区块、一或多个长程参考画面区块以及一EOI区块。存储器模块110可由速度较快的存储器实现，例如，但不限于双倍数据率同步动态随机存取存储器(double data rate synchronous dynamic random access memory；DDR SDRAM)。
于一实施例中，影像解码装置100可更包含存储器控制器150。存储器控制器150可由例如，但不限于存储器界面单元(memory interface unit；MIU)实现。在影像解码装置100中的其他电路模块，如解码电路120、后处理电路130以及处理电路140，可通过存储器控制器150对存储器模块110进行存取，以将数据储存于存储器模块110，或是自存储器模块110读取数据。
解码电路120用于根据所需的数据，例如但不限于参考画面以及影像串流封包进行解 码，并逐步将解码完成的像素储存至存储器组以及送至后处理电路130，产生解码画面DI。解码器可依据例如但不限于H.264或H.265编码标准而进行解码程序。
后处理电路130用于对解码画面DI进行后处理，例如但不限于缩放(scaling)、影像品质处理或是格式转换，以产生输出解码影像DOI。
处理电路140电性耦接于存储器模块110、后处理电路120以及解码电路130。处理电路140可以由一或多个微处理器(microprocessor)或搭配影像串流分析电路所组成，执行软固件可执行指令141，以执行影像解码装置100的功能。更详细来说，处理电路140可从影像解码装置100中包含的储存模块(未绘示)撷取软固件可执行指令141，且软固件可执行指令141包含例如但不限于影像串流控制信息解码、后处理电路120以及解码电路130等硬件模块的固件/驱动程序(firmware/driver)以及其他用以操作与控制后处理电路120以及解码电路130等硬件模块的相关指令，进一步操作与控制后处理电路120以及解码电路130等硬件模块，达到前述对影像串流ES进行解码以及后处理，并产生输出解码影像DOI。
在一实施例中，解码电路120、后处理电路130以及处理电路140，于影像串流解码及影像后处理过程中，交换所需的控制信息。
请同时参照图2。以下将搭配图1及图2，对于影像解码装置100的详细功能进行更详细的说明。
图2为本发明一实施例中，一种影像解码方法200的流程图。影像解码方法200可应用于图1所示的影像解码装置100中。影像解码方法200的一实施例如图2所示，包含下列步骤。
于步骤S210：使处理电路140读取及解码影像串流ES中的控制信息，控制信息可用于识别封包属于短程参考画面(Short Term Reference Frame；STRF)或长程参考画面(Long Term Reference Frame；LTRF)，以及用于解码的参数等。
于一实施例中，影像串流ES暂存于存储器模块110中的影像串流封包暂存区块112中。处理电路140和解码电路120可通过存储器控制器150读取影像串流封包暂存区块112，并获得影像串流ES中的控制信息以及影像串流封包(ES Packets)。
于步骤S220：根据控制信息，使解码电路120读取影像串流ES中的影像串流封包。
于一实施例中，影像串流ES除控制信息外，更包含影像串流封包。其中，影像串流ES中的控制信息包含编码的相关信息，而影像串流封包则为实际的影像数据。处理电路140可根据控制信息，得知欲进行解码的封包以及欲参考的画面为何，并控制解码电路120 通过存储器控制器150读取影像串流ES中的影像串流封包。
于步骤S230：至少根据控制信息，使解码电路120选择性地自存储器模块110的第一暂存区块114读取第一参考画面SF中的对应像素数据及/或第二暂存区块116读取第二参考画面LF中的对应像素数据。
于一实施例中，解码电路120亦可能同时依据控制信息以及影像串流封包的内容，选择性地进行上述的读取动作。
在一实施例中，第一暂存区块114的储存内容至少包含第一参考画面SF，在本实施例中，第一参考画面SF为短程参考画面。以当前解码画面在时序上为第N个画面为例，第一参考画面SF可为第N-1个画面，亦即完成解码的前一解码画面。第二暂存区块116的储存内容至少包含第二参考画面LF，在本实施例中，第二参考画面LF为长程参考画面。以当前解码画面在时序上为第N个画面为例，第二参考画面LF可为第N-5个画面，并非前一解码画面。解码电路120会依据每个当前解码画面的需求，读取所需的参考数据，可能读取短程参考画面及长程参考画面，也可能只读取短程参考画面及长程参考画面其中之一，或可能不需读取任何参考画面。
更详细的说，基于节省存储器考量，如果当前解码画面亦为短程参考画面，当前解码画面会和前一解码画面共用第一暂存区块114，当前解码画面会逐步覆盖前一解码画面，但至少需保留用于解码当前画面所需的前一解码画面区块。在本实施例中，影像串流ES包含的影像画面的画面高度为H，且画面宽度为W，影像画面的大小为H×W，且当编解码的标准设定画面间移动向量的最大搜寻行数为V时，则最大移动向量搜寻范围画面的大小为V×W。因此，第一暂存区块114的大小为H×W+V×W，第一暂存区块114可为一环状缓冲器存储器(Ring Buffer)设计，然而本发明并不以此为限。如果当前解码画面亦为长程参考画面，当前解码画面会和前一解码画面共用第二暂存区块116，其余与短程参考画面共用第一暂存区块114的操作相同，在此不赘述。
于步骤S240：控制解码电路120，根据影像串流封包，以及选择性地根据第一参考画面SF中的对应像素数据及/或第二参考画面LF中的对应像素数据进行解码，以产生解码画面DI的像素数据。
在一实施例中，解码电路120会根据视讯编解码标准，例如：H.264或H.265，将影像串流ES中的影像串流封包依序解码，并将解码完成的像素储存至存储器模块110及送至后处理电路130，直到当前画面解码完成，以产生解码画面DI。解码电路120对影像串流封包解码时，需要根据控制信号及影像串流封包数据，选择性参考第一参考画面SF 的像素数据及/或第二参考画面LF的像素数据进行解码。
于步骤S250：于进行解码的同时，控制解码电路120将解码画面DI中解码完成的像素数据依序传送至后处理电路130进行后处理，并依据控制信息，将解码画面DI中解码完成的像素数据依序储存至第一暂存区块114或第二暂存区块116。在一实施例中，若解码画面DI为短程参考画面，将解码画面DI中解码完成的像素依序储存至第一暂存区块114，或者若解码画面DI为长程参考画面，将解码画面DI中解码完成的像素依序储存至第二暂存区块116。
在另一实施例中，不限于储存一个短程参考画面和一个长程参考画面，且第一暂存区不限于储存短程参考画面，第二暂存区不限于储存长程参考画面，可由系统根据需求调整配置。
另外，于一实施例中，经由后处理电路130的后处理所产生的输出解码画面DOI，用以供外部的显示装置进行显示。
在本实施例中，当解码画面为短程参考画面时，解码电路120是边通过存储器控制器150读取第一暂存区块114中的第一参考画面SF的像素数据，边通过存储器控制器150将所产生的解码画面DI的像素数据储存至第一暂存区块114。
由于以第一暂存区块114为一环状缓冲器存储器为例，当前画面解码需要参考第一参考画面SF时，所需最大移动向量搜寻范围MF的大小为V×W，解码电路120所产生的解码画面DI必须从第一暂存区块114中第一参考画面SF之前V×W位置开始储存。解码电路120所产生的解码画面DI优先取代原本的最大移动向量搜寻范围画面MF1的内容。接着，在大小为V×W的最大移动向量搜寻范围画面MF1均被取代完后，解码电路120将接着使第一部分的第一参考画面SF被取代，直到所有的解码画面DI的数据均产生并储存完为止。
第一暂存区块114可通过上述解码画面DI逐步取代第一暂存区块114的储存内容的方式，让第一参考画面SF以及解码画面DI共享第一暂存区块114。然而，由于解码电路120进行解码时需要移动向量的信息，因此需要保留至少第一参考影像SF中符合最大移动向量搜寻的范围，以使解码画面DI在最后一部分的画面区块仍可参考第一参考影像SF而由解码电路120解码出。其中，最大移动向量搜寻的范围大小(亦即V的大小)可视需求决定。
当解码画面为长程参考画面时，解码电路120是边通过存储器控制器150读取第二暂存区块116中的第二参考画面LF，边通过存储器控制器150将所产生的解码画面DI的像 素储存至第二暂存区块116。第二暂存区块116的存取操作和前述第一暂存区块114的存取操作相同，在此不赘述。
请参照图3A至图3C。图3A至图3C分别为本发明一实施例中，第一暂存区块114的示意图。
如图3A所示，第一暂存区块114储存第一参考影像SF以及最大移动向量搜寻范围画面MF1。在解码刚开始进行时，解码电路120将从第一参考影像SF的起始位置开始读取，并在解码后自最大移动向量搜寻范围画面MF1的起始位置开始储存解码画面DI。
于一实施例中，对于第一参考影像SF的读取，可由下述的方式进行。首先，第一参考影像SF的起始位置相对第一暂存区块114的起始位置的地址偏移量，可由处理电路140纪录为参考画面起始地址偏移量Stoff。进一步地，处理电路140可通过控制信息撷取对应第一参考画面SF中，对应的参考画面区块RB的画面区块起始地址偏移量Mboff。
处理电路140进一步将画面区块起始地址偏移量Mboff与参考画面起始地址偏移量Stoff相加后，除以第一暂存区块114的大小(H×W+V×W)，以获得一个余数R1。更详细的说，余数R1＝(Mboff+Stoff)mod(H×W+V×W)。于本实施例中，由于第一参考影像SF储存的位置是连续的，画面区块起始地址偏移量Mboff与参考画面起始地址偏移量Stoff的相加结果不会超过第一暂存区块114的大小，此余数R1将与相加结果相同。
接着，处理电路140计算第一暂存区块114在存储器模块110的暂存区块起始地址IA加上余数后的读取起始地址(IA+R1)，并使解码电路120根据此读取起始地址读取所需的参考画面区块RB。
另一方面，对于解码画面DI的储存，可由下述的方式进行。首先，对于第N个解码画面DI，其起始位置相对第一暂存区块114的起始位置的地址偏移量，可由处理电路140纪录为解码画面起始地址偏移量Nfoff。而解码画面DI包含的解码画面区块相对解码画面DI起始位置的偏移量，可由处理电路140决定为解码画面区块起始地址偏移量MBoff。
处理电路140进一步将解码画面区块起始地址偏移量MBoff与解码画面起始地址偏移量Nfoff相加后，除以第一暂存区块114的大小，以获得一个余数R2。更详细的说，余数R2＝(MBoff+Nfoff)mod(H×W+V×W)。
于本实施例中，当解码画面DI尚未储存至超过最大移动向量搜寻范围画面MF1的大小时，解码画面区块起始地址偏移量MBoff与解码画面起始地址偏移量Nfoff的相加结果将不会超过第一暂存区块114的大小，此余数R2将与相加结果相同。
接着，处理电路140计算第一暂存区块114在存储器模块110的暂存区块起始地址 IA加上余数后的储存起始地址(IA+R2)，并使解码电路120根据此储存起始地址储存解码画面区块DB。
当解码画面DI储存至超过最大移动向量搜寻范围画面MF1的大小时，解码画面区块起始地址偏移量MBoff与解码画面起始地址偏移量Nfoff的相加结果将大于第一暂存区块114的大小，并使得相加结果在除以第一暂存区块114的大小后，商数将大于1。因此，通过取得余数R2，处理电路140可计算第一暂存区块114在存储器模块110的暂存区块起始地址IA加上余数后，真正的储存起始地址(IA+R2)，并使解码电路120根据此储存起始地址储存解码画面区块。
更详细的说，当解码画面DI储存至超过最大移动向量搜寻范围画面MF1的大小时，处理电路140将自第一暂存区块114的开头储存，以取代原本的第一参考画面SF。
因此，在依照上述的方式进行解码后，如图3B所示，所储存的第N个解码画面DI将作为新的第一参考画面SF，且在第一暂存区块114被分成两个部分。第一个部分时序较前，并相当于图3A中的最大移动向量搜寻范围画面MF1。第二个部分时序较后，在第一暂存区块114的地址却由于从起始地址储存而较第一个部分为前，并相当于图3A中第一参考画面SF的一部分。而图3A中的第一参考画面SF的另一部分，则成为新的最大移动向量搜寻范围画面MF1。
在进行第N+1个解码画面DI的解码时，将再次进行上述的过程。更详细的说，解码电路120将进行上述的地址计算，并从图3B中的第一参考影像SF的起始位置开始读取。在解码后进行上述的地址计算，并自图3B中的最大移动向量搜寻范围画面MF1的起始位置开始储存解码画面DI。
因此，在依照上述的方式进行解码后，如图3C所示，所储存的第N+1个解码画面DI将作为新的第一参考画面SF。而所剩下的部分第一参考画面SF，则成为新的最大移动向量搜寻范围画面MF1。
因此，本发明的影像解码装置100可通过上述依时序循环储存的机制，有效地使第一参考画面SF以及解码画面DI共享同一个暂存区块。实作上，第一暂存区块114的循环储存可通过循环式缓冲器(circular buffer)的方式达成，亦可通过设置存储器管理单元(memory management unit)来达成。
进一步地，在解码画面DI产生的同时，解码电路120可同步将解码画面DI传送到后处理电路130进行后处理，不须再另外储存解码画面DI供后处理电路130存取。因此，上述的本案机制将可达到节省存储器存取频宽的目的。
于一实施例中，解码电路120亦可先对所产生的解码画面DI进行压缩后，再储存压缩后的解码画面DI到第一暂存区块114。因此，第一暂存区块114的大小将可进一步降低，而更节省存储器的使用量。
需注意的是，上述的实施例中，均是通过配置以储存短程参考画面(第一参考画面SF)的第一暂存区块114为范例进行说明。然而，于另一实施例中，配置以储存长程参考画面(第二参考画面LF)的第二暂存区块116亦可具有上述的循环式缓冲器机制，以使作为长程参考画面的第二参考画面LF以及解码画面DI共享同一个暂存区块。
更详细的说，处理电路140可在读取控制信息后，判断当下进行解码产生的解码画面DI是要储存于对应于短程参考画面的第一暂存区块114或是对应于长程参考画面的第二暂存区块116，并通过前述的机制进行储存内容的取代。因此，关于第二暂存区块116的运作机制将不在此赘述。
再者，上述的实施例中，是以第一暂存区块114储存一张短程参考画面为范例进行说明。于其他实施例中，第一暂存区块114可储存多张短程参考画面，以使解码电路120根据多张短程参考画面进行解码。
此外，上述的实施例中，是以同时参考短程参考画面以及长程参考画面的解码机制进行说明。于其他实施例中，解码电路120亦可以仅参考短程参考画面的方式进行解码。
需注意的是，上述的实施方式仅为一范例。于其他实施例中，本领域的通常知识者当可在不违背本发明的精神下进行更动。
综合上述，本发明中的影像解码装置及方法可使影像解码所需的参考画面以及所产生的解码画面共享存储器模块中的暂存区块，有效降低存储器的使用量。
虽然本发明的实施例如上所述，然而该些实施例并非用来限定本发明，本技术领域的技术人员可依据本发明的明示或隐含的内容对本发明的技术特征施以变化，凡此种种变化均可能属于本发明所寻求的专利保护范畴，换言的，本发明的专利保护范围须视本说明书的申请专利范围所界定者为准。

Claims (20)

  1. 一种影像解码方法，其特征在于，包含：
    读取和解码一影像串流中的一控制信息；
    根据该控制信息读取该影像串流中的多个影像串流封包；
    至少根据该控制信息，使一解码电路选择性地自一存储器模块的一第一暂存区块读取一第一参考画面中的对应像素数据及/或一第二暂存区块读取一第二参考画面中的对应像素数据；
    根据所述影像串流封包，以及选择性地根据该第一参考画面中的对应像素数据及/或该第二参考画面中的对应像素数据进行解码，以产生一解码画面的像素数据；以及
    于进行解码时，将该解码画面的像素数据传送至一后处理电路，并根据该控制信息将该解码画面的像素数据储存至该第一暂存区块和该第二暂存区块的其中之一。
  2. 如权利要求1所述的影像解码方法，其特征在于，根据该控制信息将该解码画面的像素数据储存至该第一暂存区块和该第二暂存区块的其中之一的步骤更包含当该解码画面为短程参考画面时，将该解码画面的像素数据储存至该第一暂存区块。
  3. 如权利要求2所述的影像解码方法，其特征在于，将该解码画面的像素数据储存至该第一暂存区块步骤更包含将该解码画面的像素数据从该第一暂存区块中该第一参考画面往前最大移动向量搜寻范围位置开始储存。
  4. 如权利要求1所述的影像解码方法，其特征在于，根据该控制信息将该解码画面的像素数据储存至该第一暂存区块和该第二暂存区块的其中之一的步骤更包含压缩该解码画面的像素数据。
  5. 如权利要求1所述的影像解码方法，其特征在于，该第一暂存区块和该第二暂存区块位于同一动态随机存取存储器中。
  6. 一种影像解码装置，其特征在于，包含：
    一存储器模块；
    一解码电路；
    一后处理电路；以及
    一处理电路，电性耦接于该存储器模块、该解码电路以及该后处理电路，并配置以执行多个软固件可执行指令，以执行一影像解码方法，该影像解码方法包含：
    读取和解码一影像串流中的一控制信息；
    使该解码电路根据该控制信息读取该影像串流中的多个影像串流封包；
    使该解码电路至少根据该控制信息，使该解码电路选择性地自该存储器模块的一第一暂存区块读取一第一参考画面中的对应像素数据及/或一第二暂存区块读取一第二参考画面中的对应像素数据；
    使该解码电路根据所述影像串流封包，以及选择性地根据该第一参考画面中的对应像素数据及/或该第二参考画面中的对应像素数据进行解码，以产生一解码画面的像素数据；以及
    于进行解码时，使该解码电路将该解码画面的像素数据传送至一后处理电路，并根据该控制信息将该解码画面的像素数据储存至该第一暂存区块和该第二暂存区块的其中之一。
  7. 如权利要求6所述的影像解码装置，其特征在于，根据该控制信息将该解码画面的像素数据储存至该第一暂存区块和该第二暂存区块的其中之一的步骤更包含当该解码画面为短程参考画面时，将该解码画面的像素数据储存至该第一暂存区块。
  8. 如权利要求7所述的影像解码装置，其特征在于，将该解码画面的像素数据储存至该第一暂存区块步骤更包含将该解码画面的像素数据从该第一暂存区块中该第一参考画面往前最大移动向量搜寻范围位置开始储存。
  9. 如权利要求6所述的影像解码装置，其特征在于，根据该控制信息将该解码画面的像素数据储存至该第一暂存区块和该第二暂存区块的其中之一的步骤更包含压缩该解码画面的像素数据。
  10. 如权利要求6所述的影像解码装置，其特征在于，该第一暂存区块和该第二暂存区块位于同一动态随机存取存储器中。
  11. 一种影像解码方法，其特征在于，包含：
    读取和解码一影像串流中的一控制信息；
    根据该控制信息读取该影像串流中的多个影像串流封包；
    至少根据该控制信息，自一存储器模块的一第一暂存区块读取至少一第一参考画面中的对应像素数据，其中该第一暂存区块的一储存内容是依一顺序储存，且该储存内容包含顺序在前的一最大移动向量搜寻范围画面以及顺序在后的该第一参考画面；
    根据所述影像串流封包，以及根据至少该第一参考画面中的对应像素数据进行解码，以产生一解码画面的像素数据；以及
    于进行解码时，将该解码画面的像素数据传送至一后处理电路进行后处理，并根据该控制信息将该解码画面的像素数据储存至该第一暂存区块，以自该第一暂存区块中该顺序最前的该储存内容起始依序取代该储存内容。
  12. 如权利要求11所述的影像解码方法，其特征在于，该解码画面的像素数据依序取代原本的该最大移动向量搜寻范围画面以及一第一部分的该第一参考画面，以作为新的该第一参考画面，顺序较该第一部份后的一第二部分的该第一参考画面作为新的该最大移动向量搜寻范围画面。
  13. 如权利要求11所述的影像解码方法，其特征在于，读取该第一参考画面的步骤更包含：
    根据该控制信息，撷取对应该第一参考画面的一参考画面区块的一画面区块起始地址偏移量；
    将该画面区块起始地址偏移量与该第一参考画面的一参考画面起始地址偏移量相加后，除以该第一暂存区块的大小，以获得一余数；以及
    自该第一暂存区块在该存储器模块的一暂存区块起始地址加上该余数后的一读取起始地址读取该参考画面区块。
  14. 如权利要求11所述的影像解码方法，其特征在于，将该解码画面储存至该第一暂存区块的步骤更包含：
    决定对应该解码画面的一解码画面区块的一解码画面区块起始地址偏移量；
    将该解码画面区块起始地址偏移量与该解码画面的一解码画面起始地址偏移量相加后，除以该第一暂存区块的大小，以获得一余数；以及
    自该第一暂存区块在该存储器模块的一暂存区块起始地址加上该余数后的一储存起始地址储存该解码画面区块。
  15. 如权利要求11所述的影像解码方法，其特征在于，更包含：
    根据该控制信息，自该存储器模块的一第二暂存区块逐行读取至少一第二参考画面；
    根据所述影像串流封包以及根据该第一参考画面以及该第二参考画面进行解码，以产生该解码画面。
  16. 如权利要求15所述的影像解码方法，其特征在于，该第一参考画面为一短程参考画面以及一长程参考画面其中之一者，该第二参考画面为该短程参考画面以及该长程参考画面其中之另一者。
  17. 如权利要求11所述的影像解码方法，其特征在于，该最大移动向量搜寻范围画面的大小为一画面宽度与一最大搜寻行数的乘积。
  18. 如权利要求11所述的影像解码方法，其特征在于，更包含：
    将经过后处理的该解码画面的像素数据储存于该存储器模块的一显示暂存区块。
  19. 如权利要求11所述的影像解码方法，其特征在于，更包含：
    压缩该解码画面的像素数据，以将压缩后的该解码画面的像素数据储存至该第一暂存区块。
  20. 一种影像解码装置，其特征在于，包含：
    一存储器模块；
    一解码电路；
    一后处理电路；以及
    一处理电路，电性耦接于该存储器模块、该解码电路以及该后处理电路，并配置以执行多个软固件可执行指令，以执行一影像解码方法，该影像解码方法包含：
    读取一影像串流中的一控制信息；
    使该解码电路根据该控制信息读取该影像串流中的多个影像串流封包；
    使该解码电路至少根据该控制信息，自一存储器模块的一第一暂存区块读取至少一第一参考画面中的对应像素数据，其中该第一暂存区块的一储存内容是依一顺序储存，且该储存内容包含顺序在前的一最大移动向量搜寻范围画面以及顺序在后的该第一参考画面；
    使该解码电路根据所述影像串流封包，以及根据至少该第一参考画面中的对应像素数据进行解码，以产生一解码画面的像素数据；以及
    于进行解码的同时，将该解码画面的像素数据传送至一后处理电路进行后处理，并根据该控制信息将该解码画面的像素数据储存至该第一暂存区块，以自该第一暂存区块中该顺序最前的该储存内容起始依序取代该储存内容。
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