WO2020134722A1 - Flip-chip assembly, flip-chip packaging structure, and manufacturing method - Google Patents
Flip-chip assembly, flip-chip packaging structure, and manufacturing method Download PDFInfo
- Publication number
- WO2020134722A1 WO2020134722A1 PCT/CN2019/119478 CN2019119478W WO2020134722A1 WO 2020134722 A1 WO2020134722 A1 WO 2020134722A1 CN 2019119478 W CN2019119478 W CN 2019119478W WO 2020134722 A1 WO2020134722 A1 WO 2020134722A1
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- WIPO (PCT)
- Prior art keywords
- conductive
- solder
- chip
- flip chip
- pillar
- Prior art date
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 229910000679 solder Inorganic materials 0.000 claims abstract description 134
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 19
- 229910052802 copper Inorganic materials 0.000 claims description 19
- 239000010949 copper Substances 0.000 claims description 19
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 238000002360 preparation method Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 229910000570 Cupronickel Inorganic materials 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- YOCUPQPZWBBYIX-UHFFFAOYSA-N copper nickel Chemical compound [Ni].[Cu] YOCUPQPZWBBYIX-UHFFFAOYSA-N 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 13
- 230000006872 improvement Effects 0.000 description 8
- 230000008859 change Effects 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 5
- 238000005476 soldering Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000004660 morphological change Effects 0.000 description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
- 230000009466 transformation Effects 0.000 description 2
- 241000784732 Lycaena phlaeas Species 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000006740 morphological transformation Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000844 transformation Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
Abstract
Description
Claims (10)
- 一种倒装芯片组件,包括芯片、沿第一方向形成在所述芯片一侧表面的第一导电柱与第二导电柱,所述第二导电柱在垂直于第一方向的平面上的投影大于所述第一导电柱在垂直于第一方向的平面上的投影,所述第一导电柱背离所述芯片的一端设有第一焊料块,其特征在于:所述第二导电柱背离所述芯片的一端设置有若干相互间隔的第二焊料块,每一所述第二焊料块与第二导电柱之间均还设有的导电底座。A flip chip assembly includes a chip, a first conductive pillar and a second conductive pillar formed on one surface of the chip along a first direction, and a projection of the second conductive pillar on a plane perpendicular to the first direction Greater than the projection of the first conductive pillar on a plane perpendicular to the first direction, the first conductive pillar has a first solder bump at an end facing away from the chip, characterized in that the second conductive pillar faces away from A plurality of second solder blocks spaced apart from each other are provided at one end of the chip, and a conductive base is further provided between each second solder block and the second conductive post.
- 根据权利要求1所述的倒装芯片组件,其特征在于:所述第一焊料块与第二焊料块两者的规格一致。The flip chip assembly of claim 1, wherein the specifications of both the first solder bump and the second solder bump are the same.
- 根据权利要求1所述的倒装芯片组件,其特征在于:所述导电底座邻近第二焊料块的一端与所述第一导电柱背离所述芯片的一端相齐平且两者的端面结构一致。The flip chip assembly according to claim 1, wherein an end of the conductive base adjacent to the second solder block is flush with an end of the first conductive post facing away from the chip and the end surface structure of the two is consistent .
- 根据权利要求1所述的倒装芯片组件,其特征在于:同一所述第二导电柱上的相邻所述导电底座的间距一致,且使得同一所述第二导电柱上的第二焊料块亦呈等间距排布。The flip chip assembly according to claim 1, wherein the distance between adjacent conductive bases on the same second conductive post is the same, and the second solder bumps on the same second conductive post They are also arranged at equal intervals.
- 根据权利要求1所述的倒装芯片组件,其特征在于:所述倒装芯片组件还包括设置于所述第一导电柱与第一焊料块之间的基座,所述基座背离第一导电柱一侧的端面结构与所述导电底座背离第二导电柱一侧的端面结构相一致。The flip chip assembly of claim 1, wherein the flip chip assembly further comprises a base disposed between the first conductive pillar and the first solder bump, the base facing away from the first The end surface structure on the side of the conductive column is consistent with the end surface structure on the side of the conductive base facing away from the second conductive column.
- 根据权利要求1所述的倒装芯片组件,其特征在于:所述第一导电柱设置呈圆柱状;所述第二导电柱背离所述芯片的一端形成有条形的第二端面。The flip chip assembly according to claim 1, wherein the first conductive pillar is provided in a cylindrical shape; and the second conductive pillar has a strip-shaped second end surface at an end facing away from the chip.
- 根据权利要求6所述的倒装芯片组件,其特征在于:同一所述第二导电柱上的若干导电底座沿所述第二端面的长度方向呈线性间隔排布。The flip chip assembly according to claim 6, wherein a plurality of conductive bases on the same second conductive post are arranged at linear intervals along the length of the second end surface.
- 根据权利要求1所述的倒装芯片组件,其特征在于:所述第一导电柱、第二导电柱均设置为铜柱;所述导电底座由铜、镍或铜镍合金构成;所述第一焊料块与第二焊料块两者均设置由金属锡或锡合金制得。The flip chip assembly of claim 1, wherein the first conductive pillar and the second conductive pillar are both copper pillars; the conductive base is made of copper, nickel, or copper-nickel alloy; and the first Both the first solder block and the second solder block are made of metal tin or tin alloy.
- 一种倒装芯片封装结构,其特征在于:所述封装结构包括基片、如权利要求1-8任一项所述的倒装芯片组件以及绝缘层。A flip chip packaging structure, characterized in that the packaging structure includes a substrate, the flip chip assembly according to any one of claims 1-8 and an insulating layer.
- 一种倒装芯片组件的制备方法,其特征在于:A preparation method of flip chip assembly is characterized by:提供芯片,在芯片一侧表面制得第一导电柱与第二导电柱,所述第二导电柱在平行于所述芯片的平面上的投影大于所述第一导电柱在平行于所述芯片的平面上的投影;A chip is provided, and a first conductive post and a second conductive post are prepared on one side surface of the chip, the projection of the second conductive post on a plane parallel to the chip is greater than that of the first conductive post parallel to the chip Projection on the plane of在第一导电柱背离芯片的一端表面制备第一焊料块,在第二导电柱背离芯片的一端制得若干相互间隔分布的导电底座,并在所述导电底座上制备第二焊料块;A first solder block is prepared on the surface of the end of the first conductive post facing away from the chip, a plurality of conductive bases distributed at intervals are prepared on the end of the second conductive post facing away from the chip, and a second solder block is prepared on the conductive base;对第一焊料块、第二焊料块进行热处理,使得第一焊料块及第二焊料块由初始状态转变为成品状态。The first solder block and the second solder block are heat-treated so that the first solder block and the second solder block are changed from the initial state to the finished state.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811638810.4A CN111384017B (en) | 2018-12-29 | 2018-12-29 | Flip chip assembly, flip chip packaging structure and preparation method |
CN201811638810.4 | 2018-12-29 |
Publications (1)
Publication Number | Publication Date |
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WO2020134722A1 true WO2020134722A1 (en) | 2020-07-02 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/CN2019/119478 WO2020134722A1 (en) | 2018-12-29 | 2019-11-19 | Flip-chip assembly, flip-chip packaging structure, and manufacturing method |
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CN (1) | CN111384017B (en) |
WO (1) | WO2020134722A1 (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103180936A (en) * | 2010-10-12 | 2013-06-26 | 株式会社安川电机 | Electronic device and electronic component |
US20130334662A1 (en) * | 2012-06-14 | 2013-12-19 | Micrel, Inc. | Current Sensing Using a Metal-on-Passivation Layer on an Integrated Circuit Die |
US20180047691A1 (en) * | 2015-04-30 | 2018-02-15 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
CN108364920A (en) * | 2018-03-01 | 2018-08-03 | 颀中科技(苏州)有限公司 | Flip-chip assembly, flip chip packaging structure and preparation method |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN1317752C (en) * | 2004-08-30 | 2007-05-23 | 友达光电股份有限公司 | Method and structure for detecting anisotropic conductive rubber conductive particle deformation content |
CN1753176A (en) * | 2004-09-22 | 2006-03-29 | 日月光半导体制造股份有限公司 | Inversion packaging structure, semiconductor chip having convex block and its manufacturing method |
KR101130498B1 (en) * | 2010-04-27 | 2012-03-27 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device having bump |
JP6143104B2 (en) * | 2012-12-05 | 2017-06-07 | 株式会社村田製作所 | Bumped electronic component and method for manufacturing bumped electronic component |
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2018
- 2018-12-29 CN CN201811638810.4A patent/CN111384017B/en active Active
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2019
- 2019-11-19 WO PCT/CN2019/119478 patent/WO2020134722A1/en active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103180936A (en) * | 2010-10-12 | 2013-06-26 | 株式会社安川电机 | Electronic device and electronic component |
US20130334662A1 (en) * | 2012-06-14 | 2013-12-19 | Micrel, Inc. | Current Sensing Using a Metal-on-Passivation Layer on an Integrated Circuit Die |
US20180047691A1 (en) * | 2015-04-30 | 2018-02-15 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
CN108364920A (en) * | 2018-03-01 | 2018-08-03 | 颀中科技(苏州)有限公司 | Flip-chip assembly, flip chip packaging structure and preparation method |
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Publication number | Publication date |
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CN111384017B (en) | 2022-10-11 |
CN111384017A (en) | 2020-07-07 |
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