WO2020134722A1 - Flip-chip assembly, flip-chip packaging structure, and manufacturing method - Google Patents

Flip-chip assembly, flip-chip packaging structure, and manufacturing method Download PDF

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WO2020134722A1
WO2020134722A1 PCT/CN2019/119478 CN2019119478W WO2020134722A1 WO 2020134722 A1 WO2020134722 A1 WO 2020134722A1 CN 2019119478 W CN2019119478 W CN 2019119478W WO 2020134722 A1 WO2020134722 A1 WO 2020134722A1
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conductive
solder
chip
flip chip
pillar
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PCT/CN2019/119478
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French (fr)
Chinese (zh)
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梅嬿
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颀中科技(苏州)有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape

Abstract

Provided are a flip-chip assembly, a flip-chip packaging structure, and a manufacturing method. The flip-chip assembly comprises a chip, and a first conductive post and a second conductive post formed at a side surface of the chip along a first direction, wherein the second conductive post is larger than the first conductive post, a first solder bump is provided at one end of the first conductive post away from the chip, multiple mutually spaced-apart second solder bumps are provided at one end of the second conductive post away from the chip, and conductive bases are further provided between the second solder bumps and the second conductive post. The manufacturing method for the flip-chip assembly comprises: fabricating the multiple mutually spaced-apart conductive bases on the second conductive post, fabricating the corresponding second solder bumps on the conductive bases, and converting the first solder bump and the second solder bumps from an initial state to a finished state by means of a thermal treatment. The present invention adjusts solder structures on the second conductive post having a strip or elliptical shape and a large size, thereby improving product quality.

Description

倒装芯片组件、倒装芯片封装结构及制备方法Flip chip assembly, flip chip packaging structure and preparation method 技术领域Technical field
本发明涉及电子封装技术领域,尤其涉及一种倒装芯片组件、倒装芯片封装结构及制备方法。The invention relates to the technical field of electronic packaging, in particular to a flip chip assembly, a flip chip packaging structure and a preparation method.
背景技术Background technique
近些年,倒装芯片由于结构紧凑、性能高、引线短等优点得到业内越来越多的关注与重视,其能够更好地满足芯片封装结构小型化需求,提高芯片集成度,利于芯片数据处理能力的提升。倒装芯片现多采用铜柱凸块(Cu pillar)及设置在铜柱凸块顶部的一层焊料实现芯片与基板的连接,前述铜柱凸块的结构形态在焊连过程中基本保持不变,相较于传统的焊料凸块,具备更优越的导电性、导热性和结构可靠性。In recent years, due to the advantages of compact structure, high performance, short leads, etc., flip chip has received more and more attention and attention in the industry, which can better meet the needs of miniaturization of chip packaging structure, improve chip integration, and benefit chip data Improvement of processing power. Flip chips now mostly use copper pillar bumps (Cupillar) and a layer of solder placed on top of the copper pillar bumps to achieve the connection between the chip and the substrate. The structure of the aforementioned copper pillar bumps remains basically unchanged during the soldering process Compared with traditional solder bumps, it has superior electrical conductivity, thermal conductivity and structural reliability.
常见的铜柱凸块多设置呈圆形,但随着导电性、导热性及结构强度与应力需求的提升,现已公开在芯片10'表面制备具有不同长宽比的条形铜柱凸块20'(如图1所示)。前述条形铜柱凸块与传统的圆形铜柱凸块的生产及焊接工艺一致,采用回流焊将铜柱凸块顶端的焊料块熔融生成焊料帽时,条形铜柱凸块顶部的焊料帽与圆形铜柱凸块顶部的焊料帽的高度会出现差异,且不同形状的条形铜柱凸块顶部相应生成的焊料帽的高度也存在较大差异。这会导致倒装芯片表面不同铜柱凸块的高度共面性(coplanarity)较差,影响倒装芯片的封装。The common copper pillar bumps are mostly arranged in a round shape, but with the increase in electrical conductivity, thermal conductivity, structural strength and stress requirements, it has been disclosed to prepare strip copper pillar bumps with different aspect ratios on the surface of the chip 10' 20' (as shown in Figure 1). The aforementioned strip copper pillar bumps are consistent with the traditional round copper pillar bump production and soldering process. When reflow soldering is used to melt the solder bump on the top of the copper pillar bump to form a solder cap, the solder on the top of the strip copper pillar bump The height of the solder cap on the top of the cap and the round copper pillar bump will be different, and the height of the solder cap correspondingly generated on the top of the strip copper pillar bump of different shapes also has a large difference. This will result in poor coplanarity of the different copper pillar bumps on the flip chip surface, affecting the flip chip packaging.
申请人在CN108364920A中已公开一种新的倒装芯片组件,条形的第二导电柱顶端设置相互间隔的两个或多个焊料块,使得第二导电柱上的焊料块形成焊料帽时可与第一导电柱上的焊料帽高度趋于一致,提高芯片表面不同规格的导电柱在焊接、封装时的高度共面性。但据现场验证,第二导电柱上的焊料块熔融后较易沿第二导电柱端面铺展至相互粘连在一起,引起第二导电柱上的局部高度变化;而若将焊料块之间的间距设置过大,则难以满足芯片焊接强度及电性导通的性能需求。The applicant has disclosed a new flip chip assembly in CN108364920A. The strip-shaped second conductive post is provided with two or more solder bumps spaced from each other at the top so that the solder bump on the second conductive post can form a solder cap The height of the solder cap on the first conductive post tends to be consistent, which improves the height coplanarity of the conductive posts of different specifications on the chip surface during soldering and packaging. However, according to on-site verification, the solder bumps on the second conductive post are more likely to spread along the end surface of the second conductive post until they stick together, causing local height changes on the second conductive post; and if the spacing between the solder bumps If the setting is too large, it is difficult to meet the performance requirements of chip bonding strength and electrical conduction.
鉴于此,有必要提供一种新的倒装芯片组件、倒装芯片封装结构及制备方法。In view of this, it is necessary to provide a new flip chip assembly, flip chip packaging structure and preparation method.
发明内容Summary of the invention
本发明的目的在于提供一种倒装芯片组件、倒装芯片封装结构及制备方法,能够有效提 高芯片表面不同导电柱上焊料结构的高度共面性,提升产品质量。The purpose of the present invention is to provide a flip chip assembly, a flip chip packaging structure and a preparation method, which can effectively improve the highly coplanarity of the solder structures on different conductive posts on the chip surface and improve the product quality.
为实现上述发明目的,本发明提供了一种倒装芯片组件,包括芯片、沿第一方向形成在所述芯片一侧表面的第一导电柱与第二导电柱,所述第二导电柱在垂直于第一方向的平面上的投影大于所述第一导电柱在垂直于第一方向的平面上的投影,所述第一导电柱背离所述芯片的一端设有第一焊料块,其特征在于:所述第二导电柱背离所述芯片的一端设置有若干相互间隔的第二焊料块,每一所述第二焊料块与第二导电柱之间均还设有的导电底座。In order to achieve the above object of the invention, the present invention provides a flip chip assembly, including a chip, a first conductive pillar and a second conductive pillar formed on a surface of the chip along a first direction, the second conductive pillar The projection on the plane perpendicular to the first direction is greater than the projection of the first conductive pillar on the plane perpendicular to the first direction, and the end of the first conductive pillar facing away from the chip is provided with a first solder bump. The end of the second conductive column facing away from the chip is provided with a plurality of second solder blocks spaced apart from each other, and a conductive base is also provided between each second solder block and the second conductive column.
作为本发明的进一步改进,所述第一焊料块与第二焊料块两者的规格一致。As a further improvement of the present invention, the specifications of both the first solder bump and the second solder bump are the same.
作为本发明的进一步改进,所述导电底座邻近第二焊料块的一端与所述第一导电柱背离所述芯片的一端相齐平且两者的端面结构一致。As a further improvement of the present invention, an end of the conductive base adjacent to the second solder block is flush with an end of the first conductive pillar facing away from the chip and the end surface structure of the two is consistent.
作为本发明的进一步改进,同一所述第二导电柱上的相邻所述导电底座的间距一致,且使得同一所述第二导电柱上的第二焊料块亦呈等间距排布。As a further improvement of the present invention, the distance between adjacent conductive bases on the same second conductive post is consistent, and the second solder bumps on the same second conductive post are also arranged at equal intervals.
作为本发明的进一步改进,所述倒装芯片组件还包括设置于所述第一导电柱与第一焊料块之间的基座,所述基座背离第一导电柱一侧的端面结构与所述导电底座背离第二导电柱一侧的端面结构相一致。As a further improvement of the present invention, the flip chip assembly further includes a pedestal disposed between the first conductive pillar and the first solder bump, and the end structure and the side of the pedestal facing away from the first conductive pillar The structure of the end surface of the side of the conductive base facing away from the second conductive column is consistent.
作为本发明的进一步改进,所述第一导电柱设置呈圆柱状;所述第二导电柱背离所述芯片的一端形成有条形的第二端面。As a further improvement of the present invention, the first conductive pillar is arranged in a cylindrical shape; an end of the second conductive pillar facing away from the chip is formed with a strip-shaped second end surface.
作为本发明的进一步改进,同一所述第二导电柱上的若干导电底座沿所述第二端面的长度方向呈线性间隔排布。As a further improvement of the present invention, several conductive bases on the same second conductive post are arranged at linear intervals along the length direction of the second end surface.
作为本发明的进一步改进,所述第一导电柱、第二导电柱均设置为铜柱;所述导电底座由铜、镍或铜镍合金构成;所述第一焊料块与第二焊料块两者均设置由金属锡或锡合金制得。As a further improvement of the present invention, the first conductive pillar and the second conductive pillar are both configured as copper pillars; the conductive base is composed of copper, nickel or a copper-nickel alloy; the first solder block and the second solder block are both Both are made of metal tin or tin alloy.
本发明还提供一种倒装芯片封装结构,包括基片、如前所述的倒装芯片组件以及绝缘层。The invention also provides a flip chip packaging structure, including a substrate, the flip chip assembly as described above and an insulating layer.
本发明还提供一种倒装芯片组件的制备方法,主要包括:The invention also provides a method for preparing a flip chip assembly, which mainly includes:
提供芯片,在芯片一侧表面制得第一导电柱与第二导电柱,所述第二导电柱在平行于所述芯片的平面上的投影大于所述第一导电柱在平行于所述芯片的平面上的投影;A chip is provided, and a first conductive post and a second conductive post are prepared on one side surface of the chip, the projection of the second conductive post on a plane parallel to the chip is greater than that of the first conductive post parallel to the chip Projection on the plane of
在第一导电柱背离芯片的一端表面制备第一焊料块,在第二导电柱背离芯片的一端制得若干相互间隔分布的导电底座,并在所述导电底座上制备第二焊料块;A first solder block is prepared on the surface of the end of the first conductive post facing away from the chip, a plurality of conductive bases distributed at intervals are prepared on the end of the second conductive post facing away from the chip, and a second solder block is prepared on the conductive base;
对第一焊料块、第二焊料块进行热处理,使得第一焊料块及第二焊料块由初始状态转变为成品状态。The first solder block and the second solder block are heat-treated so that the first solder block and the second solder block are changed from the initial state to the finished state.
本发明的有益效果是:采用本发明倒装芯片组件通过在第二导电柱背离芯片的一端设置若干相互间隔的导电底座,再于导电底座上设置相应的第二焊料块,所述第二焊料块经热处理由初始状态转变为成品状态的过程中,其形态变化与第一焊料块的形态变化趋于一致,避免不同第二焊料块熔融状态下相互粘连,导致成品状态的第二焊料块高度差异。本发明倒装芯片组件能够真正提高芯片表面不同导电柱上焊料的高度共面性,提升产品良率。The beneficial effect of the present invention is that the flip chip assembly of the present invention is adopted by providing a plurality of mutually spaced conductive bases on the end of the second conductive column facing away from the chip, and then a corresponding second solder block is provided on the conductive base, the second solder During the heat treatment of the block to change from the initial state to the finished state, its morphological change tends to be consistent with that of the first solder block, to avoid adhesion of different second solder blocks to each other in the molten state, resulting in the height of the second solder block in the finished state difference. The flip chip assembly of the present invention can truly improve the high coplanarity of the solder on different conductive posts on the surface of the chip and improve the product yield.
附图说明BRIEF DESCRIPTION
图1是现有的一种倒装芯片组件的结构示意图;1 is a schematic structural diagram of a conventional flip chip assembly;
图2是本发明倒装芯片组件中第一焊料块与第二焊料块处于初始状态时的结构示意图;2 is a schematic structural view of the first solder bump and the second solder bump in the flip chip assembly of the present invention;
图3是图2中倒装芯片组件中第一焊料块与第二焊料块处于成品状态时的结构示意图;3 is a schematic structural diagram of the first solder bump and the second solder bump in the flip chip assembly in FIG. 2 in a finished state;
图4是本发明倒装芯片组件另一实施方式的结构示意图;4 is a schematic structural view of another embodiment of the flip chip assembly of the present invention;
图5是本发明倒装芯片封装结构的结构示意图;5 is a schematic structural view of the flip-chip packaging structure of the present invention;
图6是本发明倒装芯片组件的制备方法的主要流程示意图。6 is a schematic diagram of the main flow of the method for manufacturing a flip chip assembly of the present invention.
具体实施方式detailed description
以下将结合附图所示的实施方式对本发明进行详细描述。但该实施方式并不限制本发明,本领域的普通技术人员根据该实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。The present invention will be described in detail below with reference to the embodiments shown in the drawings. However, this embodiment does not limit the present invention, and structural, method, or functional transformations made by a person of ordinary skill in the art according to this embodiment are all included in the protection scope of the present invention.
参图2与图3所示,本发明提供的倒装芯片组件100包括芯片10、沿第一方向设置在所述芯片10一侧表面上的第一导电柱21与第二导电柱22。所述第二导电柱22在垂直于第一方向的平面上的投影大于所述第一导电柱21在垂直于第一方向的平面上的投影。所述第一导电柱21背离芯片10的一端设有第一焊料块31;所述第二导电柱22背离芯片10的一端设有若干相互间隔排布的第二焊料块32,且每一所述第二焊料块32与所述第二导电柱22之间均还设有相应的导电底座40。2 and 3, the flip chip assembly 100 provided by the present invention includes a chip 10, a first conductive post 21 and a second conductive post 22 disposed on a surface of the chip 10 along a first direction. The projection of the second conductive pillar 22 on the plane perpendicular to the first direction is greater than the projection of the first conductive pillar 21 on the plane perpendicular to the first direction. The end of the first conductive post 21 facing away from the chip 10 is provided with a first solder block 31; the end of the second conductive post 22 facing away from the chip 10 is provided with a plurality of second solder blocks 32 arranged at intervals from each other, and each A corresponding conductive base 40 is also provided between the second solder block 32 and the second conductive pillar 22.
优选地,所述第二导电柱22上的相邻所述导电底座40的间距一致,且使得同一所述第二导电柱22上的第二焊料块32亦呈等间距排布。本实施例中,所述第二导电柱22背离所 述芯片10的一端形成有条形的第二端面221,同一所述第二导电柱22上的若干导电底座40沿所述第二端面221的长度方向等间距间隔排布。Preferably, the distance between adjacent conductive bases 40 on the second conductive posts 22 is the same, and the second solder bumps 32 on the same second conductive posts 22 are also arranged at equal intervals. In this embodiment, an end of the second conductive pillar 22 facing away from the chip 10 is formed with a strip-shaped second end surface 221, and a plurality of conductive bases 40 on the same second conductive pillar 22 are along the second end surface 221 They are arranged at equal intervals in the length direction of.
所述第一导电柱21大致设置呈圆柱状且所述第一导电柱21背离所述芯片10的一端形成有圆形的第一端面211。此处,所述第一端面211相对所述芯片10表面的高度超过第二端面221相对所述芯片10表面的高度。所述导电底座40邻近第二焊料块32的一端与所述第一导电柱21的第一端面211相平齐,并且,所述导电底座40朝向所述第二焊料块32的端面与第一端面211结构一致。进一步地,所述导电底座40亦设置呈圆柱状且其直径与第一导电柱21的直径相当。The first conductive pillar 21 is substantially cylindrical, and an end of the first conductive pillar 21 facing away from the chip 10 is formed with a circular first end surface 211. Here, the height of the first end surface 211 relative to the surface of the chip 10 exceeds the height of the second end surface 221 relative to the surface of the chip 10. An end of the conductive base 40 adjacent to the second solder block 32 is flush with the first end surface 211 of the first conductive pillar 21, and the end surface of the conductive base 40 facing the second solder block 32 is parallel to the first The structure of the end surface 211 is consistent. Further, the conductive base 40 is also arranged in a cylindrical shape and its diameter is equivalent to the diameter of the first conductive pillar 21.
所述第一焊料块31与第二焊料块32两者的规格一致,其具有初始状态及成品状态,前述两者的规格一致也就是指所述第一焊料块31与第二焊料块32所采用的材料及初始状态都相同。所述初始状态对应于第一焊料块31形成于所述第一端面211、抑或第二焊料块32形成在相应导电底座40上的形态;所述成品状态则是第一焊料块31、第二焊料块32经热处理转变为“焊料帽”时的状态。在此,初始状态下的所述第一焊料块31、第二焊料块32两者的高度一致。且在初始状态下的第一焊料块31、第二焊料块32设置呈柱状,所述第一焊料块31沿其径向不超出所述第一导电柱21的第一端面211;所述第二焊料块32沿其径向则不超出其所对应导电底座40朝向该第二焊料块32的端面。The specifications of both the first solder block 31 and the second solder block 32 are the same, and they have an initial state and a finished state. The specifications of the aforementioned two are the same, which means that the first solder block 31 and the second solder block 32 are The materials used and the initial state are the same. The initial state corresponds to the form where the first solder block 31 is formed on the first end surface 211, or the second solder block 32 is formed on the corresponding conductive base 40; the finished state is the first solder block 31, the second The solder bump 32 is changed to the state when it is "solder cap" by heat treatment. Here, the heights of the first solder bump 31 and the second solder bump 32 in the initial state are the same. In the initial state, the first solder block 31 and the second solder block 32 are arranged in a column shape, and the first solder block 31 does not exceed the first end surface 211 of the first conductive pillar 21 in the radial direction; the first The second solder block 32 does not exceed the end surface of the corresponding conductive base 40 facing the second solder block 32 along its radial direction.
所述第一焊料块31、第二焊料块32也优选设置呈圆柱状且分别与所述第一导电柱21及导电底座40相对应。所述第一焊料块31、第二焊料块32在转变至成品状态的过程中,在重力、界面应力及熔融后的表面张力作用下,会出现形态变换。此处,通过前述导电底座40的设置,使得第二焊料块32与第一焊料块31两者的形态变换趋势能够更好地保持一致。除此,还需在第二焊料块32成型过程中确定初始状态下相邻第二焊料块32的间距W,所述间距W不能设计过小,其需保证相邻所述第二焊料块32在转变至成品状态时,不会出现互相粘连的状况;所述间距W亦不能设计过大,影响所述第二导电柱22电连接性能及结构强度。The first solder block 31 and the second solder block 32 are also preferably arranged in a cylindrical shape and respectively correspond to the first conductive pillar 21 and the conductive base 40. When the first solder bump 31 and the second solder bump 32 transition to the finished state, the morphological transformation will occur under the action of gravity, interface stress, and surface tension after melting. Here, the arrangement of the aforementioned conductive base 40 enables the second solder bump 32 and the first solder bump 31 to better maintain the same shape transformation tendency. In addition, the distance W between the adjacent second solder blocks 32 in the initial state needs to be determined during the forming process of the second solder blocks 32. The distance W cannot be designed to be too small, which needs to ensure that the adjacent second solder blocks 32 When transitioning to the finished state, there will be no sticking to each other; the distance W cannot be designed too large, which affects the electrical connection performance and structural strength of the second conductive pillar 22.
本发明不仅通过较大的第二导电柱22上设置相互间隔的两个或多个所述第二焊料块32,还通过所述导电底座40的设计,可使得第二焊料块32在热处理进程中,其形态变化的趋势 与第一焊料块31的变化趋势真正达成一致,有效消除第一焊料块31、第二焊料块32熔融变形后的高度差异。In the present invention, not only are two or more second solder blocks 32 spaced apart from each other on the larger second conductive pillar 22, but also through the design of the conductive base 40, the second solder block 32 can be used in the heat treatment process Among them, the morphological change trend is truly in agreement with the change trend of the first solder block 31, effectively eliminating the height difference between the first solder block 31 and the second solder block 32 after melt deformation.
一般地,所述第一导电柱21与第二导电柱22均设置为铜柱;所述第一焊料块31与第二焊料块32两者都采用金属锡或锡合金制得。所述导电底座40由铜、镍或铜镍合金构成,既需保证所述导电底座40与第二导电柱22及第二焊料块32的结合性能,还需确保该导电底座40具备良好的导电性及结构强度,而在满足上述条件下,所述导电底座40亦可采用其它导电材质制得。Generally, both the first conductive pillar 21 and the second conductive pillar 22 are configured as copper pillars; both the first solder block 31 and the second solder block 32 are made of metal tin or tin alloy. The conductive base 40 is made of copper, nickel, or copper-nickel alloy, not only to ensure the bonding performance of the conductive base 40 with the second conductive pillar 22 and the second solder block 32, but also to ensure that the conductive base 40 has good conductivity Performance and structural strength, and under the above conditions, the conductive base 40 can also be made of other conductive materials.
实际生产中,所述导电底座40可与第一导电柱21、第二导电柱22同步成型制得,换而言之,在所述第二导电柱22成型后,再于该第二导电柱22背离所述芯片10的端面上刻蚀形成间隔排布的前述导电底座40。此方法亦可有效确保所述导电底座40朝向第二焊料块32一侧的端面与第一导电柱21的第一端面211相平齐,且保持两者表面结构一致。In actual production, the conductive base 40 can be formed in synchronization with the first conductive post 21 and the second conductive post 22, in other words, after the second conductive post 22 is formed, the second conductive post 22 The foregoing conductive bases 40 are etched at intervals on the end surface facing away from the chip 10. This method can also effectively ensure that the end surface of the conductive base 40 facing the second solder block 32 is flush with the first end surface 211 of the first conductive pillar 21, and the surface structure of the two is kept the same.
参图4所示为本发明另一实施方式,其区别于前述实施例的特征在于:所述倒装芯片组件100还包括设置于所述第一导电柱21与第一焊料块31之间的基座50,所述基座50背离所述第一导电柱21一侧的端面结构与所述导电底座40背离第二导电柱22一侧的端面结构相一致。4 shows another embodiment of the present invention, which is different from the foregoing embodiment in that the flip chip assembly 100 further includes a first conductive post 21 and a first solder block 31 disposed between The base 50 has an end surface structure on the side facing away from the first conductive pillar 21 and the end surface structure on the side facing away from the second conductive pillar 22 of the conductive base 40.
优选地,所述基座50也由铜、镍或铜镍合金构成,以保证所述基座50与第一导电柱21、第一焊料块31的结合性能,还需确保该基座50具备良好的导电性及结构强度。在满足上述条件的情况下,所述基座50亦可采用其它导电材质制得。Preferably, the base 50 is also composed of copper, nickel or a copper-nickel alloy to ensure the bonding performance of the base 50 with the first conductive pillar 21 and the first solder bump 31, and it is also necessary to ensure that the base 50 has Good conductivity and structural strength. When the above conditions are satisfied, the base 50 may also be made of other conductive materials.
上述实施例中,所述第一焊料块31与第二焊料块32的规格尺寸、相邻所述第二焊料块32之间的间距均设置为一致,是为最大程度确保第一焊料块31与第二焊料块32熔融变形后能达成最佳的高度共面效果。此一点不应理解为本发明的应用限制,在发明的其它实施方式中,所述第二导电柱22上第二焊料块32、导电底座40的规格间距设计可根据实际需求进行合理排布设置,使得第二焊料块32在转变为成品状态时的高度变化保持均匀,且与第一焊料块31的高度变化尽量保持一致。In the above embodiment, the specifications of the first solder block 31 and the second solder block 32 and the spacing between the adjacent second solder blocks 32 are all set to be the same, which is to ensure the first solder block 31 to the greatest extent After melting and deforming with the second solder block 32, an optimal highly coplanar effect can be achieved. This point should not be construed as a limitation of the application of the present invention. In other embodiments of the invention, the design of the spacing between the second solder bump 32 on the second conductive pillar 22 and the conductive base 40 can be arranged reasonably according to actual needs , So that the height change of the second solder block 32 when it is converted into the finished state remains uniform, and is as consistent as possible with the height change of the first solder block 31.
如图5所示,本发明还提供一种倒装芯片封装结构200,包括基片201、绝缘层202及如前所述的倒装芯片组件100。所述第一导电柱21、第二导电柱22以及第一焊料块31、第 二焊料块32用以实现所述基片201与芯片100之间的电性连接,所述绝缘层202起着固化支撑的作用,并用以隔绝外部空气、水分的侵蚀。As shown in FIG. 5, the present invention also provides a flip chip package structure 200, which includes a substrate 201, an insulating layer 202, and the flip chip assembly 100 as described above. The first conductive pillar 21, the second conductive pillar 22 and the first solder block 31 and the second solder block 32 are used to realize the electrical connection between the substrate 201 and the chip 100, and the insulating layer 202 plays a role It solidifies and supports, and is used to isolate outside air and moisture from erosion.
如图6所示,本发明还提供一种如前所述的倒装芯片组件100的制备方法,主要包括:As shown in FIG. 6, the present invention also provides a method for manufacturing the flip chip assembly 100 as described above, which mainly includes:
S1、提供芯片10,在芯片10一侧表面沿第一方向制得第一导电柱21与第二导电柱22,所述第一导电柱21与第二导电柱22均与所述芯片10相垂直,所述第二导电柱22在垂直于第一方向的平面上的投影大于所述第一导电柱21在垂直于第一方向的平面上的投影;S1. A chip 10 is provided, and a first conductive pillar 21 and a second conductive pillar 22 are prepared along a first direction on one side surface of the chip 10, and both the first conductive pillar 21 and the second conductive pillar 22 are in phase with the chip 10 Vertical, the projection of the second conductive pillar 22 on the plane perpendicular to the first direction is greater than the projection of the first conductive pillar 21 on the plane perpendicular to the first direction;
S2、在第一导电柱21背离芯片10的一端表面制备第一焊料块31,在第二导电柱22背离芯片10的一端制备若干相互间隔的导电底座40,再于导电底座40上制备相应的第二焊料块32;S2. Prepare the first solder bump 31 on the surface of the end of the first conductive pillar 21 facing away from the chip 10, and prepare a plurality of mutually spaced conductive bases 40 on the end of the second conductive pillar 22 facing away from the chip 10, and then prepare corresponding corresponding bases on the conductive base 40 The second solder block 32;
S3、对第一焊料块31、第二焊料块32进行热处理,使得第一焊料块31及第二焊料块32由初始状态转变为成品状态。S3. Perform heat treatment on the first solder block 31 and the second solder block 32, so that the first solder block 31 and the second solder block 32 change from the initial state to the finished state.
在本发明的其它实施方式中,S2步骤还包括在所述第一导电柱21的第一端面211上制备基座50,再于该基座50背离第一导电柱21的一侧制备第一焊料块31。In other embodiments of the present invention, step S2 further includes preparing a base 50 on the first end surface 211 of the first conductive pillar 21, and then preparing a first on the side of the base 50 facing away from the first conductive pillar 21 Solder block 31.
具体地,先在芯片10一侧表面的既定区域溅镀形成金属化层,再通过曝光、电镀工艺在金属化层上制得第一导电柱21与第二导电柱22,所述第一导电柱21与第二导电柱22设置为铜柱;再次通过曝光、电镀工艺在第二导电柱22的第二端面221上定位生长得到若干相互间隔的导电底座40,前述基座50亦可与所述导电底座40同时制备;接着,再通过电镀等方法制备第一焊料块31与第二焊料块32。最后,上述热处理工艺具体采用回流焊使得所述第一焊料块31与第二焊料块32熔融变形呈帽状,同时,增强所述第一焊料块31、第二焊料块32熔与所述第一导电柱21、第二导电柱22的结合强度。Specifically, a metallization layer is formed by sputtering on a predetermined area on one side surface of the chip 10, and then a first conductive pillar 21 and a second conductive pillar 22 are formed on the metallization layer through exposure and plating processes. The first conductive The pillar 21 and the second conductive pillar 22 are configured as copper pillars; again, positioning and growing on the second end surface 221 of the second conductive pillar 22 through exposure and electroplating processes to obtain a plurality of conductive bases 40 spaced apart from each other. The conductive base 40 is prepared simultaneously; then, the first solder block 31 and the second solder block 32 are prepared by electroplating or the like. Finally, the above heat treatment process specifically uses reflow soldering to melt and deform the first solder block 31 and the second solder block 32 into a hat shape, and at the same time, strengthen the fusion of the first solder block 31 and the second solder block 32 with the first The bonding strength of a conductive pillar 21 and a second conductive pillar 22.
综上所述,本发明倒装芯片组件100及倒装芯片封装结构200通过在第二导电柱22背离芯片10的一端设置相互间隔的导电底座40及相应的第二焊料块32,使得所述第一焊料块31、第二焊料块32受热熔融时高度变化能够更好地趋于一致,且避免第二导电柱22上不同第二焊料块32出现高度变化差异,提高产品不同导电柱的高度共面性,进而提升产品良率,增强产品竞争力。同时,采用本发明制备方法得到的倒装芯片组件100还能有效的保证第一焊料块31、第二焊料块32熔与所述第一导电柱21、第二导电柱22的结合强度,避 免意外剥离。In summary, the flip-chip assembly 100 and the flip-chip packaging structure 200 of the present invention are provided with a conductive base 40 and a corresponding second solder block 32 at the end of the second conductive pillar 22 facing away from the chip 10, so that the When the first solder block 31 and the second solder block 32 are heated and melted, the height change can better converge, and the difference in height change of different second solder blocks 32 on the second conductive pillar 22 is avoided, and the height of the different conductive pillars of the product is increased. Coplanarity, thereby improving product yield and enhancing product competitiveness. At the same time, the flip chip assembly 100 obtained by the preparation method of the present invention can also effectively guarantee the bonding strength of the fusion of the first solder block 31 and the second solder block 32 to the first conductive pillar 21 and the second conductive pillar 22, to avoid Accidentally peeled off.
应当理解,虽然本说明书按照实施方式加以描述,但并非每个实施方式仅包含一个独立的技术方案,说明书的这种叙述方式仅仅是为清楚起见,本领域技术人员应当将说明书作为一个整体,各实施方式中的技术方案也可以经适当组合,形成本领域技术人员可以理解的其他实施方式。It should be understood that although this specification is described according to embodiments, not every embodiment includes only an independent technical solution. This description of the specification is for clarity only, and those skilled in the art should treat the specification as a whole, each The technical solutions in the embodiments may also be combined appropriately to form other embodiments that can be understood by those skilled in the art.
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明,它们并非用以限制本发明的保护范围,凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。The series of detailed descriptions listed above are only specific descriptions of feasible embodiments of the present invention, they are not intended to limit the scope of protection of the present invention, and equivalent embodiments or technical equivalents made without departing from the technical spirit of the present invention Changes should be included in the protection scope of the present invention.

Claims (10)

  1. 一种倒装芯片组件,包括芯片、沿第一方向形成在所述芯片一侧表面的第一导电柱与第二导电柱,所述第二导电柱在垂直于第一方向的平面上的投影大于所述第一导电柱在垂直于第一方向的平面上的投影,所述第一导电柱背离所述芯片的一端设有第一焊料块,其特征在于:所述第二导电柱背离所述芯片的一端设置有若干相互间隔的第二焊料块,每一所述第二焊料块与第二导电柱之间均还设有的导电底座。A flip chip assembly includes a chip, a first conductive pillar and a second conductive pillar formed on one surface of the chip along a first direction, and a projection of the second conductive pillar on a plane perpendicular to the first direction Greater than the projection of the first conductive pillar on a plane perpendicular to the first direction, the first conductive pillar has a first solder bump at an end facing away from the chip, characterized in that the second conductive pillar faces away from A plurality of second solder blocks spaced apart from each other are provided at one end of the chip, and a conductive base is further provided between each second solder block and the second conductive post.
  2. 根据权利要求1所述的倒装芯片组件,其特征在于:所述第一焊料块与第二焊料块两者的规格一致。The flip chip assembly of claim 1, wherein the specifications of both the first solder bump and the second solder bump are the same.
  3. 根据权利要求1所述的倒装芯片组件,其特征在于:所述导电底座邻近第二焊料块的一端与所述第一导电柱背离所述芯片的一端相齐平且两者的端面结构一致。The flip chip assembly according to claim 1, wherein an end of the conductive base adjacent to the second solder block is flush with an end of the first conductive post facing away from the chip and the end surface structure of the two is consistent .
  4. 根据权利要求1所述的倒装芯片组件,其特征在于:同一所述第二导电柱上的相邻所述导电底座的间距一致,且使得同一所述第二导电柱上的第二焊料块亦呈等间距排布。The flip chip assembly according to claim 1, wherein the distance between adjacent conductive bases on the same second conductive post is the same, and the second solder bumps on the same second conductive post They are also arranged at equal intervals.
  5. 根据权利要求1所述的倒装芯片组件,其特征在于:所述倒装芯片组件还包括设置于所述第一导电柱与第一焊料块之间的基座,所述基座背离第一导电柱一侧的端面结构与所述导电底座背离第二导电柱一侧的端面结构相一致。The flip chip assembly of claim 1, wherein the flip chip assembly further comprises a base disposed between the first conductive pillar and the first solder bump, the base facing away from the first The end surface structure on the side of the conductive column is consistent with the end surface structure on the side of the conductive base facing away from the second conductive column.
  6. 根据权利要求1所述的倒装芯片组件,其特征在于:所述第一导电柱设置呈圆柱状;所述第二导电柱背离所述芯片的一端形成有条形的第二端面。The flip chip assembly according to claim 1, wherein the first conductive pillar is provided in a cylindrical shape; and the second conductive pillar has a strip-shaped second end surface at an end facing away from the chip.
  7. 根据权利要求6所述的倒装芯片组件,其特征在于:同一所述第二导电柱上的若干导电底座沿所述第二端面的长度方向呈线性间隔排布。The flip chip assembly according to claim 6, wherein a plurality of conductive bases on the same second conductive post are arranged at linear intervals along the length of the second end surface.
  8. 根据权利要求1所述的倒装芯片组件,其特征在于:所述第一导电柱、第二导电柱均设置为铜柱;所述导电底座由铜、镍或铜镍合金构成;所述第一焊料块与第二焊料块两者均设置由金属锡或锡合金制得。The flip chip assembly of claim 1, wherein the first conductive pillar and the second conductive pillar are both copper pillars; the conductive base is made of copper, nickel, or copper-nickel alloy; and the first Both the first solder block and the second solder block are made of metal tin or tin alloy.
  9. 一种倒装芯片封装结构,其特征在于:所述封装结构包括基片、如权利要求1-8任一项所述的倒装芯片组件以及绝缘层。A flip chip packaging structure, characterized in that the packaging structure includes a substrate, the flip chip assembly according to any one of claims 1-8 and an insulating layer.
  10. 一种倒装芯片组件的制备方法,其特征在于:A preparation method of flip chip assembly is characterized by:
    提供芯片,在芯片一侧表面制得第一导电柱与第二导电柱,所述第二导电柱在平行于所述芯片的平面上的投影大于所述第一导电柱在平行于所述芯片的平面上的投影;A chip is provided, and a first conductive post and a second conductive post are prepared on one side surface of the chip, the projection of the second conductive post on a plane parallel to the chip is greater than that of the first conductive post parallel to the chip Projection on the plane of
    在第一导电柱背离芯片的一端表面制备第一焊料块,在第二导电柱背离芯片的一端制得若干相互间隔分布的导电底座,并在所述导电底座上制备第二焊料块;A first solder block is prepared on the surface of the end of the first conductive post facing away from the chip, a plurality of conductive bases distributed at intervals are prepared on the end of the second conductive post facing away from the chip, and a second solder block is prepared on the conductive base;
    对第一焊料块、第二焊料块进行热处理,使得第一焊料块及第二焊料块由初始状态转变为成品状态。The first solder block and the second solder block are heat-treated so that the first solder block and the second solder block are changed from the initial state to the finished state.
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