TW516199B - Chip scale package structure and the fabrication method thereof - Google Patents

Abstract

The present invention provides a chip scale package structure and the fabrication method thereof, wherein the lead frame is utilized for signal transmission to make the size after being packaged equal to the chip dimension. According to the technology of the present invention, the flip-chip process is applied to replace the well-known wire-bonding process for internal signal transmission, which not only can reduce the telecommunication impedance, but also can obtain a different structure of lead frame. At the same time, using lead frame as the medium to combine with the external substrate, the packaging cost can be greatly reduced due to the low cost of lead frame, and the lead frame can also be used in a high-frequency IC package to provide high additive value.

Description

516199 V. Description of the invention (1) [Scope of the invention] The present invention relates to a wafer-scale structure and a manufacturing method thereof, and particularly relates to a wafer scale in which a conventional flip-chip bonding process is replaced by a flip-chip process. Constructed structure and manufacturing method thereof. [Background of the Invention] In the current semiconductor element manufacturing technology, most of the semiconductor elements are obtained by increasing the circuit density of the semiconductor element or reducing the size of the element to obtain a high-density semiconductor element. As a result, the requirements for the reliability of Packaging, Interconnecting, and Interconnecting technology have become increasingly stringent. The traditional packaging technology is to fix the die to a paste that has been coated with paste. ) On the die pad, the interconnect pins are distributed around the die, and the wire 利用 on the chip is connected by Wi ire-Β nding, and then The epoxy encapsulates the entire lead frame. However, in recent years, with the development of semiconductor device manufacturing technology, the memory IC has a tendency to increase, but the size of the entire semiconductor package has not increased but decreased. In order to solve this problem, it is known that a “lead on chip (LOC)” structure of a lead frame that is mounted on a wafer and packaged is produced. A cross-sectional view of a traditional LOC structure is as follows: As shown in "Figure 1", this L0C structure has: a lead frame is attached to the semiconductor wafer 50, and a plurality of bonding pads are provided on the upper surface of the semiconductor wafer 50; an insulating patch 5 2 is formed on the semiconductor The two sides of the upper surface of the wafer 50; the plurality of inner pins 53 are each extended so that one end thereof is located on the surface of the semiconductor wafer 50, wherein

516199 V. Description of the invention (2) Each inner pin is an outer pin 5 6 5 6 Electrically connected to the conductor chip 5 0 Next, first, 5 3 is extended to form a plurality of surfaces to form a '' reuse of wire gas to connect to the soldered conductor chip At 50 o'clock, the lead frame agent is filled into the mold body, and then the LOC is assembled. However, the transmission of the ^ number " Lu transmission. Therefore, the higher transmission (F 1 1 ρ-chi ρ instead of the above-mentioned gold and metal are each external, the insulation instructions are prepared with an external lead insulation and attach method ( W pad 5 5, repair wire 5 is applied in the cavity outside the insulation. 4 Electrically extended from other element patch 52. There is a cloth 52 with a plurality of legs 56 above. A metal bump contact ond ng Pa is gas-connected to Corresponding solder pads 55; corresponding inner leads 53 and outer lead pieces; and a package body 5 7 surrounding the half and inner leads 53. Manufacturing method of the L0C structure of the structure. Pin 53 and the lead frame corresponding to each inner pin respectively, and then the semiconductor wafer 50 (cutting the wafer from the wafer is cut) on the semiconductor wafer) The inner pin 53 is electrically connected with a metal wire 54 and then made of epoxy resin. The predetermined part including the mold packing half and the inner pin 5 3 is ^ out of the mold, and then the epoxy resin is molded to mold the predetermined part into a package. Then the molding step is performed, and the obtained The single-column type L0C type is constructed by using a wire combination as its internal "" The transmission resistance value is too large to be suitable for high-frequency electricity. In recent years, a dense, telecommunication frequency packaging technology has been developed. This packaging technology is called flip-chip bonding technology # Bonding. This technology is Metal bumps (G ο 1 d Wire) are used to make contacts on the surface of the semiconductor die, and then the aluminum pads (A 1 · d) of the wafer and the substrate circuit are formed by the metal bumps. Join to complete the assembly, but after using the above 〇; knot knot cloth 52 feet 5 6 extension, such as making scissors, and

516199 V. Description of the invention (3) · There is a limiting factor in flip-chip bonding technology, that is, fine pitch (Fine P ith) pads (B ο nding P ads) must be manufactured during the bonding process, for example, in In the manufacture of high-density memory devices, a plurality of solder pads regularly arranged along the peripheral periphery (Periphera 1) of the aforementioned device, the spacing is less than 1 0 0 // m, and in such a small space, solder Bonding the bump (S ο 1 der Bump) to the substrate is a difficult and expensive task. In addition, the flip-chip bonding technology has several disadvantages, such as the addition of flux (F 1 u X) during the assembly process. Therefore, a step of cleaning the wafer is needed, but because the gap between the wafer and the substrate is small, it is not convenient to perform cleaning in such a small gap. At the same time, in order to increase the reliability, a gap filling and glue will be performed. (Under fi 1 1) process, that is, using a dispenser to inject the glue at the edge of the wafer, so that the glue is filled into the gap by capillary action, because the filling speed of the glue is very slow, and Dispensing program is difficult to control, and therefore it takes much time; and to cope with the above-described element having a fine pitch I / 0's, the cost of a high-density substrate and so too expensive to make. [Objective and Summary of the Invention] 'Therefore, the main object of the present invention is to provide a flip chip process instead of the conventional gold wire bonding process under the premise that the lead frame is used as a medium to be combined with the outer substrate. Wafer-scale construction of internal signal transmission and manufacturing method thereof. Another object of the present invention is to provide a method for manufacturing a wafer scale structure, which includes using metal bumps as a signal transmission inside the wafer to reduce telecommunication impedance. Another object of the present invention is to provide a low-cost wafer size structure.

516199 V. Description of the invention (4) The mounting technology is cheaper than the wire frame of the present invention, which includes the lead frame structure of the present invention, which is convenient for users. The invention includes a plurality of wire shapes. In order to achieve the above, at least one sheet is included, each of which has two power areas extending outward from the two ends of the metal projection; the conductor chip is provided with a conductive contact point for the convenience of the user. When the frame is low, another purpose can be achieved in a plurality of metals. The other purpose is that this wire is based on its needs and the other purpose is different from the conventional point. The purpose of the construction cost. To provide a wafer-sized structured structural bump as a transmission medium for internal signals. To provide a wafer-sized structured frame structure with a connection area and a dual power area to selectively overlap. Provide a lead frame structure with a wafer-sized structure 'this lead frame has ps), this lead point can be polygonal or round to this * a wafer top surface is formed with a complex metal block ejection half and a metal guide Depending on the size of the contact point, the top end of the hairpin is combined with the conductor crystal package to meet the requirements of the bump and the wire frame. It was revealed that there are multiple metal bumps in the shape of a semiconductor chip with a complex structure formed by a shape of a chip, a body, and a covered wire. The structure can be arbitrarily structured to the size of the exposed wafer. / 0 pads; electrical connection, and its structure has a surrounding semiconductor chip and; a wire when the lead frame connection area and the half-connected area and dual power area, can have multiple connections, and its lead frame polygon Or round. It is based on the following manufacturing method and includes the following steps: providing a conductor chip;

Page 7 516199 V. Description of the invention (5) The method of combining the top of the bump with a lead frame, so that the metal bump forms an electrical connection with the lead frame, wherein the structure of the lead frame has a connection area and a double power area; And molding a predetermined portion including a semiconductor wafer and a lead frame to form a package body. Before forming a metal bump, an I / O redistribution process can be used to extend the I / O pads from the periphery of the semiconductor wafer or the center of the semiconductor wafer to the I / 0 pads arranged in a surface matrix, increasing I / O pads. 0 pad spacing and improve manufacturing yield. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: [Simplified description of the drawings] Figure 1, A cross-sectional view of the LOC assembly; Figure 2 is a schematic diagram of the structure of the wafer size of the creation; Figure 3 is a plan view of the lead frame structure of "Picture 2"; Figure 4 is the wafer size of the creation It is not intended to construct the structure of another embodiment, FIG. 5 is a schematic diagram of the structure of the three-dimensional 3D structure chip size of this creation; and FIG. 6 is another diagram of the three-dimensional 3D structure chip size of this creation. For the embodiment, the structure is not intended. [Explanation of the Embodiment] In the present invention, a technology for introducing a flip chip into a lead frame is disclosed. According to the disclosed technology, the lead frame is used as a chip and an external base.

Page 8 516199 V. Description of the invention (6) Board-bonded media, and metal bumps are formed on semiconductor wafers using flip-chip processes, and metal bumps are used as media for the electrical connection between the wafer and the lead frame. The lead frame is used as a way of mounting the wafer and the external substrate, which can solve the problems of cleaning and filling operations. Because the lead frame mounting method is already a well-known technology in the industry, its process equipment is the same as that of the existing assembly plant, and it does not need to be added. At the same time, because the lead frame used is cheaper than the substrate, it can reduce the construction cost, and the flip-chip process as an internal signal transmission can reduce the telecommunication impedance and can be used as a higher frequency IC assembly 〇At the same time, the present invention discloses a lead frame structure different from the conventional one. The lead frame has a ground area and a dual power area. It can facilitate users to arbitrarily connect to different power according to their needs. Area, and the structure of the above-mentioned crystal square size structure further forms a three-dimensional 3D structure arrangement to reduce module space and increase density. The production method, structure, and details of the wafer size configuration mentioned above are detailed as follows: First, please refer to "Figure 2", which is a cross-sectional view of the wafer size configuration of the present invention. The structure includes: a semiconductor wafer (such as a silicon wafer) 60, a plurality of metal bumps 61 formed on the surface of the semiconductor wafer 60, a lead frame 63 combined with the top end 62 of the metal bump 61, and a package body 64, wherein both ends of the aforementioned lead frame 63 are accompanied by the package body 64. First, a manufacturing method for forming the above structure is described. First, a semiconductor wafer 60 having a metal bump 61 is formed.

Page 9 516199 V. Description of the invention (7) The invention does not specifically limit which bump 6 1 is used, and the user can use it as required, or any material (such as metal metal bump 6 1), and used at the same time In the I / 0 redistribution process, the I / 0 pads can be extended to the area of the matrix-area array (Metal Trace) to extend the center of the I-plane to the area-matrix arrangement, thereby improving the manufacturing quality. Of course, if you use a wafer, you do not need to carry out the above-mentioned seeding method or use any kind of alloy or its forming metal from the wafer periphery. Its up to 0 pads can be added by the welding process. What material method? (It has a long period of time between the metal bumps and the wafer. It must be directly fed to form a metal such as a long bump alloy.) Before being made, a piece of gold is used to extend the center of the wafer or the wafer. The following steps are followed by preparing corresponding lead frames with metal bumps, and mounting the semiconductor wafer 60 in the lead frame to combine them, and then soldering each metal bump 6 1 on the semiconductor wafer 60. Of the top 6 2 and It is welded with the lead frame 6 3 so that the solder ball 61 and the lead frame 63 are electrically connected, wherein both ends of the lead frame 63 are extended beyond the semiconductor wafer 60, and then the semiconductor wafer 60 is cleaned. The gap with the lead frame 63, in which the lead frame 63 has multiple holes, which allows the cleaning solvent to pass through without the presence of cleaning dead corners. Finally, the molding includes semiconductor wafers 60, metal bumps 61, and wires. A predetermined part including the frame 63 is formed to form a package body. The molding method is similar to the method of "Figure 1". The lead frame on which the aforementioned semiconductor wafer 60 is loaded is placed in a mold, and then the mold is directly placed. The packaging material (such as epoxy resin) is filled into the cavity of the mold to form a package body 6 4; wherein, during the molding process, the packaging material is directly poured into the mold, and its filling speed is faster.

Page 10 516199 V. Description of the invention (8) and only one step is needed, and at the same time, the invention does not need to perform the rubber filling (U n d e r f i 1 1) process, which can save a lot of time. Among them, the structure of the lead frame in "Figure 2" is as shown in "Figure 3". The structure of the lead frame 64 according to the present invention uses the previously mentioned I / 0 redistribution process to make the I on the crystal plane. / 0 pads 6 5 are arranged in a surface matrix to increase the spacing between welding points to improve manufacturing yield. At the same time, the lead frame 6 3 structure has a connection area 6 6 and a dual power area 6 7, which is convenient for users. It can be arbitrarily overlapped according to its needs, and its lead frame 63 has a plurality of lead points (Lead Tips) 6 8. The shape of the lead points 6 8 can be a polygon or a circle. In the above structure, the appearance of the lead frame 63 can be appropriately changed according to the needs of the user. For example, if the user wants to form a three-dimensional 3D structure arrangement to reduce the space of the mold resistance and increase the density, the "second The shape of the lead frame 63 in the figure is changed to the shape shown in "Figure 4." At this time, as long as the bottom of the package body 6 4 is coated with a bonding substance 70 to fix the 3 D stack, then each lead frame The welding material 6 9 is applied to the corresponding place of 6 3, which can be used as a joint to form a three-dimensional 3D structure arrangement. The structure diagram is shown in "Figure 5", where the three-dimensional 3D structure arrangement is The lead frame 6 3 and the lead frame 6 3 are combined with each other, and the joints will not generate stress, unlike the conventional flip chip structure, which will cause stress concentration due to the difference between the substrate and the CTE of the wafer; At this time, instead of using the cementing substance 70, the welding substance 6 9 can be directly used, and the three-dimensional 3D structure shown in FIG. 6 can be formed by welding or other joining methods. [Effect of the invention] According to the wafer size structure method disclosed in the present invention, a flip chip is used

Page 11 516199 V. The process of invention description (9) is used for the transmission of internal signals. Because the telecommunication impedance is small, it can be used as a higher frequency IC structure. Its added value is high. As a medium for bonding with the motherboard, the cost of the lead frame can be lower, which can reduce the cost of the crystal size structure. The lead frame structure of this creation can be used as a three-dimensional 3D structure arrangement, which can reduce the module space. Increase density. [Explanation of Schematic Symbols] 50 ............... ............... Semiconductor wafer 5 2 .................. ............................., renown 彖 贝 占 # 5 3 ............ ........................................ . Θ pin 5 4 ............................ ................................................................................................................... ............... ........................................ .Outer pin 5 7 .................. ...... # 装 | 体 60 ............. ............ Semiconductor wafer 6 1 ........ .......................... M ^ ^ 6 2 ... .................................. Top 6 3 ...................................... ............... #, line $ 64 ............... .............. Kyoko t I Body 65 ............... ....................... I / 0 pad6 6 ...................................... ............... Access Area 6 7 ................................................... ............... 68 Power Zone ................................................... 9................................................. ........... ^ ^ f 7 0 ... ................ # I 4

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Claims (1)

516199 6. Scope of patent application 1. A type of gold wire on the top surface of the crystal is constructed with a plurality of metal bumps, and the package body of the metal wire frame surrounds the metal bump and the patent application. The scope of the lead frame is applied for a patent. The scope of the lead frame has multiple patent applications. The profile of the contact point is applied for a patent scope. The material of the metal bump is a three-dimensional 3D structure. The package is pushed and formed into a body 3D frame, which is fixed and connected with each other, and the inner two, such as three, such as four, such as five, and such as gold. 6. The one-inch structure has a structure with a structured energy phase size of 7, such as at least: a semiconductor wafer with metal bumps, each of which is on an I / O pad; the top of the bumps are combined to form an electrical connection The two ends protrude outward from the semiconductor wafer; the semiconductor wafer and a lead frame located on the semiconductor wafer. The structure of the chip size structure described in item 1 has one access area and two power areas. The wafer size structure described in item 1, a plurality of lead contacts. The wafer size structure described in item 3 may be a polygon or a circle. The structure of the wafer size structure described in item 1 can be a tin alloy or other metal-wafer size structure. The structure is composed of a plurality of wafer rulers, which are characterized in that the wafer size structure is a lead frame outside the body, The wafers are first sized, and then a lead frame is formed through a section between the lead frames to form a three-dimensional 3D structure. Wafer size of stereo 3D structure as described in the scope of patent application No. 6 Page 13 516199 VI. The scope of the patent application, which includes the following 3D structure: each step is used to install the chip in this guide; the other way in the patent for the guide way, such as applying for the structure, includes the following Steps are directly on each type or other bonding 9, a type applied to the electric double electric 8 substrate connection area and the step: the body size wire frame makes this range the step; the guide way the chip connects the force area wire frame to each other The means capable of bonding and fixing each other can be coated with a glue substance to fix the push-fit structure; and a corresponding place can be coated with a welding substance, which can be fixed to each other by welding or a lead frame. Wafer size of the three-dimensional 3D structure as described in item 6. Means for the wire frames to be fixed to each other. The corresponding parts of the wire frames are coated with soldering material, and the lead frames are fixed to each other by welding. The size-constructed lead frame structure is used to connect to the outside, and is characterized in that the lead frame structure has a structure for facilitating the user to arbitrarily overlap according to the demand. It is applied to the chip as described in item 9 of the scope of patent application The size-structured lead frame structure, wherein the lead frame has a plurality of lead points. 1. The lead frame structure applied to the chip size structure as described in item 10 of the scope of the patent application, wherein the appearance of the lead can be a square or a circle. 2. A method for fabricating a wafer-scale structure, comprising at least the following steps: providing a semiconductor wafer having a plurality of metal bumps formed on the top surface; and by combining the top of the metal bumps with a lead frame, Page 14 516199 VI. Patent application scope The semiconductor wafer and the lead frame are electrically connected, and both ends of the lead frame protrude out of the semiconductor wafer; and a predetermined portion including the semiconductor wafer and the lead frame is molded. To form a package body. 13. The manufacturing method of the wafer size structure as described in Item 12 of the scope of patent application, wherein before forming the metal bump, an I / O redistribution process can be used to transfer the I / 0 pad from the Around the semiconductor wafer or in the center of the semiconductor wafer, it extends to I / 0 pads arranged in a surface matrix. 14. The method for manufacturing a wafer size structure as described in item 12 of the scope of patent application, further comprising a step of cleaning the semiconductor wafer before the molding step. 15. The method for manufacturing a wafer size structure as described in item 12 of the scope of patent application, which further includes a step of preparing a lead frame, and attaching the semiconductor wafer to the lead frame and combining them. A step of. 16. The manufacturing method of the wafer size structure as described in Item 12 of the scope of the patent application, wherein the means for combining the metal bump with the lead frame is a soldering means. 17. The manufacturing method of the wafer size structure as described in Item 12 of the scope of patent application, wherein the material of the metal bump may be a tin-lead alloy or other solder alloy. Page 15