CN210296353U - Three-dimensional integrated packaging structure - Google Patents
Three-dimensional integrated packaging structure Download PDFInfo
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- CN210296353U CN210296353U CN201921507743.2U CN201921507743U CN210296353U CN 210296353 U CN210296353 U CN 210296353U CN 201921507743 U CN201921507743 U CN 201921507743U CN 210296353 U CN210296353 U CN 210296353U
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- rewiring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
- H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model discloses a three-dimensional integrated packaging structure belongs to integrated circuit packaging technology field. The three-dimensional integrated packaging structure comprises a substrate and a wafer, wherein n layers of rewiring are formed on the substrate, and n is more than or equal to 1; a passive device is attached to the surface of the n layers of rewiring; the wafer is plated with salient points with different heights, and the wafer is welded with the substrate through the salient points. Through the convex points with different heights on the wafer, the problem of three-dimensional packaging of the surface of the substrate which is not on the same plane is solved, the limitation of three-dimensional packaging is made up, and the packaging integration level is increased.
Description
Technical Field
The utility model relates to an integrated circuit encapsulation technical field, in particular to three-dimensional integrated package structure.
Background
In recent years, with the continuous progress of living standards and technologies, the demand of digital electronic products for miniaturization, high bandwidth and intellectualization is increasing. To meet these demands, industry manufacturers are also constantly seeking and creating new technologies. At present, the packaging method for improving the product performance is mainly a three-dimensional stacking technology, such as CoWos, InFO and EMIB of Intel. For three-dimensional packaging, high-speed and high-bandwidth transmission of heterogeneous chips cannot be realized without high-density bumps. Currently, bumps are mainly classified into two categories: solder ball bumps and copper pillar bumps. Compared with the solder ball bump, the copper pillar bump has smaller diameter and pitch, so the copper pillar bump is more and more applied, especially the high-density interconnection among high-density I/O chips such as HBM, CPU, DSP and FPGA.
In the conventional wafer-level preparation of copper stud bumps, the bump sizes (diameter and height) are consistent. However, in practical production, since the heights of the surfaces of the substrates of some three-dimensional packages are not in the same plane, the wafers with the same bump size cannot meet the requirements of the three-dimensional packages.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a three-dimensional integrated package structure to solve the problem that three-dimensional encapsulation can't be satisfied to the wafer of present bump size unanimity.
In order to solve the technical problem, the utility model provides a three-dimensional integrated packaging structure, include:
the substrate is provided with n layers of rewiring, wherein n is more than or equal to 1; a passive device is attached to the surface of the n layers of rewiring;
the wafer is plated with salient points with different heights, and the wafer is welded with the substrate through the salient points.
Optionally, the wafer includes a chip and a plurality of metal pads in the chip, and each metal pad has n layers of rewiring formed thereon.
Optionally, the bumps with different heights are respectively formed on the n layers of redistribution traces on the metal pad.
Optionally, a tin cap is formed on the surface of the bump through electroplating, the tin cap is made of SnAg, SnPb and SnAgCu, and the height of the tin cap is not less than 0.1 μm.
Optionally, the passive device includes a capacitor, a resistor, and an inductor.
Optionally, the bumps with different heights on the wafer are prepared by the following method:
providing a chip with a metal bonding pad, and performing n-layer rewiring on the metal bonding pad;
spin-coating a negative photoresist and opening the negative photoresist according to the diameter of the bump;
electroplating in the opening to prepare a bump with the minimum height;
spraying or spin-coating positive photoresist, opening the part of the salient point which does not reach the height requirement, and electroplating in the opening to prepare the salient point with the second-smallest height; repeating the steps until all the salient points are prepared;
removing the positive photoresist, and electroplating on the surface of the salient point to form a tin cap;
removing the negative photoresist, and wet-etching the seed layer;
placing the tin plate in a reflow furnace to form an arc-shaped tin cap;
and scribing the wafer to form a packaging body with different bump heights.
Optionally, a seed layer is sputtered during the n-layer rewiring process on the metal pad, the seed layer is made of a metal material and has a thickness of more than 0.01 μm;
the metallic material includes any one or more of Ti, Cu, and TiW.
Optionally, the negative photoresist and the positive photoresist are both made of resin type high polymer materials or polyimide type high polymer materials; the thickness of the negative photoresist is not less than the highest height of the salient point to be grown; the thickness of the positive photoresist is not less than 0.1 μm.
Optionally, wet etching away the seed layer comprises:
wet etching the seed layer with an acid etching solution with a pH range of 4-7.
Optionally, the reflux temperature in the reflux furnace is not lower than 50 ℃.
The utility model provides a three-dimensional integrated packaging structure, including base plate and disk, be formed with n layers of rewiring on the base plate, n is greater than or equal to 1; a passive device is attached to the surface of the n layers of rewiring; the wafer is plated with salient points with different heights, and the wafer is welded with the substrate through the salient points.
Through the convex points with different heights on the wafer, the problem of three-dimensional packaging of the surface of the substrate which is not on the same plane is solved, the limitation of three-dimensional packaging is made up, and the packaging integration level is increased.
Drawings
Fig. 1 is a schematic view of a three-dimensional integrated package structure provided by the present invention;
FIG. 2 is a schematic diagram of different areas of a wafer having different chips distributed thereon;
FIG. 3 is a schematic diagram of chips corresponding to different regions in an MPW wafer;
FIG. 4 is a schematic diagram after n-layer rewiring;
FIG. 5 is a schematic diagram after spin-coating a negative photoresist;
FIG. 6 is a schematic view after the first electroplating;
FIG. 7 is a schematic view of a first application of a positive photoresist;
FIG. 8 is a schematic view of a second electroplating;
FIG. 9 is a schematic view of a second application of a positive photoresist;
FIG. 10 is a schematic view after a third electroplating;
FIG. 11 is a schematic view of the coating of a positive photoresist n times;
FIG. 12 is a schematic view of the nth plating;
FIG. 13 is a schematic view of an electroplated tin cap;
FIG. 14 is a schematic illustration after stripping and seed layer etching;
FIG. 15 is a schematic representation after reflow;
fig. 16 is a schematic diagram of growing bumps of different heights on the same chip.
Detailed Description
The three-dimensional integrated package structure provided by the present invention is further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.
Example one
The utility model provides a three-dimensional integrated packaging structure, the structure of which is shown in figure 1, comprising a substrate 201 and a wafer, wherein n layers of rewiring 202 are formed on the substrate 201, and n is more than or equal to 1; passive devices (including a passive device 203a, a passive device 203b and a passive device 203c) are attached to the surface of the n-layer rewiring 202; as shown in fig. 2, the wafer includes a wafer 101, different chips are distributed in different areas of the wafer, bumps 107 with different heights are plated on the chips in the different areas, and the wafer is welded to the substrate 201 through the bumps 107 with different heights.
Specifically, with reference to fig. 1, the wafer includes a chip 102 and a plurality of metal pads 103 in the chip 102, n layers of redistribution lines 104 are formed on each metal pad 103, and the bumps 107 with different heights are respectively formed on the n layers of redistribution lines 104. Furthermore, tin caps (including tin cap 109a, tin cap 109b, tin cap 109c and tin cap 109d) are formed on the surface of the bump 107 through electroplating, the tin caps are made of SnAg, SnPb and SnAgCu, and the height of the tin caps is not less than 0.1 μm; further, the passive device includes a capacitor, a resistor, and an inductor. Due to the varying size of passive devices, bumps of varying sizes in the wafer are required. Referring to fig. 1, the solder cap 109c has the largest size and is used as a power connection port in a package structure, and since the flowing current is large, the size of the solder cap and the corresponding bump is large to meet the electrical connection requirement.
The manufacturing method of the wafer electroplated with the bumps with different heights comprises the following steps:
specifically, as shown in fig. 3, a chip 102 formed with a metal pad 103 is first provided, corresponding to different regions in fig. 1; forming n-layer rewiring 104 on metal pad 103; the seed layer 105 is sputtered during the process of performing n-layer rewiring, as shown in fig. 4; wherein n is more than or equal to 1, the seed layer 105 is made of a metal material and has a thickness of more than 0.01 mu m; the metallic material includes any one or more of Ti, Cu, and TiW.
Referring to fig. 5, a negative photoresist 106 is spin-coated, wherein the material of the negative photoresist 106 is a resin type polymer material or a polyimide type polymer material, and the thickness of the negative photoresist is not less than the highest height of the bump to be grown; and forming an opening 110 on the negative photoresist 106, wherein the size of the opening 110 is determined according to the diameter of the bump to be grown.
Placing the chip in an electroplating bath for first electroplating, and electroplating in the opening to prepare a bump 107a with the smallest height, as shown in FIG. 6;
the positive photoresist 108a is sprayed or spin-coated, and the material of the positive photoresist 108a is a resin type polymer material or a polyimide type polymer material, and the thickness of the positive photoresist is not less than 0.1 μm. The positive photoresist 108a of the bump portion having reached the height requirement is retained, and the bump portion having not reached the height requirement is opened by a photolithography technique, as shown in fig. 7;
placing the substrate in an electroplating bath for second electroplating to prepare a bump 107b with the second smallest height in the opening by electroplating, as shown in FIG. 8;
the positive photoresist 108b is sprayed or spin-coated, and the material of the positive photoresist 108b is a resin type polymer material or a polyimide type polymer material, and the thickness of the positive photoresist is not less than 0.1 μm. The positive photoresist 108b of the bump portion having reached the height requirement is retained, and the bump portion having not reached the height requirement is opened by a photolithography technique, as shown in fig. 9;
placing the substrate in an electroplating bath for third electroplating to prepare a bump 107c with a third small height in the opening by electroplating, as shown in FIG. 10;
repeating the above steps;
the positive photoresist 108n is sprayed or spin-coated, and the material of the positive photoresist 108n is a resin type high polymer material or a polyimide type high polymer material, and the thickness of the positive photoresist is not less than 0.1 μm. The positive photoresist 108n of the bump portion having reached the height requirement is retained, and the bump portion having not reached the height requirement is opened by a photolithography technique, as shown in fig. 11;
placing the substrate in an electroplating bath for the nth electroplating, and electroplating in the opening to prepare a bump 107n with the largest height, as shown in FIG. 12;
as shown in fig. 13, the positive photoresist is removed, the chip is placed in an electroplating bath, and a tin cap 109 is electroplated on the surface of the bump; the tin cap 109 is made of SnAg, SnPb and SnAgCu, and the height of the tin cap is not less than 0.1 mu m;
as shown in fig. 14, the negative photoresist 106 is removed, and the seed layer 105 is wet etched away by an acid etching solution with PH ranging from 4 to 7;
placing the chip in a reflow oven at a reflow temperature of not less than 50 deg.C to form an arc-shaped solder cap 109, as shown in FIG. 15;
finally, wafer scribing is carried out according to the dotted lines in fig. 15, so that bumps with different heights are formed.
As shown in fig. 16, bumps 107 with different heights can be grown according to the above process for soldering with the substrate to prepare the three-dimensional integrated package shown in fig. 1.
The above description is only for the preferred embodiment of the present invention and is not intended to limit the scope of the present invention, and any modification and modification made by those skilled in the art according to the above disclosure are all within the scope of the claims.
Claims (5)
1. A three-dimensional integrated package structure, comprising:
the substrate is provided with n layers of rewiring, wherein n is more than or equal to 1; a passive device is attached to the surface of the n layers of rewiring;
the wafer is plated with salient points with different heights, and the wafer is welded with the substrate through the salient points.
2. The three-dimensional integrated packaging structure as claimed in claim 1, wherein the wafer comprises a chip and a plurality of metal pads in the chip, and each metal pad has n layers of rewiring formed thereon.
3. The three-dimensional integrated package structure according to claim 2, wherein the bumps of different heights are respectively formed on the n layers of redistribution lines on the metal pad.
4. The three-dimensional integrated package structure according to claim 1, wherein a solder cap is formed on the surface of the bump by electroplating, and the solder cap is made of SnAg, SnPb, and SnAgCu, and has a height of not less than 0.1 μm.
5. The three-dimensional integrated package structure of claim 1, wherein the passive devices comprise capacitors, resistors and inductors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921507743.2U CN210296353U (en) | 2019-09-11 | 2019-09-11 | Three-dimensional integrated packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921507743.2U CN210296353U (en) | 2019-09-11 | 2019-09-11 | Three-dimensional integrated packaging structure |
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| CN210296353U true CN210296353U (en) | 2020-04-10 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110600387A (en) * | 2019-09-11 | 2019-12-20 | 中国电子科技集团公司第五十八研究所 | Preparation method of bumps with different specifications and sizes |
| CN112420534A (en) * | 2020-11-27 | 2021-02-26 | 上海易卜半导体有限公司 | Method for forming semiconductor package and semiconductor package |
-
2019
- 2019-09-11 CN CN201921507743.2U patent/CN210296353U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110600387A (en) * | 2019-09-11 | 2019-12-20 | 中国电子科技集团公司第五十八研究所 | Preparation method of bumps with different specifications and sizes |
| CN112420534A (en) * | 2020-11-27 | 2021-02-26 | 上海易卜半导体有限公司 | Method for forming semiconductor package and semiconductor package |
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