WO2020134502A1 - 一种视频信号生成装置及方法 - Google Patents

一种视频信号生成装置及方法 Download PDF

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WO2020134502A1
WO2020134502A1 PCT/CN2019/113897 CN2019113897W WO2020134502A1 WO 2020134502 A1 WO2020134502 A1 WO 2020134502A1 CN 2019113897 W CN2019113897 W CN 2019113897W WO 2020134502 A1 WO2020134502 A1 WO 2020134502A1
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module
fpga
video signal
generating device
signal generating
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PCT/CN2019/113897
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English (en)
French (fr)
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刘升
李嘉伟
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西安奇维科技有限公司
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Publication of WO2020134502A1 publication Critical patent/WO2020134502A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/765—Interface circuits between an apparatus for recording and another apparatus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/222—Studio circuitry; Studio devices; Studio equipment
    • H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/2621—Cameras specially adapted for the electronic generation of special effects during image pickup, e.g. digital cameras, camcorders, video cameras having integrated special effects capability

Definitions

  • the invention belongs to the technical field of electronics, and particularly relates to a video signal generating device and method.
  • the CameraLink interface is a digital image interface. At present, it is widely used in the fields of image acquisition, security monitoring and industrial production. There are many types of image processing products based on CameraLink interface. Because CameraLink does not have a standard communication specification, although different products of various manufacturers all use CameraLink interface, there are differences in transmission timing and definition, resulting in low compatibility between different products.
  • the products of CameraLink interface mainly include the camera in the front end of image acquisition and the image processing equipment in the back end of image processing. In the development stage of these two products, joint debugging and verification of the end equipment are required. In the product use phase, due to compatibility issues, the two products often cannot change the model of the peer product. If the product model of one end needs to be replaced, the end product often needs to be replaced or modified.
  • CameraLink frame grabbers For the joint debugging and verification of CameraLink cameras, there are CameraLink frame grabbers on the market. This capture card is rich in functions, can support multiple resolutions and frame rates, and provides camera parameter control.
  • CameraLink image processing equipment there is no good joint debugging and verification equipment on the market; when changing the camera model, it often brings changes to the image processing equipment. In the process of modification, adjustment and verification of multiple parameters are required, which requires a video signal generating device with flexible parameter adjustment.
  • the present invention aims to solve the above-mentioned problems, and provides a video signal generating device and method whose parameters can be flexibly adjusted.
  • the video signal generating device of the present invention includes an FPGA main control module, a CameraLink encoding module, a PCIe communication module and a power supply module;
  • the FPGA main control module includes an FPGA, a storage module, a crystal oscillator and a communication interface; the storage module, crystal oscillator and The communication interfaces are electrically connected to the FPGA;
  • the PCIe communication module is provided with a PCIe interface;
  • the CameraLink encoding module and the power supply module are electrically connected to the FPGA;
  • the PCIe communication module is electrically connected to the FPGA through the PCIe interface.
  • the storage module includes NOR FLASH and DDR III SDRAM; the DDR III SDRAM is provided with two; the NOR FLASH is provided with a QSPI interface; NOR FLASH is used to store working codes, DDR III SDRAM is used to run cache.
  • the communication interface includes a JPTG interface, and the JPTG interface is used for debugging.
  • the encoding module is composed of an LVDS serializer module.
  • the power supply module includes a plurality of DC/DC chips arranged in parallel; the power supply module steps down the input power to various low-voltage power supplies required inside the video signal generating device for each module circuit to work use.
  • DC/DCs are in a level relationship, and generate different voltage outputs after taking power from the same voltage source.
  • the power module includes four LTM4623 chips and one TPS51100 chip.
  • the output voltages of the four LTM4623 chips are 3.3V, 1.0V, 1.2V, and 1.5V, respectively; the output voltage of the TPS51100 chip is 0.75V.
  • the generating method of the video signal generating device of the present invention transmits the video content and the control command to be displayed to the FPGA through the PCIe interface of the PCIe communication module, and the FPGA main control module buffers the video content and then uses the FPGA to control the video content according to the control command
  • the image in is subjected to image modulation processing, and then serially processed through the CameraLink encoding module and output.
  • the image modulation processing includes image scaling, DDR buffering, image sharpening, color space conversion, image superposition, frame rate conversion, and resolution setting.
  • the serial processing is to convert a 28-bit parallel data signal into an LVDS differential signal.
  • the video signal generating device and method of the present invention include an FPGA main control module, a CameraLink encoding module, a PCIe communication module, and a power supply module;
  • the FPGA main control module includes an FPGA, a storage module, a crystal oscillator, and a communication interface; the storage module, The crystal oscillator and the communication interface are electrically connected to the FPGA;
  • the CameraLink output video is generated through the FPGA, making full use of the FPGA's field-programmable features, significantly improving the flexibility of CameraLink development and debugging, and reducing development costs.
  • FIG. 1 is a schematic block diagram of the structure of a video signal generating device according to the present invention.
  • FIG. 2 is a schematic flowchart of the video signal generation method of the present invention.
  • FIG. 3 is a schematic diagram of the structure of the CameraLink encoding module of the video signal generating device of the present invention.
  • FIG. 4 is a schematic structural diagram of a PCIe communication module of a video signal generating device according to the present invention.
  • FIG. 5 is a schematic structural diagram of a power module of a video signal generating device according to the present invention.
  • the video signal generating device of the present invention includes an FPGA main control module, a CameraLink encoding module, a PCIe communication module, and a power supply module;
  • the FPGA main control module includes an FPGA, a storage module, a crystal oscillator, and a communication interface;
  • the storage module, crystal oscillator and communication interface are all electrically connected to the FPGA;
  • the PCIe communication module is provided with a PCIe interface;
  • the CameraLink encoding module and the power supply module are electrically connected to the FPGA;
  • the PCIe communication module is connected to the FPGA through the PCIe interface Phase electrical connection.
  • the storage module includes NOR FLASH and DDR III SDRAM; the DDR III SDRAM is provided with two; the NOR FLASH is provided with a QSPI interface; the NOR FLASH is used to store working codes, and the DDR III SDRAM is used to run cache.
  • the communication interface includes a JPTG interface, which is used for debugging.
  • the CameraLink encoding module is composed of an LVDS serializer module.
  • the power module includes five DC/DC chips arranged in parallel; includes four LTM4623 chips and a TPS51100 chip, and the power module steps down the input power to various low voltages required inside the video signal generating device Power supply for circuit operation of each module.
  • the output voltages of the four LTM4623 chips are 3.3V, 1.0V, 1.2V, and 1.5V; the output voltage of the TPS51100 chip is 0.75V; the input is a 12V power supply of PCIe interface.
  • the FPGA selects the XC7A100T-FGG676 model according to the number of consumed IO pins.
  • the FPGA main control module receives and connects each functional module, mainly to complete digital image processing, including image scaling, DDR cache, image sharpening, color space conversion, Image overlay, frame rate conversion, resolution setting, etc.
  • the main function of the CameraLink encoding module is to serially process the parallel 28-bit data output from the FPGA into a differential LVDS signal conforming to the CameraLink transmission specification.
  • the PCIe communication module mainly completes the data communication between the video signal generator and the PC host.
  • the communication content includes display images and control commands.
  • the power supply module steps down the power input from the host PC to various low-voltage power supplies required inside the video signal generator for the circuit operation of each module.
  • the gold finger part of the PCIe interface can be directly inserted into the PCIe slot of the PC host. As shown in FIG. 4, taking the PCIe communication of X1 rate as an example, it can be extended to the X16 rate communication of PCIe according to the usage environment.
  • the PC host provides communication and power supply for the video signal generating device through the golden finger interface.
  • the FPGA main control module is composed of FPGA, NOR FLASH of QSPI interface, DDR3 SDRAM, crystal oscillator and JTAG interface.
  • the FPGA contains 8 pairs of high-speed ports.
  • Two Micron models MT41K256M16HA-125IT:E's DDR3 SDRAM are used as image buffers.
  • the capacity is 512MB.
  • the two chips have a total of 1GB.
  • the clock frequency is up to 667MHz.
  • Data buffering requirements In data processing, the two pieces of cache do ping-pong operations to ensure normal data communication.
  • FPGA configuration ROM adopts NOR FALSH chip with QSPI interface, model is W25Q128FV, working voltage is 3.3V, and it is directly connected with FPGA.
  • the CameraLink encoding module is mainly composed of the LVDS serializer DS90CR287 chip, which converts the 28-bit 3.3V parallel data signal output by the FPGA into an LVDS differential signal, and the encoded data bits conform to the CameraLink transmission specification.
  • the output connector is CameraLink standard connector MDR26.
  • the PCIe communication module uses a PCIe bridge chip to realize the communication between the video signal generator and the PC host, and complete the video data transmission.
  • the model of the PCIe bridge chip is PEX8311.
  • PCIe is designed to use X1 connection, and the chip can reach 2.5Gbps in each direction.
  • the method for generating a video signal generating device of the present invention transmits the video content and control commands to be displayed to the FPGA through the PCIe interface of the PCIe communication module, and the FPGA main control module
  • the FPGA performs image modulation processing on the image in the video content according to control commands, and then performs serial processing through the CameraLink encoding module and outputs it.
  • the image modulation processing includes image scaling, DDR cache, image sharpening, color space conversion, image overlay, frame rate conversion, and resolution setting.
  • the serial processing is to convert 28-bit parallel data signals into LVDS differential signals.
  • the host PC generates the video to be displayed through the software in the host computer; the video content is communicated to the FPGA of the video signal generator through the PCIe interface.
  • the FPGA performs image buffering, graphics conversion, and overlay enhancement processing, it outputs and displays through the CameraLink video interface.
  • FPGA can generate custom output timing, so it generates video signals with different frame rates and resolutions.
  • the video signal generating device of the present invention adopts a modular design and a simple structural shell to form a video signal source with rich functions, which is used for debugging and emulation of various CameraLink signal processing equipment and has extremely high flexibility.

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Abstract

一种视频信号生成装置及方法，属于电子技术领域，其特征在于：包括FPGA主控模块、CameraLink编码模块、PCIe通信模块和电源模块；所述FPGA主控模块包括FPGA、存储模块、晶振和通信接口；所述存储模块、晶振和通信接口均与FPGA相电连接；所述PCIe通信模块设置有PCIe接口；所述CameraLink编码模块和电源模块均与FPGA相电连接；所述PCIe通信模块通过PCIe接口与FPGA相电连接。通过FPGA产生CameraLink输出视频，充分利用FPGA的现场可编程特性，用于多种CameraLink信号处理设备的调试和仿真，显著提高CameraLink开发调试的灵活性，降低开发成本。

Description

一种视频信号生成装置及方法 技术领域
本发明属于电子技术领域，尤其涉及一种视频信号生成装置及方法。
 背景技术
CameraLink接口是数字图像接口。目前在图像采集、安防监控和工业生产等领域大量使用，基于CameraLink接口的图像处理产品种类繁多。由于CameraLink没有标准的通信规范，各厂家的不同产品虽均采用CameraLink接口，但在传输时序和定义上存在差异，造成不同产品间的兼容性不高。CameraLink接口的产品主要包括图像采集前端的摄像头和图像处理后端的图像处理设备。在这两种产品的开发阶段，均需要对端设备进行联调和验证。在产品使用阶段，两种产品由于兼容性问题往往不能更换对端产品型号。若需要更换其中一端的产品型号，往往需要对端产品进行更换或修改。
针对CameraLink摄像头的联调和验证，市面上存在CameraLink图像采集卡。这种采集卡功能丰富，可支持多种分辨率和帧频，并提供摄像头的参数控制。对于CameraLink图像处理设备，市面上尚没有很好的联调和验证设备；当更换摄像头型号时，往往带来图像处理设备的更改。在更改的过程中，需要多种参数的调整和验证，这就需要一种参数可灵活调整的视频信号生成装置。
 技术问题
本发明旨在解决上述问题，提供一种参数可灵活调整的视频信号生成装置及方法。
 技术解决方案
本发明所述视频信号生成装置，包括FPGA主控模块、CameraLink编码模块、PCIe通信模块和电源模块；所述FPGA主控模块包括FPGA、存储模块、晶振和通信接口；所述存储模块、晶振和通信接口均与FPGA相电连接；所述PCIe通信模块设置有PCIe接口；所述CameraLink编码模块和电源模块均与FPGA相电连接；所述PCIe通信模块通过PCIe接口与FPGA相电连接。
本发明所述视频信号生成装置，所述存储模块包括NOR FLASH 和DDR III SDRAM；所述DDR III SDRAM设置有两个；所述NOR FLASH 设置有QSPI接口；NOR FLASH用于存储工作代码、DDR III SDRAM用于运行缓存。
本发明所述视频信号生成装置，所述通信接口包括JPTG接口，JPTG接口用于调试。
本发明所述视频信号生成装置，所述编码模块由LVDS串行器模块组成。
本发明所述视频信号生成装置，所述电源模块包括若干个并列设置的DC/DC芯片；电源模块将输入的电源降压为视频信号发生装置内部需要的各种低压电源，供各模块电路工作使用。若干个DC/DC处于平级关系，分别从同一电压源取电后生成不同电压输出。
本发明所述视频信号生成装置，所述电源模块包括四个LTM4623芯片和一个TPS51100芯片。
本发明所述视频信号生成装置，所述四个LTM4623芯片的输出电压分别为3.3V、1.0V、1.2V、和1.5V；所述TPS51100芯片的输出电压为0.75V。
本发明所述视频信号生成装置的生成方法，将需要显示的视频内容及控制命令通过PCIe通信模块的PCIe接口传输至FPGA，FPGA主控模块对视频内容进行缓存后通过FPGA根据控制命令对视频内容中的图像进行图像调制处理，再通过CameraLink编码模块进行串行处理后输出。
本发明所述视频信号生成装置的生成方法，所述图像调制处理包括图像缩放、DDR缓存、图像锐化、色彩空间转换、图像叠加、帧频变换和分辨率设置。
本发明所述视频信号生成装置的生成方法，所述出串行处理为将28位并行数据信号转换为LVDS差分信号。
 有益效果
本发明所述视频信号生成装置及方法，包括FPGA主控模块、CameraLink编码模块、PCIe通信模块和电源模块；所述FPGA主控模块包括FPGA、存储模块、晶振和通信接口；所述存储模块、晶振和通信接口均与FPGA相电连接；通过FPGA产生CameraLink输出视频，充分利用FPGA的现场可编程特性，显著提高CameraLink开发调试的灵活性，降低开发成本。
 附图说明
图1为本发明所述视频信号生成装置的结构示意框图；
图2为本发明视频信号生成方法的流程示意图；
图3为本发明所述视频信号生成装置的CameraLink编码模块结构示意图；
图4为本发明所述视频信号生成装置PCIe通信模块结构示意图；
图5为本发明所述视频信号生成装置电源模块结构示意图。
 本发明的实施方式
下面通过实施例对本发明所述视频信号生成装置及方法进行详细说明。
实施例一
本发明所述视频信号生成装置，如图1所示，包括FPGA主控模块、CameraLink编码模块、PCIe通信模块和电源模块；所述FPGA主控模块包括FPGA、存储模块、晶振和通信接口；所述存储模块、晶振和通信接口均与FPGA相电连接；所述PCIe通信模块设置有PCIe接口；所述CameraLink编码模块和电源模块均与FPGA相电连接；所述PCIe通信模块通过PCIe接口与FPGA相电连接。所述存储模块包括NOR FLASH 和DDR III SDRAM；所述DDR III SDRAM设置有两个；所述NOR FLASH 设置有QSPI接口；NOR FLASH用于存储工作代码、DDR III SDRAM用于运行缓存。所述通信接口包括JPTG接口，JPTG接口用于调试。
本发明所述视频信号生成装置，如图3所示，所述CameraLink编码模块由LVDS串行器模块组成。如图5所示，所述电源模块包括五个并列设置的DC/DC芯片；包括四个LTM4623芯片和一个TPS51100芯片，电源模块将输入的电源降压为视频信号发生装置内部需要的各种低压电源，供各模块电路工作使用。四个LTM4623芯片的输出电压分别为3.3V、1.0V、1.2V、和1.5V；所述TPS51100芯片的输出电压为0.75V；输入为PCIe接口的12V电源。
在本实施例中，FPGA根据消耗IO管脚数选择XC7A100T-FGG676型号，FPGA主控模块接收连接各功能模块，主要完成数字图像处理，包括图像缩放、DDR缓存、图像锐化、色彩空间转换、图像叠加、帧频变换、分辨率设置等。CameraLink编码模块主要功能是将FPGA输出的并行28位数据串行处理为符合CameraLink传输规范的差分LVDS信号。PCIe通信模块主要完成视频信号发生器与PC主机间的数据通信，通信内容包括显示图像和控制命令等。电源模块将从PC主机输入的电源降压为视频信号发生器内部需要的各种低压电源，供各模块电路工作使用。PCIe接口的金手指部分，可直接对插在PC主机的PCIe插槽内，如图4所示，以X1速率的PCIe通信为例，可根据使用环境扩展至PCIe的X16速率通信。PC主机通过金手指接口为视频信号生成装置提供通信和供电。
FPGA主控模块由FPGA、QSPI接口的NOR FLASH、DDR3 SDRAM、晶振和JTAG接口等组成。FPGA包含了8对高速口，外挂两片美光公司的型号为MT41K256M16HA-125IT:E 的DDR3 SDRAM作为图像的缓存，容量为512MB，两片共1GB，时钟频率高达667MHz，满足FPGA运算处理过程中的数据缓冲需求。在数据处理中，两片缓存做乒乓操作，保证数据正常通信。FPGA配置ROM采用QSPI接口的NOR FALSH芯片，型号为W25Q128FV，工作电压3.3V，直接与FPGA连接。
如图3所示，CameraLink编码模块主要由LVDS串行器DS90CR287芯片组成，将FPGA输出的28位3.3V并行数据信号转换为LVDS差分信号，编码的数据位符合CameraLink传输规范。输出连接器为CameraLink标准接插件MDR26。
如图4所示，PCIe通信模块采用PCIe桥芯片来实现视频信号发生器与PC主机间的通信，完成视频数据传输。在本实施例中PCIe桥芯片型号选用PEX8311。设计PCIe使用X1连接，该芯片每方向速度可达2.5Gbps。
实施例二
在实施例一的基础上，本发明所述视频信号生成装置的生成方法，如图2所示，将需要显示的视频内容及控制命令通过PCIe通信模块的PCIe接口传输至FPGA，FPGA主控模块对视频内容进行缓存后通过FPGA根据控制命令对视频内容中的图像进行图像调制处理，再通过CameraLink编码模块进行串行处理后输出。所述图像调制处理包括图像缩放、DDR缓存、图像锐化、色彩空间转换、图像叠加、帧频变换和分辨率设置。所述出串行处理为将28位并行数据信号转换为LVDS差分信号。
PC主机通过上位机内的软件产生需要显示的视频；视频内容通过PCIe接口通信至视频信号发生器的FPGA，FPGA进行图像缓存、图形变换、叠加强化等处理后，通过CameraLink视频接口进行输出显示。FPGA可产生自定义的输出时序，因此产生不同帧频和分辨率的视频信号。
本发明所述视频信号生成装置采用模块化设计，配合简单的结构外壳可形成功能丰富的视频信号源，用于多种CameraLink信号处理设备的调试和仿真，具有极高的灵活性。

Claims (10)

  1. 一种视频信号生成装置，其特征在于：包括FPGA主控模块、CameraLink编码模块、PCIe通信模块和电源模块；所述FPGA主控模块包括FPGA、存储模块、晶振和通信接口；所述存储模块、晶振和通信接口均与FPGA相电连接；所述PCIe通信模块设置有PCIe接口；所述CameraLink编码模块和电源模块均与FPGA相电连接；所述PCIe通信模块通过PCIe接口与FPGA相电连接。
  2. 根据权利要求1所述视频信号生成装置，其特征在于：所述存储模块包括NOR FLASH 和DDR III SDRAM；所述DDR III SDRAM设置有两个；所述NOR FLASH 设置有QSPI接口。
  3. 根据权利要求2所述视频信号生成装置，其特征在于：所述通信接口包括JPTG接口。
  4. 根据权利要求3所述视频信号生成装置，其特征在于：所述编码模块由LVDS串行器模块组成。
  5. 根据权利要求4所述视频信号生成装置，其特征在于：所述电源模块包括若干个并列设置的DC/DC芯片。
  6. 根据权利要求5所述视频信号生成装置，其特征在于：所述电源模块包括四个LTM4623芯片和一个TPS51100芯片。
  7. 根据权利要求6所述视频信号生成装置，其特征在于：所述四个LTM4623芯片的输出电压分别为3.3V、1.0V、1.2V、和1.5V；所述TPS51100芯片的输出电压为0.75V。
  8. 一种根据权利要求1所述视频信号生成装置的生成方法，其特征在于：将需要显示的视频内容及控制命令通过PCIe通信模块的PCIe接口传输至FPGA，FPGA主控模块对视频内容进行缓存后通过FPGA根据控制命令对视频内容中的图像进行图像调制处理，再通过CameraLink编码模块进行串行处理后输出。
  9. 根据权利要求8所述视频信号生成装置的生成方法，其特征在于：所述图像调制处理包括图像缩放、DDR缓存、图像锐化、色彩空间转换、图像叠加、帧频变换和分辨率设置。
  10. 根据权利要求9所述视频信号生成装置的生成方法，其特征在于：所述出串行处理为将28位并行数据信号转换为LVDS差分信号。
     
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