WO2020133851A1 - 阵列基板及其制备方法 - Google Patents

阵列基板及其制备方法 Download PDF

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Publication number
WO2020133851A1
WO2020133851A1 PCT/CN2019/084776 CN2019084776W WO2020133851A1 WO 2020133851 A1 WO2020133851 A1 WO 2020133851A1 CN 2019084776 W CN2019084776 W CN 2019084776W WO 2020133851 A1 WO2020133851 A1 WO 2020133851A1
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Prior art keywords
layer
pad
pad high
high layer
array substrate
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PCT/CN2019/084776
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English (en)
French (fr)
Inventor
江志雄
徐洪远
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate and a preparation method thereof.
  • the main method of reducing the resistance and capacitance delay is to reduce the resistance, for example, to replace the aluminum wire with a metal copper wire, and to increase the thickness of the copper to reduce the resistance and achieve the purpose of reducing the RC delay.
  • the copper process is more difficult to etch copper, and it is necessary to use hydrofluoric acid with a higher risk factor (Hydro fluoric acid, HF), high cost.
  • Hydrofluoric acid with a higher risk factor (Hydro fluoric acid, HF), high cost.
  • Increasing the thickness of copper increases the deposition time of copper and the etching time accordingly, which increases the cost of materials and time.
  • the increase in the thickness of the copper film will also cause the problem of warpage due to excessive substrate stress.
  • the existing technology has the problems of high production cost and product warpage in reducing RC delay.
  • the array substrate provided by the present application reduces the RC delay effect of the panel by increasing the distance between the scan line and the data line at the intersection.
  • An array substrate includes a glass substrate, a grid electrode prepared on the surface of the glass substrate, a scanning line, and a pad high layer prepared on the surface of the substrate and covering the grid and the scan line, the pad high layer includes A first area corresponding to the scan line, and a second area corresponding to the gate;
  • the pad high layer includes a first pad high layer and a second pad high layer, the first pad high layer covers the gate and the scan line, and the second pad high layer is located on either side of the insulating layer.
  • the height of the first region of the pad high layer is greater than the height of the second region of the pad high layer.
  • the first pad upper layer is made of silicon nitride
  • the second pad upper layer is made of soluble polytetrafluoroethylene layer, R/G/B trichromatic superimposed layer or black matrix photoresist Material preparation.
  • the second pad upper layer covers an area outside the second area.
  • the second pad high layer is provided with an opening corresponding to the position of the second region, and the gate is placed in the opening.
  • the first pad upper layer is made of silicon nitride
  • the second pad upper layer is made of soluble polytetrafluoroethylene layer, R/G/B trichromatic superimposed layer or black matrix photoresist Material preparation.
  • the thickness of the pad upper layer is 300-800 ⁇ .
  • the present application also provides an array substrate including a glass substrate, a grid prepared on the surface of the glass substrate, a scan line, and a pad prepared on the surface of the substrate and covering the grid and the scan line A high level, the pad high level includes a first area corresponding to the scan line, and a second area corresponding to the gate;
  • the pad high layer includes a first pad high layer and a second pad high layer, the first pad high layer covers the gate and the scan line, and the second pad high layer is located on either side of the insulating layer;
  • the first pad high layer is made of silicon nitride, and the thickness of the first pad high layer is 300-800 ⁇ ;
  • the second pad high layer is made of soluble polytetrafluoroethylene layer and R/G/B tri-color superimposed layer Or black matrix photoresist materials.
  • the height of the first region of the pad high layer is greater than the height of the second region of the pad high layer.
  • the second pad high layer is disposed in the first area.
  • the array substrate includes pixel units distributed in an array, the pixel unit includes the scan line, a data line interleaved with the scan line, and a connection between the scan line and the In the thin film transistor of the data line, the second pad high layer is located at the intersection of the scan line and the data line.
  • the second pad upper layer covers an area outside the second area.
  • the second pad high layer is provided with an opening corresponding to the position of the second region, and the gate is placed in the opening.
  • a method for preparing an array substrate is provided. The method further includes the following steps:
  • Step S10 a glass substrate is provided, and a grid and a scanning line are prepared on the surface of the glass substrate;
  • Step S20 a first pad high layer is prepared on the surface of the glass substrate, and the first pad high layer covers the gate and the scanning line;
  • Step S30 the surface of the first pad high layer is developed and exposed, and the first pad high layer on the surface of the gate is stripped;
  • Step S40 a second pad high layer is prepared on the surface of the first pad high layer, and the first pad high layer and the second pad high layer are used as pad high layers, and the pad high layer includes a first region corresponding to the scan line, and Corresponding to the second region of the gate, wherein the second pad high layer is located at the intersection of the scan line and the data line;
  • Step S50 developing and exposing the surface of the second pad high layer, stripping the second pad high layer on the scanning line, and forming a pad high layer pattern
  • Step S60 a data line is deposited on the upper surface of the second pad
  • Step S70 a passivation layer is deposited on the surface of the data line.
  • the second pad high layer includes a first part of the second pad high layer and a second part of the second pad high layer
  • the step S40 specifically includes:
  • Step S401 depositing a first portion of the second pad high layer on the first pad high layer, developing and exposing the surface of the first part of the second pad high layer, and retaining the first part of the second pad high layer on the side of the scan line, on the scan line
  • the first insulating layer pattern is left at the overlap with the high layer of the pad
  • step S402 a second portion of the second pad upper layer is deposited on the surface of the first portion of the second pad upper layer so that the film thickness and film quality of the second part of the second pad upper layer are the same as the pad upper layer including the second region of the gate.
  • the first part of the second pad upper layer includes a first insulating layer, a second insulating layer and a third insulating layer
  • the step S401 specifically includes the following steps:
  • S4011 Deposit a first insulating layer on the surface of the first pad high layer to form a first insulating layer pattern, and reserve the first pad high layer on one side of the scan line;
  • the array substrate provided by this application increases the distance between the scan line and the data line by increasing the scan line and the data line to increase the pad height, and reduces the resistance and capacitance delay effect of the panel, thereby improving the display quality of the display panel.
  • FIGS. 1a-1g are schematic structural diagrams of the preparation process of the first embodiment of the array substrate provided by the present application.
  • FIG. 2 is a flowchart of a method for manufacturing an array substrate provided in Example 1 of the present application.
  • 3a-3e are schematic structural diagrams of the flow of the second embodiment of the array substrate provided by the present application.
  • FIG. 4 is a schematic diagram of the second pad high-level structure of the array substrate provided by the present application.
  • FIG. 5 is a schematic diagram of a pixel structure provided by this application.
  • This application is directed to the existence of the resistance and capacitance delay effect in the prior art array substrate.
  • a layer of low dielectric constant organic material such as soluble polymer Photoresist materials such as tetrafluoroethylene layer, R/G/B trichromatic superimposed layer or black matrix (Black Martrix, BM), etc., which are patterned by exposure and development, and prepared at the place where the data line overlaps the scan line
  • the film thickness of the organic material layer is 2um ⁇ 4um.
  • 1a to 1g are flowcharts of preparing an array substrate provided by an embodiment of the present invention.
  • FIG. 1a it includes a glass substrate 101 on which a gate 102 and a scanning line 109 are prepared.
  • a first pad high layer 103 is prepared on the surface of the glass substrate 101, and the first pad high layer 103 covers the gate electrode 102 and the scanning line 109.
  • the first pad layer 103 on the surface of the gate 102 is peeled off the surface of the glass substrate 101, and the first pad layer 103 on the surface of the scanning line 109 remains.
  • the first pad layer 103 is provided with a second pad layer 104 on the surface of the first pad layer 103, and the second pad layer 104 is located on the scan line 109 and the data line (FIG. Where not shown).
  • the surface of the second pad layer 104 is peeled off the second pad layer 104 on the scanning line, and the second pad layer 104 on the surface of the gate 102 remains to form a pad layer pattern.
  • a data line 105 is deposited on the surface of the second pad layer 104.
  • a passivation layer 106 is deposited on the surface of the data line 105.
  • the method for preparing an array substrate provided by the present invention includes:
  • Step S10 a glass substrate is provided, and a grid and a scanning line are prepared on the surface of the glass substrate.
  • Step S20 a first pad high layer is prepared on the surface of the glass substrate, and the first pad high layer covers the gate and the scanning line.
  • step S30 the surface of the first pad high layer is developed and exposed, and the first pad high layer on the surface of the grid is peeled off.
  • Step S40 a second pad high layer is prepared on the surface of the first pad high layer, and the first pad high layer and the second pad high layer are used as pad high layers, and the pad high layer includes a first region corresponding to the scan line, and Corresponding to the second region of the gate, the second pad high layer is located at the intersection of the scan line and the data line.
  • Step S50 developing and exposing the surface of the second pad high layer, stripping the second pad high layer on the scanning line, and forming a pad high layer pattern.
  • step S60 a data line is deposited on the upper surface of the second pad.
  • Step S70 a passivation layer is deposited on the surface of the data line.
  • the array substrate prepared by this method can reduce the resistance and capacitance delay without affecting the performance of the thin film transistor device.
  • this embodiment is performed after step S30 in FIG. 2 in Embodiment 1 of the present invention.
  • FIG. 3a it can be seen that the process flow of the embodiment of the present invention has completed steps S10-S40.
  • 3a to 3e are preparation flow charts of the array substrate provided by the embodiments of the present application:
  • FIG. 3a it includes a glass substrate 301, a gate 302 and a scanning line 309 are prepared on the surface of the glass substrate, a first pad 303 is prepared on the surface of the glass substrate 301, and a surface of the first pad 303 is prepared There is a second pad high-rise first part 304.
  • a second portion 305 of a second height layer is prepared on the first portion 304 of the second height layer.
  • the surface of the second portion 305 of the second pad high layer is developed and exposed, and the second portion 305 of the second pad high layer on the gate line 302 is peeled off to form a pattern of the pad high layer.
  • the second pad high layer 304 is prepared with a data line 306.
  • the data line 306 is prepared with a passivation layer 307.
  • the second pad high layer 304 includes a second pad high layer first part 304 and a second pad high layer second part 305.
  • the method for preparing an array substrate provided by the present invention includes:
  • Step S401 depositing a first portion 304 of the second pad high layer on the scan line, developing and exposing the surface of the first portion 304 of the second pad high layer, and retaining the second pad high layer 304 on the side of the scan line 309, on the scan line
  • the first insulating layer pattern is left at the overlap of 309 and the second pad high layer 304;
  • Step S402 a second pad high layer second part 305 is deposited on the surface of the second pad high layer first part 304, so that the film thickness and film quality of the second pad high layer second part 305 are the same as the pad high layer including the gate.
  • step S401 This embodiment is performed after step S30 in FIG. 2 of the first embodiment of the present invention. From FIGS. 3a to 3e, it can be seen that the process flow of the embodiment of the present application has completed the following steps S10-S30, and in the second embodiment, step S401 This includes:
  • Step S4011 a first insulating layer is deposited on the surface of the pad high layer to form a first insulating layer pattern, and the pad high layer and the insulating layer film layer are retained.
  • Step S4012 a second insulating layer is deposited on the surface of the pad layer, and an opening for avoiding the thin film transistor is formed on the surface of the second insulating layer, so that the surface of the thin film transistor has a second insulating layer pattern.
  • Step S4013 Deposit a third insulating layer on the surface of the opening and the second insulating layer so that the thickness and quality of the third insulating layer are the same as the second insulating layer of the thin film transistor.
  • Step S4014 developing and exposing the surface of the third insulating layer, leaving the second insulating layer on the side of the scanning line, and leaving a second insulating layer pattern at the overlap of the scanning line and the first insulating layer , That is the first pad high-rise pattern.
  • the second insulating layer 408 in step S4012.
  • the opening 410 is formed on the surface of the second insulating layer 408 through an exposure process, and the thin film transistor is located in the opening 410.
  • the area of the opening 410 just wraps the second area of the gate.
  • FIG. 5 is a schematic diagram of a pixel structure provided by the present invention, including a second insulating layer 508 and an opening 510 formed on the surface of the second insulating 508 through an exposure process, the active layer 504 is located in the opening 510, and the scanning line 509 and The data lines 505 are vertically distributed, and the materials of the data lines 505 and the scanning lines 509 are made of aluminum or copper.
  • the second pad high layer 507 in this embodiment can be replaced with an organic photoresist material
  • the organic material layer is a soluble polytetrafluoroethylene layer, an R/G/B tricolor superimposed layer, or a black matrix and other photoresist materials .
  • the film thickness of the second pad height 507 is the same as the film thickness of the pad height on the surface of the grid line of the glass substrate, and the film thickness of the second pad height 507 is 2um ⁇ 4um.
  • This embodiment is similar to the first embodiment and the second embodiment described above. The difference is that after the second pad high layer is deposited and the second pad high layer is patterned, it can also be ensured that the second area at the gate line has only the pad high layer first In the second part, the following process remains unchanged. This method can also reduce the delay effect of resistance and capacitance without affecting the performance of the thin film transistor device.
  • the method of reducing RC delay may be applied to an organic light-emitting diode (Organic Light-Emitting Diode (OLED) thin film transistor (TFT) technology development, or Quantum Dot Light Emitting Diodes (QLED) TFT technology development, or micro-diode TFT technology development.
  • OLED Organic Light-Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • the beneficial effects are as follows: starting from the direction of reducing the capacitance and increasing the thickness of the second insulating layer where the data line and the scanning line overlap, the second insulating layer is thickened under the premise that the thickness of the second insulating layer at the thin film transistor remains unchanged As the film thickness increases, that is, the distance becomes larger, it can be seen that the capacitance between the scanning line and the data line becomes smaller, which reduces the resistance-capacitance delay effect of the panel, thereby improving the display quality of the display panel.

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Abstract

一种阵列基板，包括玻璃基板(101)、栅极(102)、扫描线(109)、以及制备于基板(101)表面且覆盖栅极(102)和扫描线(109)的垫高层，垫高层包括对应于扫描线(109)的第一区域，及对应于栅极(102)的第二区域；垫高层包括第一垫高层(103)和第二垫高层(104)，第一垫高层(103)覆盖栅极(102)和扫描线(109)，第二垫高层(104)位于绝缘层的任意一侧。

Description

阵列基板及其制备方法 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制备方法。
 背景技术
随着液晶显示器的发展，高阶显示受到越来越多的重视，液晶显示的分辨率也越来越高，从高清度（Full High Definition，FHD）到超高清（High Definition，UD），在到目前各大显示器件争先开发的8K显示技术；分辨率的提升带来最直接的负面效应，就是栅极负载越来越大，电阻电容（Resistor Capacitor，RC）延迟成倍增长。
现有技术的降低电阻电容延迟的主要方法是降低电阻，例如用金属铜线代替铝线，还有就是增加铜的厚度，以此来降低电阻，而达到降低RC延迟的目的。
铜制程相对于铝制程而言，铜的蚀刻难度较高，需要使用到危险系数较高的氢氟酸（Hydro fluoric acid，HF），成本高。
增加铜的厚度，一方面铜的沉积时间增加，蚀刻时间也相应增加，增加了物料成本及时间成本；另一方面铜膜厚度增加还会带来基板应力过高导致翘曲的问题。
 技术问题
现有技术在降低RC延迟上存在着生产成本高和产品翘曲的问题。
 技术解决方案
本申请提供的阵列基板，通过增加扫描线与数据线在交叠处的距离，降低面板的RC延迟效应。
为解决上述问题，本申请提供的技术方案如下：
一种阵列基板，包括玻璃基板、制备于所述玻璃基板表面的栅极、扫描线、以及制备于所述基板表面且覆盖所述栅极和所述扫描线的垫高层，所述垫高层包括对应于所述扫描线的第一区域，以及对应于所述栅极的第二区域；
所述垫高层包括第一垫高层和第二垫高层，所述第一垫高层覆盖所述栅极和所述扫描线，所述第二垫高层位于所述绝缘层的任意一侧。
在本申请所提供的阵列基板中，所述垫高层的第一区域的高度，大于所述垫高层层的第二区域的高度。
在本申请所提供的阵列基板中，所述第一垫高层采用氮化硅制备，所述第二垫高层采用可溶性聚四氟乙烯层、R/G/B三基色叠加层或者黑色矩阵光阻材料制备。
在本申请所提供的阵列基板中，所述第二垫高层覆盖所述第二区域之外的区域。
在本申请所提供的阵列基板中，所述第二垫高层对应于所述第二区域的位置设有开口，所述栅极置于所述开口内。
在本申请所提供的阵列基板中，所述第一垫高层采用氮化硅制备，所述第二垫高层采用可溶性聚四氟乙烯层、R/G/B三基色叠加层或者黑色矩阵光阻材料制备。
在本申请所提供的阵列基板中，所述垫高层的厚度为300-800Å。
本申请还提供一种阵列基板，该阵列基板包括玻璃基板、制备于所述玻璃基板表面的栅极、扫描线、以及制备于所述基板表面且覆盖所述栅极和所述扫描线的垫高层，所述垫高层包括对应于所述扫描线的第一区域，以及对应于所述栅极的第二区域；
所述垫高层包括第一垫高层和第二垫高层，所述第一垫高层覆盖所述栅极和所述扫描线，所述第二垫高层位于所述绝缘层的任意一侧；
其中，所述第一垫高层采用氮化硅制备，所述第一垫高层的厚度为300-800Å；所述第二垫高层采用可溶性聚四氟乙烯层、R/G/B三基色叠加层或者黑色矩阵光阻材料制备。
在本申请所提供的阵列基板中，所述垫高层的第一区域的高度，大于所述垫高层层的第二区域的高度。
在本申请所提供的阵列基板中，所述第二垫高层设置于所述第一区域内。
在本申请所提供的阵列基板中，所述阵列基板包括阵列分布的像素单元，所述像素单元包括所述扫描线、与所述扫描线交错设置的数据线、以及连接所述扫描线和所述数据线的薄膜晶体管，所述第二垫高层位于所述扫描线与所述数据线的交叠处。
在本申请所提供的阵列基板中，所述第二垫高层覆盖所述第二区域之外的区域。
在本申请所提供的阵列基板中，所述第二垫高层对应于所述第二区域的位置设有开口，所述栅极置于所述开口内。
依据本申请的上述目的，提供一种阵列基板制备方法，所述方法还包括以下步骤：
步骤S10，提供玻璃基板，所述玻璃基板表面制备栅极和扫描线；
步骤S20，玻璃基板表面制备第一垫高层，所述第一垫高层覆盖所述栅极和扫描线；
步骤S30，第一垫高层表面显影曝光，剥离栅极表面的第一垫高层；
步骤S40，在第一垫高层表面制备有第二垫高层，并将所述第一垫高层和第二垫高层作为垫高层，所述垫高层包括对应于所述扫描线的第一区域，以及对应于所述栅极的第二区域，其中所述第二垫高层位于所述扫描线与所述数据线的交叠处；
步骤S50，对所述第二垫高层表面显影曝光，剥离所述扫描线上的第二垫高层，形成垫高层图案；
步骤S60，第二垫高层表面沉积数据线；
步骤S70，数据线表面沉积钝化层。
根据本申请提供的一种阵列基板制备方法，所述第二垫高层包括第二垫高层第一部分和第二垫高层第二部分，所述步骤S40，具体包括：
步骤S401，在第一垫高层上沉积第二垫高层第一部分，对所述第二垫高层第一部分表面显影曝光，保留所述扫描线一侧的第二垫高层第一部分，在所述扫描线和所述垫高层的交叠处留下第一绝缘层图案；
步骤S402，在所述第二垫高层第一部分表面沉积第二垫高层第二部分，使第二垫高层第二部分的膜厚及膜质与包含栅极第二区域的垫高层相同。
根据本申请提供的一种阵列基板制备方法，所述第二垫高层第一部分包括第一绝缘层、第二绝缘层与第三绝缘层，所述步骤S401，具体包括如下步骤：
S4011，对所述第一垫高层表面沉积第一绝缘层，形成第一绝缘层图案，保留所述扫描线一侧的第一垫高层；
S4012，在所述垫高层及绝缘层膜层表面沉积第二绝缘层，在所述薄膜晶体管表面间上挖开口，使所述薄膜晶体管表面有第二绝缘层图案；
S4013，在所述开口和所述第二层绝缘层表面沉积第三绝缘层，使所述第三绝缘层的膜厚及膜质与所述薄膜晶体管的第二绝缘层相同；
S4014，对所述第三绝缘层表面显影曝光，保留所述扫描线一侧的第二绝缘层，在所述扫描线和所述第一绝缘层的交叠处留下第二绝缘层图案。
 有益效果
本申请提供的阵列基板，通过增加扫描线与数据线在交叠处增加垫高层，提高扫描线与数据线之间的距离，降低面板的电阻电容延迟效应，进而提升了显示面板的显示品质。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a-1g为本申请提供的阵列基板实施例一的制备流程结构示意图。
图2为本申请实施例一提供的阵列基板的制备方法流程图。
图3a-图3e为本申请提供的阵列基板实施例二的流程结构示意图。
图4为本申请提供的阵列基板的第二垫高层结构示意图。
图5为本申请提供的像素结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本申请针对现有技术阵列基板中存在电阻电容延迟效应，从降低阵列单元数据线和扫描线的电容的方向出发，在沉积数据线之前，覆盖一层低介电常数的有机物材料，如可溶性聚四氟乙烯层、R/G/B三基色叠加层或者黑色矩阵（Black Martrix，BM）等光阻材料，并通过曝光显影，对其进行图形化，在数据线与扫描线交叠处制备所述有机物材料层，其膜厚为2um~4um，由电容的计算公式C=(εS)/d，在数据线与扫描线交叠处膜厚增加，且介电常数K值较小即ε变小，同时距离d变大，可知扫描线与数据线之间的电容变小，从而达到减小RC延迟的目的。
实施例一
图1a～图1g为本发明实施例提供的阵列基板的制备流程图。
如图1a所示，包括玻璃基板101，所述玻璃基板表面制备有栅极102和扫描线109。
如图1b所示，所述玻璃基板101表面制备有第一垫高层103，所述第一垫高层103覆盖所述栅极102和扫描线109。
如图1c所示，玻璃基板101表面剥离栅极102表面的第一垫高层103，保留有所述扫描线109表面的第一垫高层103。
如图1d所示，所述第一垫高层103，所述第一垫高层103表面制备有第二垫高层104，所述第二垫高层104位于所述扫描线109与所述数据线（图中未示出）的交叠处。
如图1e所示，所述第二垫高层104表面剥离所述扫描线上的第二垫高层104，保留有所述栅极102表面的第二垫高层104，形成垫高层图案。
如图1f所示，所述第二垫高层104表面沉积数据线105。
如图1g所示，所述数据线105表面沉积钝化层106。
如图2所示，本发明提供的阵列基板制备方法，所述方法包括：
步骤S10，提供玻璃基板，所述玻璃基板表面制备栅极和扫描线。
步骤S20，玻璃基板表面制备第一垫高层，所述第一垫高层覆盖所述栅极和扫描线。
步骤S30，第一垫高层表面显影曝光，剥离所述栅极表面的第一垫高层。
步骤S40，在第一垫高层表面制备有第二垫高层，并将所述第一垫高层和第二垫高层作为垫高层，所述垫高层包括对应于所述扫描线的第一区域，以及对应于所述栅极的第二区域，其中所述第二垫高层位于所述扫描线与所述数据线的交叠处。
步骤S50，对所述第二垫高层表面显影曝光，剥离所述扫描线上的第二垫高层，形成垫高层图案。
步骤S60，第二垫高层表面沉积数据线。
步骤S70，数据线表面沉积钝化层。
此方法制备的阵列基板，可以在不影响薄膜晶体管器件性能的前提下，降低电阻电容延迟。
本实施例从降低电容的方向出发，在处薄膜晶体管处的垫高层膜厚不变的前提下，增加数据线与扫描线交叠处的垫高层膜厚，由电容的计算公式C=(εS)/d，垫高层膜厚增加，即距离d变大，可知扫描线与数据线之间的电容变小，从而达到减小电阻电容延迟的目的。
实施例二
如图3a～图3e，本实施例是在本发明实施例一中图2步骤S30 后面进行，由图3a所示，可知本发明实施例的工艺流程已完成步骤S10-S40。
图3a～图3e为本申请实施例提供的阵列基板的制备流程图：
如图3a所示，包括玻璃基板301，所述玻璃基板表面制备有栅极302和扫描线309，所述玻璃基板301表面制备有第一垫高层303 ，以及所述第一垫高层303表面制备有第二垫高层第一部分304。
如图3b所示，所述第二垫高层第一部分304上制备有第二垫高层第二部分305。
如图3c所示，所述第二垫高层第二部分305表面进行显影曝光，剥离所述栅线302上的第二垫高层第二部分305，形成垫高层图案。
如图3d所示，所述第二垫高层304制备有数据线306。
如图3e所示，所述数据线306制备有钝化层307。
进一步的，所述第二垫高层304包括第二垫高层第一部分304和第二垫高层第二部分305，本发明提供的阵列基板制备方法根据所述方法包括：
步骤S401，在扫描线上沉积第二垫高层第一部分304，对所述第二垫高层第一部分304表面显影曝光，保留所述扫描线309一侧的第二垫高层304，在所述扫描线309和所述第二垫高层304的交叠处留下第一绝缘层图案；
步骤S402，在所述第二垫高层第一部分304表面沉积第二垫高层第二部分305，使第二垫高层第二部分305的膜厚及膜质与包含栅极的垫高层相同。
实施例三
本实施例是在本发明实施例一的图2中步骤S30后面进行，由图3a-图3e可知本申请实施例的工艺流程已经完成如下步骤S10-S30，并且在本实施例二中步骤S401具体包括：
步骤S4011，对所述垫高层表面沉积第一绝缘层，形成第一绝缘层图案，保留垫高层及绝缘层膜层。
步骤S4012，在所述垫高层膜层表面沉积第二绝缘层，并在第二绝缘层表面开设用以避开所述薄膜晶体管的开口，使所述薄膜晶体管表面有第二绝缘层图案。
步骤S4013，在所述开口和所述第二绝缘层层表面沉积第三绝缘层，使所述第三层绝缘层的膜厚及膜质与所述薄膜晶体管的第二绝缘层相同。
步骤S4014，对所述第三绝缘层表面显影曝光，保留所述扫描线一侧的第二绝缘层，在所述扫描线和所述第一绝缘层的交叠处留下第二绝缘层图案，即第一垫高层图案。
如图4，为步骤S4012中的第二绝缘层408，所述第二绝缘层408表面通过曝光工艺形成有所述开口410，所述薄膜晶体管位于所述开口410内。
进一步的，所述开口410面积刚好包裹所述栅极的第二区域。
如图5为本发明提供的像素结构示意图，包括第二绝缘层508以及第二绝缘508表面通过曝光工艺形成的开口510，所述有源层504位于所述开口510内，其中扫描线509和数据线505垂直分布，所述数据线505和所述扫描线509材料为采用铝或铜制备。
进一步的，本实施例中的第二垫高层507可以替换成有机光阻材料，所述有机材料层为可溶性聚四氟乙烯层、R/G/B三基色叠加层或者黑色矩阵等光阻材料。
进一步的，所述第二垫高层507的膜层厚度与所述玻璃基板栅线表面的垫高层的膜厚相同，所述第二垫高层507的膜层厚度为2um~4um。
本实施例和上述实施例一和实施例二的出发点类似，其差异在于沉积第二垫高层之后，并对第二垫高层图案化，同样可以保证栅线处的第二区域只有垫高层的第二部分，后面的制程不变，该方法同样可以在不影响薄膜晶体管器件的性能的前提下，降低电阻电容延迟效应。
在本实施例中，所述减小RC延迟的方法，可以应用于有机发光二极管（Organic Light-Emitting Diode，OLED）的薄膜晶体管（Thin Film Transistor，TFT）技术开发中，或量子点发光二极管（Quantum Dot Light Emitting Diodes，QLED）的TFT技术开发中，或微型二极管的TFT技术开发中。
有益效果为：本申请从降低电容的方向出发，在保障薄膜晶体管处第二绝缘层膜厚不变的前提下，增加数据线与扫描线交叠处的第二绝缘层厚，第二绝缘层膜厚增加，即距离变大，可知扫描线与数据线之间的电容变小，降低面板的电阻电容延迟效应，进而提升了显示面板的显示品质。
综上所述，虽然本申请已将优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (17)

  1. 一种阵列基板，其中，所述阵列基板包括玻璃基板、制备于所述玻璃基板表面的栅极、扫描线、以及制备于所述基板表面且覆盖所述栅极和所述扫描线的垫高层，所述垫高层包括对应于所述扫描线的第一区域，以及对应于所述栅极的第二区域；
    所述垫高层包括第一垫高层和第二垫高层，所述第一垫高层覆盖所述栅极和所述扫描线，所述第二垫高层位于所述绝缘层的任意一侧；
    其中，所述第一垫高层采用氮化硅制备，所述第一垫高层的厚度为300-800Å；所述第二垫高层采用可溶性聚四氟乙烯层、R/G/B三基色叠加层或者黑色矩阵光阻材料制备。
  2. 根据权利要求1所述的阵列基板，其中，所述垫高层的第一区域的高度，大于所述垫高层层的第二区域的高度。
  3. 根据权利要求2所述的阵列基板，其中，所述第二垫高层设置于所述第一区域内。
  4. 根据权利要求2所述的阵列基板，其中，所述阵列基板包括阵列分布的像素单元，所述像素单元包括所述扫描线、与所述扫描线交错设置的数据线、以及连接所述扫描线和所述数据线的薄膜晶体管，所述第二垫高层位于所述扫描线与所述数据线的交叠处。
  5. 根据权利要求2所述的阵列基板，其中，所述第二垫高层覆盖所述第二区域之外的区域。
  6. 根据权利要求4所述的阵列基板，其中，所述第二垫高层对应于所述第二区域的位置设有开口，所述栅极置于所述开口内。
  7. 一种阵列基板，其中，所述阵列基板包括玻璃基板、制备于所述玻璃基板表面的栅极、扫描线、以及制备于所述基板表面且覆盖所述栅极和所述扫描线的垫高层，所述垫高层包括对应于所述扫描线的第一区域，以及对应于所述栅极的第二区域；
    所述垫高层包括第一垫高层和第二垫高层，所述第一垫高层覆盖所述栅极和所述扫描线，所述第二垫高层位于所述绝缘层的任意一侧。
  8. 根据权利要求7所述的阵列基板，其中，所述垫高层的第一区域的高度，大于所述垫高层层的第二区域的高度。
  9. 根据权利要求7所述的阵列基板，其中，所述第一垫高层采用氮化硅制备，所述第二垫高层采用可溶性聚四氟乙烯层、R/G/B三基色叠加层或者黑色矩阵光阻材料制备。
  10. 根据权利要求8所述的阵列基板，其中，所述第二垫高层设置于所述第一区域内。
  11. 根据权利要求8所述的阵列基板，其中，所述阵列基板包括阵列分布的像素单元，所述像素单元包括所述扫描线、与所述扫描线交错设置的数据线、以及连接所述扫描线和所述数据线的薄膜晶体管，所述第二垫高层位于所述扫描线与所述数据线的交叠处。
  12. 根据权利要求8所述的阵列基板，其中，所述第二垫高层覆盖所述第二区域之外的区域。
  13. 根据权利要求11所述的阵列基板，其中，所述第二垫高层对应于所述第二区域的位置设有开口，所述栅极置于所述开口内。
  14. 根据权利要求7所述的阵列基板，其中，所述第一垫高层的厚度为300-800Å。
  15. 一种阵列基板制备方法，其中，所述方法还包括以下步骤：
    步骤S10，提供玻璃基板，所述玻璃基板表面制备栅极和扫描线；
    步骤S20，玻璃基板表面制备第一垫高层，所述第一垫高层覆盖所述栅极和扫描线；
    步骤S30，对所述第一垫高层表面显影曝光，剥离栅极表面的第一垫高层；
    步骤S40，在第一垫高层表面制备有第二垫高层，并将所述第一垫高层和第二垫高层作为垫高层，所述垫高层包括对应于所述扫描线的第一区域，以及对应于所述栅极的第二区域，其中所述第二垫高层位于所述扫描线与所述数据线的交叠处；
    步骤S50，对所述第二垫高层表面显影曝光，剥离所述扫描线上的第二垫高层，形成垫高层图案；
    步骤S60，第二垫高层表面沉积数据线；
    步骤S70，数据线表面沉积钝化层。
  16. 根据权利要求15所述的阵列基板制备方法，其中，所述第二垫高层包括第一部分和第二部分，所述步骤S40，具体包括：
    步骤S401，在第一垫高层上沉积第二垫高层第一部分，对所述第二垫高层第一部分表面显影曝光，保留所述扫描线一侧的第二垫高层第一部分，在所述扫描线和所述绝缘层的交叠处留下第一垫高层图案；
    步骤S402，在所述第二垫高层第一部分表面沉积第二垫高层第二部分，使第二垫高层第二部分的膜厚及膜质与包含栅极第二区域的垫高层相同。
  17. 根据权利要求16所述的真理基板的制备方法，其中，所述第二垫高层第一部分包括第一绝缘层、第二绝缘层与第三绝缘层，所述步骤S401，具体包括如下步骤：
    步骤S4011，对所述第一垫高层表面沉积第一绝缘层，形成第一绝缘层图案，保留所述扫描线一侧的第一垫高层；
    步骤S4012，在所述垫高层及绝缘层膜层表面沉积第二绝缘层，在所述薄膜晶体管表面间上挖开口，使所述薄膜晶体管表面有第二绝缘层图案；
    步骤S4013，在所述开口和所述第二层绝缘层表面沉积第三绝缘层，使所述第三绝缘层的膜厚及膜质与所述薄膜晶体管的第二绝缘层相同；
    步骤S4014，对所述第三绝缘层表面显影曝光，保留所述扫描线一侧的第二绝缘层，在所述扫描线和所述第一绝缘层的交叠处留下第二绝缘层图案，即第一垫高层图案。
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