WO2020133740A1 - 扫描信号生成方法及装置 - Google Patents

扫描信号生成方法及装置 Download PDF

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Publication number
WO2020133740A1
WO2020133740A1 PCT/CN2019/078797 CN2019078797W WO2020133740A1 WO 2020133740 A1 WO2020133740 A1 WO 2020133740A1 CN 2019078797 W CN2019078797 W CN 2019078797W WO 2020133740 A1 WO2020133740 A1 WO 2020133740A1
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WO
WIPO (PCT)
Prior art keywords
signal
signals
scan
logic
target clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/078797
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English (en)
French (fr)
Inventor
张鑫
肖军城
田超
管延庆
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US16/612,146 priority Critical patent/US10930193B2/en
Publication of WO2020133740A1 publication Critical patent/WO2020133740A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given

Definitions

  • the present application relates to the field of display technology, and in particular, to a scanning signal generation method, device, and electronic equipment.
  • GOA Gate Driver on Array
  • Chinese full name: integrated gate drive circuit integrates the gate drive circuit on the array substrate of the display panel, so that the gate drive integrated circuit part can be omitted, from the material cost and The production process reduces the product cost in two aspects.
  • the existing GOA circuit is mainly designed in the form of a shift register, that is, the start signal and the clock signal provided by the driver chip are used to shift the start signal, and a certain number of shift registers are used to obtain the display panel drive required. Scan the signal.
  • the purpose of the embodiments of the present application is to provide a method, device and electronic device for generating a scanning signal, which can solve the high GOF circuit function requirements for the driving chip, resulting in a higher cost technical problem.
  • An embodiment of the present application provides a method for generating a scanning signal, which is applied to a driving chip, and the driving chip is electrically connected to a plurality of scanning lines, wherein the method for generating a scanning signal includes:
  • the step of processing the initial clock signal to generate a plurality of target clock signals includes:
  • a frequency divider may be used to divide the initial clock signal.
  • the step of encoding a plurality of the target clock signals according to a preset logic relationship to generate a plurality of ordered logic signals includes:
  • the step of decoding a plurality of the ordered logic signals and generating a plurality of scan signals according to the decoding result includes:
  • An embodiment of the present application also provides a scanning signal generation method, which is applied to a driving chip, and the driving chip is electrically connected to a plurality of scanning lines, respectively.
  • the scanning signal generation method includes:
  • the step of processing the initial clock signal to generate a plurality of target clock signals includes:
  • a frequency divider may be used to divide the initial clock signal.
  • the step of encoding a plurality of the target clock signals according to a preset logic relationship to generate a plurality of ordered logic signals includes:
  • the step of decoding a plurality of the ordered logic signals and generating a plurality of scan signals according to the decoding result includes:
  • An embodiment of the present application further provides a scanning signal generating device, including:
  • Acquisition module used to acquire the initial clock signal
  • a processing module configured to process the initial clock signal to generate multiple target clock signals
  • An encoding module configured to encode multiple target clock signals according to a preset logical relationship to generate multiple ordered logical signals
  • a decoding module configured to decode a plurality of the ordered logic signals and generate a plurality of scan signals according to the decoding result, wherein the scan signals correspond to the scan lines in one-to-one correspondence;
  • the processing module includes:
  • An acquiring unit for acquiring row and column information of pixel units connected to a plurality of scanning lines
  • Frequency dividing unit the frequency dividing unit is used to divide the initial clock signal according to the row and column information to generate multiple target clock signals, wherein the frequency of the i-th target clock signal is the initial clock 1/2 i of the frequency of the signal, i is a positive integer greater than 0.
  • a frequency divider may be used to divide the initial clock signal.
  • the encoding module includes:
  • a dividing unit configured to divide each of the target clock signals into a plurality of time periods, and obtain a logical value of each of the target clock signals in each of the time periods;
  • a combining unit configured to combine the logic values corresponding to a plurality of the target clock signals to obtain an ordered logic signal corresponding to each time period.
  • the decoding module includes:
  • a searching unit the searching unit is used for searching a scanning logic signal corresponding to the ordered logic signal in the decoding truth table
  • a generating unit configured to generate a corresponding scan signal according to the scan logic signal.
  • An embodiment of the present application further provides an electronic device, including a processor and a memory, a computer program is stored in the memory, and the processor is used to execute the above-mentioned by calling the computer program stored in the memory Scanning signal generation method.
  • the method, device and electronic device for generating a scan signal process the initial clock signal by acquiring the initial clock signal to generate multiple target clock signals, and multiple target clocks according to a preset logical relationship
  • the signal is encoded to generate multiple ordered logic signals, the multiple ordered logic signals are decoded, and multiple scan signals are generated according to the decoding result, so that one initial clock signal is used to generate multiple scan signals. Avoid using too many shift registers to drive the display panel.
  • FIG. 1 is a schematic flowchart of a scanning signal generation method provided by an embodiment of the present application
  • FIG. 2 is a schematic flowchart of step S102 in the scan signal generation method shown in FIG. 1;
  • FIG. 3 is a schematic flowchart of step S103 in the scan signal generation method shown in FIG. 1;
  • step S104 is a schematic flowchart of step S104 in the scan signal generation method shown in FIG. 1;
  • FIG. 5 is a schematic structural diagram of generating eight scanning signals by using the scanning line generating method according to an embodiment of the present application
  • FIG. 6 is a first timing diagram corresponding to generating 8 scan signals shown in FIG. 5;
  • FIG. 7 is a schematic diagram of encoding corresponding to generating 8 scan signals shown in FIG. 5;
  • FIG. 8 is a decoding truth table corresponding to eight scan signals generated as shown in FIG. 5;
  • FIG. 9 is a second timing diagram for generating 8 scan signals shown in FIG. 5;
  • FIG. 10 is a schematic structural diagram of a scan signal generation device provided by an embodiment of the present application.
  • first and second are used for description purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
  • the features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more, unless otherwise specifically limited.
  • connection should be understood in a broad sense, for example, it can be fixed or detachable Connected, or integrally connected; may be mechanical, electrical, or may communicate with each other; may be directly connected, or may be indirectly connected through an intermediary, may be interconnected within two components or interacted between two components relationship.
  • installation should be understood in a broad sense, for example, it can be fixed or detachable Connected, or integrally connected; may be mechanical, electrical, or may communicate with each other; may be directly connected, or may be indirectly connected through an intermediary, may be interconnected within two components or interacted between two components relationship.
  • the first feature “above” or “below” the second feature may include the direct contact of the first and second features, or may include the first and second features Not direct contact but contact through another feature between them.
  • the first feature is “above”, “above” and “above” the second feature includes that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is higher in level than the second feature.
  • the first feature is “below”, “below”, and “below” the second feature includes that the first feature is directly below and obliquely below the second feature, or simply means that the first feature is less horizontal than the second feature.
  • the scanning signal generation method provided by the embodiment of the present application is applied to a driving chip.
  • the driving chip may be any chip in the display panel.
  • the embodiments of the present application are intended to illustrate that the scan signal generation method is integrated in the chip to achieve corresponding functions.
  • the driving chip is electrically connected to a plurality of scanning lines.
  • the scan signal generation method provided by the embodiment of the present application outputs the generated multiple scan signals to multiple scan lines. That is, the multiple scan signals generated by the scan signal generation method provided in the embodiments of the present application correspond one-to-one to multiple scan lines.
  • FIG. 1 is a schematic flowchart of a scanning signal generation method according to an embodiment of the present application.
  • the scan signal generation method provided by the embodiments of the present application includes:
  • the initial clock signal is a signal with a certain frequency value and amplitude. That is, the initial clock signal is switched back and forth between a high level and a low level at a certain frequency.
  • the initial clock signal can set the frequency and amplitude according to the needs of users.
  • the driving chip works, the user can input the frequency value and amplitude according to specific needs, so that the driving chip can directly obtain the initial clock signal corresponding to the frequency value and amplitude.
  • S102 Process the initial clock signal to generate multiple target clock signals.
  • the target clock signal is a signal generated by the driving chip according to the acquired initial clock signal and having an amplitude equal to the initial clock signal and a frequency not equal. Also, the frequencies between different target clock signals are not equal.
  • step S102 includes:
  • S1021 Obtain row and column information of pixel units connected to the multiple scan lines.
  • the row and column information is the number of rows of pixel units of the display panel. For example, for a 1024-level display panel, it requires 1024 scan signals, that is, at this time, the number of rows of pixel units of the display panel is 1024.
  • the number of rows of the pixel unit of the display panel is 1024, that is, 10 target clock signals need to be generated at this time.
  • a frequency divider can be used to divide the initial clock signal.
  • a frequency divider can be used to divide the initial clock signal to obtain the first target clock signal.
  • the first target clock signal is divided by two to obtain the second target clock signal.
  • the second target clock signal is divided by two to obtain the third target clock signal.
  • the third target clock signal is divided by two to obtain the fourth target clock signal.
  • the fourth target clock signal is divided by two to obtain the fifth target clock signal.
  • the fifth target clock signal is divided by two to obtain the sixth target clock signal.
  • the sixth target clock signal is divided by two to obtain the seventh target clock signal.
  • the seventh target clock signal is divided by two to obtain the eighth target clock signal.
  • the eighth target clock signal is divided by two to obtain the ninth target clock signal.
  • the ninth target clock signal is divided by two to obtain the tenth target clock signal.
  • the ordered logic signal is formed by combining a plurality of logic signals according to a preset logic relationship.
  • the logic signal is a signal with two states. That is, the value of the logic signal may be 0 or 1.
  • the target clock signal generated in step 101 when the target clock signal is at a high level, the corresponding logic signal is 1; when the target clock signal is at a low level, the corresponding logic signal is 0.
  • the number of logic signals in the ordered logic signal is consistent with the number of target clock signals.
  • an ordered logic signal includes a logic signal corresponding to each target clock signal. For example, when three target clock signals are generated in step 102, the ordered logic signals may be: 000, 001, 010, 011, 100, 101, 110, 111.
  • step S103 includes:
  • S1031 Divide each target clock signal into a plurality of time periods, and obtain the logic value of each target clock signal in each time period.
  • the interval of each time period is the same, and the interval of each time period is equal to the period of the initial clock signal. It should be noted that the level value of any target clock signal at any time period is high level or low level. That is, the logical value corresponding to any target clock signal in any time period is 1 or 0.
  • S1032 Combine the logical values corresponding to the multiple target clock signals to obtain an ordered logical signal corresponding to each time period.
  • the first bit of the ordered logic signal is the logic value of the first target clock signal in the corresponding time period
  • the second bit of the ordered logic signal is the second target clock signal in the corresponding time period Logical value.
  • the last bit of the ordered logic signal is the logic value of the last target clock signal in the corresponding time period.
  • 001 indicates that the logical value of the first target clock signal in the corresponding time period is 1, and the logical value of the second target clock signal in the corresponding time period is 0 , The logical value of the third target clock signal in the corresponding time period is 0.
  • S104 Decode multiple ordered logic signals and generate multiple scan signals according to the decoding result.
  • step S104 includes:
  • S1042 Generate a corresponding scan signal according to the scan ordered logic signal.
  • the initial clock signal is processed to generate multiple target clock signals, and the multiple target clock signals are encoded according to a preset logical relationship to generate multiple Sequential logic signals, decode multiple ordered logic signals, and generate multiple scan signals according to the decoding results, so that an initial clock signal is used to generate multiple scan signals, which can avoid the use of too many shift registers, which can be achieved Driver for the display panel.
  • FIG. 5 is a schematic structural diagram of generating eight scan signals by using the scan line generation method according to an embodiment of the present application.
  • the scan line generating method of the embodiment of the present application first acquires the initial clock signal CK0; and then processes the initial clock signal CK0 to generate the first target clock signal CK1, the second target clock signal CK2 and The third target clock signal CK3; then, the first target clock signal CK1, the second target clock signal CK2 and the third target clock signal CK3 are encoded according to the preset logical relationship to generate the first order Logic signal S1, second ordered logic signal S2, third ordered logic signal S3, fourth ordered logic signal S4, fifth ordered logic signal S5, sixth ordered logic signal S6, first 7 ordered logic signals S7 and the 8th ordered logic signal S8; finally, the first ordered logic signal S1, the second ordered logic signal S2, the third ordered logic signal S3, the fourth The ordered logic signal S4, the fifth ordered logic signal S5, the sixth ordered logic signal S6, the seventh ordered logic signal S7 and the eighth ordered logic
  • FIG. 6 is a first timing diagram corresponding to generating 8 scan signals shown in FIG. 5.
  • the period of the initial clock signal CK0 is 2T, that is, the frequency of the initial clock signal CK0 is 1/2T.
  • the initial clock signal CK0 switches back and forth between a high level and a low level at a frequency of 1/2T.
  • the first target clock signal CK1 switches back and forth between a high level and a low level at a frequency of 1/4T.
  • the second target clock signal CK2 switches back and forth between a high level and a low level at a frequency of 1/8T.
  • the third target clock signal CK3 switches back and forth between a high level and a low level at a frequency of 1/16T.
  • FIG. 7 is a schematic diagram of encoding corresponding to generating 8 scan signals shown in FIG. 5.
  • the first target clock signal CK1 is divided into multiple time periods
  • the second target clock signal CK2 is divided into multiple time periods
  • the third target clock signal CK3 is divided into Divided into multiple time periods.
  • the interval of each time period is 2T, and each time period corresponds to a logical value.
  • the logic value of the first clock signal CK1 in the first time period t1 is 0, the logic value of the first clock signal CK1 in the second time period t2 is 1, and the logic value of the first clock signal CK1 in the third time period t3
  • the value is 0, the logic value of the first clock signal CK1 in the fourth time period t4 is 1, the logic value of the first clock signal CK1 in the fifth time period t5 is 0, and the logic value of the first clock signal CK1 is in the sixth time
  • the logical value of the segment t6 is 1, the logical value of the first clock signal CK1 in the seventh period t7 is 0, and the logical value of the first clock signal CK1 in the eighth period t8 is 1.
  • the logic value of the second clock signal CK2 in the first time period t1 is 0, the logic value of the second clock signal CK2 in the second time period t2 is 0, and the logic value of the second clock signal CK2 in the third time period t3
  • the value is 1, the logical value of the second clock signal CK2 in the fourth time period t4 is 1, the logical value of the second clock signal CK2 in the fifth time period t5 is 0, and the second clock signal CK2 is in the sixth time
  • the logical value of the segment t6 is 0, the logical value of the second clock signal CK2 in the seventh period t7 is 1, and the logical value of the second clock signal CK2 in the eighth period t8 is 1.
  • the logic value of the third clock signal CK3 in the first time period t1 is 0, the logic value of the third clock signal CK3 in the second time period t2 is 0, and the logic value of the third clock signal CK3 in the third time period t3
  • the value is 0, the logical value of the third clock signal CK3 in the fourth time period t4 is 0, the logical value of the third clock signal CK3 in the fifth time period t5 is 1, and the logical value of the third clock signal CK3 is at the sixth time
  • the logical value of the segment t6 is 1, the logical value of the third clock signal CK3 in the seventh period t7 is 1, and the logical value of the third clock signal CK3 is 1 in the eighth period t8.
  • the ordered logic signal S1 in the first time period t1 is 000
  • the ordered logic signal S2 in the second time period t2 is 001
  • the ordered logic signal S3 in the third time period t3 is 010
  • the ordered logic signal S4 in the time period t4 is 011
  • the ordered logic signal S5 in the fifth time period t5 is 100
  • the ordered logic signal S6 in the sixth time period t6 is 101
  • the sequence logic signal S7 is 110
  • the sequence logic signal S8 in the eighth time period t8 is 111.
  • FIG. 8 is a decoding truth table corresponding to the eight scan signals shown in FIG.
  • FIG. 9 is a second timing diagram for generating 8 scan signals shown in FIG. 5. As shown in FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG.
  • the scan logic signal corresponding to the first ordered logic signal S1 is 10000000
  • the scan logic signal corresponding to the second ordered logic signal S2 is 01000000
  • the scan logic signal corresponding to the third order logic signal S3 is 00100000
  • the scan logic signal corresponding to the fourth order logic signal S4 is 00010000
  • the scan logic signal corresponding to the fifth order logic signal S5 is 00001000
  • the sixth The scan logic signal corresponding to the ordered logic signal S6 is 00000100
  • the scan logic signal corresponding to the seventh ordered logic signal S7 is 00000010
  • the scan logic signal corresponding to the eighth ordered logic signal S8 is 00000001.
  • the first scan signal Gate1, the second scan signal Gate2, the third scan signal Gate3, the fourth scan signal Gate4, the fifth scan signal Gate5, and the sixth scan signal can be generated based on the decoded scan logic signal Gate6, the seventh scan signal Gate7 and the eighth scan signal Gate8.
  • FIG. 10 is a schematic structural diagram of a scanning signal generating apparatus according to an embodiment of the present application.
  • the scan signal generating device 20 includes an acquisition module 201, a processing module 202, an encoding module 203, and a decoding module 204.
  • the obtaining module 201 is used to obtain an initial clock signal.
  • the processing module 202 is configured to process the initial clock signal to generate multiple target clock signals.
  • the encoding module 203 is configured to encode multiple target clock signals according to a preset logical relationship to generate multiple ordered logical signals.
  • the decoding module 204 is used to decode multiple ordered logic signals and generate multiple scan signals according to the decoding result.
  • the processing module 202 includes an acquisition unit 2021 and a frequency division unit 2022.
  • the obtaining unit 2021 is used to obtain the row and column information of the pixel units connected to the multiple scanning lines.
  • the frequency dividing unit 2022 is used to divide the initial clock signal according to the row and column information to generate a plurality of target clock signals.
  • the encoding module 203 includes a dividing unit 2031 and a combining unit 2032.
  • the dividing unit 2031 is used to divide each target clock signal into a plurality of time periods, and obtain the logic value of each target clock signal in each time period.
  • the combining unit 2032 is used to combine the logical values corresponding to the multiple target clock signals to obtain the ordered logical signals corresponding to each time period.
  • the decoding module 204 includes a search unit 2041 and a generation unit 2042.
  • the searching unit 2041 is used to search the scan logic signal corresponding to the ordered logic signal in the decoding truth table.
  • the generating unit 2042 is used to generate a corresponding scan signal according to the scan logic signal.
  • An embodiment of the present application also provides an electronic device, including a processor and a memory, a computer program stored in the memory, and the processor is used for the scan signal generation method in the foregoing embodiment by calling the computer program stored in the memory, To achieve the following functions: obtain the initial clock signal; process the initial clock signal to generate multiple target clock signals; encode the multiple target clock signals according to the preset logical relationship to generate multiple ordered logic signals; An ordered logic signal is decoded, and multiple scan signals are generated according to the decoding result, wherein the scan signals correspond to the scan lines one-to-one.
  • the storage medium may include but is not limited to: read only memory (ROM, Read Only Memory), random access memory (RAM, Random Access Memory), magnetic disk, or optical disk.

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

扫描信号（Gate1, Gate2, …Gate8）生成方法及装置（20），获取初始时钟信号（CK0）（S101），对初始时钟信号（CK0）进行处理，以生成多个目标时钟信号（CK1, CK2, CK3）（S102），根据预设逻辑关系对多个目标时钟信号（CK1, CK2, CK3）进行编码，以生成多个有序逻辑信号（S1, S2, …S8）（S103），对多个有序逻辑信号（S1, S2, …S8）进行译码，并根据译码结果生成多个扫描信号（Gate1, Gate2, …Gate8）（S104）。

Description

[根据细则37.2由ISA制定的发明名称]　扫描信号生成方法及装置 技术领域
本申请涉及显示技术领域，特别涉及一种扫描信号生成方法、装置及电子设备。
 背景技术
GOA( 英文全称：Gate Driver on Array ，中文全称：集成栅极驱动电路)技术将栅极驱动电路集成在显示面板的阵列基板上，从而可以省掉栅极驱动集成电路部分，以从材料成本和制作工艺两方面降低产品成本。
现有的GOA电路主要是以移位寄存器的方式设计，即利用驱动芯片提供的起始信号和时钟信号对起始信号进行移位传递，利用一定数量的移位寄存器得到显示面板驱动所需要的扫描信号。
 技术问题
本申请实施例的目的是提供一种扫描信号生成方法、装置及电子设备，能解决现有的GOA电路对驱动芯片的功能需求高，从而导致成本较高的技术问题。
 技术解决方案
本申请实施例提供一种扫描信号生成方法，应用于驱动芯片中，所述驱动芯片分别与多条扫描线电性连接，其中，所述扫描信号生成方法包括：
获取初始时钟信号，所述初始时钟信号在高电平和低电平之间来回切换；
对所述初始时钟信号进行处理，以生成多个目标时钟信号；
根据预设逻辑关系对多个所述目标时钟信号进行编码，以生成多个有序逻辑信号；
对多个所述有序逻辑信号进行译码，并根据译码结果生成多个扫描信号，其中，所述扫描信号与所述扫描线一一对应。
在本申请所述的扫描信号生成方法中，所述对所述初始时钟信号进行处理，以生成多个目标时钟信号的步骤包括：
获取与多条所述扫描线相连接的像素单元的行列信息；
根据所述行列信息对所述初始时钟信号进行分频处理，以生成多个目标时钟信号，其中，第i个目标时钟信号的频率为所述初始时钟信号的频率的1/2 i,i为大于0的正整数。
在本申请所述的扫描信号生成方法中，可采用二分频器对所述初始时钟信号进行分频处理。
在本申请所述的扫描信号生成方法中，所述根据预设逻辑关系对多个所述目标时钟信号进行编码，以生成多个有序逻辑信号的步骤包括：
将每个所述目标时钟信号划分成多个时间段，并获取每个所述目标时钟信号在每个所述时间段的逻辑值；
将多个所述目标时钟信号对应的所述逻辑值进行组合，以得到每个所述时间段对应的有序逻辑信号。
在本申请所述的扫描信号生成方法中，所述对多个所述有序逻辑信号进行译码，并根据译码结果生成多个扫描信号的步骤包括：
在译码真值表中查找与所述有序逻辑信号对应的扫描逻辑信号；
根据所述扫描逻辑信号生成对应的扫描信号。
本申请实施例还提供一种扫描信号生成方法，应用于驱动芯片中，所述驱动芯片分别与多条扫描线电性连接，所述扫描信号生成方法包括：
获取初始时钟信号；
对所述初始时钟信号进行处理，以生成多个目标时钟信号；
根据预设逻辑关系对多个所述目标时钟信号进行编码，以生成多个有序逻辑信号；
对多个所述有序逻辑信号进行译码，并根据译码结果生成多个扫描信号，其中，所述扫描信号与所述扫描线一一对应。
在本申请所述的扫描信号生成方法中，所述对所述初始时钟信号进行处理，以生成多个目标时钟信号的步骤包括：
获取与多条所述扫描线相连接的像素单元的行列信息；
根据所述行列信息对所述初始时钟信号进行分频处理，以生成多个目标时钟信号，其中，第i个目标时钟信号的频率为所述初始时钟信号的频率的1/2 i,i为大于0的正整数。
在本申请所述的扫描信号生成方法中，可采用二分频器对所述初始时钟信号进行分频处理。
在本申请所述的扫描信号生成方法中，所述根据预设逻辑关系对多个所述目标时钟信号进行编码，以生成多个有序逻辑信号的步骤包括：
将每个所述目标时钟信号划分成多个时间段，并获取每个所述目标时钟信号在每个所述时间段的逻辑值；
将多个所述目标时钟信号对应的所述逻辑值进行组合，以得到每个所述时间段对应的有序逻辑信号。
在本申请所述的扫描信号生成方法中，所述对多个所述有序逻辑信号进行译码，并根据译码结果生成多个扫描信号的步骤包括：
在译码真值表中查找与所述有序逻辑信号对应的扫描逻辑信号；
根据所述扫描逻辑信号生成对应的扫描信号。
本申请实施例还提供一种扫描信号生成装置，包括：
获取模块，用于获取初始时钟信号；
处理模块，用于对所述初始时钟信号进行处理，以生成多个目标时钟信号；
编码模块，用于根据预设逻辑关系对多个所述目标时钟信号进行编码，以生成多个有序逻辑信号；
译码模块，用于对多个所述有序逻辑信号进行译码，并根据译码结果生成多个扫描信号，其中，所述扫描信号与所述扫描线一一对应；
在本申请所述的扫描信号生成装置中，所述处理模块包括：
获取单元，所述获取单元用于获取与多条扫描线相连接的像素单元的行列信息；
分频单元，所述分频单元用于根据所述行列信息对所述初始时钟信号进行分频处理，以生成多个目标时钟信号，其中，第i个目标时钟信号的频率为所述初始时钟信号的频率的1/2 i,i为大于0的正整数。
在本申请所述的扫描信号生成装置中，可采用二分频器对所述初始时钟信号进行分频处理。
在本申请所述的扫描信号生成装置中，所述编码模块包括：
划分单元，所述划分单元用于将每个所述目标时钟信号划分成多个时间段，并获取每个所述目标时钟信号在每个所述时间段的逻辑值；
组合单元，所述组合单元用于将多个所述目标时钟信号对应的所述逻辑值进行组合，以得到每个所述时间段对应的有序逻辑信号。
在本申请所述的扫描信号生成装置中，所述译码模块包括：
查找单元，所述查找单元用于在译码真值表中查找与所述有序逻辑信号对应的扫描逻辑信号；
生成单元，所述生成单元用于根据所述扫描逻辑信号生成对应的扫描信号。
本申请实施例还提供一种电子设备，包括处理器和存储器，所述存储器中存储有计算机程序，所述处理器通过调用所述存储器中存储的所述计算机程序，用于执行以上所述的扫描信号生成方法。
 有益效果
本申请实施例的扫描信号生成方法、装置及电子设备，通过获取初始时钟信号，对所述初始时钟信号进行处理，以生成多个目标时钟信号，根据预设逻辑关系对多个所述目标时钟信号进行编码，以生成多个有序逻辑信号，对多个所述有序逻辑信号进行译码，并根据译码结果生成多个扫描信号，从而采用一个初始时钟信号生成多个扫描信号，可以避免采用过多移位寄存器，即可实现对显示面板的驱动。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的扫描信号生成方法的流程示意图；
图2为图1所示的扫描信号生成方法中步骤S102的具体流程示意图；
图3为图1所示的扫描信号生成方法中步骤S103的具体流程示意图；
图4为图1所示的扫描信号生成方法中步骤S104的具体流程示意图；
图5为采用本申请实施例的扫描线生成方法生成8个扫描信号的结构示意图；
图6为图5所示生成8个扫描信号对应的第一时序图；
图7为图5所示生成8个扫描信号对应的编码示意图；
图8为图5所示生成8个扫描信号对应的译码真值表；
图9为图5所示生成8个扫描信号的第二时序图；
图10为本申请实施例提供的扫描信号生成装置的结构示意图。
 本发明的实施方式
下面详细描述本申请的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本申请，而不能理解为对本申请的限制。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
本申请实施例提供的扫描信号生成方法，应用于驱动芯片中。需要说明的是，该驱动芯片可以是显示面板中的任意一种芯片，本申请实施例旨在说明将该扫描信号生成方法集成在该芯片中，以实现相应的功能。其中，该驱动芯片分别与多条扫描线电性连接。本申请实施例提供的扫描信号生成方法将生成的多个扫描信号输出至多条扫描线。也即，本申请实施例提供的扫描信号生成方法生成的多个扫描信号与多条扫描线一一对应。
请参阅图1，图1为本申请实施例提供的扫描信号生成方法的流程示意图。如图1所示，本申请实施例提供的扫描信号生成方法包括：
S101、获取初始时钟信号。
其中，该初始时钟信号为具有一定频率值、幅值的信号。也即，该初始时钟信号是以一定的频率在高电平和低电平之间来回切换。另外，该初始时钟信号可以根据用户的需要设置频率、幅值的大小。
例如，当驱动芯片工作时，用户可以根据具体需要输入频率值和幅值，从而驱动芯片可以直接获取与该频率值和幅值相对应的初始时钟信号。
S102、对所述初始时钟信号进行处理，以生成多个目标时钟信号。
其中，该目标时钟信号为驱动芯片根据获取到的初始时钟信号生成的与初始时钟信号幅值相等、频率不相等的信号。并且，不同目标时钟信号之间的频率也不相等。
在一些实施例中，请参阅图2，图2为图1所示的扫描信号生成方法中步骤S102的具体流程示意图。如图2所示，步骤S102包括：
S1021、获取与多条所述扫描线相连接的像素单元的行列信息。
其中，该行列信息为显示面板的像素单元的行数。例如，对于一个1024级的显示面板，其需要1024个扫描信号，也即，此时，该显示面板的像素单元的行数为1024。
S1022、根据所述行列信息对所述初始时钟信号进行分频处理，以生成多个目标时钟信号。
其中，生成的目标时钟信号的数量可以根据步骤1021中获取的行列信息得到。也即，生成的目标时钟信号的数量可以根据以下关系式得到：A=2 B，A为显示面板的像素单元的行数，B为生成的目标时钟信号的数量。
例如，同样以一个1024级显示面板为例，其需要1024个扫描信号，此时，该显示面板的像素单元的行数为1024，也即，此时需要生成10个目标时钟信号。
另外，生成的目标时钟信号的频率与初始时钟信号的频率也是有关的，可以根据以下关系式得到：C i=D*1/2 i，C为第i个目标时钟信号的频率，D为初始时钟信号的频率，,i为大于0的正整数。
进一步的，可采用二分频器对初始时钟信号进行分频处理。例如，同样以一个1024级显示面板为例，可采用二分频器对初始时钟信号进行分频，得到第1个目标时钟信号。接着，对第1个目标时钟信号进行二分频，得到第2个目标时钟信号。再接着，对第2个目标时钟信号进行二分频，得到第3个目标时钟信号。再接着，对第3个目标时钟信号进行二分频，得到第4个目标时钟信号。再接着，对第4个目标时钟信号进行二分频，得到第5个目标时钟信号。再接着，对第5个目标时钟信号进行二分频，得到第6个目标时钟信号。再接着，对第6个目标时钟信号进行二分频，得到第7个目标时钟信号。再接着，对第7个目标时钟信号进行二分频，得到第8个目标时钟信号。再接着，对第8个目标时钟信号进行二分频，得到第9个目标时钟信号。最后，对第9个目标时钟信号进行二分频，得到第10个目标时钟信号。
S103、根据预设逻辑关系对多个所述目标时钟信号进行编码，以生成多个有序逻辑信号。
其中，该有序逻辑信号为多个逻辑信号按照预设逻辑关系组合形成的。需要说明的是，逻辑信号为具有两种状态的信号。也即，逻辑信号的值可以为0，也可以为1。另外，在步骤101中生成的目标时钟信号中，当目标时钟信号为高电平时，其对应的逻辑信号则为1；当目标时钟信号为低电平时，其对应的逻辑信号则为0。
进一步的，该有序逻辑信号中逻辑信号的数量与目标时钟信号的数量一致。并且一个有序逻辑信号中包括每个目标时钟信号对应的一个逻辑信号。例如，当步骤102中生成3个目标时钟信号时，则，有序逻辑信号可以为：000、001、010、011、100、101、110、111。
在一些实施例中，请参阅图3，图3为图1所示的扫描信号生成方法中步骤S103的具体流程示意图。如图3所示，步骤S103包括：
S1031、将每个所述目标时钟信号划分成多个时间段，并获取每个所述目标时钟信号在每个所述时间段的逻辑值。
其中，每个时间段的间隔均相同，且每个时间段的间隔均等于初始时钟信号的周期。需要说明的是，任一目标时钟信号在任一时间段的电平值为高电平或低电平。也即，任一目标时钟信号在任一时间段对应的逻辑值为1或0。
S1032、将多个所述目标时钟信号对应的所述逻辑值进行组合，以得到每个所述时间段对应的有序逻辑信号。
其中，从右往左数，该有序逻辑信号第1位为第1个目标时钟信号在相应时间段的逻辑值，该有序逻辑信号第2为第2个目标时钟信号在相应时间段的逻辑值。以此类推，该有序逻辑信号最后1位为最后1个目标时钟信号在相应时间段的逻辑值。
例如，同样以当步骤102中生成3个目标时钟信号为例，001表示第1个目标时钟信号在相应时间段的逻辑值为1，第2个目标时钟信号在相应时间段的逻辑值为0，第3个目标时钟信号在相应时间段的逻辑值为0。
S104、对多个所述有序逻辑信号进行译码，并根据译码结果生成多个扫描信号。
在一些实施例中，请参阅图4，图4为图1所示的扫描信号生成方法中步骤S104的具体流程示意图。如图4所示，步骤S104包括：
S1041、在译码真值表中查找与所述有序逻辑信号对应的扫描逻辑信号。
S1042、根据所述扫描有序逻辑信号生成对应的扫描信号。
本申请实施例的扫描信号生成方法，通过获取初始时钟信号，对初始时钟信号进行处理，以生成多个目标时钟信号，根据预设逻辑关系对多个目标时钟信号进行编码，以生成多个有序逻辑信号，对多个有序逻辑信号进行译码，并根据译码结果生成多个扫描信号，从而采用一个初始时钟信号生成多个扫描信号，可以避免采用过多移位寄存器，即可实现对显示面板的驱动。
下面将以生成8个扫描信号为例对本申请实施例的扫描信号生成方法进行具体说明。本领域技术人员可以以该例毫无意义推导出多个扫描信号的情况。
请参阅图5，图5为采用本申请实施例的扫描线生成方法生成8个扫描信号的结构示意图。如图5所示，本申请实施例的扫描线生成方法，先获取初始时钟信号CK0；再对初始时钟信号CK0进行处理，以生成第1个目标时钟信号CK1、第2个目标时钟信号CK2以及第3个目标时钟信号CK3；紧接着，根据预设逻辑关系对第1个目标时钟信号CK1、第2个目标时钟信号CK2以及第3个目标时钟信号CK3进行编码，以生成第1个有序逻辑信号S1、第2个有序逻辑信号S2、第3个有序逻辑信号S3、第4个有序逻辑信号S4、第5个有序逻辑信号S5、第6个有序逻辑信号S6、第7个有序逻辑信号S7以及第8个有序逻辑信号S8；最后，对第1个有序逻辑信号S1、第2个有序逻辑信号S2、第3个有序逻辑信号S3、第4个有序逻辑信号S4、第5个有序逻辑信号S5、第6个有序逻辑信号S6、第7个有序逻辑信号S7以及第8个有序逻辑信号S8进行译码，并根据译码结果生成第1个扫描信号Gate1、第2个扫描信号Gate2、第3个扫描信号Gate3、第4个扫描信号Gate4、第5个扫描信号Gate5、第6个扫描信号Gate6、第7个扫描信号Gate7以及第8个扫描信号Gate8。
请结合图5、图6，图6为图5所示生成8个扫描信号对应的第一时序图。如图5、图6所示，初始时钟信号CK0的周期为2T，也即，初始时钟信号CK0的频率为1/2T。初始时钟信号CK0以频率为1/2T在高电平和低电平之间来回切换。第1个目标时钟信号CK1以频率为1/4T在高电平和低电平之间来回切换。第2个目标时钟信号CK2以频率为1/8T在高电平和低电平之间来回切换。第3个目标时钟信号CK3以频率为1/16T在高电平和低电平之间来回切换。
请结合图5、图6、图7，图7为图5所示生成8个扫描信号对应的编码示意图。如图5、图6、图7所示，第1个目标时钟信号CK1被划分为多个时间段，第2个目标时钟信号CK2被划分为多个时间段，第3个目标时钟信号CK3被划分为多个时间段。其中，每个时间段的间隔均为2T，每个时间段均对应一逻辑值。
第1个时钟信号CK1在第1时间段t1的逻辑值为0，第1个时钟信号CK1在第2时间段t2的逻辑值为1，第1个时钟信号CK1在第3时间段t3的逻辑值为0，第1个时钟信号CK1在第4时间段t4的逻辑值为1，第1个时钟信号CK1在第5时间段t5的逻辑值为0，第1个时钟信号CK1在第6时间段t6的逻辑值为1，第1个时钟信号CK1在第7时间段t7的逻辑值为0，第1个时钟信号CK1在第8时间段t8的逻辑值为1。
第2个时钟信号CK2在第1时间段t1的逻辑值为0，第2个时钟信号CK2在第2时间段t2的逻辑值为0，第2个时钟信号CK2在第3时间段t3的逻辑值为1，第2个时钟信号CK2在第4时间段t4的逻辑值为1，第2个时钟信号CK2在第5时间段t5的逻辑值为0，第2个时钟信号CK2在第6时间段t6的逻辑值为0，第2个时钟信号CK2在第7时间段t7的逻辑值为1，第2个时钟信号CK2在第8时间段t8的逻辑值为1。
第3个时钟信号CK3在第1时间段t1的逻辑值为0，第3个时钟信号CK3在第2时间段t2的逻辑值为0，第3个时钟信号CK3在第3时间段t3的逻辑值为0，第3个时钟信号CK3在第4时间段t4的逻辑值为0，第3个时钟信号CK3在第5时间段t5的逻辑值为1，第3个时钟信号CK3在第6时间段t6的逻辑值为1，第3个时钟信号CK3在第7时间段t7的逻辑值为1，第3个时钟信号CK3在第8时间段t8的逻辑值为1。
因此，在第1时间段t1的有序逻辑信号S1为000，在第2时间段t2的有序逻辑信号S2为001，在第3时间段t3的有序逻辑信号S3为010，在第4时间段t4的有序逻辑信号S4为011，在第5时间段t5的有序逻辑信号S5为100，在第6时间段t6的有序逻辑信号S6为101，在第7时间段t7的有序逻辑信号S7为110，在第8时间段t8的有序逻辑信号S8为111。
请结合图5、图6、图7、图8、图9，图8为图5所示生成8个扫描信号对应的译码真值表。图9为图5所示生成8个扫描信号的第二时序图。如图5、图6、图7、图8、图9所示，第1个有序逻辑信号S1对应的扫描逻辑信号为10000000，第2个有序逻辑信号S2对应的扫描逻辑信号为01000000，第3个有序逻辑信号S3对应的扫描逻辑信号为00100000，第4个有序逻辑信号S4对应的扫描逻辑信号为00010000，第5个有序逻辑信号S5对应的扫描逻辑信号为00001000，第6个有序逻辑信号S6对应的扫描逻辑信号为00000100，第7个有序逻辑信号S7对应的扫描逻辑信号为00000010，第8个有序逻辑信号S8对应的扫描逻辑信号为00000001。因此，可以根据译码扫描逻辑信号生成第1个扫描信号Gate1、第2个扫描信号Gate2、第3个扫描信号Gate3、第4个扫描信号Gate4、第5个扫描信号Gate5、第6个扫描信号Gate6、第7个扫描信号Gate7以及第8个扫描信号Gate8。
本申请实施例还提供一种扫描信号生成装置。请参阅图10，图10为本申请实施例提供的扫描信号生成装置的结构示意图。如图10所示，该扫描信号生成装置20包括获取模块201、处理模块202、编码模块203以及译码模块204。
其中，获取模块201用于获取初始时钟信号。处理模块202用于对初始时钟信号进行处理，以生成多个目标时钟信号。编码模块203用于根据预设逻辑关系对多个目标时钟信号进行编码，以生成多个有序逻辑信号。译码模块204用于对多个有序逻辑信号进行译码，并根据译码结果生成多个扫描信号。
在一些实施例中，处理模块202包括获取单元2021以及分频单元2022。其中，获取单元2021用于获取与多条扫描线相连接的像素单元的行列信息。分频单元2022用于根据行列信息对初始时钟信号进行分频处理，以生成多个目标时钟信号。
在一些实施例中，编码模块203包括划分单元2031以及组合单元2032。其中，划分单元2031用于将每个目标时钟信号划分成多个时间段，并获取每个目标时钟信号在每个时间段的逻辑值。组合单元2032用于将多个目标时钟信号对应的逻辑值进行组合，以得到每个时间段对应的有序逻辑信号。
在一些实施例中，译码模块204包括查找单元2041以及生成单元2042。其中，查找单元2041用于在译码真值表中查找与有序逻辑信号对应的扫描逻辑信号。生成单元2042用于根据扫描逻辑信号生成对应的扫描信号。
本申请实施例还提供一种电子设备，包括处理器和存储器，存储器中存储有计算机程序，处理器通过调用存储器中存储的所述计算机程序，用于上述实施例中的扫描信号生成方法方法，以实现以下功能：获取初始时钟信号；对初始时钟信号进行处理，以生成多个目标时钟信号；根据预设逻辑关系对多个目标时钟信号进行编码，以生成多个有序逻辑信号；对多个有序逻辑信号进行译码，并根据译码结果生成多个扫描信号，其中，扫描信号与扫描线一一对应。
需要说明的是，本领域普通技术人员可以理解上述实施例的各种方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，该程序可以存储于计算机可读存储介质中，该存储介质可以包括但不限于：只读存储器（ROM，Read Only Memory）、随机存取存储器（RAM，Random Access Memory）、磁盘或光盘等。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种扫描信号生成方法，应用于驱动芯片中，所述驱动芯片分别与多条扫描线电性连接，其中，所述扫描信号生成方法包括：
    获取初始时钟信号，所述初始时钟信号在高电平和低电平之间来回切换；
    对所述初始时钟信号进行处理，以生成多个目标时钟信号；
    根据预设逻辑关系对多个所述目标时钟信号进行编码，以生成多个有序逻辑信号；
    对多个所述有序逻辑信号进行译码，并根据译码结果生成多个扫描信号，其中，所述扫描信号与所述扫描线一一对应。
  2. 根据权利要求1所述的扫描信号生成方法，其中，所述对所述初始时钟信号进行处理，以生成多个目标时钟信号的步骤包括：
    获取与多条所述扫描线相连接的像素单元的行列信息；
    根据所述行列信息对所述初始时钟信号进行分频处理，以生成多个目标时钟信号，其中，第i个目标时钟信号的频率为所述初始时钟信号的频率的1/2 i,i为大于0的正整数。
  3. 根据权利要求2所述的扫描信号生成方法，其中，可采用二分频器对所述初始时钟信号进行分频处理。
  4. 根据权利要求1所述的扫描信号生成方法，其中，所述根据预设逻辑关系对多个所述目标时钟信号进行编码，以生成多个有序逻辑信号的步骤包括：
    将每个所述目标时钟信号划分成多个时间段，并获取每个所述目标时钟信号在每个所述时间段的逻辑值；
    将多个所述目标时钟信号对应的所述逻辑值进行组合，以得到每个所述时间段对应的有序逻辑信号。
  5. 根据权利要求1所述的扫描信号生成方法，其中，所述对多个所述有序逻辑信号进行译码，并根据译码结果生成多个扫描信号的步骤包括：
    在译码真值表中查找与所述有序逻辑信号对应的扫描逻辑信号；
    根据所述扫描逻辑信号生成对应的扫描信号。
  6. 一种扫描信号生成方法，应用于驱动芯片中，所述驱动芯片分别与多条扫描线电性连接，其中，所述扫描信号生成方法包括：
    获取初始时钟信号；
    对所述初始时钟信号进行处理，以生成多个目标时钟信号；
    根据预设逻辑关系对多个所述目标时钟信号进行编码，以生成多个有序逻辑信号；
    对多个所述有序逻辑信号进行译码，并根据译码结果生成多个扫描信号，其中，所述扫描信号与所述扫描线一一对应。
  7. 根据权利要求6所述的扫描信号生成方法，其中，所述对所述初始时钟信号进行处理，以生成多个目标时钟信号的步骤包括：
    获取与多条所述扫描线相连接的像素单元的行列信息；
    根据所述行列信息对所述初始时钟信号进行分频处理，以生成多个目标时钟信号，其中，第i个目标时钟信号的频率为所述初始时钟信号的频率的1/2 i,i为大于0的正整数。
  8. 根据权利要求7所述的扫描信号生成方法，其中，可采用二分频器对所述初始时钟信号进行分频处理。
  9. 根据权利要求6所述的扫描信号生成方法，其中，所述根据预设逻辑关系对多个所述目标时钟信号进行编码，以生成多个有序逻辑信号的步骤包括：
    将每个所述目标时钟信号划分成多个时间段，并获取每个所述目标时钟信号在每个所述时间段的逻辑值；
    将多个所述目标时钟信号对应的所述逻辑值进行组合，以得到每个所述时间段对应的有序逻辑信号。
  10. 根据权利要求6所述的扫描信号生成方法，其中，所述对多个所述有序逻辑信号进行译码，并根据译码结果生成多个扫描信号的步骤包括：
    在译码真值表中查找与所述有序逻辑信号对应的扫描逻辑信号；
    根据所述扫描逻辑信号生成对应的扫描信号。
  11. 一种扫描信号生成装置，其特征在于，包括：
    获取模块，用于获取初始时钟信号；
    处理模块，用于对所述初始时钟信号进行处理，以生成多个目标时钟信号；
    编码模块，用于根据预设逻辑关系对多个所述目标时钟信号进行编码，以生成多个有序逻辑信号；
    译码模块，用于对多个所述有序逻辑信号进行译码，并根据译码结果生成多个扫描信号，其中，所述扫描信号与所述扫描线一一对应；
  12. 根据权利要求11所述的扫描信号生成装置，其特征在于，所述处理模块包括：
    获取单元，所述获取单元用于获取与多条扫描线相连接的像素单元的行列信息；
    分频单元，所述分频单元用于根据所述行列信息对所述初始时钟信号进行分频处理，以生成多个目标时钟信号，其中，第i个目标时钟信号的频率为所述初始时钟信号的频率的1/2 i,i为大于0的正整数。
  13. 根据权利要求12所述的扫描信号生成装置，其中，可采用二分频器对所述初始时钟信号进行分频处理。
  14. 根据权利要求11所述的扫描信号生成装置，其特征在于，所述编码模块包括：
    划分单元，所述划分单元用于将每个所述目标时钟信号划分成多个时间段，并获取每个所述目标时钟信号在每个所述时间段的逻辑值；
    组合单元，所述组合单元用于将多个所述目标时钟信号对应的所述逻辑值进行组合，以得到每个所述时间段对应的有序逻辑信号。
  15. 根据权利要求11所述的扫描信号生成装置，其特征在于，所述译码模块包括：
    查找单元，所述查找单元用于在译码真值表中查找与所述有序逻辑信号对应的扫描逻辑信号；
    生成单元，所述生成单元用于根据所述扫描逻辑信号生成对应的扫描信号。
PCT/CN2019/078797 2018-12-29 2019-03-20 扫描信号生成方法及装置 Ceased WO2020133740A1 (zh)

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CN107068105A (zh) * 2017-06-15 2017-08-18 深圳市华星光电技术有限公司 栅极芯片
CN107749271A (zh) * 2017-10-30 2018-03-02 合肥集创微电子科技有限公司 用于led显示装置的驱动电路和驱动方法

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