WO2020133446A1

WO2020133446A1 - Array substrate, display panel, and display device

Info

Publication number: WO2020133446A1
Application number: PCT/CN2018/125720
Authority: WO
Inventors: 周黎斌; 任竹运; 倪杰
Original assignee: 深圳市柔宇科技有限公司
Priority date: 2018-12-29
Filing date: 2018-12-29
Publication date: 2020-07-02
Also published as: CN112703600A

Abstract

An array substrate (100), a display panel (200), and a display device. The array substrate (100) comprises: a base (10) having a display area (101) and a non-display area (102); a plurality of gate lines (211) provided in the display area (101); a plurality of data lines (23) provided in the display area (101); and an electric transmission layer (20) provided in the display area (101) and comprising a plurality of gate guiding lines (21), wherein the plurality of gate guiding lines (21) are electrically connected to the plurality of gate lines (211), respectively, and the plurality of gate lines (211) and the plurality of data lines (23) are both led out of the same side of the display area (101) so as to be electrically connected to an external control circuit (60). Because the plurality of gate guiding lines (21) and the plurality of data lines (23) are led out of the same side of the display area (101) to the non-display area (102), and are electrically connected to the external control circuit (60), area occupied by flat cables on both sides of the array substrate (100) is reduced.

Description

Array substrate, display panel and display device

Technical field

The present application relates to the field of display technology, and in particular, to an array substrate, a display panel using the array substrate, and a display device.

Background technique

In Organic Light-Emitting Diode (OLED) display technology, thin-film transistors (Thin Film Transistor, TFT) can be used to drive and control the organic light-emitting layer in the OLED display panel, thereby achieving light-emitting display. When thin film transistors are driven and controlled, data lines, gate lines, and power lines are required to provide electrical signal support. In addition, when the thin film transistor is driven and controlled, other auxiliary circuit structures, such as a logic control circuit structure and a flip-chip thin film structure, are also required. However, the connection of these circuit structures to the thin-film transistors will complicate the arrangement of the connecting conductive lines of the display panel and increase the arrangement area, which is not conducive to the narrow and narrow design of the display panel.

Summary of the invention

In view of this, the present application proposes an array substrate, a display panel and a display device using the array substrate, aiming to improve the arrangement structure of the connecting electrical wires of the array substrate, so as to facilitate the narrow design of the display panel frame.

To this end, this application proposes an array substrate, including:

A substrate having a display area and a non-display area outside the display area;

A plurality of gate lines are arranged in the display area and are arranged in rows at intervals;

A plurality of data lines are arranged in the display area and are arranged in columns at intervals. The plurality of data lines are perpendicular to the plurality of gate lines and do not intersect each other. The plurality of gate lines and the plurality of data The lines together define the display area; and

An electric transmission layer is disposed in the display area, the electric transmission layer includes a plurality of gate guide lines, and the plurality of gate guide lines are electrically connected to the plurality of gate lines, respectively, so that the plurality of The gate lines are electrically connected to the external control circuit through the plurality of gate guide lines, and the plurality of gate guide lines and the plurality of data lines are drawn from the same side of the display area to the non-display area To be electrically connected to the external control circuit.

Optionally, the array substrate further includes a plurality of power lines disposed in the display area, and the electrical transmission layer further includes a power guide line for electrically connecting the power line and the external control circuit The power supply guide line is provided in the display area, and is drawn from the same side of the display area as the plurality of gate guide lines and the plurality of data lines to be electrically connected to the external control circuit.

Optionally, the power guide wire is arranged in a grid shape.

Optionally, the power supply guide line includes two parts, the portion of the power supply guide line located in the area where the gate guide line is not provided is grid-shaped, and the power supply guide line is located on the position provided with the gate guide The part of the line area is in the form of a strip.

Optionally, the plurality of gate guide lines are distributed in a stripe structure at intervals, and the plurality of gate guide lines are parallel to the plurality of data lines and are not coplanar.

Optionally, the lengths of the plurality of gate guide lines are not uniformly set, and the long gate guide line is wider than the short gate guide line.

Optionally, the plurality of gate guide lines are arranged in order of length.

Optionally, the shortest of the plurality of gate guide lines is located in the center of the display area, and the gate guide lines arranged from the center of the display area to both sides are longer and longer.

Optionally, it further includes a plurality of thin film transistor units and a plurality of power supply lines, the plurality of thin film transistor units are arranged in a matrix in the display area, two adjacent gate lines and two adjacent A region surrounded by the data lines defines a pixel unit, each of the thin film transistor units corresponds to a pixel unit, and each of the thin film transistor units is associated with a corresponding gate line and a The data line and the power line are electrically connected.

Optionally, it further includes a first insulating layer, the electrical transmission layer is formed on the surface of the substrate, the first insulating layer is formed on a side of the electrical transmission layer away from the substrate, the plurality of thin film transistors The cell is formed on a side of the first insulating layer away from the electric transmission layer, so that the first insulating layer insulates the electric transmission layer and the plurality of thin film transistor units from each other.

Optionally, each of the thin film transistor units includes a first transistor and a second transistor; the gate of each first transistor is electrically connected to an adjacent one of the gate lines, and the source is adjacent to One of the data lines is electrically connected, and the drain is electrically connected to the gate of the second transistor in the same thin film transistor unit; the source of each second transistor is electrically connected to a power line , The drain is used to connect with an organic light emitting unit.

Optionally, a second insulating layer, a third insulating layer, and a protective layer are also included. The gate of the first transistor and the gate of the second transistor are isolated from each other and disposed on the first insulating layer away from the electrical On one side of the transmission layer, the second insulating layer covers the gate of the first transistor, the gate of the second transistor, and the side of the first insulating layer away from the substrate, the first The channel layer of the transistor and the channel layer of the second transistor are isolated from each other on the side of the second insulating layer away from the substrate, and the third insulating layer covers the channel layer of the first transistor, the The channel layer of the second transistor and the side of the second insulating layer away from the substrate, the source and drain of the first transistor and the source and drain of the second transistor are formed at the first The three insulating layers are away from the substrate, and the protective layer covers the source and drain of the first transistor and the source and drain of the second transistor away from the substrate.

Optionally, the non-display area includes two parts respectively located on opposite sides of the display area, and both sides of the display area where the non-display area is located are perpendicular to the direction in which the data line extends, while Parallel to the direction in which the gate lines extend, the plurality of gate guide lines and the plurality of data lines are drawn from the non-display area on one side to be electrically connected to the external control circuit.

Optionally, an electrostatic discharge structure is further included, and the electrostatic discharge structure is disposed in the non-display area on a side opposite to a drawing direction of the plurality of gate guide lines and the plurality of data lines. An electrostatic discharge structure is connected to the electrical transmission layer to discharge static electricity.

In the technical solution of the present application, by changing the arrangement of the connected electrical conductors of the array substrate, the plurality of gate guide lines and the plurality of data lines are all led out to the non-linear area from the same side of the display area The display area is electrically connected to an external control circuit, thereby reducing the area of the wiring on both sides of the array substrate, which is beneficial to the narrow design of the display panel frame.

BRIEF DESCRIPTION

In order to more clearly explain the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without paying any creative work, other drawings can be obtained according to the structures shown in these drawings.

FIG. 1 is a schematic structural diagram of a display panel provided by one embodiment of the present application;

FIG. 2 is a partial schematic view of the section of FIG. 1;

3 is a schematic diagram of the circuit structure of the thin film transistor unit in FIG. 2;

4 is a schematic diagram of an arrangement of gate guide lines provided by an embodiment of this application;

FIG. 5 is a schematic diagram of a data line arrangement provided by one embodiment of the present application.

The implementation, functional characteristics and advantages of the present application will be further described in conjunction with the embodiments and with reference to the drawings.

detailed description

The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of the present application. If there are descriptions related to "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are for descriptive purposes only, and cannot be interpreted as indicating or implying their relative The importance or the number of technical features indicated is implicitly indicated. Thus, the features defined as "first" and "second" may include at least one of the features explicitly or implicitly. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary skilled in the art to achieve, when the combination of technical solutions contradicts each other or cannot be achieved, it should be considered that the combination of such technical solutions does not exist , Nor within the scope of protection required by this application.

It is understandable that, as shown in this document, the one or more interlayer substances involved in the embodiments of the present application, the positional relationship between the layers uses such terms as “lamination” or “formation” or “application” or “arrangement” To express ", those skilled in the art can understand that any term such as "lamination" or "formation" or "application" can cover all the methods, types and techniques of "lamination". For example, sputtering, electroplating, molding, chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), evaporation, hybrid physical-chemical vapor deposition (Hybrid Physical-Chemical Vapor Deposition, HPCVD) , Plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition (PECVD), low pressure chemical vapor deposition (Low Pressure Pressure Chemical Vapor Deposition (LPCVD), etc.

An embodiment of the present application provides an array substrate, and a display panel and a display device using the array substrate, wherein the array substrate includes:

In order to enable those skilled in the art to better understand the technical solutions of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings.

Please refer to FIGS. 1 to 5, FIG. 1 is a schematic structural view of a display panel provided by one embodiment of the present application; FIG. 2 is a partial structural schematic view of the cross section of FIG. 1; FIG. 3 is a circuit structure of the thin film transistor unit in FIG. 4 is a schematic diagram of an arrangement of gate guide lines provided in one embodiment of the present application; FIG. 5 is a schematic diagram of an arrangement of data lines provided in one embodiment of the present application.

Please refer to FIGS. 1 to 3. One embodiment of the present application proposes an array substrate 100 that can be applied to a display panel 200, preferably an OLED display panel. The array substrate 100 has a display area 101 and a non-display area 102 located on at least one side of the display area 101.

The array substrate 100 further includes a base 10 and an electrical transmission layer 20 formed on the base 10, a plurality of thin film transistor units 30, a plurality of gate lines 211, a plurality of data lines 23, and a plurality of power lines 221. The electrical transmission layer 20, the plurality of thin film transistor units 30, the plurality of gate lines 211, the plurality of data lines 23, and the plurality of power supply lines 221 are all correspondingly located in the display area 101.

In this embodiment, the non-display area 102 includes two parts respectively located on opposite sides of the display area 101. It should be noted that FIG. 2 only shows a schematic cross-sectional structure diagram of one thin film transistor unit 30.

As shown in FIG. 2, the display panel 200 includes a plurality of organic light-emitting units 1. The plurality of thin-film transistor units 30 can be used to drive and control the plurality of organic light-emitting units 1 in the display panel 200 to enable light-emitting display, wherein each of the thin-film transistor units 30 corresponds to one organic light-emitting unit 1 .

In some embodiments, the organic light-emitting unit 1 includes a cathode, an organic light-emitting layer, and an anode that are stacked. The organic light-emitting layer is disposed between the cathode and the anode. When an operating voltage is applied between the cathode and the anode, the organic light-emitting layer is excited to emit light, thereby enabling light-emitting display, wherein The thin film transistor unit 30 is electrically connected to the anode, so that the organic light emitting unit 1 can be driven and controlled. Understandably, the organic light-emitting unit 1 may still have more functional layer structures to achieve better light-emitting effect.

Optionally, the plurality of organic light-emitting units 1 include one or more of a red light-emitting unit, a blue light-emitting unit, and a green light-emitting unit. It can be understood that when each of the thin film transistor units 30 is connected to one of the red light emitting unit, the blue light emitting unit, or the green light emitting unit, the organic light emitting unit 1 can be made Light out in a single color.

As shown in FIGS. 2 and 3, the electrical transmission layer 20 includes a plurality of gate guide lines 21 and a plurality of power supply guide lines 22 that are insulated and isolated from each other, and the plurality of gate guide lines 21 are all connected to the plurality of data lines 23 Parallel is not coplanar. Each gate guide line 21 is connected to one gate line 211, and each power guide line 22 is connected to one power line 221. In this embodiment, the substrate 10 is made of an electrically insulating material, so that the electrical transmission layer 20 can be encapsulated and protected to avoid electrical conduction between the electrical transmission layer 20 and other external cables.

The plurality of gate lines 211 are arranged in rows at intervals, the plurality of data lines 23 are arranged in columns at intervals and are perpendicular to the plurality of gate lines 211, and two adjacent gate lines 211 are adjacent to two adjacent ones. The area surrounded by the data lines 23 defines a pixel unit, each pixel unit corresponds to a thin film transistor unit 30 and an organic light emitting unit 1, a plurality of pixel units are arranged in rows and columns to define the display area of the display panel 200, That is, the display area 101 of the array substrate 100.

The plurality of power lines 221 are arranged parallel to the plurality of gate lines 211 or spaced apart from the plurality of data lines 23. In this embodiment, the plurality of power lines 221 and the plurality of gate lines 211 are arranged in parallel and spaced apart. In some embodiments, both sides of the display panel 200 where the non-display area 102 is located are perpendicular to the direction in which the data line 23 extends, and parallel to the direction in which the gate line 211 extends.

Referring to FIG. 4, the plurality of gate guide lines 21 and the plurality of power guide lines 22 are electrically connected to an external control circuit (not shown), so that each of the gate lines 211 and each of the power supplies The line 221 and each of the data lines 23 are electrically connected to the external control circuit of the non-display area 102 on the display area 101 side, and the thin film transistor unit 30 is controlled by the external control circuit. In some embodiments, an external pin connection area 60 is provided in the non-display area 102 for connecting the plurality of gate guide lines 21, the plurality of power guide lines 22, and the plurality of data The line 23 is connected to the external control circuit. In other words, each of the gate lines 211, each of the power lines 221, and each of the data lines 23 are drawn from one side of the array substrate 100 to be connected to the external control circuit, as compared with the prior art The gate line 211, the power line 221, and the data line 23 are respectively drawn from two or more sides of the array substrate 100, the present invention can reduce the wiring on both sides of the array substrate 100 The area is beneficial to the narrow design of the display panel 200 frame. It should be noted that the external control circuit is, for example, a driver IC, which may be directly arranged in the non-display area, or may be directly arranged in the non-display area through a flexible circuit board.

A plurality of the thin film transistor units 30 are disposed on the electrical transmission layer 20, and the thin film transistor unit 30 is provided with an operating current and/or operating voltage through the electrical transmission layer 20, so that the thin film transistor unit 30 Can work normally. It can be understood that the thin film transistor unit 30 can be produced through sputtering, evaporation, vapor deposition, etching, etc., so that the thin film transistor unit 30 is disposed on the electrical transmission layer 20.

Please continue to refer to FIG. 2. Each of the thin film transistor units 30 includes a first transistor 31 and a second transistor 32. The gate of each first transistor 31 is electrically connected to an adjacent gate line 211. Connected, the source of each first transistor 31 is electrically connected to an adjacent one of the data lines 23. All the data lines 23 are electrically connected to the external control circuit of the non-display area 102 on one side. The source of the second transistor 32 in the same row is electrically connected to an adjacent power line 221.

Further, the first transistor 31 includes a first gate 311, a first semiconductor 312 corresponding to the position of the first gate 311, and a first source 313 respectively in contact with opposite sides of the first semiconductor 312 、第一排水314. It is understandable that the first gate 311 corresponds to the position of the first semiconductor 312. The first gate 311 is the gate of the first transistor 31, and the first source 313 and the first drain 314 are the source and drain of the first transistor 31, respectively. The first semiconductor 312 is the channel layer of the first transistor 31.

Similarly, the second transistor 32 includes a second gate 321, a second semiconductor 322 corresponding to the position of the second gate 321, and second source electrodes respectively in contact with opposite sides of the second semiconductor 322 323与第一排水324。 323 and the second drain 324. The second gate 321 corresponds to the position of the second semiconductor 322, the second gate 321 is the gate of the second transistor 32, the second source 323 and the second drain 324 are the source and drain of the second transistor 32 respectively, and the second semiconductor 322 is the channel layer of the second transistor 32.

The gate of the second transistor 32 is electrically connected to the drain of the first transistor 31, thereby electrically connecting the first transistor 31 and the second transistor 32 in parallel. The gate guide line 21 of the electrical transmission layer 20 is electrically connected to the gate of the first transistor 31 through the gate line 211, and the power guide line 22 is connected to the second transistor through the power line 221 The source of 32 is electrically connected to provide the thin film transistor unit 30 with an operating current and/or operating voltage. It can be understood that the source of the first transistor 31 is externally connected to the data signal current and/or voltage through the data line 23, and the drain of the second transistor 32 is electrically connected to the organic light-emitting unit 1, that is, the The thin-film transistor unit 30 can drive and control the organic light-emitting unit 1 to realize light-emitting display.

Specifically, as shown in FIG. 3, an embodiment of the present application provides a schematic diagram of a circuit structure of a thin film transistor unit 30. The gate guide line 21 and the power guide line 22 of the electrical transmission layer 20 provide the thin film transistor unit 30 with an operating current and/or operating voltage, and the source of the first transistor 31 is the thin film through the data line 23 The transistor unit 30 provides a data signal current and/or voltage.

The first transistor 31 and the second transistor 32 are organically connected to form the thin film transistor unit 30, and are arranged on the same layer structure together, for example, on the electrical transmission layer 20. This structure can conveniently provide power support for the thin film transistor unit 30 and provide stable and consistent operating current and/or operating voltage to obtain a stable control signal to improve the stability of the product. Simultaneously, the gate guide line 21, the power guide line 22, and the data line 23 that provide the thin film transistor unit 30 with an operating current and/or operating voltage are all drawn from one side of the array substrate 100 to communicate with the external The control circuit is electrically connected, thereby facilitating the design of the narrow border of the display panel 200.

Please continue to refer to FIG. 2. The array substrate 100 further includes a first insulating layer 41, a second insulating layer 42, a third insulating layer 43, a protective layer 44 and a planarization layer 45. The electrical transmission layer 20 is formed on the substrate 10, the first insulating layer 41 is formed on the electrical transmission layer 20, and the first gate 311 and the second gate 321 are isolated from each other On the first insulating layer 41, the electrical transmission layer 20 is insulated from the first gate 311 and the second gate 321 by the first insulating layer 41, respectively. The second insulating layer 42 covers the first gate 311, the second gate 321, and the first insulating layer 41, and the first semiconductor 312 and the second semiconductor 322 are isolated from each other On the second insulating layer 42. Wherein, the first gate 311 corresponds to the position of the first semiconductor 312, and the second gate 321 corresponds to the position of the second semiconductor 322.

In this embodiment, the electrical connection between the layers is performed by using vias between the layers. For example, the electrical connection between the first gate 311 and the gate guide line 21 is The via hole 411 penetrates the first insulating layer 41 and is used to achieve electrical connection between the first gate 311 and the gate guide line 21.

The third insulating layer 43 is formed on the first semiconductor 312 and the second semiconductor 322 and covers the second insulating layer 42. The third insulating layer 43 fixes and encapsulates the first semiconductor 312 and the second semiconductor 322 to protect the first semiconductor 312 and the second semiconductor 322.

Further, the first source electrode 313, the first drain electrode 314, the second source electrode 323 and the second drain electrode 324 are formed on the third insulating layer 43 at intervals, the first The source electrode 313, the first drain electrode 314, the second source electrode 323, and the second drain electrode 324 may be simultaneously patterned from the same conductive material, for example, aluminum, silver, gold, or alloys thereof and other conductive materials form. The first source electrode 313 and the first drain electrode 314 are respectively located on two opposite sides of the first semiconductor 312, and respectively pass through the via hole 431, the via hole 432 that penetrate the third insulating layer 43 and the The first semiconductor 312 is in contact. Optionally, one end of the first drain 314 is in contact with the first semiconductor 312, and the other end is electrically connected to the gate of the second transistor 32, that is, the second gate 321. Wherein, the first drain 314 is electrically connected to the second gate 321 through a via 3141 penetrating the third insulating layer 43 and the second insulating layer 42.

The second source electrode 323 and the second drain electrode 324 are respectively located on two opposite sides of the second semiconductor 322, and respectively pass through the via hole 433 and the via hole 434 penetrating the third insulating layer 43 The second semiconductor 322 is electrically connected. The power supply line 221 and the second source electrode 323 are provided on the same layer and are electrically connected. The power supply line 221 is electrically connected to the power supply guide line 22 through a via 2211. In this embodiment, a storage capacitor C (as shown in FIG. 2) is formed between the first drain 314 and the second drain 324, so as to provide a stable operating current and/or operation for the second transistor 32 Voltage.

Further, the protective layer 44 is formed on the data line 23, the first source electrode 313, the first drain electrode 314, the second source electrode 323, the second drain electrode 324, the The power line 221 and the third insulating layer 43 are used for packaging protection. The planarization layer 45 is formed on the protection layer 44 to form a flat plane. Optionally, a common electrode 50 is formed on the planarization layer 45, and the common electrode 50 is electrically connected to the drain of the second transistor 32 through a via 51, wherein the anode of the organic light-emitting unit 1 is The common electrode 50 is electrically connected, so that the thin film transistor unit 30 and the organic light emitting unit 1 are electrically connected.

It is understandable that the electrical connection between layers can be electrically connected by using vias between layers. Filling the vias penetrating the insulating layer with a metal conductive material can realize the electrical connection between the layers For connection, for example, the filling metal in the via and the corresponding metal conductive layer above the via are made of the same metal material. Of course, in some embodiments, the electrical connection between layers can also be performed by using connection line wiring.

In some embodiments, the electrical transmission layer 20 provides power support for the thin film transistor unit 30 through vias between layers. A plurality of the thin film transistor units 30 are arranged in an array on the electrical transmission layer 20 to correspondingly drive and control the plurality of organic light emitting units 1 of the display panel 200, wherein the plurality of organic light emitting units 1 are defined and formed The display area of the display panel 200.

In some embodiments, the gate guide line 21 and the power guide line 22 are provided with insulation isolation, and they cooperate with each other to form a layered structure. It is understandable that the electrical transmission layer 20 can be prepared by production processes such as sputtering, evaporation, vapor deposition, and etching. Optionally, the gate guide lines 21 are strip structures distributed at intervals, and the power guide lines 22 are connected in a layered structure, for example, a power guide layer is plated, and the power guide layers are etched separately An insulating channel is filled with an insulating material, that is, the insulating channel surrounds the gate guide line 21, so that the power guide line 22 is insulated from the gate guide line 21. In a preferred embodiment, the gate conductive line 21 and the power conductive line 22 are simultaneously patterned on the same conductive layer.

Further, the power guide wire 22 has a grid layer shape. The power guide wire 22 is arranged in a grid shape, on the one hand, it can save production materials, and on the other hand, it is beneficial to reduce the internal stress of the power guide wire 22. In particular, when the flexible display panel 200 is bent, the power guide wire 22 can be bent better, and the stress generated inside is small, thereby enhancing the bending performance of the product.

In some embodiments, as shown in FIG. 4, the electrical transmission layer 20 includes a plurality of the gate guide lines 21, and the gate guide lines 21 provide gates for the corresponding one or more thin film transistor units 30 Working current and/or working voltage. Each gate guide line 21 is electrically connected to one gate line 211 correspondingly, and the gate line 211 and the external control circuit located in the non-display area 102 are realized through the gate guide line 21 connection.

Since one side of the display panel 200 where the non-display area 102 is located in this embodiment is parallel to the direction in which the gate lines 211 are arranged, a plurality of the grids arranged in the display area 101 The distance between the epipolar line 211 and the non-display area 102 is different. As a result, the gate guide lines 21 are set to have different lengths. When the gate guide lines 21 have different lengths, the length of the gate The electrode guide line 21 is wider than the short gate guide line 21.

A plurality of the gate guide lines 21 are sequentially arranged in the order of length, which may be from the side of the display area 101, a plurality of the gate guide lines 21 are arranged in the order of length, or may be arranged from the display The two sides of the area 101 are arranged in order of length. When arranged from the two sides of the display area 101 in order of length, specifically, the shortest gate guide line 21 is located in the center of the display area 101, and the gates arranged from the center to both sides The pole guide line 21 is getting longer. At this time, the power supply guide line 22 includes two parts, a portion located in a region where the gate guide line 21 is not provided is grid-shaped, and a portion located in a region where the gate guide line 21 is provided is strip-shaped . Wherein, the power supply guide line 22 of the strip-shaped portion is arranged parallel to the gate guide line 21 at intervals.

Understandably, when the gate guide lines 21 are the same length, the gate guide lines 21 should have the same width to ensure that the electrical signals are stable and consistent. When the gate guide lines 21 are provided with inconsistent lengths, to ensure that they can provide stable and consistent electrical signals, the long gate guide lines 21 are wider than the short gate guide lines 21. The long gate guide line 21 can transmit electrical signals to other farther areas of the display panel 200, but because of its long transmission distance and relatively large impedance, the gate guide line 21 needs to be wider in design; The short gate guide line 21 can transmit electrical signals to other closer areas of the display panel 200, but due to its short transmission distance and relatively low impedance, the gate guide line 21 needs to be narrowed to This ensures that the gate guide lines 21 with different lengths can provide multiple stable and consistent electrical signals, thereby ensuring product stability. Among them, some of the gate guide lines 21 are long and wide, which can not only reduce the difficulty of the production process and improve production quality, so as to ensure that the gate guide lines 21 can provide stable and consistent electrical signals, thereby ensuring product stability .

Please refer to FIG. 5. One embodiment of the present application provides a schematic diagram of the arrangement of the source connection line of the first transistor 31, that is, the data line 23. The source of the first transistor 31 in the thin film transistor unit 30 passes through the data line 23 to provide a data electrical signal for the thin film transistor unit 30. The source of the first transistor 31 is connected to the external control circuit through the data line 23 to drive and control the thin film transistor unit 30. It can be understood that the data line 23, the gate guide line 21, and the power guide line 22 are all insulated from each other, and are all from the same side of the display panel 200 (that is, located on the side of the display area 101 The non-display area 102) is led out to be electrically connected to the external control circuit. Wherein, the gate guide line 21 and the power guide line 22 are arranged in the same layer, and can be formed by patterning the same conductive material at the same time. The data line 23 may be disposed in the same layer as the first source electrode 313, and the data line 23, the first drain electrode 314, the second source electrode 323, and the second drain electrode 324 are electrically conductive The material is simultaneously patterned.

Further, the array substrate 100 further includes a flip-chip thin film structure (not shown). The flip-chip thin film structure is located in the non-display area 102, and is electrically connected to the gate guide line 21, the power guide line 22, and the data line 23 of the first transistor 31.

The external control circuit is communicatively connected to the flip-chip thin film structure, thereby logically controlling the thin film transistor unit 30. Understandably, other IC chips may be connected to the flip-chip thin film structure to assist the external control circuit to logically control the thin film transistor unit 30, so that the thin film transistor unit 30 is connected to The organic light emitting unit 1 can normally emit light for display.

In some embodiments, the array substrate 100 further includes an electrostatic discharge structure 70 (see FIG. 1). The electrostatic discharge structure 70 is connected to the electrical transmission layer 20 to discharge static electricity. The electrostatic discharge structure 70 is disposed in the non-display area 102 on the side opposite to the drawing direction of the plurality of gate guide lines 21 and the plurality of data lines 23.

Based on the above display panel 200, an embodiment of the present application further proposes a display device. The display device includes the display panel 200. It can be understood that the display device includes but is not limited to a display device such as a smart phone, a tablet computer, a PC computer, or a smart TV.

The above-mentioned embodiments are exemplary embodiments of the present application, but the embodiments of the present application are not limited by the above-mentioned embodiments, and any other changes, modifications, substitutions, combinations, changes, modifications, substitutions, combinations, etc. made without departing from the spirit and principles of the present application Simplified, all should be equivalent replacement methods, all included in the scope of protection of this application.

Claims

An array substrate is characterized by comprising:

A substrate having a display area and a non-display area outside the display area;

A plurality of gate lines are arranged in the display area and are arranged in rows at intervals;

A plurality of data lines are arranged in the display area and are arranged in columns at intervals. The plurality of data lines are perpendicular to the plurality of gate lines and do not intersect each other. The plurality of gate lines and the plurality of data The lines together define the display area; and

An electric transmission layer is disposed in the display area, the electric transmission layer includes a plurality of gate guide lines, and the plurality of gate guide lines are electrically connected to the plurality of gate lines, respectively, so that the plurality of The gate lines are electrically connected to the external control circuit through the plurality of gate guide lines, and the plurality of gate guide lines and the plurality of data lines are drawn from the same side of the display area to the non-display area To be electrically connected to the external control circuit.
The array substrate according to claim 1, wherein the array substrate further includes a plurality of power lines disposed in the display area, and the electrical transmission layer further includes a power guide line for connecting the power supply The line is electrically connected to the external control circuit, the power supply guide line is provided in the display area, and is led out from the same side of the display area as the plurality of gate guide lines and the plurality of data lines To be electrically connected to the external control circuit.
The array substrate according to claim 2, wherein the power guide line is provided in a grid shape.
The array substrate according to claim 2, wherein the power supply guide line includes two parts, and a portion of the power supply guide line in a region where the gate guide line is not provided is grid-shaped, and the power supply The portion of the guide line located in the area where the gate guide line is provided has a bar shape.
The array substrate according to claim 1, wherein the plurality of gate guide lines are distributed in a stripe structure at intervals, and the plurality of gate guide lines are parallel to the plurality of data lines and are not coplanar.
The array substrate according to claim 5, wherein the lengths of the plurality of gate guide lines are not uniform, and the long gate guide line is wider than the short gate guide line.
The array substrate according to claim 6, wherein the plurality of gate guide lines are arranged in order of length.
The array substrate according to claim 7, wherein the shortest of the plurality of gate guide lines is located in the center of the display area, and the gate guide lines arranged from the center of the display area to the two sides Come longer.
The array substrate according to claim 1, further comprising a plurality of thin film transistor units and a plurality of power lines, the plurality of thin film transistor units are arranged in a matrix in the display area, two adjacent A region surrounded by the gate line and two adjacent data lines defines a pixel unit, each of the thin film transistor units corresponds to a pixel unit, and each of the thin film transistor units corresponds to The gate line, the data line, and the power line are electrically connected.
The array substrate according to claim 9, further comprising a first insulating layer, the electrical transmission layer is formed on the surface of the base, and the first insulating layer is formed on the electrical transmission layer away from the base On the side of the first thin film transistor unit, the plurality of thin film transistor units are formed on the side of the first insulating layer away from the electrical transmission layer, so that the first insulating layer allows the electrical transmission layer and the multiple thin film transistor units Insulated from each other.
The array substrate according to claim 10, wherein each of the thin film transistor units includes a first transistor and a second transistor; the gate of each first transistor and an adjacent one of the gates An electrode line is electrically connected, a source electrode is electrically connected to an adjacent one of the data lines, and a drain electrode is electrically connected to the gate of the second transistor in the same thin film transistor unit; The source electrode is electrically connected to a power line, and the drain electrode is used to connect to an organic light emitting unit.
The array substrate according to claim 11, further comprising a second insulating layer, a third insulating layer and a protective layer, the gate of the first transistor and the gate of the second transistor are isolated from each other The first insulating layer is away from the side of the electrical transmission layer, and the second insulating layer covers the gate of the first transistor, the gate of the second transistor, and the first insulating layer away from the On one side of the substrate, the channel layer of the first transistor and the channel layer of the second transistor are isolated from each other on the side of the second insulating layer away from the substrate, and the third insulating layer covers the A channel layer of the first transistor, a channel layer of the second transistor, and a side of the second insulating layer away from the substrate, a source, a drain of the first transistor, and a source of the second transistor A gap between the electrode and the drain is formed on a side of the third insulating layer away from the substrate, and the protective layer covers the source and drain of the first transistor and the source and drain of the second transistor The side away from the substrate.
The array substrate according to claim 1, wherein the non-display area includes two parts respectively located on two opposite sides of the display area, and both sides of the display area where the non-display area is located are The extending direction of the data line is perpendicular and parallel to the extending direction of the gate line, and the plurality of gate guide lines and the plurality of data lines are drawn from the non-display area on one side to It is electrically connected to the external control circuit.
The array substrate according to claim 13, further comprising an electrostatic discharge structure, the electrostatic discharge structure being disposed on a side opposite to a drawing direction of the plurality of gate guide lines and the plurality of data lines In the non-display area, the electrostatic discharge structure is connected to the electrical transmission layer to discharge static electricity.
A display panel, comprising the array substrate according to any one of claims 1 to 14.
A display device comprising the display panel according to claim 15.