CN111129093A - Array substrate and display panel - Google Patents
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- CN111129093A CN111129093A CN201911340586.5A CN201911340586A CN111129093A CN 111129093 A CN111129093 A CN 111129093A CN 201911340586 A CN201911340586 A CN 201911340586A CN 111129093 A CN111129093 A CN 111129093A
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- 239000000758 substrate Substances 0.000 title claims abstract description 98
- 239000010410 layer Substances 0.000 claims abstract description 155
- 239000002184 metal Substances 0.000 claims abstract description 74
- 239000011229 interlayer Substances 0.000 claims abstract description 27
- 239000003990 capacitor Substances 0.000 claims description 22
- 238000000059 patterning Methods 0.000 claims description 8
- 238000011084 recovery Methods 0.000 description 15
- 239000000463 material Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
- H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
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Abstract
The invention provides an array substrate and a display panel, wherein the array substrate is characterized in that a first power voltage line is formed on a second metal layer of the array substrate, and a first through hole is formed on an interlayer insulating layer, so that the first power voltage line on the second metal layer is connected with a second power voltage line on a source drain layer through the first through hole, and the first power voltage line is connected with the second power voltage line at least at two positions, thereby ensuring that the first power voltage line is connected with the second power voltage line in parallel, reducing the impedance of the power voltage line, relieving the problem of voltage drop on the power voltage line, avoiding increasing a film layer, not influencing the thickness of the display panel, and relieving the technical problem of uneven brightness of the display panel caused by the voltage drop on the power voltage signal line of the existing display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a display panel.
Background
An existing OLED (Organic Light-Emitting Diode) display panel is widely used due to its advantages of being bendable, Light, thin, and high color saturation, and a low temperature polysilicon array substrate is used in the OLED display panel, but in the manufacturing process of the low temperature polysilicon array substrate, threshold voltage drift of a thin film transistor due to manufacturing problems may occur, so that a driving circuit of the low temperature polysilicon array substrate needs to be compensated.
The conventional pixel compensation circuit comprises a first metal layer, a second metal layer and a source drain layer, wherein the source drain layer is provided with a VDD signal line, namely a power supply voltage signal line, the VDD signal line can drive a row of pixels on one VDD signal line of a driving circuit, and a voltage drop can occur on the VDD signal line, so that the brightness of the pixels close to the input end of the VDD signal line is higher, the brightness of the pixels far away from the input end of the VDD signal line is lower, and the integral brightness of the display panel is uneven.
Therefore, the existing display panel has the technical problem of uneven brightness of the display panel due to voltage drop on a power supply voltage signal wire.
Disclosure of Invention
The invention provides an array substrate and a display panel, which are used for solving the technical problem that the brightness of the display panel is uneven due to the fact that voltage drop exists on a power supply voltage signal line of the existing display panel.
In order to solve the above problems, the technical scheme provided by the invention is as follows:
the present invention provides an array substrate, including:
a substrate;
the first metal layer is arranged on one side of the substrate and is patterned to form a grid electrode and a first capacitor polar plate;
the second metal layer is arranged in the direction of the first metal layer far away from the substrate, and a first power supply voltage line and a second capacitor plate are formed in a patterning mode;
the interlayer insulating layer is arranged on the second metal layer and is etched to form a first through hole, and the first through hole comprises at least two sub-through holes;
the source drain layer is arranged on the interlayer insulating layer and is patterned to form a data line and a second power supply voltage line;
the first power supply voltage line and the second power supply voltage line are connected through a first via hole, and the first power supply voltage line and the second power supply voltage line are connected at least in two places.
In the array substrate provided by the invention, the projection area of the first power supply voltage line on the substrate is larger than or equal to the projection area of the second power supply voltage line on the substrate.
In the array substrate provided by the invention, the projection of the second power supply voltage line on the substrate is positioned in the projection of the first power supply voltage line on the substrate.
In the array substrate provided by the invention, the projection of the second power supply voltage line on the substrate is positioned on one side of the projection of the first power supply voltage line on the substrate.
In the array substrate provided by the present invention, the first power voltage line includes a first body portion and a first connection portion, and the first connection portion is connected to the second power voltage line through a first via hole.
In the array substrate provided by the present invention, the second power voltage line includes a second body portion and a second connection portion, and the second connection portion is connected to the first power voltage line through a first via hole.
In the array substrate provided by the invention, the array substrate further comprises an active layer, the active layer is arranged between the substrate and the first metal layer, the source drain layer is patterned to form a reset signal line, the reset signal line and the second power supply voltage line are in the same direction, the reset signal line is insulated from the data line and the second power supply voltage line, and the reset signal line is connected with the active layer.
In the array substrate provided by the invention, the first via hole comprises a first sub-via hole and a second sub-via hole, the first power voltage line and the second power voltage line are connected through the first sub-via hole and the second sub-via hole, and the distance between the first sub-via hole and the second sub-via hole is greater than the distance between one sub-pixel.
In the array substrate provided by the invention, the first power voltage line penetrates through a column of sub-pixels, and the first sub-via hole and the second sub-via hole are respectively and correspondingly arranged in the areas of two sub-pixels which are farthest away from each other in the column of sub-pixels.
Meanwhile, the invention provides a display panel which comprises the array substrate.
Has the advantages that: the invention provides an array substrate and a display panel, the array substrate comprises a substrate, a first metal layer, a second metal layer, an interlayer insulating layer and a source drain layer, the first metal layer is arranged on one side of the substrate, a grid electrode and a first electrode plate of a capacitor are formed in a patterning mode, the second metal layer is arranged in the direction of the first metal layer far away from the substrate, patterning to form a first power voltage line and a second electrode plate of the capacitor, arranging the interlayer insulating layer on the second metal layer, etching to form a first via hole, the first via hole comprises at least two sub-via holes, the source drain layer is arranged on the interlayer insulating layer and is patterned to form a data line and a second power supply voltage line, the first power supply voltage line is connected with the second power supply voltage line through a first via hole, and the first power supply voltage line is connected with the second power supply voltage line at least in two positions; through forming first mains voltage line on the second metal level at array substrate, and form first via hole on the interlayer insulation layer, make first mains voltage line on the second metal level and the second mains voltage line of source drain layer pass through first via hole connection, and first mains voltage line has two at least connections with second mains voltage line, it is parallelly connected with second mains voltage line to have guaranteed first mains voltage line, thereby reduce mains voltage line's impedance, the problem of the pressure drop appears on the mains voltage line has been alleviated, and need not to increase the rete, do not influence the thickness of display panel plate, it has the pressure drop to have alleviated current display panel and has existed on the mains voltage signal line, lead to the uneven technical problem of display panel luminance.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a conventional display panel.
Fig. 2 is a first schematic view of an array substrate according to an embodiment of the invention.
Fig. 3 is a second schematic view of an array substrate according to an embodiment of the invention.
Fig. 4 is a third schematic view of an array substrate according to an embodiment of the invention.
Fig. 5 is a schematic connection diagram of a first power voltage line and a second power voltage line according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of a display panel according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
The embodiment of the invention is used for solving the technical problem that the brightness of the display panel is not uniform due to the voltage drop of a power supply voltage signal wire of the conventional display panel.
As shown in fig. 1, the conventional display panel includes an active layer 101, a first metal layer, a second metal layer, and a source drain layer, the first metal layer is patterned to form a first scan line 102, a second scan line 103, a light emitting signal line 104, and a capacitor plate (not shown), the second metal layer is patterned to form a capacitor plate 105 and a recovery signal line 106, the source drain layer is patterned to form a data line 107 and a power voltage signal line 108, each film layer is connected through a connection hole 109, each signal line and capacitor form a pixel compensation circuit, the power voltage signal line drives a column of pixels, and due to impedance existing on the power voltage signal line, a voltage situation appears on the power voltage signal line during signal transmission, so that luminance of pixels close to an input end of the power voltage signal line is higher, luminance of pixels far from the input end of the power voltage signal line is lower, and thus the overall luminance of the display panel is uneven, therefore, the existing display panel has the technical problem of uneven brightness of the display panel due to voltage drop on a power supply voltage signal wire.
As shown in fig. 2 and 4, an embodiment of the present invention provides an array substrate, including:
a substrate 111;
a first metal layer 115 disposed on one side of the substrate 111 and patterned to form a gate and a first capacitor plate 1155;
a second metal layer 117 disposed in a direction away from the substrate 111 of the first metal layer 115, and patterned to form a first power voltage line 1171 and a second capacitor plate 1172;
the interlayer insulating layer 118 is arranged on the second metal layer 117, and a first via hole 1181 is formed by etching, wherein the first via hole 1181 comprises at least two sub-via holes;
a source/drain layer 119 disposed on the interlayer insulating layer 118 and patterned with a data line 1192 and a second power voltage line 1191;
the first power voltage line 1171 and the second power voltage line 1191 are connected by a first via 1181, and at least two connections exist between the first power voltage line 1171 and the second power voltage line 1191.
The embodiment of the invention provides an array substrate, which comprises a substrate, a first metal layer, a second metal layer, an interlayer insulating layer and a source drain layer, wherein the first metal layer is arranged on one side of the substrate, a grid electrode and a first electrode plate of a capacitor are formed in a patterning mode, the second metal layer is arranged in the direction of the first metal layer far away from the substrate, patterning to form a first power voltage line and a second electrode plate of the capacitor, arranging the interlayer insulating layer on the second metal layer, etching to form a first via hole, the first via hole comprises at least two sub-via holes, the source drain layer is arranged on the interlayer insulating layer and is patterned to form a data line and a second power supply voltage line, the first power supply voltage line is connected with the second power supply voltage line through a first via hole, and the first power supply voltage line is connected with the second power supply voltage line at least in two positions; through forming first mains voltage line on the second metal level at array substrate, and form first via hole on the interlayer insulation layer, make first mains voltage line on the second metal level and the second mains voltage line of source drain layer pass through first via hole connection, and first mains voltage line has two at least connections with second mains voltage line, it is parallelly connected with second mains voltage line to have guaranteed first mains voltage line, thereby reduce mains voltage line's impedance, the problem of the pressure drop appears on the mains voltage line has been alleviated, and need not to increase the rete, do not influence the thickness of display panel plate, it has the pressure drop to have alleviated current display panel and has existed on the mains voltage signal line, lead to the uneven technical problem of display panel luminance.
As shown in fig. 2, 3, and 4, the present invention provides an array substrate, which includes a substrate 111, a barrier layer 112, an active layer 113, a first gate insulating layer 114, a first metal layer 115, a second gate insulating layer 116, a second metal layer 117, an interlayer insulating layer 118, and a source drain layer 119, which are sequentially disposed, where the first metal layer is patterned to form a first scan line 1151, a second scan line 1152, a third scan line 1154, and a light emitting signal line 1153, and in an embodiment, as shown in fig. 3, the source drain layer 119 is etched to form a recovery signal line 1193, and a recovery signal line is prepared on the second metal layer in the existing display panel, and the directions of the recovery signal line and the capacitor plate are both horizontal, in an embodiment of the present invention, the recovery signal line is disposed on the source drain layer, so that there is a space for disposing other routing lines on the second metal layer, and thus a power supply voltage line can be prepared on the second metal layer, make second metal level and source drain layer all be formed with supply voltage line, and both can connect in parallel to reduce supply voltage line's impedance, make supply voltage line when transmitting voltage signal, the last pressure drop of supply voltage line is less, does not influence display brightness, thereby current display panel has the pressure drop on the supply voltage signal line, leads to the uneven technical problem of display panel luminance.
It should be noted that, in fig. 3 and 4, different film layers are connected through the connection hole 21, where the connection hole 21 includes a first connection hole 211 and a second connection hole 212, where the first connection hole 211 indicates that the metal trace of the source/drain layer is connected with the first plate of the capacitor formed by the first metal layer 115 through the first connection hole 211, the second connection hole 212 indicates that the second power voltage line 1191 is connected with the second plate of the capacitor formed by the second metal layer 117 through the second connection hole 212, and the remaining connection holes are all connection holes correspondingly connecting the film layers in the overlapping region.
In an embodiment, as shown in fig. 4, a projection area of the first power voltage line 1171 on the substrate is greater than or equal to a projection area of the second power voltage line 1191 on the substrate, when the first power voltage line is disposed on the second metal layer, considering that a space of the second metal layer is large, the metal routing is not too tight, the first power voltage line can be disposed to be wide, so that a projection area of the first power voltage line on the substrate is greater than or equal to a projection area of the second power voltage line on the substrate, the impedance of the first power voltage line can be reduced, after the first power voltage line and the second power voltage line are connected in parallel, the impedance of the power voltage line can be reduced, so that the voltage drop of the power voltage line is small when a signal is transmitted, and even the display effect is not affected by the voltage drop.
In one embodiment, as shown in fig. 4, the projection of the second power voltage line 1191 onto the substrate is located within the projection of the first power voltage line 1171 onto the substrate, and when the second power voltage line is set, the second power voltage line is disposed under the first power voltage line, such that when the first power voltage line is set, the first power voltage line can be positioned according to the position of the second power voltage line, and when the first power voltage line and the second power voltage line are connected, the first power voltage line and the second power voltage line are easily connected.
In an embodiment, as shown in fig. 5, the first power voltage line 1171 includes a first body portion 1711 and a first connecting portion 1712, the first connecting portion 1712 is connected to the second power voltage line 1191 through a first via 1181, and in a setting process of the first power voltage line and the second power voltage line, when it is considered that the first power voltage line and the second power voltage line cannot be correspondingly overlapped, the first power voltage line may be extended outward, so that the first connecting portion of the first power voltage line is connected to the second power voltage line through the via, thereby realizing parallel connection of the first power voltage line and the second power voltage line.
In one embodiment, the second power voltage line includes a second body portion and a second connecting portion, the second connecting portion is connected to the first power voltage line through a first via hole, and in a process of setting the first power voltage line and the second power voltage line, the second power voltage line may extend outward in consideration of a case where the first power voltage line and the second power voltage line cannot be set to overlap with each other, so that the second connecting portion of the second power voltage line is connected to the first power voltage line through the via hole, thereby achieving parallel connection of the first power voltage line and the second power voltage line.
In an embodiment, as shown in fig. 2 and 4, the array substrate further includes an active layer 113, the active layer 113 is disposed between the substrate 111 and the first metal layer 115, the source-drain layer 119 is patterned to form a recovery signal line 1193, the recovery signal line 1193 and the second power voltage line 1191 run in the same direction, the recovery signal line 1193 is insulated from the data line 1192 and the second power voltage line 1191, the recovery signal line 1193 is connected to the active layer 113, when the recovery signal line is disposed in the source-drain layer, the recovery signal line needs to be connected to the active layer, so that the recovery signal line can normally operate, and the recovery signal line can form a cross-linked network with the power voltage line, so that the recovery signal line does not affect the recovery signal line after the source-drain layer is used for manufacturing the source-drain layer.
In one embodiment, as shown in fig. 4, the first via 1181 includes a first sub-via 1811 and a second sub-via 1812, the first power voltage line 1171 and the second power voltage line 1191 are connected through the first sub-via 1811 and the second sub-via 1812, and the distance between the first sub-via 1811 and the second sub-via 1812 is greater than the distance of one sub-pixel; the first power supply voltage line and the second power supply voltage line are connected in parallel, the length of the parallel part of the first power supply voltage line and the second power supply voltage line is larger than the distance of one sub-pixel, namely, the voltage drop of a signal passing through the sub-pixel is low or even no voltage drop, so that the voltage signal can not be dropped during transmission, and the display brightness of one column of sub-pixels is consistent during display.
In one embodiment, as shown in fig. 4, the first power voltage line 1171 penetrates through a column of sub-pixels, the first sub-via 1811 and the second sub-via 1812 correspond to two sub-pixel regions that are farthest from each other in the column of sub-pixels, when the first power voltage line is disposed, the length of the first power voltage line is greater than that of the column of sub-pixels, the distance between the first sub-via and the second sub-via is greater than that of the column of sub-pixels, and the parallel distance between the first power voltage line and the second power voltage line is greater than that of the column of sub-pixels, so that during the transmission of the voltage signal, the voltage drop of the voltage signal on the column of sub-pixels is small, and the luminance of the column of sub-pixels is kept uniform.
As shown in fig. 6, an embodiment of the present invention provides a display panel, including:
an array substrate;
a planarization layer 21 disposed on the array substrate;
a pixel electrode layer 311 disposed on the planarization layer 21;
a pixel defining layer 313 disposed on the pixel electrode layer 311;
a light-emitting material layer 312 disposed in the light-emitting region defined by the pixel defining layer 313;
a common electrode layer 314 disposed on the light emitting material layer 312;
the array substrate comprises a substrate 111, a first metal layer 115, a second metal layer 117, an interlayer insulating layer 118 and a source drain layer 119, wherein the first metal layer 115 is arranged on one side of the substrate 111, a gate and capacitor first plate 1155 is patterned, the second metal layer 117 is disposed in a direction away from the substrate 111 of the first metal layer 115, a first power voltage line 1171 and a second capacitor plate 1172 are patterned, the interlayer insulating layer 118 is disposed on the second metal layer 117, a first via 1181 is etched, the first via hole 1181 includes at least two sub-via holes, the source and drain layer 119 is disposed on the interlayer insulating layer 118, and is patterned to form a data line 1192 and a second power voltage line 1191, wherein the first power voltage line 1171 and the second power voltage line 1191 are connected through a first via 1181, the first power supply voltage line 1171 and the second power supply voltage line 1191 are connected at least at two places.
The embodiment of the invention provides a display panel, which comprises an array substrate, a planarization layer, a pixel electrode layer, a pixel definition layer, a luminescent material layer and a common electrode layer, wherein the array substrate comprises a substrate, a first metal layer, a second metal layer, an interlayer insulating layer and a source drain electrode layer, the first metal layer is arranged on one side of the substrate and is patterned to form a grid electrode and a first capacitor plate, the second metal layer is arranged in the direction of the first metal layer away from the substrate and is patterned to form a first power voltage line and a second capacitor plate, the interlayer insulating layer is arranged on the second metal layer and is etched to form a first through hole, the first through hole comprises at least two sub-through holes, the source drain electrode layer is arranged on the interlayer insulating layer and is patterned to form a data line and a second power voltage line, and the first power voltage line is connected with the second power voltage line through the first through hole, the first power supply voltage line is connected with the second power supply voltage line at least at two positions; through forming first mains voltage line on the second metal level at array substrate, and form first via hole on the interlayer insulation layer, make first mains voltage line on the second metal level and the second mains voltage line of source drain layer pass through first via hole connection, and first mains voltage line has two at least connections with second mains voltage line, it is parallelly connected with second mains voltage line to have guaranteed first mains voltage line, thereby reduce mains voltage line's impedance, the problem of the pressure drop appears on the mains voltage line has been alleviated, and need not to increase the rete, do not influence the thickness of display panel plate, it has the pressure drop to have alleviated current display panel and has existed on the mains voltage signal line, lead to the uneven technical problem of display panel luminance.
According to the above embodiment:
the embodiment of the invention provides an array substrate and a display panel, the array substrate comprises a substrate, a first metal layer, a second metal layer, an interlayer insulating layer and a source drain layer, the first metal layer is arranged on one side of the substrate, a grid electrode and a first electrode plate of a capacitor are formed in a patterning mode, the second metal layer is arranged in the direction of the first metal layer far away from the substrate, patterning to form a first power voltage line and a second electrode plate of the capacitor, arranging the interlayer insulating layer on the second metal layer, etching to form a first via hole, the first via hole comprises at least two sub-via holes, the source drain layer is arranged on the interlayer insulating layer and is patterned to form a data line and a second power supply voltage line, the first power supply voltage line is connected with the second power supply voltage line through a first via hole, and the first power supply voltage line is connected with the second power supply voltage line at least in two positions; through forming first mains voltage line on the second metal level at array substrate, and form first via hole on the interlayer insulation layer, make first mains voltage line on the second metal level and the second mains voltage line of source drain layer pass through first via hole connection, and first mains voltage line has two at least connections with second mains voltage line, it is parallelly connected with second mains voltage line to have guaranteed first mains voltage line, thereby reduce mains voltage line's impedance, the problem of the pressure drop appears on the mains voltage line has been alleviated, and need not to increase the rete, do not influence the thickness of display panel plate, it has the pressure drop to have alleviated current display panel and has existed on the mains voltage signal line, lead to the uneven technical problem of display panel luminance.
The array substrate and the display panel provided by the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are explained herein by applying specific examples, and the description of the embodiments is only used to help understand the technical solutions and the core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. An array substrate, comprising:
a substrate;
the first metal layer is arranged on one side of the substrate and is patterned to form a grid electrode and a first capacitor polar plate;
the second metal layer is arranged in the direction of the first metal layer far away from the substrate, and a first power supply voltage line and a second capacitor plate are formed in a patterning mode;
the interlayer insulating layer is arranged on the second metal layer and is etched to form a first through hole, and the first through hole comprises at least two sub-through holes;
the source drain layer is arranged on the interlayer insulating layer and is patterned to form a data line and a second power supply voltage line;
the first power supply voltage line and the second power supply voltage line are connected through a first via hole, and the first power supply voltage line and the second power supply voltage line are connected at least in two places.
2. The array substrate of claim 1, wherein a projected area of the first supply voltage line on the substrate is greater than or equal to a projected area of the second supply voltage line on the substrate.
3. The array substrate of claim 2, wherein a projection of the second supply voltage line on the substrate is within a projection of the first supply voltage line on the substrate.
4. The array substrate of claim 2, wherein a projection of the second supply voltage line on the substrate is located on a side of a projection of the first supply voltage line on the substrate.
5. The array substrate of claim 4, wherein the first supply voltage line comprises a first body portion and a first connection portion, the first connection portion being connected to the second supply voltage line through a first via.
6. The array substrate of claim 4, wherein the second supply voltage line includes a second body portion and a second connection portion, the second connection portion being connected to the first supply voltage line through a first via.
7. The array substrate of claim 1, further comprising an active layer disposed between the substrate and the first metal layer, wherein the source and drain layers are patterned to form a reset signal line, wherein the reset signal line is in the same direction as the second power voltage line, and wherein the reset signal line is insulated from the data line and the second power voltage line, and wherein the reset signal line is connected to the active layer.
8. The array substrate of claim 1, wherein the first via comprises a first sub-via and a second sub-via, the first supply voltage line and the second supply voltage line are connected by the first sub-via and the second sub-via, and a distance between the first sub-via and the second sub-via is greater than a distance of one sub-pixel.
9. The array substrate of claim 8, wherein the first power voltage line penetrates through a column of sub-pixels, and the first sub-via and the second sub-via are respectively disposed in regions of two sub-pixels that are farthest apart from each other in the column of sub-pixels.
10. A display panel comprising the array substrate according to any one of claims 1 to 9.
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| CN201911340586.5A CN111129093A (en) | 2019-12-23 | 2019-12-23 | Array substrate and display panel |
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| CN201911340586.5A CN111129093A (en) | 2019-12-23 | 2019-12-23 | Array substrate and display panel |
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