CN112582458A - Display panel, preparation method thereof and display device - Google Patents
Display panel, preparation method thereof and display device Download PDFInfo
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- CN112582458A CN112582458A CN202011453307.9A CN202011453307A CN112582458A CN 112582458 A CN112582458 A CN 112582458A CN 202011453307 A CN202011453307 A CN 202011453307A CN 112582458 A CN112582458 A CN 112582458A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
- H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
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Abstract
The embodiment of the application provides a display panel, a preparation method of the display panel and display equipment, wherein the display panel comprises a display area and a non-display area, the non-display area comprises a substrate, an auxiliary signal line, an interlayer insulating layer and a negative voltage signal line which are sequentially stacked, and the auxiliary signal line is electrically connected with the negative voltage signal line through a via hole formed in the interlayer insulating layer. According to the embodiment of the application, the technical problems that the brightness of the display panel is not uniform and the display is abnormal when the display panel displays can be solved, and the display effect of the display panel is improved.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a display panel, a manufacturing method of the display panel and display equipment.
Background
With the development of science and technology and economy, the display panel is used as a core component of display equipment, and is more and more widely applied in production and life of people, for example, the display panel can be seen as a figure of a watch, a mobile phone, a computer and a television.
However, the inventor of the present application finds that, in some narrow-bezel display devices, the display panel has the problems of non-uniform brightness and abnormal display during display, which seriously affects the display effect and user experience of the display panel.
Disclosure of Invention
The embodiment of the application provides a display panel, a preparation method thereof and display equipment, and can solve the technical problems of uneven brightness and abnormal display of the display panel during display.
In a first aspect, an embodiment of the present application provides a display panel, where the display panel includes a display area and a non-display area, where the non-display area includes a substrate, an auxiliary signal line, an interlayer insulating layer, and a negative voltage signal line, which are stacked in sequence, where the auxiliary signal line is electrically connected to the negative voltage signal line via a via hole formed in the interlayer insulating layer.
In some embodiments, an orthographic projection of the negative voltage signal line on the substrate covers an orthographic projection of the auxiliary signal line on the substrate.
In some embodiments, the display panel further includes, in the non-display area: a gate insulating layer between the substrate and the interlayer insulating layer; the auxiliary signal line extends between the gate insulating layer and the capacitor dielectric layer, and is electrically connected with the negative voltage signal line through via holes arranged on the capacitor dielectric layer and the interlayer insulating layer; or the auxiliary signal line extends between the capacitor dielectric layer and the interlayer insulating layer.
In some embodiments, the display panel further includes, in the non-display area: a gate insulating layer between the substrate and the interlayer insulating layer; and the capacitance dielectric layer is positioned between the gate insulating layer and the interlayer insulating layer, wherein the auxiliary signal line comprises a first conducting wire part and a second conducting wire part, the first conducting wire part extends between the gate insulating layer and the capacitance dielectric layer, the second conducting wire part extends between the capacitance dielectric layer and the interlayer insulating layer, the orthographic projection of the first conducting wire part on the substrate is overlapped with the orthographic projection of the second conducting wire part on the substrate, and the first conducting wire part is electrically connected with the second conducting wire part through a through hole arranged on the capacitance dielectric layer.
The display panel further includes, in the non-display area: the retaining wall structure is arranged around the display area and is positioned on one side, far away from the substrate, of the negative pressure signal line; and the orthographic projection of the auxiliary signal line on the substrate is overlapped with the orthographic projection of the retaining wall structure on the substrate.
In some embodiments, the retaining wall structure includes at least two sub-retaining walls spaced from each other, each sub-retaining wall is disposed around the display area, the auxiliary signal line includes at least two sub-auxiliary signal lines, the number of the sub-auxiliary signal lines is less than or equal to the number of the sub-retaining walls, and an orthographic projection of each sub-auxiliary signal line on the substrate overlaps with an orthographic projection of one sub-retaining wall on the substrate.
In some embodiments, the bus width of the auxiliary signal line is 20% to 75% of the total line width of the negative voltage signal line.
In some embodiments, the negative voltage signal line includes a third conductor portion and a fourth conductor portion, the third conductor portion is located on a side of the interlayer insulating layer facing away from the substrate, the fourth conductor portion is located on a side of the third conductor portion facing away from the substrate, and an orthographic projection of the third conductor portion on the substrate overlaps with an orthographic projection of the fourth conductor portion on the substrate.
In some embodiments, the display panel further comprises:
the light-emitting element layer is positioned on one side, away from the substrate, of the interlayer insulating layer and comprises a plurality of light-emitting elements, each light-emitting element comprises a first electrode, an organic light-emitting layer and a second electrode which are sequentially arranged in the direction away from the substrate, and the negative-voltage signal line is electrically connected with the second electrodes of the light-emitting elements.
In a second aspect, an embodiment of the present application provides a method for manufacturing a display panel, where the method includes: providing a substrate; forming an auxiliary signal line on the substrate; forming an interlayer insulating layer on the auxiliary signal line, and forming a via hole on the interlayer insulating layer; and forming a negative voltage signal line on the interlayer insulating layer, wherein the negative voltage signal line is electrically connected with the auxiliary signal line through a via hole formed in the interlayer insulating layer.
In a third aspect, an embodiment of the present application provides a display device, which is characterized by comprising the display panel according to any one of the embodiments of the first aspect.
The display panel comprises a display area and a non-display area, wherein the non-display area comprises a substrate, an auxiliary signal line, an interlayer insulating layer and a negative voltage signal line which are sequentially stacked, and the auxiliary signal line is electrically connected with the negative voltage signal line through a via hole formed in the interlayer insulating layer. Therefore, the auxiliary signal line is electrically connected with the negative-pressure signal line in the non-display area of the display panel, so that the cross-sectional area of the auxiliary signal line is increased on the basis of the original cross-sectional area of the negative-pressure signal line, the resistance of the negative-pressure signal line is reduced, the resistance drop at two ends of the display panel is reduced, the technical problems that the brightness of the display panel is not uniform and the display is abnormal due to the resistance drop are weakened or even eliminated, and the display effect and the user experience of the display panel are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a top view of a display panel provided in an embodiment of the present application;
FIG. 2 is a schematic cross-sectional view of a non-display region at B1-B2 of a display panel provided in the first embodiment of the present application;
fig. 3 is a schematic cross-sectional view of a display area of a display panel provided in an embodiment of the present application;
FIG. 4 is a schematic cross-sectional view of a non-display region at B1-B2 of a display panel provided in the second embodiment of the present application;
FIG. 5 is a schematic cross-sectional view of a non-display region at B1-B2 of a display panel provided in the third embodiment of the present application;
FIG. 6 is a schematic cross-sectional view of a non-display region at B1-B2 of a display panel provided in a fourth embodiment of the present application;
FIG. 7 is a schematic cross-sectional view of a non-display region at B1-B2 of a display panel provided in a fifth embodiment of the present application;
FIG. 8 is a schematic cross-sectional view of a non-display region at B1-B2 of a display panel provided in a sixth embodiment of the present application;
FIG. 9 is a schematic cross-sectional view of a non-display region at B1-B2 of a display panel provided in a seventh embodiment of the present application;
FIG. 10 is a schematic cross-sectional view of a non-display region at B1-B2 of a display panel provided in an eighth embodiment of the present application;
FIG. 11 is a schematic cross-sectional view of a non-display region at B1-B2 of a display panel provided in a ninth embodiment of the present application;
fig. 12 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present application.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.
As described in the background art, in some narrow-bezel display devices, the display panel has problems of non-uniform brightness and abnormal display during display.
The inventor of the present application finds that the problems of non-uniform brightness and abnormal display of the display panel during display of the display device with the narrow frame mainly occur due to the limitation of the narrow frame, so that the wiring space of the negative voltage signal line (abbreviated as ELVSS line) in the narrow frame is insufficient, the width of the negative voltage signal line is narrow, the resistance of the negative voltage signal line is increased, and further the resistance drop (IR-drop) at two ends of the display panel is increased, and the technical problems of non-uniform brightness and abnormal display of the display panel during display of the display panel occur.
Based on the above findings, embodiments of the present application provide a display panel, a manufacturing method thereof, and a display device, so as to solve the technical problems of uneven brightness and abnormal display in the display of the display panel.
The technical idea of the embodiment of the application is as follows: the auxiliary signal line is additionally arranged in the non-display area of the display panel and is electrically connected with the negative-pressure signal line, so that the cross-sectional area of the auxiliary signal line is increased on the basis of the original cross-sectional area of the negative-pressure signal line, the resistance of the negative-pressure signal line is reduced, the resistance voltage drop at two ends of the display panel is reduced, the technical problems that the brightness of the display panel is not uniform and abnormal display is caused by the resistance voltage drop when the display panel displays are weakened or even eliminated, and the display effect and the user experience of the display panel are improved.
The following first describes a display panel provided in an embodiment of the present application.
Fig. 1 is a top view of a display panel provided in an embodiment of the present application. As shown in fig. 1, the display panel 100 includes a display area 100a and a non-display area 100b surrounding the display area 100 a.
Fig. 2 is a schematic cross-sectional view of a non-display region at B1-B2 of a display panel provided in the first embodiment of the present application. As shown in fig. 2, the non-display area 100b includes a substrate 110, an auxiliary signal line 120, an interlayer insulating layer 130, and a negative voltage signal line 140, which are sequentially stacked, wherein the auxiliary signal line 120 is electrically connected to the negative voltage signal line 140 through a via 121 provided on the interlayer insulating layer 130.
In the embodiment of the present application, the substrate 110 may be made of Polyimide (PI), for example, but may also be made of other organic materials, and the present application is not limited thereto.
The interlayer insulating layer 130 may be made of, for example, silicon oxide (SiOx) or silicon nitride (SiNx), or may be made of other materials, which is not limited thereto. In the display region 100a, the interlayer insulating layer 130 is mainly used to stabilize the characteristics of the transistor covered by the interlayer insulating layer 130, for example, to improve the leakage current problem of the transistor.
The embodiment of the application adds the auxiliary signal line to be electrically connected with the negative pressure signal line in the non-display area of the display panel, so that the cross-sectional area of the auxiliary signal line is increased on the basis of the original cross-sectional area of the negative pressure signal line, the resistance of the negative pressure signal line is reduced, the resistance drop at two ends of the display panel is reduced, the technical problems that the brightness of the display panel is not uniform and the display is abnormal due to the resistance drop are weakened or even eliminated, and the display effect and the user experience of the display panel are improved.
In the embodiment of the present application, the negative voltage signal line is connected to the cathode of the light emitting element in the display area 100a, and is mainly used for providing a negative voltage to each light emitting element.
Fig. 3 is a schematic cross-sectional view of a display area of a display panel provided in an embodiment of the present application. As shown in fig. 3, the display area 100a includes: the capacitor comprises a substrate 110, a gate insulating layer 150, a capacitor dielectric layer 160, an interlayer insulating layer 130, a transistor 170 and a capacitor second metal layer 180, wherein the substrate 110, the gate insulating layer 150, the capacitor dielectric layer 160 and the interlayer insulating layer 130 are sequentially stacked. The transistor 170 includes a gate metal layer 1701, a source/drain metal layer 1702, and an active layer 1703. Gate metal layer 1701, which is located below capacitor second metal layer 180 and is also referred to as a capacitor first metal layer, forms a capacitor together with capacitor second metal layer 180.
The display area 100a further includes:
a planarization layer 190 on a side of the interlayer insulating layer 130 facing away from the substrate 110;
a first electrode layer 2001, located on a side of the planarization layer 190 away from the substrate 110, and electrically connected to the source-drain metal layer 1702 via a via hole disposed on the planarization layer 190;
a pixel defining layer 210 on a side of the planarization layer 190 facing away from the substrate 110, the pixel defining layer 210 including a plurality of pixel openings, the first electrode layer 2001 corresponding to the pixel openings;
an organic light emitting layer 2002 on a side of the first electrode layer 2001 facing away from the substrate 110 and electrically connected to the first electrode layer 2001, at least a portion of the organic light emitting layer 2002 being disposed in the pixel opening;
a support post 220 on a side of the pixel defining layer 210 facing away from the substrate 110;
and a second electrode layer 2003 on a side of the pixel defining layer 210 facing away from the substrate 110 and electrically connected to the organic light emitting layer 2002.
Here, the first electrode layer 2001, the organic light-emitting layer 2002, and the second electrode layer 2003 constitute the light-emitting element layer 200. In the display region 100a, the light-emitting element layer 200 may include a plurality of light-emitting elements each including a first electrode (located in the first electrode layer 2001), an organic light-emitting layer (located in the organic light-emitting layer 2002), and a second electrode (located in the second electrode layer 2003) which are sequentially provided in a direction away from the substrate 110. The second electrodes of the light-emitting elements are common electrodes, also called common cathodes. In the embodiment of the present application, the negative voltage signal line is electrically connected to the common cathode, that is, the negative voltage signal line is electrically connected to the second electrode layer 2003.
Fig. 4 is a schematic cross-sectional view of a non-display region at B1-B2 of a display panel provided in the second embodiment of the present application. As shown in fig. 4, the display area 100b may further include, corresponding to fig. 3:
a gate insulating layer 150 between the substrate 110 and the interlayer insulating layer 130; and
and a capacitor dielectric layer 160 between the gate insulating layer 150 and the interlayer insulating layer 130.
As shown in fig. 4, in some embodiments, the auxiliary signal line 120 may extend between the gate insulating layer 150 and the capacitor dielectric layer 160, and the auxiliary signal line 120 is electrically connected to the negative voltage signal line 140 through vias disposed on the capacitor dielectric layer 160 and the interlayer insulating layer 130.
Fig. 5 is a schematic cross-sectional view of a non-display region at B1-B2 of a display panel provided in the third embodiment of the present application. As shown in fig. 5, in some embodiments, the auxiliary signal line 120 may also extend between the capacitor dielectric layer 160 and the interlayer insulating layer 130, and the auxiliary signal line 120 is electrically connected to the negative voltage signal line 140 through a via hole disposed on the interlayer insulating layer 130.
Fig. 6 is a schematic cross-sectional view of a non-display region at B1-B2 of a display panel provided in a fourth embodiment of the present application. As shown in fig. 6, in order to further reduce the resistance of the negative voltage signal line 140, reduce the resistance drop across the display panel, and improve the display effect, in some embodiments, the auxiliary signal line 120 includes an upper layer and a lower layer. Specifically, the auxiliary signal line 120 may include a first conducting portion 120a and a second conducting portion 120b, the first conducting portion 120a extends between the gate insulating layer 150 and the capacitor dielectric layer 160, the second conducting portion 120b extends between the capacitor dielectric layer 160 and the interlayer insulating layer 130, an orthogonal projection of the first conducting portion 120a on the substrate 110 overlaps an orthogonal projection of the second conducting portion 120b on the substrate 110, the first conducting portion 120a is electrically connected to the second conducting portion 120b through a via hole disposed on the capacitor dielectric layer 160, and the second conducting portion 120b is electrically connected to the negative voltage signal line 140 through a via hole disposed on the interlayer insulating layer 130.
The auxiliary signal line 120 is a double-layer structure, so that the cross-sectional area of the negative voltage signal line is further increased, the resistance of the negative voltage signal line is further reduced, the resistance drop at two ends of the display panel is further reduced, and the display effect is improved.
Fig. 7 is a schematic cross-sectional view of a non-display region at B1-B2 of a display panel provided in a fifth embodiment of the present application.
In order to further improve the encapsulation effect of the display panel and prevent moisture from invading the display panel along the encapsulation layer, as shown in fig. 7, in some embodiments, the non-display area 100b may further include:
the retaining wall structure 161 is also called a dam structure, the retaining wall structure 161 is disposed around the display region 100a, and the retaining wall structure 161 is located on a side of the negative voltage signal line 140 away from the substrate 110.
In the process of forming the packaging layer by ink-jet printing the organic material, the retaining wall structure can prevent the organic material from overflowing to the outer side of the retaining wall structure, so that the organic material is prevented from overflowing, the packaging failure caused by the invasion of water vapor caused by the overflow of the organic material is avoided, and the packaging effect is improved.
In order to further block the overflow of the organic material, as shown in fig. 7, the orthographic projection of the auxiliary signal line 120 on the substrate 110 overlaps with the orthographic projection of the barrier wall structure 161 on the substrate 110, i.e., at least a partial region of the auxiliary signal line 120 is located right below the barrier wall structure 161. Therefore, at least partial region of the auxiliary signal line is located under the retaining wall structure, so that the height of the retaining wall structure is increased, the capability of the retaining wall structure for blocking the overflow of the organic material is improved, the risk of overflow is reduced, and the reliability of packaging is improved.
Fig. 8 is a schematic cross-sectional view of a non-display region at B1-B2 of a display panel provided in a sixth embodiment of the present application.
In order to further block the overflow of the organic material, as shown in fig. 8, the bank structure 161 may include at least two sub-banks spaced apart from each other, for example, a sub-bank 161a and a sub-bank 161b, each of which is disposed around the display region in the non-display region. Meanwhile, in order to further reduce the resistance of the negative voltage signal line, the auxiliary signal line 120 may include at least two sub-auxiliary signal lines, such as a sub-auxiliary signal line 120c and a sub-auxiliary signal line 120d, where the number of the sub-auxiliary signal lines is less than or equal to the number of the sub-barriers. As an example, an orthogonal projection of each sub auxiliary signal line on the substrate 110 overlaps an orthogonal projection of one sub-bank on the substrate 110. Therefore, at least partial area of each sub auxiliary signal line is positioned under each sub retaining wall, so that the height of each sub retaining wall is increased, the capability of each sub retaining wall for blocking the overflow of the organic material is improved, the risk of overflow is reduced, and the reliability of packaging is improved.
In some embodiments, in order to meet the design requirements of narrow frames with different widths, the bus width of the auxiliary signal line 120 may be determined according to the bus width of the negative voltage signal line. Alternatively, the bus width of the auxiliary signal line 120 may be determined according to a distance between a first boundary and the bank structure, wherein the first boundary is a boundary between the display region 100a and the non-display region 100 b.
Specifically, as shown in fig. 8, the line widths of the first and second line portions 120a and 120b may be determined according to the total line width of the negative voltage signal line, for example, as the total line width of the negative voltage signal line is smaller, the line widths of the first and second line portions 120a and 120b are larger, so that the resistance of the negative voltage signal line is maintained within a preset range, the resistance drop across the display panel is not too large, and the display effect is improved. Similarly, the number of the sub auxiliary signal lines can be flexibly set according to the bus width of the negative voltage signal line, and the application is not limited thereto.
In some embodiments, the orthographic projection of the negative voltage signal line 140 on the substrate 110 covers the orthographic projection of the auxiliary signal line 120 on the substrate 110, i.e., the total line width of the negative voltage signal line 140 may be greater than the total line width of the auxiliary signal line 120. As an example, the bus width of the auxiliary signal line may be 20% to 75% of the total line width of the negative voltage signal line, that is, the bus width of the auxiliary signal line may be flexibly adjusted within a range of 20% to 75% of the total line width of the negative voltage signal line. Along with the increase of the bus width of the auxiliary signal line, the bus width of the negative-pressure signal line can be reduced, and the distance between the first boundary and the retaining wall structure is favorably reduced, so that the design of a narrow frame is more favorably realized.
Fig. 9 is a schematic cross-sectional view of a non-display region at B1-B2 of a display panel provided in a seventh embodiment of the present application.
As shown in fig. 9, in some embodiments, the non-display area 100b may further include:
and a planarization layer 190 and a first electrode layer 2001, which are located between the negative voltage signal line 140 and the retaining wall structure 161, wherein the planarization layer 190 is located on a side of the negative voltage signal line 140 facing away from the substrate 110 and covers the first electrode layer 2001.
Fig. 10 is a schematic cross-sectional view of a non-display region at B1-B2 of a display panel provided in an eighth embodiment of the present application.
As shown in fig. 10, in some embodiments, the retaining wall structure 161 may comprise an upper and a lower double layer. The material of the first layer may be the same as the material of the pixel defining layer 210 in fig. 3, for example, both polyimide. The material of the second layer may be the same as the material of the support posts 220 in fig. 3, for example, both polyimide. It is easily understood that the first layer of the barrier structures 161 of the non-display area 100b may be prepared together with the pixel defining layer 210 in the display area 100a, and the second layer may be prepared together with the supporting pillars 220 in the display area 100 a.
Fig. 11 is a schematic cross-sectional view of a non-display region at B1-B2 of a display panel provided in a ninth embodiment of the present application.
As shown in fig. 11, in some embodiments, the negative voltage signal line 140 includes a third wire portion 140a and a fourth wire portion 140b, the third wire portion 140a is located on a side of the interlayer insulating layer 130 facing away from the substrate 110, the fourth wire portion 140b is located on a side of the third wire portion 140a facing away from the substrate 110, and an orthographic projection of the third wire portion 140a on the substrate 110 overlaps with an orthographic projection of the fourth wire portion 140b on the substrate 110.
The embodiment of the application further provides a preparation method of the display panel, which can be used for manufacturing the display panel of the foregoing embodiment. A method for manufacturing the display panel will be described below with reference to the manufacturing process of the display panel 100 according to the first embodiment.
Fig. 12 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present application, the method for manufacturing a display panel including steps S110 to S140.
In step S110, a substrate is provided.
In step S120, an auxiliary signal line is formed on the substrate.
In step S130, an interlayer insulating layer is formed on the auxiliary signal line, and a via hole is formed on the interlayer insulating layer.
In step S140, a negative voltage signal line is formed on the interlayer insulating layer, wherein the negative voltage signal line is electrically connected to the auxiliary signal line through a via hole provided on the interlayer insulating layer.
According to the display panel prepared by the preparation method of the display panel, the auxiliary signal line is additionally arranged in the non-display area of the display panel and is electrically connected with the negative-pressure signal line, so that the cross sectional area of the auxiliary signal line is increased on the basis of the original cross sectional area of the negative-pressure signal line, the resistance of the negative-pressure signal line is reduced, the resistance voltage drop at two ends of the display panel is reduced, the technical problems of uneven brightness and abnormal display of the display panel caused by the resistance voltage drop during display are weakened or even eliminated, and the display effect and the user experience of the display panel are improved.
In some embodiments, the auxiliary signal line may be prepared together with the gate metal layer and/or the capacitor second electrode metal layer of the display region of the display panel.
In some embodiments, the orthographic projection of the negative voltage signal line on the substrate covers the orthographic projection of the auxiliary signal line on the substrate.
In some embodiments, before step S120, the method for manufacturing a display panel may further include:
forming a gate insulating layer on a substrate;
forming a capacitor dielectric layer on the gate insulating layer;
in some embodiments, the auxiliary signal line extends between the gate insulating layer and the capacitor dielectric layer, and the auxiliary signal line is electrically connected to the negative voltage signal line through via holes disposed on the capacitor dielectric layer and the interlayer insulating layer. In some embodiments, the auxiliary signal line extends between the capacitor dielectric layer and the interlayer insulating layer.
In some embodiments, the auxiliary signal line includes a first conducting portion and a second conducting portion, the first conducting portion extends between the gate insulating layer and the capacitor dielectric layer, the second conducting portion extends between the capacitor dielectric layer and the interlayer insulating layer, an orthographic projection of the first conducting portion on the substrate overlaps an orthographic projection of the second conducting portion on the substrate, and the first conducting portion is electrically connected to the second conducting portion through a via hole disposed on the capacitor dielectric layer.
In some embodiments, the method for manufacturing a display panel may further include:
and arranging a retaining wall structure around the display area on the side of the negative-pressure signal line far away from the substrate, wherein the orthographic projection of the auxiliary signal line on the substrate is overlapped with the orthographic projection of the retaining wall structure on the substrate.
In some embodiments, the retaining wall structure includes at least two sub-retaining walls spaced from each other, each sub-retaining wall is disposed in the non-display region to surround the display region, the auxiliary signal line includes at least two sub-auxiliary signal lines, the number of the sub-auxiliary signal lines is less than or equal to the number of the sub-retaining walls, and an orthographic projection of each sub-auxiliary signal line on the substrate overlaps an orthographic projection of one sub-retaining wall on the substrate.
In some embodiments, the bus width of the auxiliary signal line may be 20% to 75% of the total line width of the negative voltage signal line.
In some embodiments, the negative voltage signal line includes a third conductive portion and a fourth conductive portion, the third conductive portion is located on a side of the interlayer insulating layer facing away from the substrate, the fourth conductive portion is located on a side of the third conductive portion facing away from the substrate, and an orthographic projection of the third conductive portion on the substrate overlaps with an orthographic projection of the fourth conductive portion on the substrate.
In some embodiments, the method for manufacturing a display panel may further include:
when the display region is prepared, a light-emitting element layer is formed on the side of the interlayer insulating layer away from the substrate. The light-emitting element layer comprises a plurality of light-emitting elements, and each light-emitting element comprises a first electrode, an organic light-emitting layer and a second electrode which are sequentially arranged in the direction away from the substrate. In the embodiment of the present application, the negative voltage signal line is electrically connected to the second electrodes of the plurality of light emitting elements.
The embodiment of the present application further provides a display device, for example, a device with an image display function, such as a mobile phone and a tablet computer, including the display panel 100 of any of the above embodiments.
According to the display device provided by the embodiment of the application, the auxiliary signal line is additionally arranged in the non-display area of the display panel of the display device and is electrically connected with the negative voltage signal line, so that the cross sectional area of the auxiliary signal line is increased on the basis of the original cross sectional area of the negative voltage signal line, the resistance of the negative voltage signal line is reduced, the resistance voltage drop at two ends of the display panel is reduced, the technical problems that the brightness of the display panel is not uniform and the display is abnormal due to the resistance voltage drop are weakened or even eliminated, and the display effect and the user experience of the display panel are improved.
In accordance with the above-described embodiments of the present invention, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. The display panel is characterized by comprising a display area and a non-display area, wherein the non-display area comprises a substrate, an auxiliary signal line, an interlayer insulating layer and a negative voltage signal line which are sequentially stacked, and the auxiliary signal line is electrically connected with the negative voltage signal line through a via hole formed in the interlayer insulating layer.
2. The display panel according to claim 1, wherein an orthogonal projection of the negative-voltage signal line on the substrate covers an orthogonal projection of the auxiliary signal line on the substrate.
3. The display panel according to claim 1, wherein the non-display region further comprises:
a gate insulating layer between the substrate and the interlayer insulating layer; and
a capacitor dielectric layer between the gate insulating layer and the interlayer insulating layer,
the auxiliary signal line extends between the gate insulating layer and the capacitor dielectric layer, and is electrically connected with the negative voltage signal line through via holes arranged on the capacitor dielectric layer and the interlayer insulating layer; or
The auxiliary signal line extends between the capacitor dielectric layer and the interlayer insulating layer.
4. The display panel according to claim 1, wherein the non-display region further comprises:
a gate insulating layer between the substrate and the interlayer insulating layer; and
a capacitor dielectric layer between the gate insulating layer and the interlayer insulating layer,
the auxiliary signal line comprises a first conducting wire portion and a second conducting wire portion, the first conducting wire portion extends between the grid insulating layer and the capacitor dielectric layer, the second conducting wire portion extends between the capacitor dielectric layer and the interlayer insulating layer, an orthographic projection of the first conducting wire portion on the substrate is overlapped with an orthographic projection of the second conducting wire portion on the substrate, and the first conducting wire portion is electrically connected with the second conducting wire portion through a through hole formed in the capacitor dielectric layer.
5. The display panel according to claim 1, wherein the non-display region further comprises:
the retaining wall structure is arranged around the display area and is positioned on one side, far away from the substrate, of the negative-pressure signal line;
and the orthographic projection of the auxiliary signal line on the substrate is overlapped with the orthographic projection of the retaining wall structure on the substrate.
6. The display panel according to claim 5, wherein the dam structure comprises at least two sub-dams spaced from each other, each sub-dam is disposed around the display region, the auxiliary signal lines comprise at least two sub-auxiliary signal lines, the number of the sub-auxiliary signal lines is less than or equal to the number of the sub-dams, and an orthographic projection of each sub-auxiliary signal line on the substrate overlaps with an orthographic projection of one sub-dam on the substrate.
7. The display panel according to claim 1, wherein the negative voltage signal line includes a third wiring portion and a fourth wiring portion, the third wiring portion is located on a side of the interlayer insulating layer facing away from the substrate, the fourth wiring portion is located on a side of the third wiring portion facing away from the substrate, and an orthographic projection of the third wiring portion on the substrate overlaps with an orthographic projection of the fourth wiring portion on the substrate.
8. The display panel according to claim 1, characterized in that the display panel further comprises:
the light-emitting element layer is positioned on one side, away from the substrate, of the interlayer insulating layer and comprises a plurality of light-emitting elements, each light-emitting element comprises a first electrode, an organic light-emitting layer and a second electrode which are sequentially arranged in the direction away from the substrate, and the negative-voltage signal line is electrically connected with the second electrodes of the light-emitting elements.
9. A method for manufacturing a display panel, the method comprising:
providing a substrate;
forming an auxiliary signal line on the substrate;
forming an interlayer insulating layer on the auxiliary signal line, and forming a via hole on the interlayer insulating layer;
and forming a negative voltage signal line on the interlayer insulating layer, wherein the negative voltage signal line is electrically connected with the auxiliary signal line through a via hole formed in the interlayer insulating layer.
10. A display device characterized by comprising the display panel according to any one of claims 1 to 8.
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Cited By (1)
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| WO2023070404A1 (en) * | 2021-10-27 | 2023-05-04 | 京东方科技集团股份有限公司 | Display panel and preparation method therefor, and display apparatus |
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