CN112838099A - Display panel and display device - Google Patents
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- CN112838099A CN112838099A CN202110017059.1A CN202110017059A CN112838099A CN 112838099 A CN112838099 A CN 112838099A CN 202110017059 A CN202110017059 A CN 202110017059A CN 112838099 A CN112838099 A CN 112838099A
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- 239000002184 metal Substances 0.000 claims abstract description 143
- 238000009413 insulation Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 abstract description 26
- 230000005684 electric field Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 238000009826 distribution Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000001846 repelling effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- -1 argon ions Chemical class 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000005288 electromagnetic effect Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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Abstract
The invention provides a display panel and a display device, wherein the display panel comprises a first metal layer and an insulating layer arranged on the first metal layer; the first metal layer comprises a first overlapping area, the first overlapping area is an area where the first metal layer and the insulating layer are overlapped, and the first overlapping area comprises at least one hollow-out area; the scheme can reduce the positive area of the first metal layer and the insulating layer so as to reduce the difference between the concentration of negative ions and the concentration of positive ions deposited on the first metal layer, thereby improving the compactness of the insulating layer.
Description
Technical Field
The invention relates to the technical field of display, in particular to the field of manufacturing of display devices, and particularly relates to a display panel and a display device.
Background
The Mini LED (sub-millimeter Light Emitting Diode) technology is a technology for integrating an LED array having a size of 100 μm on a chip, and a Mini LED display panel manufactured by using the technology has advantages of adjustable area brightness, high color rendering, high contrast, and the like.
At present, the current conducted by a part of metal wires in a Mini LED panel driven by active addressing is large, so the width of the metal wires is correspondingly set to be large. In the process of forming an insulating layer on the metal wire by Physical Vapor Deposition (PVD), one side of the metal wire close to the target is positively charged, and the larger width results in a larger area of the metal wire facing the plasma, and one side of the metal wire close to the target attracts more negative ions in the plasma and repels more positive ions in the plasma, so that the negative ions and the positive ions in the plasma cannot be uniformly deposited on the metal wire, which results in an excessively large difference between the concentration of the negative ions and the concentration of the positive ions in the insulating layer, and reduces the compactness of the insulating layer.
In view of the above, it is desirable to provide a display panel and a display device in which the density of an insulating layer can be improved.
Disclosure of Invention
The invention aims to provide a display panel and a display device, which comprise a first metal layer and an insulating layer arranged on the first metal layer, wherein the overlapped area of the first metal layer and the insulating layer is set to comprise at least one hollow area, so that the problem that in the prior art, negative ions and positive ions in plasma cannot be uniformly deposited on a metal wire due to the fact that the positive area of the metal wire and the plasma is large, and the formed insulating layer is low in compactness is solved.
The embodiment of the invention provides a display panel, which comprises a first metal layer and an insulating layer arranged on the first metal layer;
the first metal layer comprises a first overlapping area, the first overlapping area is an area where the first metal layer and the insulating layer are overlapped, and the first overlapping area comprises at least one hollow-out area.
In an embodiment, a shape of one of the at least one hollow-out area is a rectangle, a circle or a sawtooth.
In an embodiment, the at least one hollow area includes a plurality of hollow areas, and the plurality of hollow areas are arranged in an array or arranged in parallel.
In one embodiment, the insulating layer includes:
a plurality of insulating portions provided at intervals;
the first overlap region includes:
a plurality of first sub-overlapping areas, wherein the plurality of first sub-overlapping areas are a plurality of areas where the first metal layer and the insulating layer overlap, and each of the plurality of first sub-overlapping areas includes at least one hollowed-out area.
In one embodiment, the first metal layer further comprises:
the first connecting areas are included between two adjacent first sub-overlapping areas in the plurality of first sub-overlapping areas, and the first connecting areas connect the two corresponding first sub-overlapping areas.
In an embodiment, the first connection region is a continuous region.
In an embodiment, the width of the first connection region is greater than the width of the corresponding two first sub-overlapping regions.
In one embodiment, the display panel further includes:
the second metal layer is arranged on one side, far away from the first metal layer, of the insulating layer and comprises a second overlapping area, the second overlapping area is an area where the second metal layer and the insulating layer are overlapped, and the second overlapping area comprises at least one hollow area.
The embodiment of the invention also provides a display device, which comprises any one of the display panels.
The embodiment of the invention also provides a display panel, which comprises a first metal layer and an insulating layer arranged on the first metal layer;
the insulating layer comprises a plurality of insulating parts which are arranged at intervals;
the first metal layer comprises a plurality of first overlapping areas and a plurality of first connecting areas, the plurality of first sub overlapping areas are a plurality of areas where the first metal layer and the insulating layer are overlapped, a first connecting area is arranged between two adjacent first sub overlapping areas in the plurality of first sub overlapping areas, and the first connecting areas are connected with the corresponding two first sub overlapping areas;
wherein a width of each of the plurality of first sub-overlapping regions is smaller than a width of each of the plurality of first connection regions and a width of the corresponding insulation portion.
The invention provides a display panel and a display device, wherein the display panel comprises a first metal layer and an insulating layer arranged on the first metal layer, the first metal layer comprises a first overlapping area, the first overlapping area is an area where the first metal layer and the insulating layer are overlapped, and the first overlapping area comprises at least one hollow-out area. According to the invention, the first overlapping area is set to comprise at least one hollow-out area, so that the facing area of the first metal layer and the insulating layer is reduced, the capability of the first metal layer for attracting negative ions and the capability of the first metal layer for repelling positive ions are reduced, the difference between the concentration of the negative ions and the concentration of the positive ions deposited on the first metal layer is reduced, and the compactness of the insulating layer formed on the first metal layer is improved.
Drawings
The invention is further illustrated by the following figures. It should be noted that the drawings in the following description are only for illustrating some embodiments of the invention, and that other drawings may be derived from those drawings by a person skilled in the art without inventive effort.
Fig. 1 is a top view of a first display panel according to an embodiment of the invention.
Fig. 2 is a top view of a second display panel according to an embodiment of the invention.
Fig. 3 is a top view of a third display panel according to an embodiment of the invention.
Fig. 4 is a top view of a fourth display panel according to an embodiment of the invention.
Fig. 5 is a top view of a fifth display panel according to an embodiment of the invention.
Fig. 6 is a top view of a sixth display panel according to an embodiment of the invention.
Fig. 7 is a top view of a seventh display panel according to an embodiment of the invention.
Fig. 8 is a top view of an eighth display panel according to an embodiment of the present invention.
Fig. 9 is a top view of a ninth display panel according to an embodiment of the invention.
Fig. 10 is a top view of a tenth display panel according to an embodiment of the invention.
Fig. 11 is a top view of an eleventh display panel according to an embodiment of the invention.
Fig. 12 is a top view of a twelfth display panel according to an embodiment of the disclosure.
Fig. 13 is a top view of a thirteenth display panel according to an embodiment of the disclosure.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "far away", "close", "vertical", and the like indicate the orientation or positional relationship based on the drawings, wherein "upper" simply means the surface above the object, specifically refers to the right above, obliquely above, and upper surface, and "close" means the side having a smaller distance to the target in comparison as long as the object is on the level, and the above orientation or positional relationship is only for convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus cannot be construed as limiting the present invention.
In addition, it should be noted that the drawings only provide the structures closely related to the present invention and omit some details not so related to the present invention, so as to simplify the drawings and make the invention clear, but not to show the actual device or the same as the drawings and not to limit the actual device and method.
The present invention provides a display panel including, but not limited to, the following embodiments and combinations between the following embodiments.
In one embodiment, as shown in fig. 1 to 3, the display panel 00 includes a first metal layer 10 and an insulating layer 20 disposed on the first metal layer 10; the first metal layer 10 includes a first overlapping region 01, the first overlapping region 01 is a region where the first metal layer 10 and the insulating layer 20 overlap, and the first overlapping region 01 includes at least one hollow-out region 011.
It can be understood that, in the process of forming the insulating layer 20 on the first metal layer 10 by PVD, a substrate bearing a target is applied with a negative voltage, and a substrate bearing the first metal layer 10 is applied with a positive voltage, so as to form an electric field pointing from the first metal layer 10 to the target, and under the action of the electric field, the positively charged argon ions bombard the target, and target atoms sputtered from the target are sputtered to a side of the first metal layer 10 close to the target with a certain energy, so as to form the insulating layer 20. However, the electric field also causes the side of the first metal layer 10 close to the target to be positively charged, so as to attract more negative ions in the target atoms and repel more positive ions in the target atoms, so that the negative ions and the positive ions in the target atoms cannot be uniformly deposited on the first metal layer 10, and the compactness of the insulating layer 20 finally formed on the first metal layer 10 is reduced.
Therefore, as shown in fig. 1 to 3, by providing at least one hollowed-out region 011 in the first overlapping region 01, which is equivalent to performing a hollowing process on a partial region in the first overlapping region 01, in the process of forming the insulating layer 20 on the first metal layer 10 by PVD, the facing areas of the first metal layer 10 and the target atoms are reduced, the coverage area of the electric field formed between the first metal layer 10 and the target atoms is reduced, the ability of the first metal layer 10 to attract negative ions and the ability of the first metal layer 10 to repel positive ions are reduced, and thus the compactness of the insulating layer 20 formed on the first metal layer 10 is improved.
When the insulating layer 20 is a continuous film, the insulating layer 20 may cover the entire area of the first metal layer 10, or the insulating layer 20 may cover a partial area of the first metal layer 10. When the insulating layer 20 covers the entire area of the first metal layer 10, the first overlapping area 01 is the entire area of the first metal layer 10, that is, the entire area of the first metal layer 10 may be patterned; when the insulating layer 20 covers a partial region of the first metal layer 10, the first overlapping region 01 is the partial region of the first metal layer 10, that is, the partial region of the first metal layer 10 may be subjected to patterning.
It should be noted that the number, size and shape of the at least one hollowed-out region 011 can be set according to the size, position and shape of the first overlapping region 01 on the first metal layer 10. For example, when the size of the first overlap region 01 on the first metal layer 10 is larger, the number of the at least one hollow-out region 011 may be larger or the size may be larger; the at least one hollowed-out region 011 and the shape may be the same as the shape of the first overlapping region 01 to improve the uniformity of the current distribution in the first metal layer 10.
In an embodiment, as shown in fig. 1, a shape of one of the at least one hollow area 011 is rectangular, circular or zigzag.
Specifically, when the at least one hollow-out region 011 includes one hollow-out region 011, the hollow-out region 011 can be close to or include the middle region of the first overlapping region 01, so as to avoid the heat generation caused by the excessive local current in the first overlapping region 01. The shape of the hollowed-out region 011 is rectangular, circular or zigzag, and further, the hollowed-out region 011 can be an axisymmetric pattern or a centrosymmetric pattern so as to improve the uniformity of current distribution in the first overlapping region 01.
Specifically, when the at least one hollow area 011 includes a plurality of hollow areas 011, the at least one hollow area 011 can be uniformly arranged in the first overlapping area 01. Each of the plurality of hollowed-out regions 011 can be the same or different in shape, for example, each hollowed-out region 011 can be rectangular, circular or zigzag, and for example, as shown in fig. 1, the plurality of hollowed-out regions 011 includes a rectangular hollowed-out region 011, a circular hollowed-out region 011 and a zigzag hollowed-out region 011. It is understood that the number, size and shape of the at least one hollowed-out region 011 can be set according to the related description above.
It should be noted that, no matter that the at least one hollow area 011 includes one hollow area 011 or a plurality of hollow areas 011, the shape of the hollow area 011 can also be elliptical, triangular, fan-shaped, and the like, as long as the hollow area 011 is a single communication area, and correspondingly, the at least one hollow area 011 makes the first overlapping area 01 be a multi-communication area.
In an embodiment, as shown in fig. 2 to 5, the at least one hollow area 011 includes a plurality of hollow areas 011, and the plurality of hollow areas 011 are arranged in an array or arranged in parallel.
Specifically, as shown in fig. 2, the plurality of hollow-out regions 011 can be all square, and the plurality of hollow-out regions 011 can be all the same in size, and the plurality of hollow-out regions 011 can be arranged in an array of 3 × 3. The shape of the whole of the plurality of hollow-out regions 011 can be consistent with the shape of each hollow-out region 011. For example, when each of the plurality of hollow areas 011 is shaped as a centrosymmetric pattern, the plurality of hollow areas 011 can be arranged in a square matrix; when the shape of each hollowed-out area 011 is a non-centrosymmetric figure, the hollowed-out areas 011 can be arranged in a rectangular square matrix in an array manner, and the distribution condition of the long side and the short side of the rectangular square matrix can be similar to the size of the edge of each hollowed-out area 011.
Specifically, as shown in fig. 3, the first overlapping area 01 is illustrated as a rectangle. The shapes of the plurality of hollowed-out regions 011 can be rectangular, the sizes of the plurality of hollowed-out regions 011 can be the same, the plurality of hollowed-out regions 011 can be parallel to the long edge of the first overlapping region 01, and the distance between two adjacent hollowed-out regions 011 can be equal. The shapes of the plurality of hollow-out regions 011 can be saw-tooth, wave or linear shapes similar to strips with certain widths. It is understood that the plurality of c may be uniformly arranged along a predetermined direction in a shape similar to a stripe.
Specifically, as shown in fig. 4, the shapes of the plurality of hollow-out regions 011 can be all parallelograms, and it can also be understood that the plurality of hollow-out regions 011 in fig. 4 are formed by inclining the plurality of hollow-out regions 011 in fig. 3 along a preset direction; specifically, as shown in fig. 5, on the basis that the plurality of hollow areas 011 are all obliquely arranged along a preset direction, the upper sides and the lower sides of the plurality of hollow areas 011 can also be located on the same horizontal line respectively.
In one embodiment, as shown in fig. 6-9, the insulating layer 20 includes: a plurality of insulating parts 201, the insulating parts 201 being arranged at intervals; the first overlap region 01 includes: a plurality of first sub-overlapping areas 012, where the plurality of first sub-overlapping areas 012 are areas where the first metal layer 10 and the insulating layer 20 overlap, and each of the plurality of first sub-overlapping areas 012 includes at least one hollowed-out area 0121.
The hollowed areas 0121 in the first sub-overlapping areas 012 may be the same or different, and the shape, size, number, and arrangement of the hollowed areas 0121 in each first sub-overlapping area 012 may refer to the related description of the hollowed areas 0121 in the first sub-overlapping areas 012 above.
Specifically, the first metal layer 10 is described as including two first sub-overlapping areas 012, as shown in fig. 6, the two first sub-overlapping areas 012 are different from each other in that a plurality of hollowed-out areas 0121 in the left first sub-overlapping area 012 are arranged in parallel to one side of the first sub-overlapping area 012, and a plurality of hollowed-out areas 0121 in the right first sub-overlapping area 012 are arranged in parallel to the other side of the first sub-overlapping area 012; as shown in fig. 7, the hollowed areas 0121 in the two first sub-overlapping areas 012 are the same, and the hollowed areas 0121 in the two first sub-overlapping areas 012 are all parallel to each other along a direction parallel to one side of the first sub-overlapping areas 012.
Further, as shown in fig. 8, a plurality of hollowed-out areas 0121 in the two first sub-overlapping areas 012 are all arranged in parallel to one side of the first sub-overlapping area 012, and the hollowed-out areas 0121 also extend into the non-overlapping area of the first metal layer 10 and the insulating layer 20, so as to further reduce the facing area of the first metal layer 10 and the insulating layer 20; further, as shown in fig. 9, a plurality of hollow areas 0121 in the two first sub-overlapping areas 012 are all arranged in parallel to one side of the first sub-overlapping area 012, and the two hollow areas 0121 in the same position in the two first sub-overlapping areas 012 extend to each other, so that the two hollow areas 0121 form a single communicating area, which is equivalent to reducing the number of the single communicating areas in the first metal layer 10, and reducing the difficulty of patterning.
In one embodiment, as shown in fig. 6-9, the first metal layer 10 further includes: and a plurality of first connection regions 03, one first connection region 03 being included between two adjacent first sub-overlap regions 012 among the plurality of first sub-overlap regions 012, and the first connection region 03 connecting the corresponding two first sub-overlap regions 012.
The first connection region 03 may be understood as a region located between two adjacent insulating portions 201 and connecting two corresponding first sub-overlapping regions 012, and the first connection region 03 makes the first metal layer 10 have a continuous structure so that a current can be transmitted from the first sub-overlapping region 012 close to the left side to the first sub-overlapping region 012 close to the right side.
In one embodiment, as shown in fig. 6-8, the first connection region 03 is a continuous region. It can be understood that, when the first connection region 03 does not include any hollow region, any region within the outer contour of the first connection region 03 can conduct current, so as to reduce the current per unit area, and effectively reduce the risk of the first metal layer 10 being blown.
In one embodiment, as shown in fig. 10, the width of the first connecting area 03 is greater than the width of the corresponding two first sub-overlapping areas 012. It can be understood that at least one hollowed-out region 0121 is disposed in the first sub-overlapping region 012, which results in an increase in resistance of the first sub-overlapping region 012, so that the current per unit area is relatively large, and the width of the first connection region 03 is set to be greater than the width of the two corresponding first sub-overlapping regions 012, which can share relatively more current, thereby effectively reducing the risk of the first metal layer 10 being burned out.
In one embodiment, as shown in fig. 11, the display panel 00 further includes: the second metal layer 30, the second metal layer 30 is disposed on a side of the insulating layer 20 away from the first metal layer 10, the second metal layer 30 includes a second overlapping area 04, the second overlapping area 04 is an area where the second metal layer 30 and the insulating layer 20 overlap, and the second overlapping area 04 includes at least one hollow area 041.
It is understood that the insulating layer 20 is used to insulate the first metal layer 10 and the second metal layer 30, so that the vertical projection of the second metal layer 30 on the insulating layer 20 does not exceed the boundary of the insulating layer 20, and short circuit between the second metal layer 30 and the first metal layer 10 or other conductive layers is avoided. Therefore, the second overlapped area 04 may be understood as the entire area of the second metal layer 30.
Specifically, the shape, size, number and arrangement of the at least one hollowed-out area 041 in the second overlapping area 0 may refer to the related description of the hollowed-out area 0121 in the first sub-overlapping area 012 above.
It should be noted that in this embodiment, the magnitude of the current conducted in the second metal layer 30 may be smaller than the magnitude of the current conducted in the first metal layer 10. For example, when the display panel 00 is an OLED (Organic Light-Emitting Diode) display panel or a Mini LED display panel, since the Light Emitting device is driven by current, when the driving transistor of the Light Emitting device is an N-type transistor, the first metal layer 10 may be a power line, and the second metal layer 30 may be a data line, and according to the operating characteristics of the N-type transistor, the current conducted in the second metal layer 30 is much smaller than the current conducted in the first metal layer 10, and therefore, the width of the second metal layer 30 may be much smaller than the width of the first metal layer 10.
Specifically, as shown in fig. 12, the second metal layer 30 may include a plurality of second metal portions 301, the plurality of second metal portions 301 are strip-shaped, the plurality of second metal portions 301 are parallel to each other, at least two second metal portions 301 may be disposed on each of the insulating portions 201, and the two second metal portions 301 respectively transmit corresponding power voltage signals to corresponding N-type transistors.
The present invention also provides a display panel including, but not limited to, the following embodiments and combinations between the following embodiments.
In one embodiment, as shown in fig. 13, the display panel 000 includes a first metal layer 100 and an insulating layer 200 disposed on the first metal layer 100; the insulating layer 200 comprises a plurality of insulating parts 201, and the insulating parts 201 are arranged at intervals; the first metal layer 100 includes a plurality of first overlapping regions 101 and a plurality of first connecting regions 102, the plurality of first sub-overlapping regions 101 are regions where the first metal layer 100 and the insulating layer 200 overlap, a first connecting region 102 is included between two adjacent first sub-overlapping regions 101 in the plurality of first sub-overlapping regions 101, and the first connecting region 102 connects the two corresponding first sub-overlapping regions 101; wherein a width of each of the first sub-overlapping regions 101 is smaller than a width of each of the first connection regions 102 and a width of the corresponding insulating portion 201 in the first sub-overlapping regions 101.
It can be understood that the difference between this embodiment and the embodiment shown in fig. 8 is that the first metal layer 100 in this embodiment may be configured as a continuous film, that is, the plurality of first overlapping regions 101 are a single connected region and do not include any hollow region. It can be understood that, in the present embodiment, by setting the width of each first sub-overlap region 101 to be smaller than the width of each first connection region 102 in the plurality of first connection regions 102, during the formation of the insulating layer 200 on the first metal layer 10 by PVD, the facing areas of the first metal layer 100 and the target atoms are reduced, the coverage of the electric field formed between the first metal layer 100 and the target atoms is reduced, the ability of the first metal layer 100 to attract negative ions and the ability of the first metal layer 10 to repel positive ions are reduced, and thus the compactness of the insulating layer 200 formed on the first metal layer 100 is improved.
It can be understood that, in any of the above display panels, the facing areas of the first metal layer and the second metal layer are also reduced accordingly, so that, when the first metal layer and the second metal layer respectively conduct current at a later stage, the coverage area covered by the magnetic field generated by the "electromagnetic effect" between the first metal layer and the second metal layer is also reduced. Therefore, the display panel can reduce the magnetic field between the first metal layer and the second metal layer, reduce the probability of breakdown of the insulating layer, and improve the compactness of the insulating layer.
The present invention provides a display device, the display device comprising the display panel described above.
The invention provides a display panel and a display device, wherein the display panel comprises a first metal layer and an insulating layer arranged on the first metal layer, the first metal layer comprises a first overlapping area, the first overlapping area is an area where the first metal layer and the insulating layer are overlapped, and the first overlapping area comprises at least one hollow-out area. According to the invention, the first overlapping area is set to comprise at least one hollow-out area, so that the facing area of the first metal layer and the insulating layer is reduced, the capability of the first metal layer for attracting negative ions and the capability of the first metal layer for repelling positive ions are reduced, the difference between the concentration of the negative ions and the concentration of the positive ions deposited on the first metal layer is reduced, and the compactness of the insulating layer formed on the first metal layer is improved.
The display panel and the display device provided by the embodiment of the present invention are described in detail above, and the principle and the embodiment of the present invention are explained in detail herein by applying specific examples, and the description of the above embodiments is only used to help understanding the technical solution and the core idea of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. The display panel is characterized by comprising a first metal layer and an insulating layer arranged on the first metal layer;
the first metal layer comprises a first overlapping area, the first overlapping area is an area where the first metal layer and the insulating layer are overlapped, and the first overlapping area comprises at least one hollow-out area.
2. The display panel of claim 1, wherein a shape of one of the at least one hollowed-out region is rectangular, circular, or zigzag.
3. The display panel of claim 1, wherein the at least one hollow area comprises a plurality of hollow areas, and the plurality of hollow areas are arranged in an array or arranged in parallel.
4. The display panel of claim 1, wherein:
the insulating layer includes:
a plurality of insulating portions provided at intervals;
the first overlap region includes:
a plurality of first sub-overlapping areas, wherein the plurality of first sub-overlapping areas are a plurality of areas where the first metal layer and the insulating layer overlap, and each of the plurality of first sub-overlapping areas includes at least one hollowed-out area.
5. The display panel of claim 4, wherein the first metal layer further comprises:
the first connecting areas are included between two adjacent first sub-overlapping areas in the plurality of first sub-overlapping areas, and the first connecting areas connect the two corresponding first sub-overlapping areas.
6. The display panel of claim 5, wherein the first connection region is a continuous region.
7. The display panel of claim 5, wherein the first connection region has a width greater than a width of the corresponding two first sub-overlap regions.
8. The display panel of claim 1, wherein the display panel further comprises:
the second metal layer is arranged on one side, far away from the first metal layer, of the insulating layer and comprises a second overlapping area, the second overlapping area is an area where the second metal layer and the insulating layer are overlapped, and the second overlapping area comprises at least one hollow area.
9. A display device characterized in that it comprises a display panel according to any one of claims 1 to 8.
10. A display panel, comprising a first metal layer and an insulating layer disposed on the first metal layer;
the insulating layer comprises a plurality of insulating parts which are arranged at intervals;
the first metal layer comprises a plurality of first overlapping areas and a plurality of first connecting areas, the plurality of first sub overlapping areas are a plurality of areas where the first metal layer and the insulating layer are overlapped, a first connecting area is arranged between two adjacent first sub overlapping areas in the plurality of first sub overlapping areas, and the first connecting areas are connected with the corresponding two first sub overlapping areas;
wherein a width of each of the plurality of first sub-overlapping regions is smaller than a width of each of the plurality of first connection regions and a width of the corresponding insulation portion.
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| CN202110017059.1A CN112838099B (en) | 2021-01-07 | 2021-01-07 | Display panel and display device |
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| CN202110017059.1A CN112838099B (en) | 2021-01-07 | 2021-01-07 | Display panel and display device |
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| US4132614A (en) * | 1977-10-26 | 1979-01-02 | International Business Machines Corporation | Etching by sputtering from an intermetallic target to form negative metallic ions which produce etching of a juxtaposed substrate |
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| WO2020093487A1 (en) * | 2018-11-09 | 2020-05-14 | 惠科股份有限公司 | Display panel, manufacturing method, and display device |
| WO2020133446A1 (en) * | 2018-12-29 | 2020-07-02 | 深圳市柔宇科技有限公司 | Array substrate, display panel, and display device |
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| US4132614A (en) * | 1977-10-26 | 1979-01-02 | International Business Machines Corporation | Etching by sputtering from an intermetallic target to form negative metallic ions which produce etching of a juxtaposed substrate |
| CN106252418A (en) * | 2016-09-22 | 2016-12-21 | 南京华东电子信息科技股份有限公司 | A kind of thin film transistor (TFT) |
| CN109003940A (en) * | 2018-07-18 | 2018-12-14 | 深圳市华星光电技术有限公司 | Tft array substrate and preparation method thereof |
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