CN116828898A - Display panel and preparation method thereof - Google Patents
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Abstract
The application relates to a display panel and a preparation method thereof, wherein the display panel comprises an array substrate, a pixel limiting layer and a light-emitting functional layer which are sequentially formed on the array substrate, and a plurality of auxiliary electrodes positioned on one side of the pixel limiting layer, which is far away from the array substrate, wherein second electrode layers corresponding to two adjacent sub-pixels are disconnected at the edges of the auxiliary electrodes, the auxiliary electrodes comprise conductive parts and covering parts positioned on one side of the conductive parts, which is far away from the array substrate, the extending direction of metal wires formed by the conductive parts is perpendicular to a first direction, the first direction is the vapor deposition direction of the display panel, and the orthographic projection of the covering parts on the array substrate covers the orthographic projection of the conductive parts on the array substrate; the pixel defining layer is further formed with a groove accommodating the conductive portion, the groove extending at least in the first direction such that the pitch of two adjacent sub-pixels decreases at least in the first direction. The display panel can reduce the cathode signal transmission resistance, eliminate the device crosstalk between the luminous sub-pixels and improve the pixel aperture opening ratio.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a preparation method thereof.
Background
As the size of organic electroluminescent diodes (Organic LightEmitting Diode, abbreviated as OLED) increases, the area of the cathode layer of the light emitting element increases. The cathode layer of the top-emitting OLED display panel needs to meet the light transmittance requirement and must not be too thick, so that a large area of the cathode layer necessarily causes a decrease in-plane voltage (IR-Drop), affecting the brightness uniformity of the display. For this reason, the related art generally provides an auxiliary electrode on the pixel defining layer so that it can overlap with the cathode layer, and the overall resistance of the cathode layer is reduced by using the auxiliary electrode. In addition, the light emitting device generally adopts a fine metal mask plate as shielding, and three-color sub-pixels are deposited through an evaporation process. However, for large-size OLED display panels, the sagging amount of the metal mask is too large, and the area bridged by the openings of the fine mask also limits the effective area of the pixel light-emitting area for vapor deposition, which is not beneficial to the improvement of the aperture ratio.
Disclosure of Invention
The application aims to provide a display panel and a preparation method thereof, wherein the display panel can reduce the cathode signal transmission resistance, eliminate the device crosstalk between luminous sub-pixels and improve the pixel aperture opening ratio.
In a first aspect, an embodiment of the present application provides a display panel, including an array substrate, and a pixel defining layer and a light emitting functional layer sequentially formed on the array substrate, where a plurality of first electrodes arranged in an array are formed on the array substrate, the pixel defining layer includes a plurality of pixel openings, and at least a portion of the first electrodes are exposed by the pixel openings; the light-emitting functional layer comprises a plurality of pixel units, wherein each pixel unit comprises a plurality of sub-pixels, and each sub-pixel comprises a light-emitting structure positioned on the first electrode and a second electrode layer positioned on the light-emitting structure; the display panel further comprises a plurality of auxiliary electrodes positioned on one side of the pixel limiting layer, which is far away from the array substrate, wherein the second electrode layers corresponding to the two adjacent sub-pixels are disconnected at the edges of the auxiliary electrodes, the auxiliary electrodes comprise conductive parts and covering parts positioned on one side of the conductive parts, which is far away from the array substrate, the extending direction of metal wires formed by the conductive parts is perpendicular to the first direction, the first direction is the evaporation plating direction of the display panel, and the orthographic projection of the covering parts on the array substrate covers the orthographic projection of the conductive parts on the array substrate; the pixel defining layer is further formed with a groove accommodating the conductive portion, the groove extending at least in the first direction so that a pitch between two adjacent sub-pixels is reduced at least in the first direction.
In one possible embodiment, the depth of the recess is h, the thickness of the pixel defining layer is t, and the following condition is satisfied: h= (1/3 to 1/2) t.
In one possible embodiment, the recess extends through the pixel defining layer.
In one possible embodiment, the grooves further extend in a second direction such that the pitch between two adjacent sub-pixels decreases in the second direction, the second direction intersecting the first direction.
In one possible embodiment, the display panel further includes a planarization layer, the planarization layer is located between the array substrate and the plurality of first electrodes, the planarization layer is provided with a plurality of vias, and orthographic projections of the vias on the array substrate are located between orthographic projections of two adjacent first electrodes on the array substrate.
In a second aspect, an embodiment of the present application further provides a method for manufacturing a display panel, including: providing an array substrate, wherein a plurality of first electrodes arranged in an array are formed on the array substrate; forming a patterned pixel defining layer on the array substrate, the pixel defining layer including a plurality of pixel openings exposing at least a portion of the first electrode; forming a plurality of auxiliary electrodes on the pixel limiting layer, wherein the auxiliary electrodes comprise conductive parts and covering parts positioned on one side of the conductive parts away from the array substrate, the extending direction of metal wires formed by the conductive parts is perpendicular to a first direction, the first direction is the evaporation direction of the display panel, and the orthographic projection of the covering parts on the array substrate covers the orthographic projection of the conductive parts on the array substrate; evaporating a light-emitting functional layer on the pixel limiting layer and the auxiliary electrodes, wherein the light-emitting functional layer comprises a plurality of pixel units, each pixel unit comprises a plurality of sub-pixels, each sub-pixel comprises a light-emitting structure positioned on the first electrode and a second electrode layer positioned on the light-emitting structure, and the second electrode layers corresponding to two adjacent sub-pixels are disconnected at the edge of the auxiliary electrode; wherein a groove accommodating the conductive portion is further formed in the pixel defining layer, the groove extending at least in the first direction so that a pitch between two adjacent sub-pixels is reduced at least in the first direction.
In one possible embodiment, the grooves are blind grooves; alternatively, the recess extends through the pixel defining layer.
In one possible embodiment, the grooves further extend in a second direction such that the pitch between two adjacent sub-pixels decreases in the second direction, the second direction intersecting the first direction.
In one possible embodiment, before the plurality of first electrodes arranged in an array are formed on the array substrate, the method further includes: and forming a patterned planarization layer on the array substrate, wherein the planarization layer is provided with a plurality of through holes, and orthographic projections of the through holes on the array substrate are positioned between orthographic projections of two adjacent first electrodes on the array substrate.
In one possible embodiment, forming the plurality of auxiliary electrodes on the pixel defining layer includes: forming a conductive layer on the pixel defining layer; forming an eave layer on the conductive part; the eave layer and the conductive layer are synchronously etched to form a covering part and a conductive part of the plurality of auxiliary electrodes respectively.
According to the display panel and the preparation method thereof provided by the embodiment of the application, the display panel comprises an array substrate, a pixel limiting layer, a light-emitting functional layer and a plurality of auxiliary electrodes, wherein the pixel limiting layer, the light-emitting functional layer and the auxiliary electrodes are sequentially formed on the array substrate; the light-emitting functional layer comprises a plurality of pixel units, and the pixel units comprise a plurality of sub-pixels; the sub-pixel comprises a light emitting structure positioned on the first electrode and a second electrode layer positioned on the light emitting structure; the second electrode layers corresponding to the two adjacent sub-pixels are disconnected at the edge of the auxiliary electrode; the auxiliary electrode comprises a conductive part and a covering part positioned at one side of the conductive part, which is far away from the array substrate, wherein the extending direction of a metal wire formed by the conductive part is vertical to a first direction, the first direction is the evaporation direction of the display panel, and the orthographic projection of the covering part on the array substrate covers the orthographic projection of the conductive part on the array substrate; by further forming a groove accommodating the conductive portion in the pixel defining layer, the groove extends at least in the first direction so that the pitch between adjacent two sub-pixels is reduced at least in the first direction. Therefore, the film layer where the conductive part is located can be reduced, the height between the covering part and the pixel limiting layer above the first electrode is reduced, the distance between two adjacent sub-pixels is reduced, the cathode signal transmission resistance is reduced, the device crosstalk between the light-emitting sub-pixels is eliminated, and the pixel aperture opening ratio can be improved.
Drawings
Features, advantages, and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, like parts are designated with like reference numerals. The drawings are not drawn to scale, but are merely for illustrating relative positional relationships, and the layer thicknesses of certain portions are exaggerated in order to facilitate understanding, and the layer thicknesses in the drawings do not represent the actual layer thickness relationships.
Fig. 1 is a schematic cross-sectional structure of a related art display panel;
FIG. 2 shows a schematic top view of the display panel of FIG. 1;
fig. 3 shows a schematic distribution diagram of vapor deposition material gas emitted from a vapor deposition source along a first direction;
fig. 4 is a schematic view showing the distribution of the vapor deposition material gas in the second direction in fig. 3;
fig. 5 is a schematic structural diagram of a display panel according to a first embodiment of the present application;
FIG. 6 shows a schematic top view of the display panel shown in FIG. 5;
fig. 7 is a schematic structural diagram of a display panel according to a second embodiment of the present application;
fig. 8 is a schematic structural diagram of a display panel according to a third embodiment of the present application;
fig. 9 is a flowchart illustrating a method for manufacturing a display panel according to a fourth embodiment of the present application.
Reference numerals illustrate:
1. an array substrate; 1a, a substrate; 1b, driving the array layer; 11. a first electrode; 2. a pixel defining layer; 21. a pixel opening; 3. a light-emitting functional layer; px, sub-pixels; 31. a light emitting structure; 32. a second electrode layer; 4. an auxiliary electrode; 41. a conductive portion; 42. a cover part; 5. a planarization layer; 6. a touch layer; H. a via hole; 7. an encapsulation layer; θ, evaporation angle.
Detailed Description
Features and exemplary embodiments of various aspects of the application are described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the application by showing examples of the application. In the drawings and the following description, at least some well-known structures and techniques have not been shown in detail in order not to unnecessarily obscure the present application; also, the size of the region structures may be exaggerated for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
The directional terms appearing in the following description are those directions shown in the drawings and do not limit the specific structure of the application. In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be directly connected or indirectly connected. The specific meaning of the above terms in the present application can be understood as appropriate by those of ordinary skill in the art.
Currently, there are three general mass production methods for light emitting devices in OLED display panels: firstly, adopting a fine metal mask plate as a mask, and carrying out deposition of three-color sub-pixels through an evaporation process; secondly, adopting an ink-jet printing process to accurately print sub-pixels at different positions; and thirdly, carrying out whole-surface film formation by adopting an evaporation process, and then etching the film-formed substrate by adopting a photoetching process to separate out three-color sub-pixels. With the increasing popularity of large-size display panels, the sagging amount of the metal mask plate is too large when the first mode is adopted, so that the mode of combining the third evaporation and etching has become an industry inner layer trend. The method comprises the steps of firstly carrying out whole-surface film formation by an evaporation process, enabling the tail end of a cathode of a sub-pixel to form lap joint with an auxiliary electrode by virtue of a special structure of an evaporation source, and then etching a film-formed substrate by a photoetching process to separate three-color sub-pixels.
Fig. 1 is a schematic cross-sectional structure of a related art display panel; fig. 2 shows a schematic top view of the display panel of fig. 1.
As shown in fig. 1, the display panel in the related art includes an array substrate 1, and a pixel defining layer 2 and a light emitting function layer 3 sequentially formed on the array substrate 1, wherein a plurality of first electrodes 11 arranged in an array are formed on the array substrate 1, the pixel defining layer 2 includes a plurality of pixel openings 21, and the pixel openings 21 expose at least a portion of the first electrodes 11; the light emitting functional layer 3 includes a plurality of pixel units including a plurality of sub-pixels Px including a light emitting structure 31 on the first electrode 11 and a second electrode layer 32 on the light emitting structure 31; the display panel further comprises a plurality of auxiliary electrodes 4 positioned on one side of the pixel limiting layer 2 away from the array substrate 1, the second electrode layers 32 corresponding to two adjacent sub-pixels Px are disconnected at the edges of the auxiliary electrodes 4, the auxiliary electrodes 4 comprise conductive portions 41 and covering portions 42 positioned on one side of the conductive portions 41 away from the array substrate 1, the extending direction of metal wires formed by the conductive portions 41 is perpendicular to the first direction X, the first direction X is the evaporation direction of the display panel, and the orthographic projection of the covering portions 42 on the array substrate 1 covers the orthographic projection of the conductive portions 41 on the array substrate 1.
As shown in fig. 2, the pixel unit of the display panel includes 3 sub-pixels, namely, a red sub-pixel, a blue sub-pixel and a green sub-pixel. The light emitting functional layer 3 of the display panel is covered over the first electrode 11, the second electrode layer 32 is covered over the light emitting functional layer 3, and the second electrode layers 32 of two adjacent sub-pixels Px are disconnected at the edges of the auxiliary electrode 4 and electrically connected with the conductive portion 41 in lap joint. The sub-pixels of the light-emitting functional layer 3 are formed into a film entirely by an evaporation process.
Fig. 3 shows a schematic distribution diagram of vapor deposition material gas emitted from a vapor deposition source along a first direction; fig. 4 is a schematic view showing the distribution of the vapor deposition material gas in the second direction in fig. 3.
As shown in fig. 3 and 4, the first direction X is the vapor deposition direction (also referred to as the Nozzle direction) of the display panel, and the second direction Y is the moving direction (also referred to as the Scan direction). When the luminescent material is actually evaporated, the evaporation source forms one piece of evaporation cloud in the first direction X, and the angle is limited by the unlimited plate, so that the evaporation angle of the material is larger; and in the second direction Y, the evaporation angle of the material can be controlled by the restrictor plate.
As shown in fig. 1, the vertical distance between the edge of the pixel defining layer 2 and the edge of the cover portion 42 of the adjacent auxiliary electrode 4 is a, the vertical distance between the edge of the cover portion 42 and the middle portion of the conductive portion 41 is b, the vapor deposition angle is different, and the value of a influenced in the first direction X or the second direction Y is also different. Due to the uneven film thickness of the a-value region, which cannot be used for device light emission, the opening 21 of the pixel defining layer 2 must avoid this region to eliminate device crosstalk between light emitting sub-pixels. The pitch between adjacent sub-pixels must be > 2 (a+b), and the pitch between adjacent sub-pixels in the first direction X is greater than the pitch between adjacent sub-pixels in the second direction Y.
Meanwhile, the wiring resistance of the second electrode layer 32 in the display area is large, resulting in voltage difference between the near end and the far end of the signal, which generates in-plane display non-uniformity, and the reduction of the wiring resistance of the second electrode layer 32 needs to be solved from the design end.
In view of this, embodiments of the present application provide a display panel that can reduce the cathode signal transmission resistance, eliminate the device crosstalk between the light emitting sub-pixels, and improve the pixel aperture ratio.
First embodiment
Fig. 5 is a schematic structural diagram of a display panel according to a first embodiment of the present application; fig. 6 shows a schematic top view of the display panel shown in fig. 5.
As shown in fig. 5 and 6, a display panel provided in a first embodiment of the present application includes an array substrate 1, and a pixel defining layer 2 and a light emitting functional layer 3 sequentially formed on the array substrate 1, wherein a plurality of first electrodes 11 arranged in an array are formed on the array substrate 1, the pixel defining layer 2 includes a plurality of pixel openings 21, and at least a portion of the first electrodes 11 are exposed by the pixel openings 21; the light emitting functional layer 3 includes a plurality of pixel units including a plurality of sub-pixels Px including a light emitting structure 31 on the first electrode 11 and a second electrode layer 32 on the light emitting structure 31.
The display panel further comprises a plurality of auxiliary electrodes 4 positioned on one side of the pixel limiting layer 2 away from the array substrate 1, the second electrode layers 32 corresponding to two adjacent sub-pixels Px are disconnected at the edges of the auxiliary electrodes 4, the auxiliary electrodes 4 comprise conductive portions 41 and covering portions 42 positioned on one side of the conductive portions 41 away from the array substrate 1, the extending direction of metal wires formed by the conductive portions 41 is perpendicular to the first direction X, the first direction X is the evaporation direction of the display panel, and the orthographic projection of the covering portions 42 on the array substrate 1 covers the orthographic projection of the conductive portions 41 on the array substrate 1.
Wherein the pixel defining layer 2 is further formed with a recess 22 accommodating the conductive portion 41, the recess 22 extending at least along the first direction X such that the pitch between two adjacent sub-pixels Px decreases at least along the first direction X.
In this embodiment, the display panel is a top emission structure, the first electrode 11 is an anode, the second electrode layer 32 is a cathode laid on the whole surface, wherein the second electrode layers 32 corresponding to two adjacent sub-pixels are disconnected at the edge of the auxiliary electrode 4, so that the edge of the auxiliary electrode 4 can be overlapped with the conductive portion 41 of the auxiliary electrode 4, and the overall resistance of the second electrode layer 32 can be reduced by using the auxiliary electrode 4.
Optionally, an auxiliary electrode 4 is provided on at least one sub-pixel in at least one pixel cell. The larger the number of the auxiliary electrodes 4, the smaller the voltage drop of the overall resistance of the second electrode layer 32, which is advantageous for improving the luminance uniformity of the display panel.
Optionally, the shape of the sub-pixels is any one or a combination of at least two of circular, elliptical and polygonal. The polygon may be a polygon such as, but not limited to, triangle, trapezoid, rectangle, quadrilateral, pentagon, hexagon, and the like. In the pixel unit, the shapes of the sub-pixels can be the same or different, and the shape is determined according to specific pixel arrangement structures.
As shown in fig. 5, since the pixel defining layer 2 is further formed with the groove 22 for accommodating the conductive portion 41, and the groove 22 extends along the first direction X, the conductive portion 41 of the auxiliary electrode 4 is entirely submerged along the first direction X, so that the height between the cover portion 42 of the auxiliary electrode 4 and the pixel defining layer 2 above the first electrode 11 is reduced, so that the vertical distance a between the edge of the pixel defining layer 2 and the edge of the cover portion 42 of the adjacent auxiliary electrode 4 can be reduced, the distance between the adjacent sub-pixels along the first direction X is reduced, the occupied space of the sub-pixels is increased, and the pixel aperture ratio is improved.
The display panel provided in the first embodiment of the present application is formed with the grooves 22 accommodating the conductive portions 41 in the pixel defining layer 2, and the grooves 22 extend at least in the first direction X, so that the pitch between two adjacent sub-pixels is reduced at least in the first direction X. Thereby, the film layer where the conductive portion 41 is located can be reduced, and the height between the cover portion 42 and the pixel defining layer 2 above the first electrode 11 can be reduced, so that the pitch between adjacent sub-pixels can be reduced, and the pixel aperture ratio can be improved while reducing the cathode signal transmission resistance and eliminating the device crosstalk between the light emitting sub-pixels.
In some embodiments, the depth of the recess 22 is h, the thickness of the pixel defining layer 2 is t, and the following condition is satisfied: h= (1/3 to 1/2) t.
As shown in fig. 5, the pixel defining layer 2 is formed with a groove 22, the groove 22 being a blind groove having a preset depth, so that the overall height of the auxiliary electrode 4 is reduced by a distance corresponding to the preset depth.
In some embodiments, the grooves 22 also extend in the second direction Y such that the spacing between two adjacent sub-pixels Px decreases in the second direction Y, which intersects the first direction X.
Since the vapor deposition angle of the sub-pixel in the second direction Y is limited by the limiting plate, the smaller the vapor deposition angle is, the lower the utilization ratio of the vapor deposition material is. When the grooves 22 are also extended in the second direction Y, the pixel aperture ratio can be maintained unchanged while the evaporation angle is increased to improve the utilization rate of the evaporation material on the premise of ensuring that the performance of the light emitting device satisfies the requirements.
In some embodiments, the display panel further includes a planarization layer 5, where the planarization layer 5 is located between the array substrate 1 and the plurality of first electrodes 11. The array substrate 1 comprises a substrate and a driving array layer positioned on the substrate, the driving array layer comprises a pixel circuit, and the planarization layer 5 covers the surface of the array substrate 1, so that the surface of the array substrate 1 is in a planarization state, and a plurality of first electrodes 11 are conveniently prepared on the planarization layer 5 in the follow-up process. The substrate may be made of glass or polyimide.
Optionally, the light emitting functional layer 3 further includes a first common layer and a second common layer. The first common layer includes a hole injection layer (Hole Injection Layer, HIL) on the first electrode 11 and a hole transport layer (Hole Transport Layer, HTL) on a side surface of the hole injection layer facing away from the array substrate 1. The second common layer comprises an electron transport layer (Electron Transport Layer, ETL) on the surface of the light emitting structure 31 and an electron injection layer (Electron Injection Layer, EIL) on the side surface of the electron transport layer facing away from the light emitting structure 31.
Further, the display panel further includes an encapsulation layer (not shown in the drawing) covering the light emitting function layer 3 and the plurality of auxiliary electrodes 4. The encapsulation layer includes a first inorganic layer, an organic layer, and a second inorganic layer sequentially disposed in a direction away from the array substrate 1. Wherein the first inorganic layer and the second inorganic layer are transparent inorganic film layers, and the material of the first inorganic layer and the second inorganic layer can comprise one of the following materialsOr a plurality of: al (Al) 2 O 3 、TiO 2 、ZrO 2 、MgO、HFO 2 、Ta 2 O 5 、Si 3 N 4 、AlN、SiN、SiNO、SiO、SiO 2 SiC, siCNx, ITO, IZO. The inorganic materials have good light transmission performance and good water and oxygen barrier performance. The material of the organic layer is transparent organic conductive resin, and specifically comprises transparent matrix resin, conductive molecules and/or conductive ions. Specifically, the transparent conductive resin is formed by stirring and completely dissolving polyaniline, a crosslinking monomer, toluene and the like doped with organic acid; alternatively, a conductive molecule such as polyaniline is added to the transparent conductive resin; alternatively, conductive ions such as nano-sized antimony-doped SiO are added to the transparent conductive resin 2 Nanoscale conductive ions such as nanoscale indium tin oxide or nanoscale silver can also be used.
The first inorganic layer and the second inorganic layer made of inorganic materials completely cover the light emitting functional layer 3 and the plurality of auxiliary electrodes 4, so that the invasion of moisture from the side can be prevented from affecting the electrical performance of the light emitting functional layer 3. The patterned organic layer has higher elasticity, is clamped between the first inorganic layer and the second inorganic layer, can inhibit the cracking of the inorganic film, release the stress between inorganic matters, and can improve the flexibility of the whole packaging layer, thereby realizing reliable flexible packaging.
Second embodiment
Fig. 7 is a schematic structural diagram of a display panel according to a second embodiment of the present application.
As shown in fig. 7, the display panel according to the second embodiment of the present application is similar to the display panel according to the first embodiment in that the pixel defining layer 2 is different in structure.
Specifically, the recess 22 of the pixel defining layer 2 penetrates the pixel defining layer 2, that is, the recess 22 is a through groove for accommodating the conductive portion 41 of the auxiliary electrode 4, and the recess 22 extends along the first direction X, so that the conductive portion 41 of the auxiliary electrode 4 is entirely sunk along the first direction X, and the height between the cover portion 42 of the auxiliary electrode 4 and the pixel defining layer 2 above the first electrode 11 is reduced. The height between the cover portion 42 of the auxiliary electrode 4 and the pixel defining layer 2 above the first electrode 11 is lower than that of the first embodiment, so that the vertical distance a between the edge of the pixel defining layer 2 and the edge of the cover portion 42 of the adjacent auxiliary electrode 4 can be made smaller, further the pitch between adjacent sub-pixels in the first direction X can be further reduced, the occupied space of the sub-pixels can be increased, and the pixel aperture ratio can be improved.
Further, the grooves 22 also extend in the second direction Y such that the pitch between two adjacent sub-pixels Px decreases in the second direction Y, which intersects the first direction X.
Since the vapor deposition angle of the sub-pixel in the second direction Y is limited by the limiting plate, the smaller the vapor deposition angle is, the lower the utilization ratio of the vapor deposition material is. When the grooves 22 are also extended in the second direction Y, the pixel aperture ratio can be maintained unchanged while the evaporation angle is increased to improve the utilization rate of the evaporation material on the premise of ensuring that the performance of the light emitting device satisfies the requirements.
Third embodiment
Fig. 8 is a schematic structural diagram of a display panel according to a third embodiment of the present application.
As shown in fig. 8, the display panel according to the third embodiment of the present application is similar to the display panel according to the first or second embodiment, except that the planarization layer 5 is different in structure.
Specifically, the planarization layer 5 is provided with a plurality of vias 51, and orthographic projections of the vias 51 on the array substrate 1 are located between orthographic projections of two adjacent first electrodes 11 on the array substrate 1. Since the pixel defining layer 2 is located on the side of the planarization layer 5 facing away from the array substrate 1, the pixel defining layer 2 may be filled in the via hole 51, resulting in the formation of the recess 22 on the side of the pixel defining layer 2 facing away from the array substrate 1, and further, the conductive portion 41 of the auxiliary electrode 4 is accommodated in the recess 22, so that the height between the covering portion 42 of the auxiliary electrode 4 and the pixel defining layer 2 above the first electrode 11 is reduced. The grooves 22 may be blind grooves or through grooves, and will not be described again.
Fourth embodiment
Fig. 9 is a flowchart illustrating a method for manufacturing a display panel according to a fourth embodiment of the present application.
As shown in fig. 9, a method for manufacturing a display panel according to a fourth embodiment of the present application includes steps S1 to S4.
Step S1: providing an array substrate 1, wherein a plurality of first electrodes 11 are formed on the array substrate 1 in an array arrangement;
step S2: forming a patterned pixel defining layer 2 on the array substrate 1, the pixel defining layer 2 including a plurality of pixel openings 21, the pixel openings 21 exposing at least a portion of the first electrode 11;
step S3: forming a plurality of auxiliary electrodes 4 on the pixel defining layer 2, wherein the auxiliary electrodes 4 comprise conductive parts 41 and covering parts 42 positioned on one side of the conductive parts 41 away from the array substrate 1, the extending direction of metal wires formed by the conductive parts 41 is perpendicular to a first direction X, the first direction X is the evaporation direction of the display panel, and the orthographic projection of the covering parts 42 on the array substrate 1 covers the orthographic projection of the conductive parts 41 on the array substrate 1;
step S4: evaporating a light-emitting functional layer 3 on the pixel defining layer 2 and the auxiliary electrodes 4, wherein the light-emitting functional layer 3 comprises a plurality of pixel units, each pixel unit comprises a plurality of sub-pixels Px, each sub-pixel Px comprises a light-emitting structure 31 positioned on the first electrode 11 and a second electrode layer 32 positioned on the light-emitting structure 31, and the second electrode layers 32 corresponding to the two adjacent sub-pixels Px are disconnected at the edge of the auxiliary electrode 4;
in which a groove 22 accommodating the conductive portion 41 is further formed in the pixel defining layer 2, the groove 22 extending at least in the first direction X so that the pitch between two adjacent sub-pixels Px decreases at least in the first direction X. Since the grooves 22 extend at least along the first direction X, the film layer where the conductive portions 41 are located can be reduced, and the height between the cover portions 42 and the pixel defining layer 2 above the first electrode 11 can be reduced, so that the space between adjacent sub-pixels along at least the first direction X is reduced, and the pixel aperture ratio can be improved while reducing the cathode signal transmission resistance and eliminating the device crosstalk between the light emitting sub-pixels.
Optionally, the recess 22 is a blind recess; or, alternatively, the recess 22 extends through the pixel defining layer 2.
Further, the grooves 22 also extend in the second direction Y so that the pitch between adjacent two sub-pixels decreases in the second direction Y, which intersects the first direction X.
Since the vapor deposition angle of the sub-pixel in the second direction Y is limited by the limiting plate, the smaller the vapor deposition angle is, the lower the utilization ratio of the vapor deposition material is. When the grooves 22 are also extended in the second direction Y, the pixel aperture ratio can be maintained unchanged while the evaporation angle is increased to improve the utilization rate of the evaporation material on the premise of ensuring that the performance of the light emitting device satisfies the requirements.
Further, before forming the plurality of first electrodes 11 arranged in an array on the array substrate 1, it further includes:
step S0: a patterned planarization layer 5 is formed on the array substrate 1, and the planarization layer 5 is provided with a plurality of vias 51, and orthographic projections of the vias 51 on the array substrate 1 are located between orthographic projections of two adjacent first electrodes 11 on the array substrate 1.
Step S4, i.e. forming the plurality of auxiliary electrodes 4 on the pixel defining layer 2, comprises:
step S41: forming a conductive layer on the pixel defining layer 2;
step S42: forming an eave layer on the conductive portion 41;
step S43: the eave layer and the conductive layer are simultaneously etched to form the covering portions 42 and the conductive portions 41 of the plurality of auxiliary electrodes 4, respectively.
In this embodiment, the first electrode 11 is etched on one side of the array substrate 1, the pixel defining layer 2 is deposited, the plurality of auxiliary electrodes 4 are formed on the pixel defining layer 2, the light emitting functional layer 3 is evaporated, and the evaporation source is above the array substrate 1 and the fine metal mask plate during evaporation, the light emitting structure 31 is evaporated, and the second electrode layer 32 is evaporated. The second electrode layers 32 corresponding to the adjacent two sub-pixels are disconnected at the covering portions 42 of the auxiliary electrode 4, so that the second electrode layers 32 are overlapped and connected with the conductive portions 41 according to the adjusted vapor deposition angle θ. The specific etching process can refer to the prior art, and will not be described in detail.
According to the method for manufacturing the display panel provided by the embodiment of the application, the grooves 22 for accommodating the conductive parts 41 are formed in the pixel defining layer 2, and the grooves 22 extend at least along the first direction X, so that the interval between two adjacent sub-pixels is reduced at least along the first direction X. Thereby, the film layer where the conductive portion 41 is located can be reduced, and the height between the cover portion 42 and the pixel defining layer 2 above the first electrode 11 can be reduced, so that the pitch between adjacent sub-pixels can be reduced, and the pixel aperture ratio can be improved while reducing the cathode signal transmission resistance and eliminating the device crosstalk between the light emitting sub-pixels.
It should be readily understood that the terms "on … …", "above … …" and "above … …" in this disclosure should be interpreted in the broadest sense so that "on … …" means not only "directly on something" but also includes "on something" with intermediate features or layers therebetween, and "above … …" or "above … …" includes not only the meaning "on something" or "above" but also the meaning "above something" or "above" without intermediate features or layers therebetween (i.e., directly on something).
The term "substrate" as used herein refers to a material upon which subsequent layers of material are added. The substrate itself may be patterned. The material added atop the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide range of materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material (e.g., glass, plastic, or sapphire wafer, etc.).
The term "layer" as used herein may refer to a portion of material that includes regions having a certain thickness. The layer may extend over the entire underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of a continuous structure, either homogenous or non-homogenous, having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of lateral planes at the top and bottom surfaces. The layers may extend laterally, vertically and/or along a tapered surface. The array substrate may be a layer, may include one or more layers therein, and/or may have one or more layers located thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (within which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.
Claims (10)
1. The display panel comprises an array substrate, and a pixel limiting layer and a light-emitting functional layer which are sequentially formed on the array substrate, wherein a plurality of first electrodes are formed on the array substrate in an array arrangement mode, the pixel limiting layer comprises a plurality of pixel openings, and at least part of the first electrodes are exposed by the pixel openings; the light-emitting functional layer comprises a plurality of pixel units, wherein each pixel unit comprises a plurality of sub-pixels, and each sub-pixel comprises a light-emitting structure positioned on the first electrode and a second electrode layer positioned on the light-emitting structure; it is characterized in that the method comprises the steps of,
the display panel further comprises a plurality of auxiliary electrodes positioned on one side of the pixel limiting layer, which is away from the array substrate, wherein the second electrode layers corresponding to two adjacent sub-pixels are disconnected at the edges of the auxiliary electrodes, the auxiliary electrodes comprise conductive parts and covering parts positioned on one side of the conductive parts, which is away from the array substrate, the extending direction of metal wires formed by the conductive parts is perpendicular to a first direction, the first direction is the evaporation direction of the display panel, and the orthographic projection of the covering parts on the array substrate covers the orthographic projection of the conductive parts on the array substrate;
wherein the pixel defining layer is further formed with a groove accommodating the conductive portion, the groove extending at least in a first direction such that a pitch between two adjacent sub-pixels decreases at least in the first direction.
2. The display panel according to claim 1, wherein the depth of the groove is h, the thickness of the pixel defining layer is t, and the following condition is satisfied: h= (1/3 to 1/2) t.
3. The display panel of claim 1, wherein the recess extends through the pixel defining layer.
4. A display panel according to any one of claims 1 to 3, wherein the grooves further extend in a second direction such that the spacing between two adjacent sub-pixels decreases in the second direction, the second direction intersecting the first direction.
5. The display panel of claim 4, further comprising a planarization layer between the array substrate and the plurality of first electrodes, the planarization layer being provided with a plurality of vias, the orthographic projections of the vias on the array substrate being located between the orthographic projections of adjacent two of the first electrodes on the array substrate.
6. A method for manufacturing a display panel, comprising:
providing an array substrate, wherein a plurality of first electrodes arranged in an array are formed on the array substrate;
forming a patterned pixel defining layer on the array substrate, the pixel defining layer including a plurality of pixel openings exposing at least a portion of the first electrode;
forming a plurality of auxiliary electrodes on the pixel limiting layer, wherein the auxiliary electrodes comprise conductive parts and covering parts positioned on one side of the conductive parts, which is away from the array substrate, and the extending direction of metal wires formed by the conductive parts is perpendicular to a first direction, wherein the first direction is the evaporation direction of the display panel, and the orthographic projection of the covering parts on the array substrate covers the orthographic projection of the conductive parts on the array substrate;
evaporating a light-emitting functional layer on the pixel limiting layer and the auxiliary electrodes, wherein the light-emitting functional layer comprises a plurality of pixel units, each pixel unit comprises a plurality of sub-pixels, each sub-pixel comprises a light-emitting structure on the first electrode and a second electrode layer on the light-emitting structure, and the second electrode layers corresponding to two adjacent sub-pixels are disconnected at the edge of the auxiliary electrode;
wherein a groove accommodating the conductive portion is further formed in the pixel defining layer, the groove extending at least in a first direction such that a pitch between two adjacent sub-pixels is reduced at least in the first direction.
7. The method of claim 6, wherein the grooves are blind grooves; alternatively, the recess extends through the pixel defining layer.
8. The method of manufacturing according to claim 6 or 7, wherein the grooves further extend in a second direction such that a pitch between two adjacent sub-pixels decreases in the second direction, the second direction intersecting the first direction.
9. The method of manufacturing according to claim 8, further comprising, before forming the plurality of first electrodes arranged in an array on the array substrate:
and forming a patterned planarization layer on the array substrate, wherein the planarization layer is provided with a plurality of through holes, and orthographic projections of the through holes on the array substrate are positioned between orthographic projections of two adjacent first electrodes on the array substrate.
10. The method of manufacturing according to claim 6, wherein the forming a plurality of auxiliary electrodes on the pixel defining layer includes:
forming a conductive layer on the pixel defining layer;
forming an eave layer on the conductive part;
and etching the eave layer and the conductive layer simultaneously to form the covering parts and the conductive parts of the auxiliary electrodes respectively.
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