WO2020132805A1 - 双功能电路、显示面板及其测试方法、静电防护方法 - Google Patents

双功能电路、显示面板及其测试方法、静电防护方法 Download PDF

Info

Publication number
WO2020132805A1
WO2020132805A1 PCT/CN2018/123101 CN2018123101W WO2020132805A1 WO 2020132805 A1 WO2020132805 A1 WO 2020132805A1 CN 2018123101 W CN2018123101 W CN 2018123101W WO 2020132805 A1 WO2020132805 A1 WO 2020132805A1
Authority
WO
WIPO (PCT)
Prior art keywords
film transistor
thin film
sub
signal
display panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/123101
Other languages
English (en)
French (fr)
Inventor
张盛鹉
张祖强
倪杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Royole Technologies Co Ltd
Original Assignee
Shenzhen Royole Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Royole Technologies Co Ltd filed Critical Shenzhen Royole Technologies Co Ltd
Priority to PCT/CN2018/123101 priority Critical patent/WO2020132805A1/zh
Priority to CN201880095912.8A priority patent/CN112639601A/zh
Publication of WO2020132805A1 publication Critical patent/WO2020132805A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the invention belongs to the field of display technology, and in particular relates to a dual-function circuit, a display panel, a test method thereof, and an electrostatic protection method.
  • the production line of the display panel includes a dot screen test process, which is mainly to detect the bad phenomena that occur in the preparation process of the display screen, including various spots, blocks and stains.
  • a dot screen test process which is mainly to detect the bad phenomena that occur in the preparation process of the display screen, including various spots, blocks and stains.
  • electrostatic discharge will cause damage to the electronic components in the display panel, resulting in the problem of function failure.
  • the present invention provides a dual-function circuit that can have both a test function and an electrostatic protection function, saving space for wiring.
  • the specific technical solution is as follows.
  • a dual-function circuit includes at least one sub-circuit unit, and each sub-circuit unit is connected to a corresponding sub-pixel unit through a corresponding data line of a display panel;
  • each sub-circuit unit transmits the test signal to the corresponding sub-pixel unit through the corresponding data line of the display panel to test the corresponding sub-pixel unit;
  • each sub-circuit unit receives the electrostatic signal of the corresponding sub-pixel unit through the corresponding data line of the display panel and discharges it.
  • each sub-circuit unit includes a first end, a second end, a third end and a fourth end, wherein the fourth end is used to connect with the corresponding data line of the display panel and connect with the corresponding sub-pixel unit;
  • the first end is connected to the first control signal
  • the second end is connected to the second control signal
  • the third end is connected to the test signal
  • the sub-circuit unit is in Under the control of the first control signal and the second control signal
  • the test signal is transmitted from the third end to the fourth end
  • the test signal is transmitted to the display panel through the fourth end
  • the data line is used for testing the corresponding sub-pixel unit of the display panel.
  • each sub-circuit unit includes a first end, a second end, a third end and a fourth end, wherein the fourth end is used to connect with the corresponding data line of the display panel and connect with the corresponding sub-pixel unit;
  • the first end is connected to the first level signal
  • the second end is connected to the second level signal
  • the third end is connected to the third level signal.
  • the sub-circuit unit discharges the electrostatic signal transmitted by the data line received by the fourth terminal under the control of the first level signal, the second level signal, and the third level signal.
  • the sub-circuit unit includes a first thin film transistor and a second thin film transistor;
  • the first thin film transistor is connected to the second thin film transistor, the first end and the fourth end, and the second thin film transistor is also connected to the second end, the third end and the fourth end;
  • the first end is connected to the first control signal
  • the second end is connected to the second control signal
  • the third end is connected to the test signal
  • the first control signal Controlling the first thin film transistor to be turned off
  • the second control signal controlling the second thin film transistor to be turned on
  • the test signal connected to the third terminal is transmitted to the first through the turned on second thin film transistor Four ends, and transmit the test signal to the data line of the display panel through the fourth end, for testing the corresponding sub-pixel unit of the display panel.
  • the sub-circuit unit includes a first thin film transistor and a second thin film transistor;
  • the first thin film transistor is connected to the second thin film transistor, the first end and the fourth end, and the second thin film transistor is also connected to the second end, the third end and the fourth end;
  • the first thin film transistor When the dual-function circuit is in the electrostatic protection function, the first thin film transistor is in an off or on state according to the electrostatic signal received by the fourth terminal and the first level signal received by the first terminal, and the second The thin film transistor is in an on or off state according to the electrostatic signal received by the fourth end, the second level signal received by the second end, and the third level signal received by the third end; the electrostatic signal passes The first thin film transistor or the second thin film transistor in the on state is released.
  • the first thin film transistor and the second thin film transistor respectively include a gate, a first pole and a second pole;
  • the gate of the first thin film transistor is connected to the fourth terminal, the first electrode of the first thin film transistor is connected to the first terminal, and the second electrode of the first thin film transistor is connected to the fourth terminal;
  • the gate of the second thin film transistor is connected to the second terminal, the first electrode of the second thin film transistor is connected to the third terminal, and the second electrode of the second thin film transistor is connected to the fourth terminal.
  • the first control signal is a high-level signal
  • the second control signal is a high-level signal
  • the first thin film transistor is an N-type transistor
  • the first The two thin film transistors are N-type transistors.
  • the first control signal is a low-level signal
  • the second control signal is a low-level signal
  • the first thin film transistor is a P-type transistor
  • the first The two thin film transistors are P-type transistors.
  • the first level signal is greater than the second level signal and the third level signal; when the voltage value of the electrostatic signal is greater than the voltage value of the first level signal When the first thin film transistor is turned on, the second thin film transistor is turned off, the electrostatic signal is released from the fourth end to the first end through the turned on first thin film transistor; when the When the voltage value of the electrostatic signal is less than the voltage values of the second level signal and the third level signal, the first thin film transistor is turned off, the second thin film transistor is turned on, and the electrostatic signal passes the turned on Two thin film transistors are released from the third end to the first end.
  • each of the three sub-circuit units constitutes a circuit unit
  • each circuit unit corresponds to a pixel unit in the display panel
  • the three sub-circuit units constituting the circuit unit are respectively connected to corresponding pixel units The red sub-pixel unit, the green sub-pixel unit and the blue sub-pixel unit.
  • the first terminals of the three sub-circuit units are connected to the same first control signal or the first level signal, and the second terminals of the three sub-circuit units are connected to the same The second control signal or the second level signal.
  • the third terminals of the three sub-circuit units are respectively connected to different test signal lines or different third-level signal lines.
  • the present invention also provides a display panel including the dual-function circuit according to any one of the above.
  • the display area and the non-display area of the display panel, the display panel further includes:
  • An output line connected to the pixels in the display area and provided in the non-display area;
  • the dual function circuit is disposed on a side of the output line away from the display area, and is disposed in the non-display area.
  • the non-display area of the display panel further includes a binding area, the binding area is connected to the output line, and the binding area is provided on a side of the output line away from the display area
  • the dual-function circuit is connected to the binding area, and is disposed on the side of the binding area away from the output line.
  • the invention also provides a test method for a display panel.
  • the display panel includes a dual-function circuit.
  • the dual-function circuit includes at least one sub-circuit unit. Each sub-circuit unit passes through a corresponding data line of the display panel and a corresponding sub-pixel. Unit connection; the sub-circuit unit includes a first end, a second end, a third end, and a fourth end, wherein the fourth end is used to connect to the corresponding data line of the display panel and to the corresponding sub-pixel unit;
  • the test methods of the display panel include:
  • the data line is used for testing the corresponding sub-pixel unit of the display panel.
  • the sub-circuit unit includes a first thin film transistor and a second thin film transistor; the first thin film transistor is connected to the second thin film transistor, the first end and the fourth end, and the second thin film transistor is also connected to The second end, the third end and the fourth end are connected;
  • the "controlling transmission of the test signal from the third end to the fourth end according to the first control signal and the second control signal” includes:
  • the first control signal controls the first thin film transistor to be turned off
  • the second control signal controls the second thin film transistor to be turned on
  • the test signal is transmitted to the second thin film transistor through the third terminal, And transmitted to the fourth terminal through the second thin film transistor.
  • the invention also provides an electrostatic protection method for a display panel.
  • the display panel includes a dual-function circuit.
  • the dual-function circuit includes at least one sub-circuit unit. Each sub-circuit unit passes through a corresponding data line of the display panel and a corresponding sub-circuit.
  • the pixel unit is connected; the sub-circuit unit includes a first end, a second end, a third end, and a fourth end, wherein the fourth end is used to connect with the corresponding data line of the display panel and connect with the corresponding sub-pixel unit;
  • the test methods of the display panel include:
  • the electrostatic signal transmitted by the data line received by the fourth terminal is controlled to be discharged according to the first level signal, the second level signal, and the third level signal.
  • the dual-function circuit provided by the present invention has both a test function and an electrostatic protection function for the sub-pixel unit in the display panel. Compared with a circuit that can only implement the test function or the electrostatic protection function alone, the circuit of the present invention The dual-function circuit can reduce the number of devices in the display panel or reduce the circuit wiring, which can save space.
  • FIG. 1 is a schematic diagram of a dual-function circuit provided by the first embodiment of the present invention.
  • FIG. 2 is a schematic diagram of another dual-function circuit provided by the first embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a dual function circuit provided by the present invention in a test function.
  • FIG. 4 is a schematic diagram of another dual-function circuit provided by the present invention in a test function.
  • FIG. 5 is a schematic diagram of a dual-function circuit provided by the present invention in an electrostatic protection function.
  • FIG. 6 is a schematic diagram of another dual-function circuit provided by the present invention in an electrostatic protection function.
  • FIG. 7 is a schematic diagram of a dual-function circuit provided by a second embodiment of the present invention.
  • FIG. 8 is a signal timing diagram of a dual-function circuit in the test phase provided by the second embodiment.
  • FIG. 9 is a level signal diagram of a dual-function circuit in the static protection stage provided by the second embodiment.
  • FIG. 10 is a schematic diagram of a display panel provided by the present invention.
  • FIG. 11 is a flowchart of a method for testing a display panel provided by the present invention.
  • FIG. 12 is a flowchart of a static electricity protection method for a display panel provided by the present invention.
  • the first embodiment of the present invention provides a dual-function circuit 10.
  • the dual-function circuit 10 includes at least one sub-circuit unit 100.
  • Each sub-circuit unit 100 passes through a corresponding data line 30 of the display panel 20 and a corresponding sub-circuit
  • the pixel unit 40 is connected.
  • each sub-circuit unit 100 transmits the test signal to the corresponding sub-pixel unit 40 through the corresponding data line 30 of the display panel 20 to test the corresponding sub-pixel unit 40.
  • the test signal is input for testing, if the corresponding sub-pixel unit 40 is not lit, it means that the sub-pixel unit 40 is damaged or the line between the test signal and the sub-pixel unit 40 is damaged, such as the corresponding sub-pixel unit 40 is lit, it means that the line or device between the test signal and the sub-pixel unit 40 has good performance and is not damaged, so as to achieve the test purpose.
  • each sub-circuit unit 100 receives the electrostatic signal of the corresponding sub-pixel unit 40 through the corresponding data line 30 of the display panel 20 and discharges it.
  • the sub-pixel unit will generate an electrostatic discharge phenomenon, and the electrostatic discharge will damage the electronic components connected to it, thereby invalidating the function of the components in the display panel 20. Therefore, it is necessary to protect the electrostatic discharge phenomenon.
  • the dual-function circuit 10 can be used to discharge the electrostatic signal of the sub-pixel unit 40 for protection purposes. It can be understood that the electrostatic signal may be a high-voltage electrostatic signal or a low-voltage electrostatic signal.
  • the dual-function circuit 10 provided by the present invention has both a test function and an electrostatic protection function for the sub-pixel unit 40 in the display panel 20. Compared with a circuit that can only implement the test function or the electrostatic protection function alone, the dual-function circuit of the present invention 10 can reduce the number of devices in the display panel 20 or reduce circuit traces, which can save space.
  • each sub-circuit unit 100 includes a first terminal 110, a second terminal 120, a third terminal 130 and a fourth terminal 140, wherein the fourth terminal 140 is used to communicate with the display panel 20
  • the corresponding data line 30 is connected to the corresponding sub-pixel unit 40.
  • the first terminal 110 is connected to the first control signal
  • the second terminal 120 is connected to the second control signal
  • the third terminal 130 is connected to the test signal
  • the sub-circuit unit 100 is in the first control
  • the test signal is transmitted from the third terminal 130 to the fourth terminal 140 under the control of the signal and the second control signal
  • the test signal is transmitted to the data line 30 of the display panel 20 through the fourth terminal 140 for the display panel 20
  • the corresponding sub-pixel unit 40 is tested.
  • first control signal, the second control signal, and the test signal are provided to the sub-circuit unit 100 through their respective lines.
  • each sub-circuit unit 100 includes a first end 110, a second end 120, a third end 130, and a fourth end 140, wherein the fourth end 140 is used for the corresponding data line 30 of the display panel 20 The connection is further connected to the corresponding sub-pixel unit 40.
  • the first terminal 110 is connected to the first level signal
  • the second terminal 120 is connected to the second level signal
  • the third terminal 130 is connected to the third level signal
  • the sub-circuit unit 100 releases the electrostatic signal transmitted by the data line 30 received by the fourth terminal 140 under the control of the first level signal, the second level signal, and the third level signal. That is, the electrostatic signal generated by the sub-pixel unit 40 in the display panel 20 is transmitted from the fourth terminal 140 to the sub-circuit unit 100 and is discharged.
  • each sub-circuit unit 100 includes a first thin film transistor 150 and a second thin film transistor 160.
  • the first thin film transistor 150 is connected to the second thin film transistor 160, the first terminal 110 and the fourth terminal 140, and the second thin film transistor 160 is also connected to the second terminal 120, the third terminal 130 and the fourth terminal 140.
  • the first end 110 of the corresponding sub-circuit unit 100 is connected to the first control signal
  • the second end 120 is connected to the second control signal
  • the third end 130 is connected to the test signal
  • the first The control signal controls the first thin film transistor 150 to be turned off
  • the second control signal controls the second thin film transistor 160 to be turned on
  • the test signal connected to the third terminal 130 is transmitted to the fourth terminal 140 through the turned on second thin film transistor 160 and passes
  • the fourth terminal 140 transmits the test signal to the data line 30 of the display panel 20 for testing the corresponding sub-pixel unit 40 of the display panel 20.
  • the first control in the case where the signal between the third terminal 130 and the fourth terminal 140 is ensured and the signal between the first terminal 110 and the fourth terminal 140 is not connected, the first control in other embodiments
  • the type of signal and the element with which the signal is to be turned on or off are not limited to the thin film transistor of the present invention.
  • the first thin film transistor 150 is in an off or on state according to the electrostatic signal received by the fourth terminal 140 and the first level signal received by the first terminal 110, and the second thin film transistor 160 is based on
  • the electrostatic signal received by the fourth terminal 140, the second level signal received by the second terminal 120, and the third level signal received by the third terminal 130 are in the on or off state; the electrostatic signal passes through the first film in the on state
  • the transistor 150 or the second thin film transistor 160 is released.
  • the electrostatic signal received by the fourth terminal 140 may be a high-voltage or low-voltage electrostatic signal.
  • the first thin film transistor 150 includes a gate 151, a first pole 152, and a second pole 153
  • the second thin film transistor 160 includes a gate 161, a first pole 162, and a second pole 163, respectively.
  • the first electrodes 152 and 162 can be source electrodes
  • the second electrodes 153 and 163 can be drain electrodes.
  • the gate 151 of the first thin film transistor 150 is connected to the fourth terminal 140, the first electrode 152 of the first thin film transistor 150 is connected to the first terminal 110, and the second electrode 130 of the first thin film transistor 150 is connected to the fourth terminal 140.
  • the gate electrode 161 of the second thin film transistor 160 is connected to the second terminal 120, the first electrode 162 of the second thin film transistor 160 is connected to the third terminal 130, and the second electrode 163 of the second thin film transistor 160 is connected to the fourth terminal 140.
  • the first control signal is a high-level signal
  • the second control signal is a high-level signal
  • the first thin film transistor 150 is an N-type transistor
  • the second thin film The transistor 160 is an N-type transistor. It can be understood that the high-level signal can control the N-type transistor to be turned on, and the low-level signal can control the N-type transistor to be turned off. Referring to FIG.
  • the first control signal for controlling the first thin film transistor 150 is a high-level signal P1, and the high-level signal P1 is derived from the first electrode 152 of the first thin-film transistor 150
  • the voltage input to the gate 151 of the first thin film transistor 150 is high voltage, that is, the gate 151 of the first thin film transistor 150 is connected with a low-level signal L1, which controls the first thin film The transistor 150 is turned off.
  • the second control signal for controlling the second thin film transistor 160 is a high level signal P2, and the high level signal P2 is input from the gate 161 of the second thin film transistor 160, that is, the second thin film transistor 160 is controlled to conduct through.
  • the first thin film transistor 150 is turned off and the second thin film transistor 160 is turned on.
  • the test signal M can be transmitted from the third terminal 130 to the fourth terminal through the turned-on second thin film transistor 160 140, and then transmitted to the corresponding sub-pixel unit 40 for testing.
  • the first control signal is a low-level signal
  • the second control signal is a low-level signal
  • the first thin film transistor 150 is a P-type transistor
  • the second thin film The transistor 160 is a P-type transistor. It can be understood that the low-level signal can control the P-type transistor to be turned on, and the high-level signal can control the P-type transistor to be turned off. Referring to FIG.
  • the first control signal for controlling the first thin film transistor 150 is a low-level signal L2, and the low-level signal L2 is derived from the first electrode 152 of the first thin-film transistor 150
  • the voltage input to the gate 151 of the first thin film transistor 150 is low, that is, the gate 151 of the first thin film transistor 150 is connected with a high-level signal P3, which controls the first thin film The transistor 150 is turned off.
  • the second control signal for controlling the second thin film transistor 160 is a low level signal L3, and the low level signal L3 is input from the gate 161 of the second thin film transistor 160, that is, the second thin film transistor 160 is controlled to conduct through.
  • the first thin film transistor 150 is turned off and the second thin film transistor 160 is turned on.
  • the test signal M can be transmitted from the third terminal 130 to the fourth terminal 140 through the turned on second thin film transistor 160 , And then transmitted to the corresponding sub-pixel unit 40 for testing.
  • the first level signal is greater than the second level signal and the third level signal.
  • the voltage of static electricity discharged from the sub-pixel unit 40 is generally a positive and negative voltage with a large absolute value, such as +1000V (volt) or -1000 (volt).
  • the absolute value of the static electricity voltage is greater than the first level signal and the second power The voltage of the level signal and the third level signal.
  • the first thin film transistor 150 When the voltage value of the electrostatic signal is greater than the voltage value of the first level signal, the first thin film transistor 150 is turned on, the second thin film transistor 160 is turned off, and the electrostatic signal passes from the fourth terminal 140 to the first through the turned on first thin film transistor 150 One end 110 is released.
  • the voltage value of the electrostatic signal J1 when the voltage value of the electrostatic signal J1 is a positive voltage and is greater than the first level signal H1, for the first thin film transistor 150, a high voltage electrostatic signal J1 is transmitted to the first thin film transistor 150
  • the first level signal H1 whose voltage value is relatively lower than the electrostatic signal J1 is transmitted to the first electrode 152 of the first thin film transistor 150.
  • the voltage of the gate 151 is greater than the voltage of the first electrode 152.
  • a thin film transistor 150 is turned on, and the high-voltage electrostatic signal J1 is discharged from the fourth terminal 140 to the first terminal 110.
  • the voltage connected to the gate 161 of the second thin film transistor 160 is a low level, and the electrostatic signal J1 connected to the second electrode 163 is a high voltage.
  • the second thin film transistor 160 is turned off. That is to say, when the electrostatic signal J1 is an electrostatic signal of a higher voltage, the electrostatic signal J1 is discharged by the first thin film transistor 150.
  • the first thin film transistor 150 and the second thin film transistor 160 are N-type transistors. When the first thin film transistor 150 and the second thin film transistor 160 are P-type transistors, the electrostatic signal J1 is electrostatically discharged from the second thin film transistor 160.
  • the first thin film transistor 150 When the voltage value of the electrostatic signal is less than the voltage values of the second level signal and the third level signal, the first thin film transistor 150 is turned off, the second thin film transistor 160 is turned on, and the electrostatic signal passes through the turned on second thin film transistor 160 from The third end 130 is released to the first end 110.
  • the electrostatic signal J2 when the voltage value of the electrostatic signal J2 is negative and less than the first level signal H1, for the first thin film transistor 150, the electrostatic signal J2 of a low voltage value is transmitted to the first thin film transistor 150
  • the first level signal H1 whose voltage value is relatively higher than the electrostatic signal J2 is transmitted to the first electrode 152 of the first thin film transistor 150.
  • the voltage of the gate 151 is less than the voltage of the first electrode 152.
  • a thin film transistor 150 is turned off.
  • the second level signal H2 connected to the gate 161 of the second thin film transistor 160 is a high voltage relative to the electrostatic signal J2 connected to the second electrode 163.
  • the second thin film transistor 160 is turned on, and the low voltage electrostatic signal J2 It is released from the fourth end 140 to the first end 110. That is to say, when the electrostatic signal J2 is an electrostatic signal of a lower voltage, the electrostatic signal J2 is discharged by the second thin film transistor 160.
  • the first thin film transistor 150 and the second thin film transistor 160 are N-type transistors. When the first thin film transistor 150 and the second thin film transistor 160 are P-type transistors, the electrostatic signal J2 is electrostatically discharged from the first thin film transistor 150.
  • a second embodiment of the present invention provides a dual-function circuit 10a.
  • every three sub-circuit units 100 constitute a circuit unit 200, and each circuit unit 200 and one of the display panel 20
  • the pixel unit 300 corresponds, and the three sub-circuit units 100 constituting the circuit unit 200 are respectively connected to the red sub-pixel unit 310, the green sub-pixel unit 320, and the blue sub-pixel unit 330 in the corresponding pixel unit 300.
  • the sub-circuit unit 100 a corresponds to the red sub-pixel unit 310
  • the sub-circuit unit 100 b corresponds to the green sub-pixel unit 320
  • the sub-circuit unit 100 c corresponds to the blue sub-pixel unit 330.
  • the first terminals 110 of the three sub-circuit units 100 are connected to the same first control signal or first level signal, and the second terminals 120 of the three sub-circuit units 100 are connected to the same second control signal Or a second level signal.
  • the first terminals 110 in the three sub-circuit units 100 are connected to the same signal line A, and the signal line A is used to provide a first control signal or a first level signal.
  • the second terminals 120 of the three sub-circuit units 100 are connected to the same signal line B, and the signal line B is used to provide a second control signal or a second level signal.
  • the third terminals 130 of the three sub-circuit units 100 are respectively connected to different test signal lines or different third-level signal lines. As shown in FIG. 7, the third terminal 130 in the sub-circuit unit 100a is connected to the signal line C, the third terminal 130 in the sub-circuit unit 100b is connected to the signal line D, and the third terminal 130 in the sub-circuit unit 100c is connected to the signal line E .
  • FIG. 8 is a signal timing diagram in the test stage in the second embodiment
  • FIG. 9 is a level signal diagram in the static electricity protection stage in the second embodiment.
  • the first thin film transistor 150 and the second thin film transistor 160 are N-type transistors.
  • the first control signal provided by the signal line A and the second control signal provided by the signal line B are both high voltage high, at this time, the sub-circuit unit 100a 1.
  • the first thin film transistor 150 in the sub circuit unit 100b is turned off, and the second thin film transistor 160 is turned on.
  • the third terminal 130 in the sub-circuit unit 100a provides a test signal M1 through the signal line C within the time period t1, and M1 tests the corresponding connected red sub-pixel unit 310.
  • the third terminal 130 in the sub-circuit unit 100b provides the test signal M2 through the signal line D, and M2 tests the corresponding connected green sub-pixel unit 320.
  • the sub-circuit unit The third terminal 130 in 100c provides a test signal M3 through the signal line E, and M3 tests the corresponding connected blue sub-pixel unit 330.
  • the first level signal provided by the signal line A is high voltage high
  • the second level signal provided by the signal line B is low voltage low
  • the signal line C is low voltage low
  • the signal line C is low voltage low
  • the signal line D is all low voltage low.
  • the electrostatic signal connected to the fourth terminal 140 in the sub-circuit unit 100a and the sub-circuit unit 100b is a high-voltage electrostatic signal
  • the first thin film transistor 150 is turned on and the second thin film transistor 160 is turned off.
  • the electrostatic signals output from the red sub-pixel unit 310, the green sub-pixel unit 320, and the blue sub-pixel unit 330 are discharged from the fourth terminal 140 to the first terminal 110.
  • the electrostatic signal connected to the fourth terminal 140 in the sub-circuit unit 100a and the sub-circuit unit 100b is a low-voltage electrostatic signal
  • the first thin film transistor 150 is turned off and the second thin film transistor 160 is on.
  • the electrostatic signals output from the red sub-pixel unit 310, the green sub-pixel unit 320, and the blue sub-pixel unit 330 are discharged from the fourth terminal 140 to the third terminal 130.
  • the red sub-pixel unit 310, the green sub-pixel unit 320, and the blue sub-pixel unit 330 in the circuit unit 200 are tested separately in different time periods.
  • the test signal may also be provided to the signal line C, the signal line D, and the signal line E at the same time, or two or two tests may be performed at the same time, and the order of the test methods is not limited.
  • the circuit unit 200 may further include other numbers of sub-pixel units 100, and there may be multiple combinations, which are not limited to the combination provided in the second embodiment.
  • the present invention further provides a display panel 20.
  • the display panel 20 includes a dual-function circuit 10 as described above.
  • the dual-function circuit 10 in the display panel 20 provided by the present invention has both a test function and an electrostatic protection function, so that the display panel 20 has fewer traces, and saves the layout space of the display panel 20.
  • the display panel 20 includes a display area 21 and a non-display area 22.
  • the display area 21 refers to the area where the display panel 20 displays light emission
  • the non-display area 22 refers to the area other than the display area 21.
  • the display panel 20 further includes an output line 23 that is connected to the pixels in the display area 21 and is provided in the non-display area 22. It can be understood that the output line 23 includes many lines, and each line corresponds to a sub-pixel in a pixel.
  • the dual-function circuit 10 is provided on the side of the output line 23 away from the display area 21 and in the non-display area 22.
  • Setting the output line 23 between the dual-function circuit 10 and the display area 21 can enable the dual-function circuit 10 to detect whether the output line 23 is on when in the test function, and when the output line 23 is off, the corresponding display area 21
  • the sub-pixels in are not lit, and it can be judged that the damage in the display panel 20 is between the output line 23 or the sub-pixels, and the specific damage location can be further eliminated through other detection methods. In other words, when the display panel 20 is tested, whether the output line 23 is turned on or not can be tested.
  • the non-display area 22 of the display panel 20 further includes a binding area 24.
  • the binding area 24 is connected to the output line 23, and the binding area 24 is disposed on the side of the output line 23 away from the display area 21
  • the dual-function circuit 10 is connected to the binding area 24 and is disposed on the side of the binding area 24 away from the output line 23.
  • the binding area 24 is an area where each line in the output line 23 is concentrated. In this embodiment, the dual function circuit 10 can test the binding area 24 between it and the display area 21.
  • the electrostatic discharge phenomenon in the display panel 20 is more likely to occur at the beginning of the circuit, that is, away from the end of the display area 21.
  • the present invention places the dual-function circuit 10 at the end away from the display area 21, which can effectively avoid electrostatic damage To better protect the components and circuits in the display panel 20.
  • the present invention also provides a test method of the display panel 20.
  • the display panel 20 includes a dual-function circuit 10.
  • the dual-function circuit 10 includes at least one sub-circuit unit 100. Each sub-circuit unit 100 passes the display.
  • the corresponding data line 30 of the panel 20 is connected to the corresponding sub-pixel unit 40, and the sub-circuit unit 100 includes a first terminal 110, a second terminal 120, a third terminal 130, and a fourth terminal 140, wherein the fourth terminal 140 is used for displaying
  • the corresponding data line 30 of the panel 20 is connected to the corresponding sub-pixel unit 40, and the test method of the display panel 20 includes step S100-I, step S200-I, step S300-I, and step S400-I.
  • the detailed steps are as follows.
  • step S100-I Provide a first control signal to the first terminal 110 (step S100-I), and provide a second control signal to the second terminal 120 (step S200-I), and provide a test signal to the third terminal 130 (step S300-I) .
  • the test signal is controlled to be transmitted from the third terminal 130 to the fourth terminal 140, and the test signal is transmitted to the data line 30 of the display panel 20 through the fourth terminal 140 for the display panel
  • the corresponding sub-pixel unit 100 of 20 is tested (step S400-I).
  • the structural design of the dual-function circuit 10 can have both a test function and an electrostatic protection function.
  • the dual-function circuit 10 is in the test function, the display panel 20 is tested.
  • the sub-circuit unit 100 includes a first thin film transistor 150 and a second thin film transistor 160, the first thin film transistor 150 is connected to the second thin film transistor 160, the first terminal 110 and the fourth terminal 140, the second thin film The transistor 160 is also connected to the second terminal 120, the third terminal 130, and the fourth terminal 140.
  • Controlling the transmission of the test signal from the third terminal 130 to the fourth terminal 140 according to the first control signal and the second control signal includes the first control signal controlling the first thin film transistor 150 to be turned off, and the second control signal controlling the second thin film transistor 160 to be turned on The test signal is transmitted to the second thin film transistor 160 through the third terminal 130 and to the fourth terminal 140 through the second thin film transistor 160.
  • the present invention also provides an electrostatic protection method for the display panel 20.
  • the display panel 20 includes a dual-function circuit 10, and the dual-function circuit 10 includes at least one sub-circuit unit 100, and each sub-circuit unit 100 passes The corresponding data line 30 of the display panel 20 is connected to the corresponding sub-pixel unit 40.
  • the sub-circuit unit 100 includes a first terminal 110, a second terminal 120, a third terminal 130, and a fourth terminal 140, wherein the fourth terminal 140 is used to The corresponding data line 30 of the display panel 20 is connected to the corresponding sub-pixel unit 40, and the test method of the display panel 20 includes steps S100-II, S200-II, S300-II, and S400-II. The detailed steps are as follows.
  • Step S100-II Provide a first level signal to the first terminal 110 (step S100-II); and provide a second level signal to the second terminal 120 (step S200-II); and provide a third level signal to the third terminal 130 ( Step S300-II).
  • the electrostatic signal transmitted by the data line received by the fourth terminal 140 is controlled to be discharged according to the first level signal, the second level signal, and the third level signal (step S400-II).
  • the structure design of the dual-function circuit 10 in the test method of the display panel 20 provided by the present invention can have both a test function and an electrostatic protection function.
  • the dual-function circuit 10 is in the electrostatic protection function, the static electricity in the display panel 20 is discharged.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本发明提供了一种双功能电路(10)，包括至少一个子电路单元(100)，每一子电路单元(100)通过显示面板(20)的对应数据线(30)与对应的子像素单元(100)连接；当处于测试功能时，每一子电路单元(10)将测试信号通过对应数据线(30)传输至对应的子像素单元(100)，以对相应的子像素单元(100)进行测试；当处于静电防护功能时，每一子电路单元(10)通过对应数据线(30)接收对应的子像素单元(100)的静电信号，并进行释放。本发明还提供一种显示面板及其测试方法、静电防护方法。本发明提供的双功能电路对显示面板中的子像素单元同时具有测试功能和静电防护功能，可以减少在显示面板中的器件的数量或者减少电路走线，可节省空间。

Description

双功能电路、显示面板及其测试方法、静电防护方法 技术领域
本发明属于显示技术领域，具体涉及一种双功能电路、显示面板及其测试方法、静电防护方法。
背景技术
随着显示技术的发展，有机发光显示或者液晶发光显示的显示面板产品得到广泛的应用，应用到工作、生活、作业以及航天等领域中，如液晶电视、数字电视、电脑、手机、车载显示、摄像机、电子手表、计算器等等。显示面板的生产线中包括点屏测试工序，其主要是检测显示屏在制备过程中出现的不良现象，包括各种斑、区块及污渍等。显示面板在正常工作时，还会存在静电放电现象，静电放电会造成显示面板中的电子元件损坏，导致功能失效的问题。在现有技术中具有单独对显示面板进行点屏测试的电路，或者单独对显示面板进行静电防护的电路，但是单独设置的测试电路和静电防护电路，会占用较多的布线空间。
发明内容
有鉴于此，本发明提供一种能够同时具有测试功能和静电防护功能的双功能电路，节约走线空间。具体技术方案如下。
一种双功能电路，所述双功能电路包括至少一个子电路单元，每一子电路单元通过显示面板的对应数据线与对应的子像素单元连接；
当双功能电路处于测试功能时，每一子电路单元将测试信号通过显示面板的对应数据线传输至对应的子像素单元，以对相应的子像素单元进行测试；
当双功能电路处于静电防护功能时，每一子电路单元通过显示面板的对应数据线接收 对应的子像素单元的静电信号，并进行释放。
优选的，每一子电路单元包括第一端、第二端、第三端以及第四端，其中第四端用于与显示面板的对应数据线连接而与对应的子像素单元连接；
当双功能电路处于测试功能时，所述第一端接入第一控制信号，所述第二端接入第二控制信号，所述第三端接入测试信号时，所述子电路单元在第一控制信号和所述第二控制信号的控制下将所述测试信号从所述第三端传输到所述第四端，并通过所述第四端将所述测试信号传输给显示面板的数据线，以用于对显示面板的对应子像素单元进行测试。
优选的，每一子电路单元包括第一端、第二端、第三端以及第四端，其中第四端用于与显示面板的对应数据线连接而与对应的子像素单元连接；
当双功能电路处于静电防护功能时，所述第一端接入第一电平信号，所述第二端接入第二电平信号，所述第三端接入第三电平信号，所述子电路单元在所述第一电平信号、所述第二电平信号及所述第三电平信号的控制下将所述第四端接收的数据线传输的静电信号进行释放。
优选的，所述子电路单元包括第一薄膜晶体管和第二薄膜晶体管；
所述第一薄膜晶体管与所述第二薄膜晶体管、第一端及第四端连接，所述第二薄膜晶体管还与所述第二端、第三端及第四端连接；
当双功能电路处于测试功能时，所述第一端接入第一控制信号，所述第二端接入第二控制信号，所述第三端接入测试信号时，所述第一控制信号控制所述第一薄膜晶体管截止，所述第二控制信号控制所述第二薄膜晶体管导通，所述第三端接入的测试信号通过导通的所述第二薄膜晶体管传输到所述第四端，并通过所述第四端将所述测试信号传输给显示面板的数据线，以用于对显示面板的对应子像素单元进行测试。
优选的，所述子电路单元包括第一薄膜晶体管和第二薄膜晶体管；
所述第一薄膜晶体管与所述第二薄膜晶体管、第一端及第四端连接，所述第二薄膜晶体管还与所述第二端、第三端及第四端连接；
当双功能电路处于静电防护功能时，所述第一薄膜晶体管根据所述第四端接收的静电信号和所述第一端接收的第一电平信号处于截止或导通状态，所述第二薄膜晶体管根据所述第四端接收的静电信号和所述第二端接收的第二电平信号、所述第三端接收的第三电平信号处于导通或截止状态；所述静电信号通过处于导通状态的第一薄膜晶体管或第二薄膜晶体管进行释放。
优选的，所述第一薄膜晶体管和所述第二薄膜晶体管分别包括栅极、第一极和第二极；
所述第一薄膜晶体管的栅极连接所述第四端，所述第一薄膜晶体管的第一极连接所述第一端，所述第一薄膜晶体管的第二极连接所述第四端；所述第二薄膜晶体管的栅极连接所述第二端，所述第二薄膜晶体管的第一极连接所述第三端，所述第二薄膜晶体管的第二极连接所述第四端。
优选的，当双功能电路处于测试功能时，所述第一控制信号为高电平信号，所述第二控制信号为高电平信号，所述第一薄膜晶体管为N型晶体管，所述第二薄膜晶体管为N型晶体管。
优选的，当双功能电路处于测试功能时，所述第一控制信号为低电平信号，所述第二控制信号为低电平信号，所述第一薄膜晶体管为P型晶体管，所述第二薄膜晶体管为P型晶体管。
优选的，当双功能电路处于静电防护功能时；所述第一电平信号大于第二电平信号和第三电平信号；当所述静电信号的电压值大于第一电平信号的电压值时，所述第一薄膜晶体管导通，所述第二薄膜晶体管截止，所述静电信号通过导通的所述第一薄膜晶体管自所述第四端向所述第一端释放；当所述静电信号的电压值小于第二电平信号和第三电平信号的电压值时，所述第一薄膜晶体管截止，所述第二薄膜晶体管导通，所述静电信号通过导通的所述第二薄膜晶体管自所述第三端向所述第一端释放。
优选的，所述每三个所述子电路单元构成一个电路单元，每个电路单元与显示面板中的一像素单元对应，构成电路单元的三个所述子电路单元分别连接对应的像素单元中的红 色子像素单元、绿色子像素单元以及蓝色子像素单元。
优选的，三个所述子电路单元中的第一端接入同一所述第一控制信号或者所述第一电平信号，三个所述子电路单元中的第二端接入同一所述第二控制信号或者第二电平信号。
优选的，三个所述子电路单元中的第三端分别连接不同的测试信号线或者不同的第三电平信号线。
本发明还提供一种显示面板，所述显示面板包括如上述任一项所述的双功能电路。
优选的，所述显示面板显示区和非显示区，所述显示面板还包括：
输出线路，所述输出线路与所述显示区中的像素连接，且设置在所述非显示区中；
所述双功能电路设置在所述输出线路远离所述显示区的一侧，且设置在所述非显示区中。
优选的，所述显示面板的非显示区中还包括绑定区，所述绑定区与所述输出线路连接，且所述绑定区设置在所述输出线路远离所述显示区的一侧；所述双功能电路与所述绑定区连接，且设置在所述绑定区远离所述输出线路的一侧。
本发明还提供一种显示面板的测试方法，所述显示面板包括双功能电路，所述双功能电路包括至少一个子电路单元，每一子电路单元通过显示面板的对应数据线与对应的子像素单元连接；所述子电路单元包括第一端、第二端、第三端以及第四端，其中第四端用于与显示面板的对应数据线连接而与对应的子像素单元连接；所述显示面板的测试方法包括：
提供第一控制信号给所述第一端；以及
提供第二控制信号给所述第二端；以及
提供测试信号给所述第三端；
根据所述第一控制信号和所述第二控制信号控制所述测试信号从所述第三端传输到所述第四端，并通过所述第四端将所述测试信号传输给显示面板的数据线，以用于对显示面板的对应子像素单元进行测试。
优选的，所述子电路单元包括第一薄膜晶体管和第二薄膜晶体管；所述第一薄膜晶体 管与所述第二薄膜晶体管、第一端及第四端连接，所述第二薄膜晶体管还与所述第二端、第三端及第四端连接；
所述“根据所述第一控制信号和所述第二控制信号控制所述测试信号从所述第三端传输到所述第四端”包括：
所述第一控制信号控制所述第一薄膜晶体管截止，所述第二控制信号控制所述第二薄膜晶体管导通，所述测试信号通过所述第三端传输到所述第二薄膜晶体管，并通过所述第二薄膜晶体管传输到所述第四端。
本发明还提供一种显示面板的静电防护方法，所述显示面板包括双功能电路，所述双功能电路包括至少一个子电路单元，每一子电路单元通过显示面板的对应数据线与对应的子像素单元连接；所述子电路单元包括第一端、第二端、第三端以及第四端，其中第四端用于与显示面板的对应数据线连接而与对应的子像素单元连接；所述显示面板的测试方法包括：
提供第一电平信号给所述第一端；以及
提供第二电平信号给所述第二端；以及
提供第三电平信号给所述第三端；
根据所述第一电平信号、所述第二电平信号及所述第三电平信号控制所述第四端接收的数据线传输的静电信号进行释放。
本发明的有益效果：本发明提供的双功能电路对显示面板中的子像素单元同时具有测试功能和静电防护功能，相较于采用只能单独实现测试功能或者静电防护功能的电路，本发明的双功能电路可以减少在显示面板中的器件的数量或者减少电路走线，可节省空间。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域 普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本发明第一实施例提供的一种双功能电路的示意图。
图2为本发明第一实施例提供的另一种双功能电路的示意图。
图3为本发明提供的一种双功能电路处于测试功能的示意图。
图4为本发明提供的另一种双功能电路处于测试功能的示意图。
图5为本发明提供的一种双功能电路处于静电防护功能的示意图。
图6为本发明提供的另一种双功能电路处于静电防护功能的示意图。
图7为本发明第二实施例提供的一种双功能电路的示意图。
图8是第二实施例提供的一种双功能电路在测试阶段的信号时序图。
图9是第二实施例提供的一种双功能电路在静电防护阶段的电平信号图。
图10为本发明提供的一种显示面板的示意图。
图11为本发明提供的一种显示面板的测试方法流程图。
图12为本发明提供的一种显示面板的静电防护方法流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的说明书和权利要求书及所述附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选 地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本发明的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
请参阅图1，本发明第一实施例提供一种双功能电路10，双功能电路10包括至少一个子电路单元100，每一子电路单元100通过显示面板20的对应数据线30与对应的子像素单元40连接。
当双功能电路10处于测试功能时，每一子电路单元100将测试信号通过显示面板20的对应数据线30传输至对应的子像素单元40，以对相应的子像素单元40进行测试。可以理解的是，当输入测试信号进行测试时，如相应的子像素单元40不亮，则说明子像素单元40损坏或者测试信号到子像素单元40之间的线路损坏，如相应的子像素单元40被点亮，则说明测试信号到子像素单元40之间的线路或者器件性能良好，没有损坏，以达到测试目的。
当双功能电路10处于静电防护功能时，每一子电路单元100通过显示面板20的对应数据线30接收对应的子像素单元40的静电信号，并进行释放。显示面板20在正常工作时，子像素单元会产生静电放电现象，静电放电会损坏与其相连接的电子元件，进而使显示面板20中的元件功能失效，因此需要对静电放电现象进行防护，本发明的双功能电路10可用于对子像素单元40的静电信号进行释放达到防护目的。可以理解的是，静电信号可以是高电压的静电信号，也可以是低电压的静电信号。
本发明提供的双功能电路10对显示面板20中的子像素单元40同时具有测试功能和静电防护功能，相较于采用只能单独实现测试功能或者静电防护功能的电路，本发明的双功能电路10可以减少在显示面板20中的器件的数量或者减少电路走线，可节省空间。
请参阅图2，在进一步的实施例中，每一子电路单元100包括第一端110、第二端120、 第三端130以及第四端140，其中第四端140用于与显示面板20的对应数据线30连接进而与对应的子像素单元40连接。
当双功能电路10处于测试功能时，第一端110接入第一控制信号，第二端120接入第二控制信号，第三端130接入测试信号时，子电路单元100在第一控制信号和第二控制信号的控制下将测试信号从第三端130传输到第四端140，并通过第四端140将测试信号传输给显示面板20的数据线30，以用于对显示面板20的对应子像素单元40进行测试。
可以理解的是，第一控制信号、第二控制信号以及测试信号通过其各自的线路提供给子电路单元100。
在进一步的实施例中，每一子电路单元100包括第一端110、第二端120、第三端130以及第四端140，其中第四端140用于与显示面板20的对应数据线30连接进而与对应的子像素单元40连接。
当双功能电路10处于静电防护功能时，第一端110接入第一电平信号，第二端120接入第二电平信号，第三端130接入第三电平信号，子电路单元100在第一电平信号、第二电平信号及第三电平信号的控制下将第四端140接收的数据线30传输的静电信号进行释放。也就是说，显示面板20中的子像素单元40产生的静电信号从第四端140传输到子电路单元100，并将其释放。
在进一步的实施例中，每一子电路单元100包括第一薄膜晶体管150和第二薄膜晶体管160。第一薄膜晶体管150与第二薄膜晶体管160、第一端110及第四端140连接，第二薄膜晶体管160还与第二端120、第三端130及第四端140连接。
当双功能电路10处于测试功能时，相应子电路单元100的第一端110接入第一控制信号，第二端120接入第二控制信号，第三端130接入测试信号时，第一控制信号控制第一薄膜晶体管150截止，第二控制信号控制第二薄膜晶体管160导通，第三端130接入的测试信号通过导通的第二薄膜晶体管160传输到第四端140，并通过第四端140将测试信号传输给显示面板20的数据线30，以用于对显示面板20的对应子像素单元40进行测试。 可以理解的是，在保证第三端130与第四端140之间信号导通，第一端110与第四端140之间信号不导通的情况下，在其他实施例中的第一控制信号的类型以及与其要控制信号导通或截止的元件不限于本发明的薄膜晶体管。
当双功能电路10处于静电防护功能时，第一薄膜晶体管150根据第四端140接收的静电信号和第一端110接收的第一电平信号处于截止或导通状态，第二薄膜晶体管160根据第四端140接收的静电信号和第二端120接收的第二电平信号、第三端130接收的第三电平信号处于导通或截止状态；静电信号通过处于导通状态的第一薄膜晶体管150或第二薄膜晶体管160进行释放。其中，第四端140接收到的静电信号可以为高电压或者低电压的静电信号。
在进一步的实施例中，第一薄膜晶体管150包括栅极151、第一极152和第二极153，第二薄膜晶体管160分别包括栅极161、第一极162和第二极163。其中，第一极152、162可为源极，第二极153、163可为漏极。
第一薄膜晶体管150的栅极151连接第四端140，第一薄膜晶体管150的第一极152连接第一端110，第一薄膜晶体管150的第二极130连接第四端140。第二薄膜晶体管160的栅极161连接第二端120，第二薄膜晶体管160的第一极162连接第三端130，第二薄膜晶体管160的第二极163连接第四端140。
在进一步的实施例中，当双功能电路10处于测试功能时，第一控制信号为高电平信号，第二控制信号为高电平信号，第一薄膜晶体管150为N型晶体管，第二薄膜晶体管160为N型晶体管。可以理解的是，高电平信号能够控制N型晶体管导通，低电平信号控制N型晶体管截止。请参阅图3，在该实施例中，用于控制第一薄膜晶体管150的第一控制信号为高电平信号P1，且该高电平信号P1是从第一薄膜晶体管150的第一极152输入的，其相对于第一薄膜晶体管150的栅极151电压是高压，也就是说第一薄膜晶体管150栅极151接入的是低电平信号L1，该低电平信号L1控制第一薄膜晶体管150截止。而用于控制第二薄膜晶体管160的第二控制信号为高电平信号P2，且该高电平信号P2是从第二薄膜晶 体管160的栅极161输入的，即控制第二薄膜晶体管160导通。也就是说，在该实施例中，第一薄膜晶体管150截止，第二薄膜晶体管160导通，此时测试信号M可以从第三端130通过导通的第二薄膜晶体管160传输到第四端140，进而传输到对应的子像素单元40进行测试。
在进一步的实施例中，当双功能电路10处于测试功能时，第一控制信号为低电平信号，第二控制信号为低电平信号，第一薄膜晶体管150为P型晶体管，第二薄膜晶体管160为P型晶体管。可以理解的是，低电平信号能够控制P型晶体管导通，高电平信号控制P型晶体管截止。请参阅图4，在该实施例中，用于控制第一薄膜晶体管150的第一控制信号为低电平信号L2，且该低电平信号L2是从第一薄膜晶体管150的第一极152输入的，其相对于第一薄膜晶体管150的栅极151电压是低压，也就是说第一薄膜晶体管150栅极151接入的是高电平信号P3，该高电平信号P3控制第一薄膜晶体管150截止。而用于控制第二薄膜晶体管160的第二控制信号为低电平信号L3，且该低电平信号L3是从第二薄膜晶体管160的栅极161输入的，即控制第二薄膜晶体管160导通。也就是说在该实施例中，第一薄膜晶体管150截止，第二薄膜晶体管160导通，此时测试信号M可以从第三端130通过导通的第二薄膜晶体管160传输到第四端140，进而传输到对应的子像素单元40进行测试。
在进一步的实施例中，当双功能电路10处于静电防护功能时；第一电平信号大于第二电平信号和第三电平信号。可以理解的是，可将第一电平信号设为高电平，第二电平信号为低电平，第三电平信号为低电平，各具体电压值可根据实际情况来设定。子像素单元40释放的静电的电压一般为绝对值较大的正负电压，例如+1000V(伏)或-1000(伏)，静电的电压的绝对值均大于第一电平信号、第二电平信号和第三电平信号的电压。
当静电信号的电压值大于第一电平信号的电压值时，第一薄膜晶体管150导通，第二薄膜晶体管160截止，静电信号通过导通的第一薄膜晶体管150自第四端140向第一端110释放。如图5所示，当静电信号J1的电压值为正电压而大于第一电平信号H1时，对于第 一薄膜晶体管150来说，高电压值的静电信号J1传输到第一薄膜晶体管150的栅极151，电压值相对低于静电信号J1的第一电平信号H1传输到第一薄膜晶体管150的第一极152，此时，栅极151的电压大于第一极152的电压，该第一薄膜晶体管150导通，高电压的静电信号J1自第四端140向第一端110释放。其中第二薄膜晶体管160中栅极161接入的电压为低电平，第二极163接入的静电信号J1为高压，此时第二薄膜晶体管160截止。也就是说，在静电信号J1为较高电压的静电信号时，该静电信号J1是通过第一薄膜晶体管150来进行静电释放。可以理解的是，在该实施例中，第一薄膜晶体管150和第二薄膜晶体管160为N型晶体管。当第一薄膜晶体管150和第二薄膜晶体管160为P型晶体管时，该静电信号J1从第二薄膜晶体管160来进行静电释放。
当静电信号的电压值小于第二电平信号和第三电平信号的电压值时，第一薄膜晶体管150截止，第二薄膜晶体管160导通，静电信号通过导通的第二薄膜晶体管160自第三端130向第一端110释放。如图6所述，当静电信号J2的电压值为负电压而小于第一电平信号H1时，对于第一薄膜晶体管150来说，低电压值的静电信号J2传输到第一薄膜晶体管150的栅极151，电压值相对高于静电信号J2的第一电平信号H1传输到第一薄膜晶体管150的第一极152，此时，栅极151的电压小于第一极152的电压，该第一薄膜晶体管150截止。其中第二薄膜晶体管160中栅极161接入的第二电平信号H2相对第二极163接入的静电信号J2是高电压，此时第二薄膜晶体管160导通，低电压的静电信号J2自第四端140向第一端110释放。也就是说，在静电信号J2为较低电压的静电信号时，该静电信号J2是通过第二薄膜晶体管160来进行静电释放。可以理解的是，在该实施例中，第一薄膜晶体管150和第二薄膜晶体管160为N型晶体管。当第一薄膜晶体管150和第二薄膜晶体管160为P型晶体管时，该静电信号J2从第一薄膜晶体管150来进行静电释放。
请参阅图7，本发明第二实施例提供一种双功能电路10a，在双功能电路10a中，每三个子电路单元100构成一个电路单元200，每个电路单元200与显示面板20中的一像素单元300对应，构成电路单元200的三个子电路单元100分别连接对应的像素单元300中的 红色子像素单元310、绿色子像素单元320以及蓝色子像素单元330。图7中，子电路单元100a对应连接红色子像素单元310，子电路单元100b对应连接绿色子像素单元320，子电路单元100c对应连接蓝色子像素单元330。
在进一步的实施例中，三个子电路单元100中的第一端110接入同一第一控制信号或者第一电平信号，三个子电路单元100中的第二端120接入同一第二控制信号或者第二电平信号。如图7所示，三个子电路单元100中的第一端110接入同一信号线A，该信号线A用于提供第一控制信号或者第一电平信号。三个子电路单元100中的第二端120接入同一信号线B，该信号线B用于提供第二控制信号或者第二电平信号。
在进一步的实施例中，三个子电路单元100中的第三端130分别连接不同的测试信号线或者不同的第三电平信号线。如图7所示，子电路单元100a中的第三端130连接信号线C，子电路单元100b中的第三端130连接信号线D，子电路单元100c中的第三端130连接信号线E。
请参阅图7至图9，下面举例说明该实施例的工作过程。其中图8是第二实施例中在测试阶段的信号时序图，图9是第二实施例中在静电防护阶段的电平信号图。在该实施中，第一薄膜晶体管150和第二薄膜晶体管160为N型晶体管。
请参阅图7和图8，当双功能电路10a处于测试功能时，信号线A提供的第一控制信号和信号线B提供的第二控制信号均为高电压high，此时，子电路单元100a、子电路单元100b子电路单元100c中的第一薄膜晶体管150截止，第二薄膜晶体管160导通。子电路单元100a中的第三端130通过信号线C在t1时间段内提供测试信号M1，M1对对应连接的红色子像素单元310进行测试。同样的，在t2时间段内,子电路单元100b中的第三端130通过信号线D提供测试信号M2，M2对对应连接的绿色子像素单元320进行测试，在t3时间段内,子电路单元100c中的第三端130通过信号线E提供测试信号M3，M3对对应连接的蓝色子像素单元330进行测试。
当双功能电路10a处于静电防护功能时，信号线A提供的第一电平信号为高电压high， 信号线B提供的第二电平信号为低电压low，信号线C、信号线D及信号线E提供的第三电平信号H3均为低电压low。此时，子电路单元100a、子电路单元100b子电路单元100c中的第四端140接入的静电信号为高电压的静电信号时，第一薄膜晶体管150导通，第二薄膜晶体管160截止。自红色子像素单元310、绿色子像素单元320及蓝色子像素单元330输出的静电信号自第四端140向第一端110释放。在其他实施例中，当子电路单元100a、子电路单元100b子电路单元100c中的第四端140接入的静电信号为低电压的静电信号时，第一薄膜晶体管150截止，第二薄膜晶体管160导通。自红色子像素单元310、绿色子像素单元320及蓝色子像素单元330输出的静电信号自第四端140向第三端130释放。
在该实施例中，对电路单元200中的红色子像素单元310、绿色子像素单元320及蓝色子像素单元330在不同的时间段内分别测试的。可以理解的是，在其他实施例中，还可以同时对信号线C、信号线D及信号线E提供测试信号，也可以两两同时测试，测试的方式顺序不限。还可以理解的是，电路单元200还可以包括其他个数的子像素单元100，组合方式可以有多种，不限于第二实施例提供的组合方式。
请参阅图10，本发明还提供一种显示面板20，显示面板20包括如上述任一项的双功能电路10。本发明提供的显示面板20中的双功能电路10同时具有测试功能和静电防护功能，使得显示面板20的走线更少，节约显示面板20中的线路布局空间。
在进一步的实施例中，显示面板20包括显示区21和非显示区22。显示区21是指显示面板20中显示发光的区域，非显示区22是指出显示区21以外的区域。显示面板20还包括输出线路23，输出线路23与显示区21中的像素连接，且设置在非显示区22中。可以理解的是，输出线路23中包括很多条线路，且每一条线路对应一个像素中的子像素。双功能电路10设置在输出线路23远离显示区21的一侧，且设置在非显示区22中。将输出线路23设置在双功能电路10与显示区21之间，可以使得双功能电路10在处于测试功能时可以检测输出线路23是否导通，当输出线路23不通时，与其对应的显示区21中的子像素不被点亮，进而可以判断该显示面板20中的损坏是发生在输出线路23或者子像素之间， 可通过其他检测方式进一步来排除具体损坏的位置。也就是说该显示面板20在测试时，输出线路23的导通与否能够被测试出。
在进一步的实施例中，显示面板20的非显示区22中还包括绑定区24，绑定区24与输出线路23连接，且绑定区24设置在输出线路23远离显示区21的一侧，双功能电路10与绑定区24连接，且设置在绑定区24远离输出线路23的一侧。其中绑定区24是将输出线路23中的各线路集中的区域。在该实施例中，双功能电路10可以对其与显示区21之间的绑定区24进行测试。
另外，显示面板20中的静电放电现象较容易发生在线路的始端，也就是远离显示区21的末端，本发明将双功能电路10设置在远离显示区21的末端，可以有效的避免静电击伤，更好的保护显示面板20中的元器件和线路。
请参阅图2和图11，本发明还提供一种显示面板20的测试方法，显示面板20包括双功能电路10，双功能电路10包括至少一个子电路单元100，每一子电路单元100通过显示面板20的对应数据线30与对应的子像素单元40连接，子电路单元100包括第一端110、第二端120、第三端130以及第四端140，其中第四端140用于与显示面板20的对应数据线30连接而与对应的子像素单元40连接，显示面板20的测试方法包括步骤S100-Ⅰ、步骤S200-Ⅰ、步骤S300-Ⅰ和步骤S400-Ⅰ。详细步骤如下所述。
提供第一控制信号给第一端110(步骤S100-Ⅰ)，以及提供第二控制信号给第二端120(步骤S200-Ⅰ)，以及提供测试信号给第三端130(步骤S300-Ⅰ)。
根据第一控制信号和第二控制信号控制测试信号从第三端130传输到第四端140，并通过第四端140将测试信号传输给显示面板20的数据线30，以用于对显示面板20的对应子像素单元100进行测试(步骤S400-Ⅰ)。
本发明提供的显示面板20的测试方法中双功能电路10的结构设计可以同时兼具测试功能和静电防护功能，双功能电路10处于测试功能时，对显示面板20进行测试。
在进一步的实施例中，子电路单元100包括第一薄膜晶体管150和第二薄膜晶体管160， 第一薄膜晶体管150与第二薄膜晶体管160、第一端110及第四端140连接，第二薄膜晶体管160还与第二端120、第三端130及第四端140连接。
“根据第一控制信号和第二控制信号控制测试信号从第三端130传输到第四端140”包括第一控制信号控制第一薄膜晶体管150截止，第二控制信号控制第二薄膜晶体管160导通，测试信号通过第三端130传输到第二薄膜晶体管160，并通过第二薄膜晶体管160传输到第四端140。
请参阅图2和图12，本发明还提供一种显示面板20的静电防护方法，显示面板20包括双功能电路10，双功能电路10包括至少一个子电路单元100，每一子电路单元100通过显示面板20的对应数据线30与对应的子像素单元40连接，子电路单元100包括第一端110、第二端120、第三端130以及第四端140，其中第四端140用于与显示面板20的对应数据线30连接而与对应的子像素单元40连接，显示面板20的测试方法包括步骤S100-Ⅱ、步骤S200-Ⅱ、步骤S300-Ⅱ和步骤S400-Ⅱ。详细步骤如下所述。
提供第一电平信号给第一端110(步骤S100-Ⅱ)；以及提供第二电平信号给第二端120(步骤S200-Ⅱ)；以及提供第三电平信号给第三端130(步骤S300-Ⅱ)。
根据第一电平信号、第二电平信号及第三电平信号控制第四端140接收的数据线传输的静电信号进行释放(步骤S400-Ⅱ)。
本发明提供的显示面板20的测试方法中双功能电路10的结构设计可以同时兼具测试功能和静电防护功能，双功能电路10处于静电防护功能时，对显示面板20中的静电进行释放。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种双功能电路，其特征在于，所述双功能电路包括至少一个子电路单元，每一子电路单元通过显示面板的对应数据线与对应的子像素单元连接；
    当双功能电路处于测试功能时，每一子电路单元将测试信号通过显示面板的对应数据线传输至对应的子像素单元，以对相应的子像素单元进行测试；
    当双功能电路处于静电防护功能时，每一子电路单元通过显示面板的对应数据线接收对应的子像素单元的静电信号，并进行释放。
  2. 如权利要求1所述的双功能电路，其特征在于，每一子电路单元包括第一端、第二端、第三端以及第四端，其中第四端用于与显示面板的对应数据线连接进而与对应的子像素单元连接；
    当双功能电路处于测试功能时，所述第一端接入第一控制信号，所述第二端接入第二控制信号，所述第三端接入测试信号时，所述子电路单元在第一控制信号和所述第二控制信号的控制下将所述测试信号从所述第三端传输到所述第四端，并通过所述第四端将所述测试信号传输给显示面板的数据线，以用于对显示面板的对应子像素单元进行测试。
  3. 如权利要求1所述的双功能电路，其特征在于，每一子电路单元包括第一端、第二端、第三端以及第四端，其中第四端用于与显示面板的对应数据线连接进而与对应的子像素单元连接；
    当双功能电路处于静电防护功能时，所述第一端接入第一电平信号，所述第二端接入第二电平信号，所述第三端接入第三电平信号，所述子电路单元在所述第一电平信号、所述第二电平信号及所述第三电平信号的控制下将所述第四端接收的数据线传输的静电信号进行释放。
  4. 如权利要求2所述的双功能电路，其特征在于，所述子电路单元包括第一薄膜晶体管和第二薄膜晶体管；
    所述第一薄膜晶体管与所述第二薄膜晶体管、第一端及第四端连接，所述第二薄膜晶 体管还与所述第二端、第三端及第四端连接；
    当双功能电路处于测试功能时，所述第一端接入第一控制信号，所述第二端接入第二控制信号，所述第三端接入测试信号时，所述第一控制信号控制所述第一薄膜晶体管截止，所述第二控制信号控制所述第二薄膜晶体管导通，所述第三端接入的测试信号通过导通的所述第二薄膜晶体管传输到所述第四端，并通过所述第四端将所述测试信号传输给显示面板的数据线，以用于对显示面板的对应子像素单元进行测试。
  5. 如权利要求3所述的双功能电路，其特征在于，所述子电路单元包括第一薄膜晶体管和第二薄膜晶体管；
    所述第一薄膜晶体管与所述第二薄膜晶体管、第一端及第四端连接，所述第二薄膜晶体管还与所述第二端、第三端及第四端连接；
    当双功能电路处于静电防护功能时，所述第一薄膜晶体管根据所述第四端接收的静电信号和所述第一端接收的第一电平信号处于截止或导通状态，所述第二薄膜晶体管根据所述第四端接收的静电信号和所述第二端接收的第二电平信号、所述第三端接收的第三电平信号处于导通或截止状态；所述静电信号通过处于导通状态的第一薄膜晶体管或第二薄膜晶体管进行释放。
  6. 如权利要求4或5所述的双功能电路，其特征在于，所述第一薄膜晶体管和所述第二薄膜晶体管分别包括栅极、第一极和第二极；
    所述第一薄膜晶体管的栅极连接所述第四端，所述第一薄膜晶体管的第一极连接所述第一端，所述第一薄膜晶体管的第二极连接所述第四端；所述第二薄膜晶体管的栅极连接所述第二端，所述第二薄膜晶体管的第一极连接所述第三端，所述第二薄膜晶体管的第二极连接所述第四端。
  7. 如权利要求6所述的双功能电路，其特征在于，当双功能电路处于测试功能时，所述第一控制信号为高电平信号，所述第二控制信号为高电平信号，所述第一薄膜晶体管为N型晶体管，所述第二薄膜晶体管为N型晶体管。
  8. 如权利要求6所述的双功能电路，其特征在于，当双功能电路处于测试功能时，所述第一控制信号为低电平信号，所述第二控制信号为低电平信号，所述第一薄膜晶体管为P型晶体管，所述第二薄膜晶体管为P型晶体管。
  9. 如权利要求6所述的双功能电路，其特征在于，当双功能电路处于静电防护功能时；所述第一电平信号大于第二电平信号和第三电平信号；当所述静电信号的电压值大于第一电平信号的电压值时，所述第一薄膜晶体管导通，所述第二薄膜晶体管截止，所述静电信号通过导通的所述第一薄膜晶体管自所述第四端向所述第一端释放；当所述静电信号的电压值小于第二电平信号和第三电平信号的电压值时，所述第一薄膜晶体管截止，所述第二薄膜晶体管导通，所述静电信号通过导通的所述第二薄膜晶体管自所述第三端向所述第一端释放。
  10. 如权利要求1所述的双功能电路，其特征在于，所述每三个所述子电路单元构成一个电路单元，每个电路单元与显示面板中的一像素单元对应，构成电路单元的三个所述子电路单元分别连接对应的像素单元中的红色子像素单元、绿色子像素单元以及蓝色子像素单元。
  11. 如权利要求10所述的双功能电路，其特征在于，三个所述子电路单元中的第一端接入同一所述第一控制信号或者所述第一电平信号，三个所述子电路单元中的第二端接入同一所述第二控制信号或者第二电平信号。
  12. 如权利要求11所述的双功能电路，其特征在于，三个所述子电路单元中的第三端分别连接不同的测试信号线或者不同的第三电平信号线。
  13. 一种显示面板，其特征在于，所述显示面板包括如权利要求1-12任一项所述的双功能电路。
  14. 如权利要求13所述的显示面板，其特征在于，所述显示面板显示区和非显示区，所述显示面板还包括：
    输出线路，所述输出线路与所述显示区中的像素连接，且设置在所述非显示区中；
    所述双功能电路设置在所述输出线路远离所述显示区的一侧，且设置在所述非显示区中。
  15. 如权利要求14所述的显示面板，其特征在于，所述显示面板的非显示区中还包括绑定区，所述绑定区与所述输出线路连接，且所述绑定区设置在所述输出线路远离所述显示区的一侧；所述双功能电路与所述绑定区连接，且设置在所述绑定区远离所述输出线路的一侧。
  16. 一种显示面板的测试方法，其特征在于，所述显示面板包括双功能电路，所述双功能电路包括至少一个子电路单元，每一子电路单元通过显示面板的对应数据线与对应的子像素单元连接；所述子电路单元包括第一端、第二端、第三端以及第四端，其中第四端用于与显示面板的对应数据线连接而与对应的子像素单元连接；所述显示面板的测试方法包括：
    提供第一控制信号给所述第一端；以及
    提供第二控制信号给所述第二端；以及
    提供测试信号给所述第三端；
    根据所述第一控制信号和所述第二控制信号控制所述测试信号从所述第三端传输到所述第四端，并通过所述第四端将所述测试信号传输给显示面板的数据线，以用于对显示面板的对应子像素单元进行测试。
  17. 如权利要求16所述的测试方法，其特征在于，所述子电路单元包括第一薄膜晶体管和第二薄膜晶体管；所述第一薄膜晶体管与所述第二薄膜晶体管、第一端及第四端连接，所述第二薄膜晶体管还与所述第二端、第三端及第四端连接；
    所述“根据所述第一控制信号和所述第二控制信号控制所述测试信号从所述第三端传输到所述第四端”包括：
    所述第一控制信号控制所述第一薄膜晶体管截止，所述第二控制信号控制所述第二薄膜晶体管导通，所述测试信号通过所述第三端传输到所述第二薄膜晶体管，并通过所述第 二薄膜晶体管传输到所述第四端。
  18. 一种显示面板的静电防护方法，其特征在于，所述显示面板包括双功能电路，所述双功能电路包括至少一个子电路单元，每一子电路单元通过显示面板的对应数据线与对应的子像素单元连接；所述子电路单元包括第一端、第二端、第三端以及第四端，其中第四端用于与显示面板的对应数据线连接而与对应的子像素单元连接；所述显示面板的测试方法包括：
    提供第一电平信号给所述第一端；以及
    提供第二电平信号给所述第二端；以及
    提供第三电平信号给所述第三端；
    根据所述第一电平信号、所述第二电平信号及所述第三电平信号控制所述第四端接收的数据线传输的静电信号进行释放。
PCT/CN2018/123101 2018-12-24 2018-12-24 双功能电路、显示面板及其测试方法、静电防护方法 Ceased WO2020132805A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2018/123101 WO2020132805A1 (zh) 2018-12-24 2018-12-24 双功能电路、显示面板及其测试方法、静电防护方法
CN201880095912.8A CN112639601A (zh) 2018-12-24 2018-12-24 双功能电路、显示面板及其测试方法、静电防护方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/123101 WO2020132805A1 (zh) 2018-12-24 2018-12-24 双功能电路、显示面板及其测试方法、静电防护方法

Publications (1)

Publication Number Publication Date
WO2020132805A1 true WO2020132805A1 (zh) 2020-07-02

Family

ID=71129402

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/123101 Ceased WO2020132805A1 (zh) 2018-12-24 2018-12-24 双功能电路、显示面板及其测试方法、静电防护方法

Country Status (2)

Country Link
CN (1) CN112639601A (zh)
WO (1) WO2020132805A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113570989A (zh) * 2021-07-30 2021-10-29 友达光电（昆山）有限公司 测试电路及显示面板
CN114830330A (zh) * 2020-10-27 2022-07-29 京东方科技集团股份有限公司 显示基板及其裂纹检测方法、显示装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113834992B (zh) * 2021-09-24 2025-01-28 昆山龙腾光电股份有限公司 测试电路和显示面板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202550507U (zh) * 2012-03-15 2012-11-21 京东方科技集团股份有限公司 静电保护电路、阵列基板及显示装置
CN206040646U (zh) * 2016-04-26 2017-03-22 京东方科技集团股份有限公司 静电防护与测试复合单元、阵列基板以及显示装置
CN108847176A (zh) * 2018-07-13 2018-11-20 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102854679A (zh) * 2012-09-25 2013-01-02 南京中电熊猫液晶显示科技有限公司 一种液晶显示面板及其修复方法
CN105070239B (zh) * 2015-08-27 2018-10-16 武汉华星光电技术有限公司 一种液晶显示面板
CN107564416B (zh) * 2017-09-15 2019-08-30 上海天马微电子有限公司 一种显示面板及显示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202550507U (zh) * 2012-03-15 2012-11-21 京东方科技集团股份有限公司 静电保护电路、阵列基板及显示装置
CN206040646U (zh) * 2016-04-26 2017-03-22 京东方科技集团股份有限公司 静电防护与测试复合单元、阵列基板以及显示装置
CN108847176A (zh) * 2018-07-13 2018-11-20 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114830330A (zh) * 2020-10-27 2022-07-29 京东方科技集团股份有限公司 显示基板及其裂纹检测方法、显示装置
CN113570989A (zh) * 2021-07-30 2021-10-29 友达光电（昆山）有限公司 测试电路及显示面板
CN113570989B (zh) * 2021-07-30 2024-04-05 友达光电（昆山）有限公司 测试电路及显示面板

Also Published As

Publication number Publication date
CN112639601A (zh) 2021-04-09

Similar Documents

Publication Publication Date Title
US10699643B2 (en) Pixel driving compensation circuit, driving compensation method therefor and display device
KR102059936B1 (ko) 유기 발광 표시 장치
US9470943B2 (en) Array substrate, display panel and display device
US10067384B2 (en) Detection unit, array structure, liquid crystal display device and detection method
US10109225B2 (en) Panel function test circuit, display panel, and methods for function test and electrostatic protection
US10229619B2 (en) Test circuit, test method, display panel and display apparatus
US20110292005A1 (en) Display apparatus and method for eliminating ghost thereof
US11605323B2 (en) Display panel, detection method and display device
CN101882416A (zh) 显示装置及其残影消除方法
CN104849881A (zh) 一种显示装置及其驱动方法
US20170025051A1 (en) Detecting Circuit, Detecting Method and Display Device
CN204287637U (zh) 阵列基板、显示面板和显示装置
US10102783B2 (en) Array substrate and detecting method for an array substrate
WO2020140236A1 (zh) 信号保护电路、其驱动方法及设备
CN113160744B (zh) 一种显示面板及其驱动方法、显示装置
CN110136618A (zh) 一种显示面板检测电路、显示装置和显示面板检测方法
CN102110400A (zh) 双栅极线显示装置的测试结构及线缺陷测试方法
WO2020132805A1 (zh) 双功能电路、显示面板及其测试方法、静电防护方法
CN103698911A (zh) 一种阵列基板及显示装置
US20170186348A1 (en) Detecting method and detecting apparatus for scan driving circuit and liquid crystal panel
CN107909979A (zh) 液晶显示装置及改善显示面板掉电闪屏的方法
WO2019223623A1 (zh) 显示基板、显示面板和显示装置
WO2016192171A1 (zh) 显示面板及显示装置
CN104570417A (zh) 一种液晶显示屏和电子设备
CN106783877B (zh) 阵列基板、显示面板及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18944220

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18944220

Country of ref document: EP

Kind code of ref document: A1