WO2020130039A1 - Élément de jonction de dispositif à semi-conducteur - Google Patents

Élément de jonction de dispositif à semi-conducteur Download PDF

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Publication number
WO2020130039A1
WO2020130039A1 PCT/JP2019/049601 JP2019049601W WO2020130039A1 WO 2020130039 A1 WO2020130039 A1 WO 2020130039A1 JP 2019049601 W JP2019049601 W JP 2019049601W WO 2020130039 A1 WO2020130039 A1 WO 2020130039A1
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Prior art keywords
semiconductor device
voids
joining
metal
bonding
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PCT/JP2019/049601
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English (en)
Japanese (ja)
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福井　彰
としゑ 福井
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株式会社半導体熱研究所
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Publication of WO2020130039A1 publication Critical patent/WO2020130039A1/fr

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/30—Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C5/00—Alloys based on noble metals
    • C22C5/02—Alloys based on gold
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C5/00—Alloys based on noble metals
    • C22C5/06—Alloys based on silver
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C9/00—Alloys based on copper
    • C22C9/02—Alloys based on copper with tin as the next major constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector

Definitions

  • the present invention relates to a semiconductor device joining member used for joining a semiconductor device and a substrate.
  • HV Hybrid Vehicle
  • EV Electric Vehicle
  • IGBT insulated gate bipolar transistor
  • the first-generation IGBT module For the first-generation IGBT module, initially a DBC (Direct Bonded Cupper; an insulating ceramic substrate joined with Cu with excellent conductivity as a circuit layer) was considered as the insulating circuit substrate, but it was more severe. DBA (Direct Bonded Aluminum, which has a highly conductive Al joined as a circuit layer to a ceramic substrate.) that can be used in the usage environment has come to be used. After that, by omitting the heat dissipation board and thermal grease, and adopting a structure in which the DBA and the cooler are joined with Al punching metal, the second-generation IGBT module reduces thermal resistance by 30% compared to the first-generation IGBT module. Was put to practical use.
  • DBC Direct Bonded Cupper; an insulating ceramic substrate joined with Cu with excellent conductivity as a circuit layer
  • heat path A structure in which a heat dissipation path (hereinafter, referred to as “heat path”) is provided on one surface of a semiconductor device, like the first-generation IGBT module and the second-generation IGBT module, is called a single-sided cooling structure.
  • the 3rd generation IGBT module has a double-sided cooling structure in which Cu thin plates are soldered on both sides of the semiconductor device, and the semiconductor device is insulated by Si 4 N 3 ceramic (hereinafter referred to as “SIN ceramic”). Then, it is joined to the cooler with an insulating resin adhesive (insulating grease).
  • SIN ceramic Si 4 N 3 ceramic
  • an insulating resin adhesive insulating grease
  • the heat radiation path from the semiconductor device used in the 3rd generation IGBT module has a simple structure in which the electrode substrate, the SIN ceramic plate material, and the radiator of the cooler are joined. Bonding of a semiconductor device and a substrate such as an electrode substrate is called die bonding (or die attachment or chip bonding). The material used for die bonding is called a die bond material.
  • the electrode substrate, the SIN ceramic plate material, and the radiator of the cooler are joined with an insulating resin adhesive (insulating grease). Since the heat path composed of these members can be used for both double-sided cooling structure and single-sided cooling structure, it is considered to be widely used in the future as a heat path for IGBT modules.
  • the present inventor has proposed a heat dissipation electrode substrate containing a metal and diamond as main components, in which the thermal resistance of the Cu electrode is reduced (the thermal conductivity is higher than Cu) in order to improve the heat dissipation efficiency in the IGBT module ( Patent Document 1). Further, a high thermal conductive insulating resin composite member used for joining a heat dissipation substrate or an electrode to a cooler is also proposed (Patent Document 2). This high thermal conductive insulating resin composite member has a main layer in which diamond or ceramic is placed in an insulating resin material, and protective bonding layers placed on the front and back surfaces of the main layer. By using this high heat conductive insulating resin composite member in place of the conventional insulating member made of a resin adhesive and ceramic, the thermal resistance can be significantly reduced.
  • the thermal resistance of the heat path in the IGBT module is reduced by using the heat dissipation substrate and the high thermal conductive insulating resin composite member proposed by the present inventors in Patent Documents 1 and 2.
  • the main heat path also includes a die bond for joining a semiconductor device and a substrate (for example, an electrode substrate).
  • the thermal resistance of the die bond material must be reduced in order to further reduce the size and improve the performance of the IGBT module by mounting the semiconductor device whose maximum operating temperature reaches 300°C. Further, reliability during operation of the semiconductor device is also required.
  • the DBA is equipped with a Si semiconductor device with a maximum operating temperature of about 150°C.
  • the coefficient of linear expansion of Si which is the material for semiconductor devices, is 4.5 ppm/K.
  • the linear expansion coefficient of DBA is 7 ppm/K.
  • the reliability of the die bond of the solder thus formed can be ensured by confirming the meniscus state of the solder on the outer periphery and confirming defects such as voids by measuring the inside of the solder with X-rays or ultrasonic waves. , Has been used for a long time.
  • the meniscus state of the solder means a state in which the solder flows to the outer periphery of the joint.
  • the linear expansion coefficient of Cu is 17 ppm/K.
  • the difference in the linear expansion coefficient of the electrodes increases to 12.5 ppm/K, and the die bond breaks.
  • DBC diamond-diene styrene
  • peeling of the Cu electrode and destruction of the ceramic occur at the portion where the thermal stress is concentrated. Therefore, when the maximum operating temperature becomes high, it becomes difficult for the die bond material such as solder to relax the thermal stress generated between them.
  • Sn solder In-vehicle IGBT modules are Pb-free, Sn-based solder (Sn-based solder) such as SnCu (melting point 228°C), SnAg-based (melting point 221°C), SnAgCu-based (melting point 219°C). , SnSb-based (melting point 240 °C) solder is used. Further, those Sn-based solders filled with Ni balls to adjust the thickness of the die bond are also used. However, all of these have melting points below 300°C. Moreover, the thermal conductivity is as low as 60 W/mK or less. Furthermore, the electric conductivity is also extremely low at 25% IACS or less.
  • IACS International Annealed Copper Standard
  • Sn has a melting point of 234° C., a thermal conductivity of 66 ppm/m ⁇ K, and an electrical conductivity of 15% IACS. Therefore, it is difficult to use the Sn-based solder containing Sn as a main component to release heat emitted from a semiconductor device having a maximum operating temperature of 300° C. or to use for joining such a semiconductor device and an electrode.
  • Au solder A solder that uses a eutectic of Au and an additive material, which has higher heat resistance than Sn-based solder, is also used.
  • AuSi solder containing Si as an additive has a melting point of 370° C., but is brittle, and has a low thermal conductivity of 53 W/m ⁇ K and a low electrical conductivity of 22% IACS.
  • the AuGe solder containing Ge as an additive also has a melting point of 356° C., but is brittle, and has a low thermal conductivity of 44 W/m ⁇ K and a low electrical conductivity of 17% IACS.
  • these Au-based solders are expensive and unsuitable for use as a material for joining semiconductor devices having particularly large dimensions.
  • Ag wax material In addition to the above, there is also a method of joining the semiconductor device and the electrode with Ag wax material having high heat resistance.
  • Ag wax has good properties in that it has high thermal conductivity and high electrical conductivity.
  • the melting point of Ag wax material is generally 600° C. or higher, and there is a problem in that when a semiconductor device and an electrode are fusion-bonded using Ag wax material, the semiconductor device is damaged by heat.
  • Non-Patent Document 1 Nano-sized Ag particles (including those generated by reduction of silver oxide) and flake-shaped Ag particles are sintered at a temperature lower than the melting point of the bulk material due to their surface activity. It has been proposed to utilize the low temperature fusion phenomenon of being (low temperature sintered). The sintered body that is sintered by utilizing the low temperature fusion phenomenon of nano Ag does not melt up to the melting point of the bulk material.
  • Non-Patent Document 1 a power semiconductor module using nano Ag as a die bond material is the same as the case of using solder as a die bond material based on the result of a heat cycle test in which cooling to -40°C and heating to 125°C are repeated. It is said that some degree of reliability can be obtained.
  • the secondary particles grown from the nano Ag particles are not sintered, and there are clear grain boundaries and voids of the nanoparticles inside. Therefore, sufficient strength cannot be obtained, and a heat cycle test reaching 300° C. tends to cause deterioration starting from a grain boundary. Therefore, it is difficult to use as a die-bonding material for joining semiconductor devices whose maximum operating temperature reaches 300°C.
  • Non-Patent Document 2 there are problems that it is difficult to thicken the die bond and the bonding strength is unstable.
  • the price of nano Ag powder is 100 times or more that of ordinary powder. This is several times more expensive than Au solder and extremely expensive.
  • Non-Patent Document 2 proposes that an AgSn alloy produced by sintering a mixture of Ag and Sn powders at a load of 5 MPa by utilizing a low temperature fusion phenomenon is used as a die bond.
  • This sintered body contains a large amount of Ag 3 Sn, and voids are reduced.
  • this AgSn alloy has a low thermal conductivity of about 70 W/mK. This is slightly higher than the thermal conductivity of Sn solder (about 60 W/mK).
  • Ag 3 Sn aggregates at the grain boundaries. It is said that this AgSn alloy has a high die shear strength (bonding strength between a semiconductor device and an electrode substrate), but when a heat cycle test is performed, Ag 3 Sn aggregated at grain boundaries causes die bond deterioration.
  • the problem to be solved by the present invention is to provide a semiconductor device bonding member that can be used for bonding a semiconductor device including a semiconductor element whose maximum operating temperature reaches 300° C. and a substrate such as an electrode substrate.
  • the thermal conductivity of the die bond of the semiconductor device whose maximum operating temperature is 150°C (the thermal conductivity of solder is 60 W/mK It is required to have a thermal conductivity more than twice that of the following), that is, a thermal conductivity of 120 W/m ⁇ K or more.
  • the heat resistance temperature of the die bond is preferably 500° C. or higher in order to ensure reliability during operation.
  • the electric conductivity is preferably 50% IACS or more.
  • the linear expansion coefficients of the main materials constituting semiconductor devices are 4.1 ppm/K for Si, 4.5 ppm/K for SiC, and 3.2-5.6 ppm/K for GaN, which are all small.
  • Cu which is a typical electrode material, has a high thermal conductivity of 17 ppm/K. Therefore, the die bond for joining the semiconductor device and the electrode substrate must be capable of relieving a large thermal stress generated during the operation of the semiconductor device due to the difference in linear expansion coefficient between the two.
  • the thickness of the die bond is preferably 0.01 mm or more and 0.3 mm or less.
  • the joining of the semiconductor devices must be performed at a temperature and a load that do not damage the semiconductor devices.
  • Some of the conventional joining examples have been reported to reach a peak temperature of about 450°C during joining.
  • the maximum temperature at the time of bonding is preferably 350°C or lower.
  • the limit value of the pressure applied to the semiconductor device mounted on the IGBT module the maximum value of the pressure that does not cause the destruction of the semiconductor device
  • no specific value has been reported, but it is applied when the semiconductor device is bonded.
  • the pressure applied is preferably less than 5 MPa.
  • low temperature and low load are not always preferable, and it is necessary to determine the temperature and load so that the semiconductor device and the electrode substrate are bonded with sufficient strength.
  • These conditions differ depending on the material to be joined, the joining method, and the joining apparatus, and there are optimum conditions for each, but most of them are know-how, and manufacturers rarely present detailed joining conditions.
  • the low-temperature fusion phenomenon referred to here is that Sn is melted and reacted with Ag at a temperature lower than Ag of the bulk material.
  • a method utilizing this low temperature fusion phenomenon is hereinafter referred to as "low temperature low pressure fusion reaction joining method".
  • the low-temperature low-pressure fusion reaction joining method referred to here is different from the low-temperature fusion phenomenon caused by the surface activity of particles as seen in nano Ag.
  • the melting point of Ag is 961°C
  • the melting point of Sn is 232°C
  • the melting point of Cu is 1083°C. Therefore, the bonding temperature can be lowered by appropriately changing the content ratio of these.
  • the thermal conductivity greatly decreases.
  • heat of Ag 3 Sn alloy of 60Ag40Sn (Ag content: 60 weight percent, Sn content: 40 weight percent) produced by a pressure sintering method. It has a low conductivity of 70 W/mK, which is far from the thermal conductivity of BAg-18 (215 W/mK).
  • the thermal conductivity of 60Ag40Sn produced by the melting method is as low as 83 W/mK.
  • the thermal conductivity of 90Ag10Sn was 310 W/mK, which was extremely high.
  • Samples 1 to 10 in which a die bond having a thickness of 0.2 mm was formed between the SiC semiconductor device and the electrode were prepared by placing the SiC semiconductor device and the electrode under a pressure of 1 MPa or 5 MPa at 300° C. for 10 minutes in a vacuum atmosphere. Then, in order to confirm the suitability of use in the mounted state, each remelting temperature was measured, and subsequently, a heat cycle test was performed to judge the pass/fail. Then, the reliability of Samples 1 to 10 was confirmed from the results of the remelting temperature and the heat cycle test. Table 1 shows the compositions of Samples 1 to 10, the pressurization conditions, the remelting temperature, and the results of the heat cycle test.
  • the present invention obtained from the above study is a semiconductor device joining member for joining a joined surface of a semiconductor device and a joined surface of a substrate on which the semiconductor device is mounted, Ag, Cu, and at least one of Au and Sn as a main component, including a layer made of an alloy having a melting point of 500 °C or more, Inside, having a plurality of voids having a total volume of 5% or more and 40% or less, Characterized by having a thermal conductivity of 120 W/mK or more and an electrical conductivity of 50% IACS or more after 300 heat cycle tests in which cooling to -40°C and heating to 300°C are repeated. ..
  • the semiconductor device joining member according to the present invention is a member arranged between the joining surfaces of the semiconductor device and the substrate in order to join the joining surfaces.
  • the semiconductor device bonding member according to the present invention contains at least one kind of Ag, Cu, and Au and Sn as a main component, and includes a layer made of an alloy having a melting point of 500° C. or higher, and therefore, the It has sufficient heat resistance as a material for bonding semiconductor devices whose temperature is 300°C or higher.
  • the semiconductor device bonding member according to the present invention has a plurality of voids having a total volume of 5% or more and 40% or less of the whole inside thereof, and these voids allow deformation of the semiconductor device bonding member.
  • the thermal stress caused by the difference in linear expansion coefficient between the semiconductor device and the substrate such as the electrode substrate is relaxed.
  • the effect of relieving the thermal stress largely depends on the amount of voids. If the proportion of voids is less than 5 volume percent, the effect of relaxing the thermal stress is not sufficient, and if it exceeds 40 volume percent, the material itself tends to break.
  • the shape and number of voids may be appropriately determined according to the use environment and manufacturing process of the object to be joined, but the guideline for the size of one void is, for example, when the voids are approximated to spheres of the same volume.
  • the diameter is 0.005 mm or more and 3 mm or less. If it is smaller than 0.005 mm, it is difficult to obtain the effect of relieving stress. If it is larger than 3 mm, the thermal resistance tends to increase at the position of the void.
  • the size of one void is more preferably 0.2 mm or more and 2 mm or less.
  • the size and distribution of the voids only need to satisfy the above requirement that the total volume of the plurality of voids be 5% or more and 40% or less of the whole, and need not necessarily be uniform over the entire semiconductor device bonding member. Absent. For example, it may have a layer having a high porosity at the center of the member and a layer having a low porosity (or almost no voids) on its front and back surfaces. Conversely, it may have a layer having a low porosity (or almost no voids) in the center of the member and a layer having a high porosity on the front and back surfaces thereof. Alternatively, the front and back surfaces may have different porosities.
  • the thermal conductivity is 120 W/mK or more, and the electrical conductivity is 50% IACS or more, The heat generated during the operation of the semiconductor device can be efficiently released, and excessive Joule heat is not generated in the semiconductor device joining member. Since the semiconductor device bonding member according to the present invention has these characteristics, it can be used for bonding a semiconductor device whose maximum temperature during operation reaches 300° C. and a substrate on which the semiconductor device is mounted.
  • the content of Sn in the layer made of the above alloy is 2% by weight or more and 20% by weight or less.
  • Non-Patent Document 2 an AgSn alloy containing a large amount of Ag 3 Sn (for example, occupying 50% by volume of the whole) is produced, whereas in the semiconductor device bonding member according to the present invention, Ag contained in the layer made of the alloy is Ag.
  • the ratio of 3 Sn is 10 volume% or less. More preferably, the proportion of Ag 3 Sn is 5 volume% or less, and even more preferably 3 volume% or less.
  • the presence of eutectic at grain boundaries is likely to be the origin of cracks. By setting the Sn content in the above range, it becomes difficult for eutectic to exist at the grain boundaries. Thereby, generation of cracks can be suppressed and durability can be improved.
  • the semiconductor device bonding member according to the present invention it is possible to bond a semiconductor device having a maximum operating temperature of 300° C. and an electrode substrate or the like on which the semiconductor device is mounted. Moreover, in the semiconductor device bonding member according to the present invention, expensive nano Ag is not necessarily used. Furthermore, the technology and equipment cultivated up to now for soldering can be used.
  • voids In solder, when 5% or more of voids (voids) are present, the voids become the starting point in the heat cycle test, and cracks are chained and broken in the low-strength, brittle eutectic alloy existing in the grain boundaries. .. Further, in the AgSn alloy containing a large amount of Ag 3 Sn as described in Non-Patent Document 2, the void ratio is small, but in the heat cycle test, the void is the starting point, and Ag 3 Sn with low strength existing at the grain boundary is present. Cracks are chained to break the part of the eutectic alloy.
  • the primary particles are sintered at a temperature lower than the melting point of Ag of the bulk material, but the secondary particles formed by sintering do not sinter unless the temperature is 400° C. or higher, so a grain boundary is formed, A void occurs there.
  • the voids become the starting points in the heat cycle test, and the cracks of the secondary particles having low strength are chained and destroyed.
  • fracture due to cracking of Ag 3 Sn eutectic alloy and secondary particles occurs even in the absence of voids.
  • a semiconductor device or an electrode substrate is joined by a low-temperature low-pressure melting reaction joining method using Ag and Sn, and high heat conductivity and heat resistance are secured by Ag, AgSn alloy, etc. Then, the thermal stress is relaxed by the voids, and the spread of cracks originating from the voids is suppressed by using Ag, AgSn alloy or the like.
  • the present invention is based on the idea opposite to the conventional material development of eliminating defects such as voids, so that the voids do not become the origin of defects by surrounding the voids with a highly heat-resistant and strong material. By doing so, the voids are used for relaxing the thermal stress.
  • the semiconductor device joining member according to the present invention is as described above, but its technical idea can be generalized. Specifically, the technical idea of the present invention is to provide a semiconductor device joining member for joining a joined surface of a semiconductor device and a joined surface of a substrate on which the semiconductor device is mounted, An alloy containing a first metal and a second metal having a melting point lower than that of the first metal as main components, a content of the second metal of 2% by weight or more and 20% by weight or less, and a melting point of 500° C. or more.
  • the thermal conductivity is 120W/mK or more and the electrical conductivity is 50%IACS or more after the heat cycle test in which cooling to -40°C and heating to 300°C are repeated 300 times.
  • the semiconductor device bonding member 10 of this embodiment is a so-called die bond, and is used for bonding the semiconductor device 11 to a substrate such as the electrode substrate 12 as schematically shown in FIG.
  • the semiconductor device bonding member 10 of the present embodiment is one in which voids (voids) 102 are provided at a predetermined ratio inside a skeleton 101 made of an alloy or the like. Note that, in FIG. 1, the structure of the semiconductor device bonding member 10 in the case of being manufactured by introducing the second metal into the through hole provided in the plate material of the first metal, that is, an example in which the voids 102 are arranged in the vertical direction of the drawing.
  • the voids 102 may be randomly located inside the skeleton 101.
  • the size and shape of the voids need not be constant.
  • the voids (voids) 102 do not necessarily have to be evenly distributed over the entire semiconductor device bonding member 10. For example, if there is a place where stress tends to increase during operation, many voids are concentrated in that place. It may be arranged in a desired manner. Further, it may be a stack of a layer containing many voids and a layer containing few voids (or few voids).
  • the above-mentioned low-temperature low-pressure melting reaction joining method can be preferably used for producing the alloy forming the skeleton 101 of the semiconductor device joining member 10.
  • a powder method or a skeleton method can be used.
  • an appropriate method can be used as long as a semiconductor device bonding member satisfying the requirements of the claims can be manufactured.
  • the first metal is, for example, one or more of Ag, Cu, Au, and alloys thereof.
  • a metal having a high melting point, a high thermal conductivity, and a high electrical conductivity is used as the first metal.
  • a metal in which an intermetallic compound is less likely to be formed by a reaction with a second metal (Sn or the like) is used.
  • Ag can be preferably used as the first metal.
  • Cu the amount of Ag used can be reduced and a semiconductor device bonding member can be manufactured at low cost. It is also possible to use Au, or an alloy of Ag, Cu, and Au.
  • the second metal melts and reacts with the first metal to alloy at low temperatures. Sn can be preferably used for the second metal.
  • the ratio of the second metal is preferably in the range of 2% by weight or more and 20% by weight or less of the semiconductor device joining member to be obtained, although it varies depending on the temperature and pressure applied during the production of the semiconductor device joining member. As a result, no problem occurs in the heat cycle test, and the required characteristics can be obtained.
  • the first metal is Ag and the second metal is Sn
  • the Sn content reacted with Ag is reduced to 20% by weight or less
  • the formation of a eutectic substance composed of Ag 3 Sn is suppressed.
  • the presence of eutectic at grain boundaries is likely to cause cracking.
  • the Sn content is less than 2% by weight, it is difficult to disperse the Sn uniformly, so that the temperature at the time of joining with a semiconductor device or the like tends to vary.
  • the junction temperature may exceed 450° C. (the temperature at which the semiconductor device may be destroyed) at the position where Sn does not exist.
  • one or more of Cu, Ag, Pb, Cd, Zn, Sb, Ni, Mn, Ti, In, Mo, Si, V, Ge and Li are added metals. May be further included.
  • One of the members to be joined is a semiconductor device, and the other is a substrate (for example, an electrode substrate) on which the semiconductor device is mounted.
  • a metal layer made of Ni, Pt, Co or the like is provided on the joint surface.
  • An IGBT module often has a Ni layer with a thickness of about 2 ⁇ m.
  • a metal layer made of Ti, W, Co or the like may be provided on the bonding surface of the electrode substrate or the heat dissipation substrate.
  • a metal layer made of Ni, Pt, Co or the like may be provided in order to prevent reaction with the Ag brazing material.
  • electrolytic Ni plating which is a Ni-based plating, electroless Ni-P, Ni-B, or the like is used.
  • one or more plating layers of Ag, Au, Cu, Zn, etc. may be provided on each of the above layers.
  • electrodes made of thin Ni-based metal may be placed on the front and back surfaces of the semiconductor device, and in that case, such electrodes are called a semiconductor device.
  • a layer made of Au, Ag, Cu, a metal such as Sn, or an alloy thereof may be provided, and in that case, a semiconductor device including this layer is also included. be called. That is, it can be construed as a semiconductor device in a broad sense, including a layer integrally formed with the semiconductor device before being bonded to the electrode substrate.
  • a protruding auxiliary electrode may be provided on the surface to be joined of the electrode substrate.
  • Such an auxiliary electrode is attached to a flat plate such as Cu by a brazing material or a die bonding material.
  • Such an auxiliary electrode may also be provided with a Ni-based plating layer for improving the bondability with a semiconductor device, or a layer made of a metal such as Au, Ag, Cu, Sn, or an alloy thereof. In that case, including these layers, it is called an electrode substrate. That is, it can be interpreted as an electrode substrate in a broad sense, including a layer integrally formed with the electrode substrate before being bonded to the semiconductor device.
  • the Ag layer formed on the surface to be joined of the semiconductor device to enhance the joining property is a part of the semiconductor device, and the layer formed by alloying Ag and Sn contained in the Ag layer is the semiconductor device joining. It can be interpreted as being part of a member.
  • the metal disposed on the surface layer of DBC or DBA is a part of the electrode substrate, and the layer formed by alloying the metal and Sn can be interpreted as a part of the semiconductor device bonding member. it can.
  • One of the methods for producing the semiconductor device joining member 10 is a powder method. This is a method in which a mixture of Ag and Sn powders or a powder obtained by Sn-plating Ag particles is sintered and bonded to a member to be bonded (semiconductor device or electrode substrate).
  • the other is the skeleton method. This has a void by making a plate material made of AgSn alloy with less Ag or Ag 3 Sn in a sintered body, or by subjecting the plate material to laser processing, drill processing, etching processing, punching processing, reticulation processing, etc.
  • the skeleton is made in advance, and the skeleton is made to react with Ag by impregnating the skeleton with molten Sn or the like, and is joined to a member to be joined (semiconductor device or electrode substrate). Further, the powder method and the skeleton method may be appropriately combined. In addition, for the reaction between the first metal and the second metal, a suitable method such as a sintering method, an impregnation method, or a partial reaction joining method may be used.
  • the powder method it is possible to use, for example, particles with a particle size in the range of 10 nm to 0.3 mm.
  • the powder used may have a uniform size, or may be a mixed powder having different particle sizes.
  • the skeleton may be produced by an appropriate method such as a sintering method. Although details of the manufacturing method will be described later, for example, a skeleton containing voids can be manufactured by heating and sintering at 750° C. or higher in vacuum, hydrogen+nitrogen, and hydrogen atmosphere.
  • a plate-shaped product When using a plate-shaped product, it is possible to use, for example, a product having a thickness of 0.02 to 0.3 mm.
  • a plate-shaped member When a plate-shaped member is used, holes having a size and number corresponding to the void ratio to be formed inside the semiconductor device bonding member to be obtained are formed.
  • the low temperature and low pressure conditions are not always optimal for joining semiconductor devices and the like by die bonding. It is necessary to secure the performance and quality suitable for the composition of the die bond and the target semiconductor module.
  • the pressure sintering infiltration method uses a mixed powder of Ag, Sn, etc., or an Ag plate with holes formed in advance, and melts Sn and alloys while pressurizing, while joining the semiconductor device and the cooler. is there.
  • the melting reaction method the semiconductor devices and electrode substrates are joined while melting and alloying Sn arranged above and below the skeleton of Ag, and the target can be achieved with a low pressure.
  • the Ag plate Sn reaction method is a semiconductor device in which one or more Ag plates or Ag nets having holes are arranged on top and bottom of a layered one, and the Sn is melted and reacted with Ag to form an alloy. And an electrode substrate. This gives the highest strength AgSn alloy. Further, the target can be achieved with a low pressure.
  • one or more plating layers made of Ag or/and Sn may be provided on the surface of the prepared alloy.
  • a layer made of an alloy is formed on the front surface and the back surface of the semiconductor device bonding member, and a layer having a high porosity made of only Ag can be formed in the central portion sandwiched between them.
  • Each of the above methods can be used as the above-mentioned low temperature low pressure fusion reaction joining method.
  • a plate material of the second metal is arranged above and below the skeleton, or the surface of the skeleton is plated with a second metal.
  • the second metal can be arranged.
  • the powdery first metal is used, the powder of the first metal and the powder of the second metal may be mixed and sintered to produce a skeleton of the mixed powder.
  • the second metal and the first metal can be effectively impregnated with Sn. In this case, the entire semiconductor device bonding member is likely to be alloyed.
  • the second metal may be plated on the bonding surface of the semiconductor device and/or the bonding surface of the substrate (electrode substrate or the like), and they may be arranged above and below the skeleton. Even if one or a plurality of plating layers made of Ni, Ag, Ti or the like are formed on the bonding surface of the semiconductor device and/or the bonding surface of the substrate before the second metal is plated on the bonding surface. Good. In particular, by forming the Ni plating layer, the bondability with the AgSn alloy can be improved.
  • the first metal When the dissolved second metal enters the hole of the first metal, the first metal gradually dissolves from the surface of the hole, and the second metal is impregnated inside the skeleton of the first metal. Similarly, on the surface of the skeleton, the first metal gradually dissolves and is impregnated with the second metal.
  • pressure may be applied. On the other hand, if excessive pressure is applied, the semiconductor element may be damaged, so the applied pressure is preferably less than 5 MPa, more preferably 0.5 to 4.0 MPa.
  • the second metal melted by the impregnation reacts with the first metal forming the skeleton to be alloyed, whereby the semiconductor device and the electrode substrate are die-bonded with high strength. Also, when the mixed powder of the first metal and the second metal is used, the second metal is melted to be alloyed, whereby the semiconductor device and the electrode substrate are die-bonded with high strength.
  • the melting point of the alloy layer included in the semiconductor device joining member is 500° C. or higher because heat may be locally generated during the operation of the semiconductor device. Also, in the case of AgSn alloy, brittle Ag 3 Sn particles agglomerate at grain boundaries in alloys with a melting point of 500°C or lower, causing damage such as cracks and chips in the heat cycle test, and lowering properties such as thermal conductivity.
  • Die bonding can be performed in a vacuum atmosphere, non-oxidizing atmosphere, nitrogen atmosphere, hydrogen atmosphere, hydrogen nitrogen atmosphere.
  • the melting point of Sn is 235° C.
  • the re-melting point of AgSn alloy becomes 500° C. or higher by reacting with Ag to form an alloy.
  • the thermal conductivity of the semiconductor device bonding member (die bond) included in the test piece was obtained by comparing the thermal conductivity of the test piece with the thermal conductivity of the SiC comparative piece and the Cu comparative piece.
  • a thermal conductivity of 120 W/m ⁇ K was used as a standard, and one having a thermal conductivity of more than this was regarded as a pass.
  • a laser processing machine is used to cut out a test piece with a diameter of 10 mm and a thickness of 2.0 mm, and the electrical conductivity is measured by the four-terminal method using an electrical conductivity measuring device (RT70V manufactured by Napson Corporation). did. Separately from this test piece, a W comparison piece (having a Ni plating layer on one side) and a Cu comparison piece (having a Ni plating layer on one side) having a diameter of 10 mm and a thickness of 2.0 mm were prepared. The electrical conductivity was measured in the same manner as above. Then, the electrical conductivity of the test piece was determined by comparing the electrical conductivity of the test piece with the electrical conductivity of the W comparative piece and the Cu comparative piece.
  • Example 1 The value of each parameter is the value related to Example 2.
  • Examples 1 and 3 to 15 were produced by appropriately changing the parameter values as shown in Table 2 below.
  • Step 1 A 12 mm square Ag plate material having a thickness of 0.2 mm and one through hole having a diameter of 0.36 mm per 1 mm square was formed by laser processing (hereinafter referred to as a skeleton).
  • Process 2 A 30 ⁇ m square, 1.5 mm thick Cu plate material was provided with a 2 ⁇ m thick Ni plating layer on one surface (joint surface), and a 12 mm square, 0.009 mm thick Sn plating layer was provided in the center thereof. The thing (henceforth this is called an electrode substrate) was produced.
  • Process 3 12 mm square, a 2 ⁇ m-thick Ni plating layer is provided on one surface (bonding surface) of the SiC plate material, and a 0.009 mm-thick Sn plating layer is further provided thereon (hereinafter referred to as a semiconductor device. Called a plate).
  • Step 4 A laminated body was produced in which the electrode substrate, the skeleton, and the semiconductor device plate were sequentially stacked.
  • Step 5 The laminate was heated to 300° C. in a vacuum atmosphere, kept at 300° C., a pressure of 1 MPa was applied, kept for 5 minutes and gradually cooled.
  • Step 6 A heat resistance test, a heat cycle test, a measurement of thermal conductivity, and a measurement of electrical conductivity were performed on the semiconductor device plate and the electrode substrate joined by the above treatment.
  • Example 1 the void ratio is 5 vol% and the Sn content is 3.7 wt% (5 vol%).
  • the weight is 1.888 ⁇ g (Ag density: 10.49g/cm -3 ).
  • the total volume of Ag and Sn is 0.19 mm 3 , and the total weight is 1.961 ⁇ g.
  • a 10% void is formed on a plate material with a 1 mm square and a thickness of 0.2 mm. It can be seen that it is sufficient to form a 0.005 mm thick Sn layer. If the voids formed in the plate material are approximated to cylindrical through holes, it is understood that one through hole having a diameter of 0.36 mm should be provided for each 1 mm square.
  • the skeleton of Example 9 (AgCu described in Table 2) is an alloy containing 30% by weight of Ag and 70% of Cu.
  • the ratio of the voids is determined in advance, and the size of the material to be used and the size of the through-hole to be formed in advance are determined.
  • the voids (voids) of the semiconductor device bonding member after creation are determined. The ratio of can be evaluated by various measurements.
  • the cross section of the semiconductor device bonding member is photographed by an electron microscope or the like, and the ratio of the voids included in the semiconductor device bonding member is evaluated by using the ratio of the voids appearing in the cross section as a representative value.
  • the ratio of voids included in the semiconductor device bonding member can be evaluated from the theoretical density of the non-alloy and the density of the manufactured semiconductor device bonding member.
  • Table 2 shows the produced Examples 1 to 15 and their evaluation results, and the Comparative Examples 1 to 9 produced for comparison and their evaluation results.
  • Comparative Example 1 the semiconductor device and the electrode substrate could not be joined, and in Comparative Example 6, the powder was not sintered, so that neither test piece could be produced.
  • Comparative Examples 2 to 5 and 7 to 9 test pieces could be produced, but when the temperature was raised to 500° C., melting was observed in the joint portion, and therefore the heat cycle test was not performed.
  • the thermal conductivity after the heat cycle test was 120 W/m ⁇ K or more, and the electrical conductivity was 50%. More than IACS.
  • the semiconductor device bonding member of each of the above-described embodiments satisfies the requirements required when bonding a semiconductor device having a maximum operating temperature of 300° C. to a substrate.
  • voids inside semiconductor device bonding members have been considered to be defects, and void-free materials have been developed, but the present invention has found that voids are effective in alleviating thermal stress. ..
  • this semiconductor device joining member can be suitably used when a semiconductor device is joined to an electrode substrate to conduct electricity in a vertical conduction type IGBT which is a power semiconductor module. Further, it can be suitably used also for bonding a semiconductor device to a heat dissipation board (non-energized) in a module in the other plane conduction type semiconductor fields (communication, arithmetic, memory, laser, LED, sensor, etc.). .. Further, not only the SiC semiconductor device but also the IGBT module having a semiconductor device such as Si, GaN or GaAs mounted thereon can be suitably used.
  • the semiconductor device bonding member according to the present invention can be preferably used.
  • INDUSTRIAL APPLICABILITY The semiconductor device joining member according to the present invention can greatly contribute to future miniaturization and high performance of semiconductor modules and cost reduction. Further, energy saving can be realized by using the above semiconductor module in an electric vehicle or an industrial machine. In the specification of the present application, the semiconductor module has been mainly described.
  • a semiconductor package (a terminal that serves as a contact for wrapping a semiconductor element or an integrated circuit with resin or the like to protect it from the surroundings and inputting and outputting electric power and electric signals)
  • the semiconductor device joining member according to the present invention can be preferably used for a packaging member provided with or wiring.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Die Bonding (AREA)

Abstract

L'élément de jonction de dispositif à semi-conducteur 10 selon l'invention est utilisé pour joindre une surface à joindre d'un dispositif à semi-conducteur 11 et une surface à joindre d'un substrat 12 sur lequel ledit dispositif à semi-conducteur 11 doit être placé, lequel élément de jonction comprend une couche comprenant un alliage 102 qui contient, en tant que composants principaux, Sn et au moins un élément choisi parmi Ag, Cu et Au, et a un point de fusion d'au moins 500 °C. L'intérieur dudit élément de jonction a une pluralité de vides 101, dont le volume représente 5 à 40 % du volume total de l'élément de jonction. L'élément de jonction est conçu pour avoir une conductivité thermique d'au moins 120 W/m·K et une conductivité électrique d'au moins 50 % IACS après avoir subi un test de cycle thermique dans lequel un cycle de refroidissement à -40 °C et de chauffage à 300 °C est répété 300 fois.
PCT/JP2019/049601 2018-12-18 2019-12-18 Élément de jonction de dispositif à semi-conducteur WO2020130039A1 (fr)

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JP6803106B1 (ja) * 2020-09-18 2020-12-23 株式会社半導体熱研究所 半導体デバイスの接合部材

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011114751A1 (fr) * 2010-03-19 2011-09-22 古河電気工業株式会社 Élément de connexion conducteur et son procédé de fabrication
WO2012077228A1 (fr) * 2010-12-10 2012-06-14 三菱電機株式会社 Alliage de soudure sans plomb, dispositif semi-conducteur et méthode de fabrication d'un dispositif semi-conducteur
JP2017157582A (ja) * 2016-02-29 2017-09-07 株式会社東芝 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011114751A1 (fr) * 2010-03-19 2011-09-22 古河電気工業株式会社 Élément de connexion conducteur et son procédé de fabrication
WO2012077228A1 (fr) * 2010-12-10 2012-06-14 三菱電機株式会社 Alliage de soudure sans plomb, dispositif semi-conducteur et méthode de fabrication d'un dispositif semi-conducteur
JP2017157582A (ja) * 2016-02-29 2017-09-07 株式会社東芝 半導体装置

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