WO2020127442A3 - Module semiconducteur comportant un semiconducteur et un boîtier renfermant partiellement le semiconducteur - Google Patents

Module semiconducteur comportant un semiconducteur et un boîtier renfermant partiellement le semiconducteur Download PDF

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Publication number
WO2020127442A3
WO2020127442A3 PCT/EP2019/085883 EP2019085883W WO2020127442A3 WO 2020127442 A3 WO2020127442 A3 WO 2020127442A3 EP 2019085883 W EP2019085883 W EP 2019085883W WO 2020127442 A3 WO2020127442 A3 WO 2020127442A3
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WO
WIPO (PCT)
Prior art keywords
semiconductor
housing
manufacturing
same
intermediate product
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Application number
PCT/EP2019/085883
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English (en)
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WO2020127442A2 (fr
Inventor
Martin Becker
Jacek Rudzki
Ronald Eisele
Frank Osterwald
André Bastos Abibe
Original Assignee
Danfoss Silicon Power Gmbh
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Publication date
Application filed by Danfoss Silicon Power Gmbh filed Critical Danfoss Silicon Power Gmbh
Publication of WO2020127442A2 publication Critical patent/WO2020127442A2/fr
Publication of WO2020127442A3 publication Critical patent/WO2020127442A3/fr

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • HELECTRICITY
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
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    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
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    • H01L2224/061Disposition
    • H01L2224/0618Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181On opposite sides of the body
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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    • H01L2224/838Bonding techniques
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    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/1033Gallium nitride [GaN]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

Un module semiconducteur comportant un semiconducteur et un boîtier renfermant le semiconducteur est caractérisé en ce que le boîtier est constitué d'un matériau électroconducteur et présente un évidement occupé par le semiconducteur, le côté du semiconducteur opposé à l'évidement étant coplanaire avec la surface du boîtier ayant l'évidement.
PCT/EP2019/085883 2018-12-20 2019-12-18 Module semiconducteur comportant un semiconducteur et un boîtier renfermant partiellement le semiconducteur WO2020127442A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102018133089.8A DE102018133089A1 (de) 2018-12-20 2018-12-20 Halbleitermodul mit einem Halbleiter und einem den Halbleiter teilweise einhausenden Gehäuse
DE102018133089.8 2018-12-20

Publications (2)

Publication Number Publication Date
WO2020127442A2 WO2020127442A2 (fr) 2020-06-25
WO2020127442A3 true WO2020127442A3 (fr) 2020-07-30

Family

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Application Number Title Priority Date Filing Date
PCT/EP2019/085883 WO2020127442A2 (fr) 2018-12-20 2019-12-18 Module semiconducteur comportant un semiconducteur et un boîtier renfermant partiellement le semiconducteur

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DE (1) DE102018133089A1 (fr)
WO (1) WO2020127442A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11842953B2 (en) 2021-04-28 2023-12-12 Infineon Technologies Ag Semiconductor package with wire bond joints and related methods of manufacturing

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0513410A1 (fr) * 1991-05-15 1992-11-19 IXYS Semiconductor GmbH Module semi-conducteur de puissance et procédé de fabrication d'un tel module
US20070012947A1 (en) * 2002-07-15 2007-01-18 International Rectifier Corporation Direct FET device for high frequency application
US20170338190A1 (en) * 2015-02-25 2017-11-23 Mitsubishi Electric Corporation Power module

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7235877B2 (en) * 2004-09-23 2007-06-26 International Rectifier Corporation Redistributed solder pads using etched lead frame
JP6248803B2 (ja) * 2014-05-20 2017-12-20 富士電機株式会社 パワー半導体モジュール

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0513410A1 (fr) * 1991-05-15 1992-11-19 IXYS Semiconductor GmbH Module semi-conducteur de puissance et procédé de fabrication d'un tel module
US20070012947A1 (en) * 2002-07-15 2007-01-18 International Rectifier Corporation Direct FET device for high frequency application
US20170338190A1 (en) * 2015-02-25 2017-11-23 Mitsubishi Electric Corporation Power module

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Publication number Publication date
DE102018133089A1 (de) 2020-06-25
WO2020127442A2 (fr) 2020-06-25

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