WO2020125408A1 - 数据的传输方法及装置 - Google Patents

数据的传输方法及装置 Download PDF

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Publication number
WO2020125408A1
WO2020125408A1 PCT/CN2019/122791 CN2019122791W WO2020125408A1 WO 2020125408 A1 WO2020125408 A1 WO 2020125408A1 CN 2019122791 W CN2019122791 W CN 2019122791W WO 2020125408 A1 WO2020125408 A1 WO 2020125408A1
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Prior art keywords
clock signal
data
signal
data transmission
clock
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PCT/CN2019/122791
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English (en)
French (fr)
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王明良
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惠科股份有限公司
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Publication of WO2020125408A1 publication Critical patent/WO2020125408A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • This application relates to the field of communication technology, and in particular, to a data transmission method and device.
  • differential signals With the increasing size and resolution of LCD TVs, and the need to transmit more and more data, differential signals have become popular as a high-speed transmission protocol.
  • the data signal (Data) is accompanied by a clock signal, and the data signal is relatively stable when the clock signal rises or falls. At this time, the receiving end obtains the target data in the data signal.
  • the main purpose of the present application is to provide a data transmission method and device, aiming to avoid erroneous data capture.
  • the data transmission method includes the following steps:
  • the step of increasing the output amplitude of the clock signal includes:
  • the target amplitude is determined according to the initial amplitude, and the output amplitude of the clock signal is increased to the target amplitude.
  • the step of increasing the output amplitude of the clock signal includes:
  • the sending end of the clock signal receives a signal whose amplitude is too low, and increases the output amplitude of the clock signal.
  • the sending end of the clock signal includes at least a timing driving chip.
  • the value of the preset threshold is 0-0.3V.
  • the method further includes:
  • the current time point is used as the starting time point to obtain the potential of the clock signal in the time interval in real time.
  • the method further includes:
  • the step of acquiring the clock period of the clock signal includes:
  • the zero-volt time point of the clock signal is obtained, and the clock period of the clock signal is obtained according to the time interval between two adjacent zero-volt time points.
  • the method further includes:
  • the step of acquiring data of the data signal according to the clock signal after the output amplitude increases includes:
  • the present application also provides a data transmission method, wherein the data transmission method includes the following steps:
  • the step of increasing the output amplitude of the clock signal to a preset amplitude includes:
  • the sending end of the clock signal receives a signal whose amplitude is too low, and increases the output amplitude of the clock signal.
  • the sending end of the clock signal includes at least a timing driving chip.
  • the step of acquiring the potential of the clock signal in half of the clock period in real time includes:
  • the potential of the clock signal in the second half of the clock period of the zero-volt time point is obtained in real time.
  • the present application also provides a data transmission device, wherein the data transmission device includes: a memory, a processor, and data stored on the memory and operable on the processor
  • the data transmission program when the data transmission program is executed by the processor, the steps of the data transmission method described above are implemented.
  • the step of increasing the output amplitude of the clock signal includes:
  • the target amplitude is determined according to the initial amplitude, and the output amplitude of the clock signal is increased to the target amplitude.
  • the method further includes:
  • the current time point is used as the starting time point to obtain the potential of the clock signal in the time interval in real time.
  • the method further includes:
  • the step of acquiring data of the data signal according to the clock signal after the output amplitude increases includes:
  • the zero-volt time point of the clock signal is obtained, and the clock period of the clock signal is obtained according to the time interval between two adjacent zero-volt time points.
  • a data transmission method and device proposed in the embodiments of the present application start acquiring clock signals corresponding to data signals when it is detected that data transmission exists. And determine the potential of the clock signal within a time interval, where the time interval is less than or equal to half a clock cycle. When it is detected that the potential in the clock signal within the time interval is less than the preset threshold, a signal with a too low amplitude is fed back to the sending end of the clock signal (for example, a timing driving chip), so that the sending end of the clock signal increases the clock The output amplitude of the signal.
  • the sending end of the clock signal for example, a timing driving chip
  • the clock signal After the output amplitude of the clock signal is increased, the clock signal conforms to the new output amplitude, and the potential corresponding to the time point when the potential is lower than the preset threshold is increased, so that no rising or falling edge will occur near this time point , Effectively avoiding the wrong data capture.
  • FIG. 1 is a schematic diagram of a terminal structure of a hardware operating environment according to an embodiment of the present application
  • FIG. 2 is a schematic flowchart of an embodiment of a data transmission method of this application.
  • FIG. 3 is a schematic waveform diagram of the data transmission method of this application.
  • FIG. 4 is another waveform diagram of the data transmission method of this application.
  • FIG. 5 is a schematic flowchart of another embodiment of a data transmission method of this application.
  • FIG. 6 is a schematic flowchart of still another embodiment of a data transmission method of this application.
  • the actual generated clock signal is uneven.
  • the receiving end is likely to mistake the fluctuation near the uneven wave as a rising or falling edge, and according to the rising The transmission data is acquired along the edge or the falling edge, resulting in a data acquisition error.
  • the present application provides a solution for starting to obtain a clock signal corresponding to a data signal when it detects the presence of data transmission. And determine the potential of the clock signal within a time interval, where the time interval is less than or equal to half a clock cycle. When it is detected that the potential in the clock signal within the time interval is less than the preset threshold, a signal with a too low amplitude is fed back to the sending end of the clock signal (for example, a timing driving chip), so that the sending end of the clock signal increases the clock The output amplitude of the signal.
  • the clock signal After the output amplitude of the clock signal is increased, the clock signal conforms to the new output amplitude, and the potential corresponding to the time point when the potential is lower than the preset threshold is increased, so that no rising or falling edge will occur near this time point , Effectively avoiding the wrong data capture.
  • FIG. 1 is a schematic diagram of a terminal structure of a hardware operating environment involved in a solution of an embodiment of the present application.
  • the terminal may be a data signal data extraction device, a television, or a computer.
  • the terminal may include: a processor 1001, such as a CPU, a memory 1002, a communication bus 1003, and a data driver (Data Driver) 1004, sequential drive chip (TCON IC) 1005.
  • the communication bus 1003 is configured to implement connection communication between the components in the terminal.
  • the memory 1002 may be a high-speed random access memory or a stable memory (non-volatile memory), such as disk storage.
  • the memory 1002 may optionally be a storage device independent of the foregoing processor 1001.
  • the data driver 1004 performs data signal processing, and may include at least one of a frequency judgment unit, a potential judgment unit, and an internal processing module.
  • the timing driving chip 1005 is used to generate and transmit data signals and clock signals.
  • FIG. 1 does not constitute a limitation on the terminal in the embodiments of the present application, and may include more or fewer components than those illustrated, or a combination of certain components, or different components. Layout.
  • the memory 1002 as a computer storage medium may include a data transmission program.
  • the processor 1001 may be used to call a data transmission program stored in the memory 1002, and perform the following operations:
  • processor 1001 can call the data transmission program stored in the memory 1002, and also perform the following operations:
  • the target amplitude is determined according to the initial amplitude, and the output amplitude of the clock signal is increased to the target amplitude.
  • processor 1001 can call the data transmission program stored in the memory 1002, and also perform the following operations:
  • the current time point is used as the starting time point to obtain the potential of the clock signal in the time interval in real time.
  • processor 1001 can call the data transmission program stored in the memory 1002, and also perform the following operations:
  • processor 1001 can call the data transmission program stored in the memory 1002, and also perform the following operations:
  • the zero-volt time point of the clock signal is obtained, and the clock period of the clock signal is obtained according to the time interval between two adjacent zero-volt time points.
  • processor 1001 can call the data transmission program stored in the memory 1002, and also perform the following operations:
  • processor 1001 can call the data transmission program stored in the memory 1002, and also perform the following operations:
  • processor 1001 can call the data transmission program stored in the memory 1002, and also perform the following operations:
  • processor 1001 can call the data transmission program stored in the memory 1002, and also perform the following operations:
  • the potential of the clock signal in the second half of the clock period of the zero-volt time point is obtained in real time.
  • the data transmission method includes:
  • Step S10 When a data signal is detected, obtain a clock signal corresponding to the data signal.
  • Step S20 acquiring the potential of the clock signal in real time within a time interval, where the time interval is less than or equal to half a clock cycle of the clock signal.
  • the upper part of the figure is the waveform of the data signal, and the lower part is the waveform generated by the clock signal.
  • the shape of the clock signal changes.
  • a concave point A and a corresponding convex point B When the potential of point A is less than a certain value, it is easy to identify the point when the signal is recognized. The potential of is regarded as a negative value.
  • a rising edge is formed on the right side of point A, and then the data in the data signal is captured according to the generated rising edge, and an abnormal capture phenomenon occurs, resulting in a data capture error.
  • a falling edge is formed on the right side of point B, and the falling edge is used to capture the data in the data signal, resulting in an incorrect data capture.
  • the present application provides a data transmission method.
  • it When it is detected that there is data transmission, it starts to obtain a clock signal corresponding to the data signal. And determine the potential of the clock signal in the time interval, where the potential direction of the clock signal in the half clock cycle is the same, so the clock cycle is half a clock cycle, so the time interval is half a clock cycle a period of time.
  • the data drive Data Driver
  • the real-time detection of the potential of the clock signal within the time interval is started.
  • the potential of the clock signal in the ⁇ t time interval is detected. It is easy to understand that during the half period of the clock signal, the clock signal rises with an output amplitude potential and then decreases to a sinusoidal shape. There is a time point where the potential is small during the beginning of the rise and the end of the decline. , May be lower than the preset threshold.
  • the time interval for acquiring the clock signal potential in real time is a partial time period within a half cycle, that is, a period after the start of the half cycle and a period before the end of the half cycle.
  • Step S30 When the acquired potential is lower than a preset threshold, increase the output amplitude of the clock signal.
  • the signal whose amplitude is too low is fed back to the sender of the clock signal (for example, a timing driver chip) for the sender of the clock signal to increase The output amplitude of the large clock signal.
  • the preset threshold is a critical value for signal judgment, usually 0-0.3V.
  • the data signal is transmitted in a sinusoidal waveform.
  • the positive and negative of the potential at each time point in the signal wave are relative.
  • the above can be regarded as an example for the previous half cycle.
  • the judgment direction is opposite, that is, when the potential is higher than the preset threshold, the output amplitude of the clock signal is increased, and the preset threshold is a negative value; or, the second half is changed In the direction of the potential of the cycle, after the potential of the second half of the cycle is reversed to a positive value, it is judged whether the potential is lower than the preset threshold.
  • the potential in the ⁇ t time period of the clock signal is detected.
  • the potential at point C is detected to be less than 0.3V
  • the feedback information of a larger value is fed back to the clock signal output terminal, and the clock signal output terminal increases the subsequent clock
  • the output amplitude of the signal forms the clock signal wave corresponding to the solid line behind (the dotted line is the clock signal wave before the output amplitude increases).
  • the potential at point D corresponding to the period of point C is increased and received at the data driver.
  • To the clock signal after the amplitude is increased correctly identify the high level or low level, there will be no rising or falling edge of the misjudgment near the point D, to avoid the wrong capture of data.
  • the initial amplitude of the initial clock signal sent by each clock signal sending end is different, when the output amplitude of the clock signal increases, the initial amplitude is obtained first, and then the target amplitude is determined according to the initial amplitude, Increase the output amplitude of the clock signal to the target amplitude.
  • the target amplitude is determined to be 0.8, that is, the subsequent generation and transmission of the clock signal with 0.8V as the output amplitude;
  • the initial amplitude is 0.4V, then the target amplitude can be 0.6V.
  • the increase of the specific amplitude is determined by experiment, and here is only an example.
  • the clock signal corresponding to the data signal starts to be acquired. And determine the potential of the clock signal within the time interval, wherein the time interval is less than half a clock cycle.
  • a signal with a too low amplitude is fed back to the sending end of the clock signal (for example, a timing driving chip), so that the sending end of the clock signal increases the clock The output amplitude of the signal.
  • the clock signal After the output amplitude of the clock signal is increased, the clock signal conforms to the new output amplitude, and the potential corresponding to the time point when the potential is lower than the preset threshold is increased, so that no rising or falling edge will occur near this time point , Effectively avoiding the wrong data capture.
  • step S10 further includes:
  • Step S40 Obtain the clock cycle of the clock signal.
  • Data Driver In the data drive (Data Driver) is provided with a frequency judgment unit, through which the frequency of the clock signal can be obtained. Since the period and the frequency are reciprocal to each other, the clock cycle of the clock signal can be obtained according to the obtained frequency.
  • the potential judgment unit set in the Driver can obtain the zero-volt time point with a potential of 0V in the clock signal.
  • the time interval between two adjacent zero-volt time points in the clock signal is half a clock cycle. Therefore, according to the two The clock cycles are obtained at two adjacent zero volt time points.
  • the clock period of the clock signal can also be obtained in other ways, and will not be described again one by one again.
  • the clock cycle is obtained according to the clock signal, so as to subsequently determine the judgment time interval for detecting whether there is an abnormal grabbing point of data in the clock signal according to the clock cycle, that is, to determine the time interval
  • the judgment time interval for detecting whether there is an abnormal grabbing point of data in the clock signal according to the clock cycle, that is, to determine the time interval
  • step S30 further includes:
  • Step S50 Obtain the data of the data signal according to the clock signal after the output amplitude is increased.
  • the clock signal after the output amplitude is increased can still effectively capture the data signal corresponding to the clock signal. Valid data. Moreover, after the increase of the output amplitude of the clock signal, some pre-existing abnormal grab points are removed. Therefore, according to this clock signal, the data in the data signal can be accurately captured to improve the accuracy of data capture.
  • the rising edge and/or the falling edge of the clock signal is acquired, and a time point corresponding to the rising edge or the falling edge in the data signal is determined, And grab the data in the data signal at the determined time point.
  • a rising edge and/or a falling edge of the clock signal is acquired, and it is determined that the data signal corresponds to the rising edge or the falling edge of the data signal.
  • the period and frequency of the clock signal have not been changed, so the clock signal after the output amplitude is increased can still effectively capture the data signal corresponding to the clock signal Valid data in.
  • some pre-existing abnormal grab points are removed. Therefore, according to this clock signal, the data in the data signal can be accurately captured to improve the accuracy of data capture.
  • the embodiments of the present application also provide a data transmission method.
  • the clock signal corresponding to the data signal is started to be obtained, and the clock cycle of the clock signal is obtained. Since the potential direction is the same in half a complete clock cycle, the potential of the clock signal is obtained in real time.
  • the potential in the clock signal is less than the preset threshold, it indicates that the time point corresponding to the potential may be mistaken for a negative voltage by the signal receiving end. At this time point, it is easy to generate a rising edge or a falling edge, and then use the rising edge or the falling edge as the data grabbing point.
  • the signal whose amplitude is too low is fed back to the sender of the clock signal (for example, a timing driver chip) for the sender of the clock signal to increase The output amplitude of the large clock signal. Acquire a preset amplitude, and increase the output amplitude of the clock signal to the preset amplitude. After the output amplitude of the clock signal is increased, the clock signal conforms to the new output amplitude, and the potential corresponding to the time point when the potential is lower than the preset threshold is increased, so that no rising or falling edge will occur near this time point , Effectively avoiding the wrong data capture.
  • the sender of the clock signal for example, a timing driver chip
  • the embodiments of the present application also provide a data transmission device.
  • the data transmission device includes: a memory, a processor, and a data transmission program stored on the memory and executable on the processor. When the data transmission program is executed by the processor, the steps of the data transmission method described in the above embodiments are implemented.
  • the present application may also include a computer-readable storage medium that stores a data transmission program on the computer-readable storage medium, and the data transmission program is used for execution by a processor as described in the above embodiments Steps of the data transmission method.
  • the methods in the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware, but in many cases the former is optional Implementation.
  • the technical solution of the present application can be embodied in the form of a software product in essence or part that contributes to the existing technology, and the computer software product is stored in a storage medium (such as ROM/RAM) as described above , Disk, CD), including several instructions to make a terminal device (which can be a mobile phone, computer, server, air conditioner, or network equipment, etc.) to perform the method described in each embodiment of the present application.

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Abstract

本申请公开了一种数据的传输方法，所述数据的传输方法包括以下步骤：检测到数据信号时，获取所述数据信号对应的时钟信号；在时间间隔内实时获取所述时钟信号的电位，其中，所述时间间隔小于或等于所述时钟信号的半个时钟周期；以及，当获取的所述电位低于预设阈值时，增大所述时钟信号的输出幅值。本申请还公开了一种数据的传输装置。

Description

数据的传输方法及装置
相关申请
本申请要求2018年12月19日申请的，申请号为201811559201.X名称为“数据的传输方法及装置”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及通信技术领域，尤其涉及数据的传输方法及装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着液晶电视尺寸越来越大，解析度越来越高，需要传输的数据也日益增多，差分信号作为一种高速的传输协议得到普及。在以差分信号进行数据传输过程中，数据信号（Data）伴随着时钟信号，并在时钟信号上升沿或下降沿时数据信号相对稳定，此时，接收端获取到数据信号中的目标数据。
然而，在实际情况中，由于传输走线特征阻抗的不一致性，信号在传输的过程中会遇到反射现象，反射回来的信号再与初始信号进行叠加，导致实际的信号波形凹凸不平。故，当时钟信号受到反射影响时，实际产生的时钟信号凹凸不平，当凹凸处的电位较低时，接收端容易误将该凹凸波附近的波动作为上升沿或下降沿，并根据误认的上升沿或下降沿获取传输数据，导致数据获取错误。
申请内容
本申请的主要目的在于提供一种数据的传输方法及装置，旨在避免数据的错误抓取。
为实现上述目的，本申请提供一种数据的传输方法，所述数据的传输方法包括以下步骤：
检测到数据信号时，获取所述数据信号对应的时钟信号；
在时间间隔内实时获取所述时钟信号的电位，其中，所述时间间隔小于或等于所述时钟信号的半个时钟周期；
以及，当获取的所述电位低于预设阈值时，增大所述时钟信号的输出幅值。
可选的，所述增大所述时钟信号的输出幅值的步骤包括：
获取所述时钟周期内所述时钟信号的初始幅值；
根据所述初始幅值确定目标幅值，并将所述时钟信号的输出幅值增大至所述目标幅值。
可选的，所述增大所述时钟信号的输出幅值的步骤包括：
所述时钟信号的发送端接收到幅值过低的信号，增大所述时钟信号的输出幅值。
可选的，所述时钟信号的发送端至少包括时序驱动芯片。
可选的，所述预设阈值的取值为0-0.3V。
可选的，所述获取所述数据信号对应的时钟信号的步骤之后，还包括：
实时监测所述时钟信号的电位为零伏的零伏时间点；
在所述零伏时间点延迟预设时长时，以当前时间点为起始时间点实时获取所述时间间隔内所述时钟信号的电位。
可选的，所述获取所述数据信号对应的时钟信号的步骤之后，还包括：
获取所述时钟信号的时钟周期。
可选的，所述获取所述时钟信号的时钟周期的步骤包括：
获取所述时钟信号的频率，根据所述频率获取所述时钟信号的时钟周期；
或者，获取所述时钟信号的零伏时间点，根据相邻两个所述零伏时间点之间的时间间隔获取所述时钟信号的时钟周期。
可选的，所述增大所述时钟信号的输出幅值的步骤之后，还包括：
根据输出幅值增大后的所述时钟信号获取所述数据信号的数据。
可选的，所述根据输出幅值增大后的所述时钟信号获取所述数据信号的数据的步骤包括：
获取所述输出幅值增大后的所述时钟信号的上升沿和下降沿；
确定所述数据信号中与所述上升沿和所述下降沿对应的时间点；
以及，抓取所述数据信号中所述时间点对应的数据。
此外，为实现上述目的，本申请还提供一种数据的传输方法，其中，所述数据的传输方法包括以下步骤：
检测到数据信号时，获取所述数据信号对应的时钟信号；
获取所述时钟信号的时钟周期；
实时获取半个所述时钟周期内所述时钟信号的电位；
以及，当获取的所述电位低于预设阈值时，将所述时钟信号的输出幅值增大至预设幅值。
可选的，将所述时钟信号的输出幅值增大至预设幅值的步骤包括：
所述时钟信号的发送端接收到幅值过低的信号，增大所述时钟信号的输出幅值。
可选的，所述时钟信号的发送端至少包括时序驱动芯片。
可选的，所述实时获取半个所述时钟周期内所述时钟信号的电位的步骤包括：
监测所述时钟信号的电位为零伏的零伏时间点；
实时获取所述零伏时间点后半个所述时钟周期内所述时钟信号的电位。
此外，为实现上述目的，本申请还提供一种数据的传输装置，其中，所述数据的传输装置包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的数据的传输程序，所述数据的传输程序被所述处理器执行时实现如上所述的数据的传输方法的步骤。
可选的，所述增大所述时钟信号的输出幅值的步骤包括：
获取所述时钟周期内所述时钟信号的初始幅值；
根据所述初始幅值确定目标幅值，并将所述时钟信号的输出幅值增大至所述目标幅值。
可选的，所述获取所述数据信号对应的时钟信号的步骤之后，还包括：
实时监测所述时钟信号的电位为零伏的零伏时间点；
在所述零伏时间点延迟预设时长时，以当前时间点为起始时间点实时获取所述时间间隔内所述时钟信号的电位。
可选的，所述增大所述时钟信号的输出幅值的步骤之后，还包括：
根据输出幅值增大后的所述时钟信号获取所述数据信号的数据。
可选的，所述根据输出幅值增大后的所述时钟信号获取所述数据信号的数据的步骤包括：
获取所述输出幅值增大后的所述时钟信号的上升沿和下降沿；
确定所述数据信号中与所述上升沿和所述下降沿对应的时间点；
以及，抓取所述数据信号中所述时间点对应的数据。
可选的，获取所述时钟信号的频率，根据所述频率获取所述时钟信号的时钟周期；
或者，获取所述时钟信号的零伏时间点，根据相邻两个所述零伏时间点之间的时间间隔获取所述时钟信号的时钟周期。
本申请实施例提出的一种数据的传输方法及装置，在检测到存在数据传输时，开始获取数据信号对应的时钟信号。并确定时间间隔内该时钟信号的电位，其中，所述时间间隔小于或等于半个时钟周期。在检测到所述时间间隔内时钟信号中存在电位小于预设阈值时，反馈幅值过低的信号给时钟信号的发送端（例如，时序驱动芯片），以供时钟信号的发送端增大时钟信号的输出幅值。在时钟信号的输出幅值得到增加后，时钟信号为符合新的输出幅值，电位低于预设阈值的时间点对应的电位被提高，从而在此时间点附近不会出现上升沿或下降沿，有效地避免了数据的错误抓取。
附图说明
图1是本申请的一实施例方案涉及的硬件运行环境的终端结构示意图；
图2为本申请数据的传输方法的一实施例的流程示意图；
图3为本申请数据的传输方法的一波形示意图；
图4为本申请数据的传输方法的另一波形示意图；
图5为本申请数据的传输方法的另一实施例的流程示意图；
图6为本申请数据的传输方法的又一实施例的流程示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请实施例的主要解决方案是：
检测到数据信号时，获取所述数据信号对应的时钟信号；
在时间间隔内实时获取所述时钟信号的电位，其中，所述时间间隔小于或等于所述时钟信号的半个时钟周期；
以及，当获取的所述电位低于预设阈值时，增大所述时钟信号的输出幅值。
由于当时钟信号受到反射影响时，实际产生的时钟信号凹凸不平，当凹凸处的电位较低时，接收端容易误将该凹凸波附近的波动作为上升沿或下降沿，并根据误认的上升沿或下降沿获取传输数据，导致数据获取错误。
本申请提供一种解决方案，在检测到存在数据传输时，开始获取数据信号对应的时钟信号。并确定时间间隔内该时钟信号的电位，其中，所述时间间隔小于或等于半个时钟周期。在检测到所述时间间隔内时钟信号中存在电位小于预设阈值时，反馈幅值过低的信号给时钟信号的发送端（例如，时序驱动芯片），以供时钟信号的发送端增大时钟信号的输出幅值。在时钟信号的输出幅值得到增加后，时钟信号为符合新的输出幅值，电位低于预设阈值的时间点对应的电位被提高，从而在此时间点附近不会出现上升沿或下降沿，有效地避免了数据的错误抓取。
如图1所示，图1是本申请实施例方案涉及的硬件运行环境的终端结构示意图。
本申请实施例终端可以是一种数据信号的数据提取装置，也可以是电视机，也可以是计算机。
如图1所示，该终端可以包括：处理器1001，例如CPU，存储器1002，通信总线1003，数据驱动器（Data Driver）1004，时序驱动芯片（TCON IC）1005。其中，通信总线1003设置为实现该终端中各组成部件之间的连接通信。存储器1002可以是高速随机存取存储器，也可以是稳定的存储器（non-volatile memory），例如磁盘存储器。存储器1002可选的还可以是独立于前述处理器1001的存储装置。数据驱动器1004进行数据信号的处理，可以是包括频率判断单元、电位判断单元和内部处理模块中的至少一个。时序驱动芯片1005，用于生成并发送数据信号以及时钟信号。
本领域技术人员可以理解，图1中示出的终端的结构并不构成对本申请实施例终端的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
如图1所示，作为一种计算机存储介质的存储器1002中可以包括传数据的传输程序。
在图1所示的服务器中，处理器1001可以用于调用存储器1002中存储的数据的传输程序，并执行以下操作：
测到数据信号时，获取所述数据信号对应的时钟信号；
在时间间隔内实时获取所述时钟信号的电位，其中，所述时间间隔小于所述时钟信号的半个时钟周期；
以及，当获取的所述电位低于预设阈值时，增大所述时钟信号的输出幅值。
进一步地，处理器1001可以调用存储器1002中存储的数据的传输程序，还执行以下操作：
获取所述时钟周期内所述时钟信号的初始幅值；
根据所述初始幅值确定目标幅值，并将所述时钟信号的输出幅值增大至所述目标幅值。
进一步地，处理器1001可以调用存储器1002中存储的数据的传输程序，还执行以下操作：
实时监测所述时钟信号的电位为零伏的零伏时间点；
在所述零伏时间点延迟预设时长时，以当前时间点为起始时间点实时获取所述时间间隔内所述时钟信号的电位。
进一步地，处理器1001可以调用存储器1002中存储的数据的传输程序，还执行以下操作：
获取所述时钟信号的时钟周期。
进一步地，处理器1001可以调用存储器1002中存储的数据的传输程序，还执行以下操作：
获取所述时钟信号的频率，根据所述频率获取所述时钟信号的时钟周期；
或者，获取所述时钟信号的零伏时间点，根据相邻两个所述零伏时间点之间的时间间隔获取所述时钟信号的时钟周期。
进一步地，处理器1001可以调用存储器1002中存储的数据的传输程序，还执行以下操作：
根据输出幅值增大后的所述时钟信号获取所述数据信号的数据。
进一步地，处理器1001可以调用存储器1002中存储的数据的传输程序，还执行以下操作：
获取所述输出幅值增大后的所述时钟信号的上升沿和下降沿；
确定所述数据信号中与所述上升沿和所述下降沿对应的时间点；
以及，抓取所述数据信号中所述时间点对应的数据。
进一步地，处理器1001可以调用存储器1002中存储的数据的传输程序，还执行以下操作：
检测到数据信号时，获取所述数据信号对应的时钟信号；
获取所述时钟信号的时钟周期；
实时获取半个所述时钟周期内所述时钟信号的电位；
以及，当获取的所述电位低于预设阈值时，将所述时钟信号的输出幅值增大至预设幅值。
进一步地，处理器1001可以调用存储器1002中存储的数据的传输程序，还执行以下操作：
监测所述时钟信号的电位为零伏的零伏时间点；
实时获取所述零伏时间点后半个所述时钟周期内所述时钟信号的电位。
参照图2，本申请数据的传输方法一实施例，所述数据的传输方法包括：
步骤S10，检测到数据信号时，获取所述数据信号对应的时钟信号。
步骤S20，在时间间隔内实时获取所述时钟信号的电位，其中，所述时间间隔小于或等于所述时钟信号的半个时钟周期。
在现今生活中，随着通信技术越来越发达，越来越多的采用信号传输的方式来实现数据的传输。以数字电视的技术领域为例，随着液晶电视尺寸越来越大，解析度越来越高，需要传输的数据也日益增多，差分信号作为数据信号中一种高速的传输协议便得到广泛普及。但在数据信号在实际传输的过程中，由于传输走线特征阻抗的不一致性，数据信号在传输的过程中会遇到反射现象，反射回来的数据信号再与初始的时钟信号进行信号叠加，导致实际得到的时钟信号的波形出现凹凸不平现象，如果这时再直接根据该时钟信号去提取数据信号的数据，就可能会提取到错误的数据。
如图3所示，图中上方为数据信号的波形，下方为时钟信号产生的波形。当时钟信号受到反射影响时，时钟信号的形状发生变化，如图3中出现凹陷的A点和对应凸起的B点，当A点的电位小于一定值时，信号识别时，容易将该点的电位视为负值，此时，在A点右侧形成上升沿，进而根据产生的上升沿抓取数据信号中的数据，出现异常抓取现象，导致数据抓取错误。同样的，在B点的右侧形成下降沿，以此下降沿抓取数据信号中的数据，导致数据的抓取错误。在接收端接收到错误的数据时，容易造成数据显示异常或噪点的出现。
为了避免上述异常抓取数据的现象发生，本申请提供一种数据的传输方法，在检测到存在数据传输时，开始获取数据信号对应的时钟信号。并确定时间间隔内该时钟信号的电位，其中，时钟信号在半个时钟周期内的电位方向相同，所以所述时钟周期为半个时钟周期，故，所述时间间隔为半个时钟周期内的一段时间。在数据驱动器（Data Driver）添加有电位判断单元，在数据驱动器获取到时钟信号后，通过电位判断单元能够获取时钟信号各个时间点对应的电位。
进一步的，在检测到时钟信号的电位为0V时的零伏时间点延迟一定预设时长后，开始实时检测所述时间间隔内的时钟信号的电位。如图4所示，检测时钟信号在Δt时间间隔内的电位。容易理解的是，在时钟信号的半个周期内，时钟信号以输出幅值电位升高后降低呈正弦曲线状，在开始上升和接近下降结束中存在一定时间段内，电位较小的时间点，可能低于预设阈值，故，实时获取时钟信号电位的所述时间间隔为半个周期内的部分时间段，即扣除半个周期开始后的一段时间和半个周期结束前的一段时间。避免对造成异常抓取点（C点）的误判，在输出幅值能够满足时钟信号的正常数据抓取时，对输出幅值增大，徒增时钟信号发送端的工作量。
步骤S30，当获取的所述电位低于预设阈值时，增大所述时钟信号的输出幅值。
在检测到所述时间间隔内时钟信号中存在电位小于预设阈值时，表明该电位对应的时间点可能被信号接收端误认为是负电压，在此时间点处容易产生上升沿或下降沿，进而将上升沿或下降沿作为数据抓取点。为避免形成错误的数据抓取点，在获取到电位低于预设阈值时，反馈幅值过低的信号给时钟信号的发送端（例如，时序驱动芯片），以供时钟信号的发送端增大时钟信号的输出幅值。在时钟信号的输出幅值得到增加后，时钟信号为符合新的输出幅值，电位低于预设阈值的时间点对应的电位被提高，从而在此时间点附近不会出现上升沿或下降沿，有效地避免了数据的错误抓取。其中，预设阈值为信号判断的临界值，通常可取0-0.3V。
此外，数据信号以正弦波形传输，信号波中各个时间点处的电位的正负是相对的，上述可视为以前半周期为例说明。当检测时为后半周期时，判断方向相反，即当在获取到电位高于预设阈值时，增大时钟信号的输出幅值，此时预设阈值为负值；或者是，更改后半周期的电位方向，将后半周期的电位取相反数成为正值后，再进行电位是否低于预设阈值的判断。
如图4所示，检测时钟信号中Δt时间段内的电位，当检测到C点的电位小于0.3V时，给时钟信号输出端反馈增大幅值的反馈信息，时钟信号输出端增大后续时钟信号的输出幅值，形成后面实线对应的时钟信号波（虚线为输出幅值增大前的时钟信号波），此时，与C点周期对应的D点的电位得到提高，在数据驱动器接收到幅值增大后的时钟信号，正确识别高电平或低电平，D点附近不会再产生误判的上升沿或下降沿，避免数据的错误抓取。
进一步的，由于每个时钟信号发送端发送的初始时钟信号的初始幅值不同，所以在对时钟信号的输出幅值增大时，先获取初始幅值，再根据初始幅值确定目标幅值，将该时钟信号的输出幅值增大至目标幅值。例如，当初始幅值为0.5V时，表明以0.5V为输出幅值，存在异常抓取点，则确定目标幅值为0.8，即后续以0.8V为输出幅值生成并发送时钟信号；若初始幅值为0.4V，则目标幅值可为0.6V。具体幅值的增加幅度由实验确定，在此仅为举例说明。
在本实施例中，在检测到存在数据传输时，开始获取数据信号对应的时钟信号。并确定时间间隔内该时钟信号的电位，其中，所述时间间隔小于半个时钟周期。在检测到所述时间间隔内时钟信号中存在电位小于预设阈值时，反馈幅值过低的信号给时钟信号的发送端（例如，时序驱动芯片），以供时钟信号的发送端增大时钟信号的输出幅值。在时钟信号的输出幅值得到增加后，时钟信号为符合新的输出幅值，电位低于预设阈值的时间点对应的电位被提高，从而在此时间点附近不会出现上升沿或下降沿，有效地避免了数据的错误抓取。
进一步的，参照图5，本申请数据的传输方法另一实施例，基于上述一实施例，所述步骤S10之后，还包括：
步骤S40，获取所述时钟信号的时钟周期。
在数据驱动器（Data Driver）中设置有频率判断单元，通过频率判断单元能够获取时钟信号的频率，由于周期与频率互为倒数，故根据获取到的频率即可得到时钟信号的时钟周期。
此外，通过数据驱动器（Data Driver）中设置的电位判断单元能够获取到时钟信号中电位为0V的零伏时间点，时钟信号中两个相邻的零伏时间点间的时间间隔为半个时钟周期，故，可根据两个相邻的零伏时间点获取时钟周期。还可以通过其他方式以获取时钟信号的时钟周期，再次将不再一一赘述。
在本实施例中，在获取到时钟信号后，根据时钟信号获取时钟周期，以便于后续根据时钟周期确定检测时钟信号中是否存在数据的异常抓取点的判断时间间隔，即确定所述时间间隔，以在时间间隔内实时获取所述时钟信号的电位，有助于对数据异常抓取点的消除，避免数据获取错误。
进一步的，参照图6，本申请数据的传输方法另一实施例，基于上述各个实施例，所述步骤S30之后，还包括：
步骤S50，根据输出幅值增大后的所述时钟信号获取所述数据信号的数据。
虽然时钟信号的输出幅值得到增大，但是该时钟信号的周期和频率均未受到改变，因此根据输出幅值增大后的所述时钟信号依然能够有效抓取该时钟信号对应的数据信号中的有效数据。且，时钟信号经过输出幅值的增大后，一些先前存在的异常抓取点被去除，故，依据此时钟信号能够准确抓取到数据信号中的数据，提高数据抓取的准确性。
在通过幅值增大后的时钟信号抓取数据时，获取该时钟信号的的上升沿和/或下降沿，确定对应所述数据信号中与该上升沿或者所述下降沿对应的时间点，并在确定的时间点处抓取数据信号中的数据。
在本实施例中，在通过幅值增大后的时钟信号抓取数据时，获取该时钟信号的的上升沿和/或下降沿，确定对应所述数据信号中与该上升沿或者所述下降沿对应的时间点，并在确定的时间点处抓取数据信号中的数据。虽然时钟信号的输出幅值得到增大，但是该时钟信号的周期和频率均未收到改变，因此根据输出幅值增大后的所述时钟信号依然能够有效抓取该时钟信号对应的数据信号中的有效数据。且，时钟信号经过输出幅值的增大后，一些先前存在的异常抓取点被去除，故，依据此时钟信号能够准确抓取到数据信号中的数据，提高数据抓取的准确性。
此外，本申请实施例还提出一种数据的传输方法，在检测到存在数据传输时，开始获取数据信号对应的时钟信号，并获取该时钟信号的时钟周期。由于在半个完整的时钟周期内电位方向相同，所以实时获取时钟信号的电位，当时钟信号中存在电位小于预设阈值时，表明该电位对应的时间点可能被信号接收端误认为是负电压，在此时间点处容易产生上升沿或下降沿，进而将上升沿或下降沿作为数据抓取点。为避免形成错误的数据抓取点，在获取到电位低于预设阈值时，反馈幅值过低的信号给时钟信号的发送端（例如，时序驱动芯片），以供时钟信号的发送端增大时钟信号的输出幅值。获取预设幅值，将时钟信号的输出幅值增大至该预设幅值。在时钟信号的输出幅值得到增加后，时钟信号为符合新的输出幅值，电位低于预设阈值的时间点对应的电位被提高，从而在此时间点附近不会出现上升沿或下降沿，有效地避免了数据的错误抓取。
进一步的，为使得时钟信号的电位的采集时间段为完整的半个时钟周期，检测时钟信号的电位为零伏的零伏时间点，并以所述零伏时间点为起始时间点，获取半个时钟周期内时钟信号的电位。
此外，本申请实施例还提出一种数据的传输装置，所述数据的传输装置包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的数据的传输程序，所述数据的传输程序被所述处理器执行时实现如上各个实施例所述的数据的传输方法的步骤。
此外，本申请还可以包括一种计算机可读存储介质，所述计算机可读存储介质上存储有数据的传输程序，所述数据的传输程序用于被处理器执行时实现如上各个实施例所述的数据的传输方法的步骤。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者系统不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者系统所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者系统中还存在另外的相同要素。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是可选的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在如上所述的一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，空调器，或者网络设备等)执行本申请各个实施例所述的方法。
以上仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种数据的传输方法，其中，所述数据的传输方法包括以下步骤：
    检测到数据信号时，获取所述数据信号对应的时钟信号；
    在时间间隔内实时获取所述时钟信号的电位，其中，所述时间间隔小于或等于所述时钟信号的半个时钟周期；
    以及，当获取的所述电位低于预设阈值时，增大所述时钟信号的输出幅值。
  2. 如权利要求1所述的数据的传输方法，其中，所述增大所述时钟信号的输出幅值的步骤包括：
    获取所述时钟周期内所述时钟信号的初始幅值；
    根据所述初始幅值确定目标幅值，并将所述时钟信号的输出幅值增大至所述目标幅值。
  3. 如权利要求1所述的数据的传输方法，其中，所述增大所述时钟信号的输出幅值的步骤包括：
    所述时钟信号的发送端接收到幅值过低的信号，增大所述时钟信号的输出幅值。
  4. 如权利要求3所述的数据的传输方法，其中，所述时钟信号的发送端至少包括时序驱动芯片。
  5. 如权利要求1所述的数据的传输方法，其中，所述预设阈值的取值为0-0.3V。
  6. 如权利要求1所述的数据的传输方法，其中，所述获取所述数据信号对应的时钟信号的步骤之后，还包括：
    实时监测所述时钟信号的电位为零伏的零伏时间点；
    在所述零伏时间点延迟预设时长时，以当前时间点为起始时间点实时获取所述时间间隔内所述时钟信号的电位。
  7. 如权利要求1所述的数据的传输方法，其中，所述获取所述数据信号对应的时钟信号的步骤之后，还包括：
    获取所述时钟信号的时钟周期。
  8. 如权利要求7所述的数据的传输方法，其中，所述获取所述时钟信号的时钟周期的步骤包括：
    获取所述时钟信号的频率，根据所述频率获取所述时钟信号的时钟周期；
    或者，获取所述时钟信号的零伏时间点，根据相邻两个所述零伏时间点之间的时间间隔获取所述时钟信号的时钟周期。
  9. 如权利要求1所述的数据的传输方法，其中，所述增大所述时钟信号的输出幅值的步骤之后，还包括：
    根据输出幅值增大后的所述时钟信号获取所述数据信号的数据。
  10. 如权利要求9所述的数据的传输方法，其中，所述根据输出幅值增大后的所述时钟信号获取所述数据信号的数据的步骤包括：
    获取所述输出幅值增大后的所述时钟信号的上升沿和下降沿；
    确定所述数据信号中与所述上升沿和所述下降沿对应的时间点；
    以及，抓取所述数据信号中所述时间点对应的数据。
  11. 一种数据的传输方法，其中，所述数据的传输方法包括以下步骤：
    检测到数据信号时，获取所述数据信号对应的时钟信号；
    获取所述时钟信号的时钟周期；
    实时获取半个所述时钟周期内所述时钟信号的电位；
    以及，当获取的所述电位低于预设阈值时，将所述时钟信号的输出幅值增大至预设幅值。
  12. 如权利要求11所述的数据的传输方法，其中，将所述时钟信号的输出幅值增大至预设幅值的步骤包括：
    所述时钟信号的发送端接收到幅值过低的信号，增大所述时钟信号的输出幅值。
  13. 如权利要求12所述的数据的传输方法，其中，所述时钟信号的发送端至少包括时序驱动芯片。
  14. 如权利要求11所述的数据的传输方法，其中，所述实时获取半个所述时钟周期内所述时钟信号的电位的步骤包括：
    监测所述时钟信号的电位为零伏的零伏时间点；
    实时获取所述零伏时间点后半个所述时钟周期内所述时钟信号的电位。
  15. 一种数据的传输装置，其中，所述数据的传输装置包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的数据的传输程序，所述数据的传输程序被所述处理器执行时实现如下所述的数据的传输方法的步骤：
    检测到数据信号时，获取所述数据信号对应的时钟信号；
    在所述时钟信号的时钟周期内实时获取所述时钟信号的电位；
    以及，当获取的所述电位低于预设阈值时，增大所述时钟信号的输出幅值。
  16. 如权利要求15所述的数据的传输装置，其中，所述增大所述时钟信号的输出幅值的步骤包括：
    获取所述时钟周期内所述时钟信号的初始幅值；
    根据所述初始幅值确定目标幅值，并将所述时钟信号的输出幅值增大至所述目标幅值。
  17. 如权利要求15所述的数据的传输装置，其中，所述获取所述数据信号对应的时钟信号的步骤之后，还包括：
    实时监测所述时钟信号的电位为零伏的零伏时间点；
    在所述零伏时间点延迟预设时长时，以当前时间点为起始时间点实时获取所述时间间隔内所述时钟信号的电位。
  18. 如权利要求15所述的数据的传输装置，其中，所述增大所述时钟信号的输出幅值的步骤之后，还包括：
    根据输出幅值增大后的所述时钟信号获取所述数据信号的数据。
  19. 如权利要求18所述的数据的传输装置，其中，所述根据输出幅值增大后的所述时钟信号获取所述数据信号的数据的步骤包括：
    获取所述输出幅值增大后的所述时钟信号的上升沿和下降沿；
    确定所述数据信号中与所述上升沿和所述下降沿对应的时间点；
    以及，抓取所述数据信号中所述时间点对应的数据。
  20. 如权利要求15所述的数据的传输装置，其中，
    获取所述时钟信号的频率，根据所述频率获取所述时钟信号的时钟周期；
    或者，获取所述时钟信号的零伏时间点，根据相邻两个所述零伏时间点之间的时间间隔获取所述时钟信号的时钟周期。
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