WO2020124888A1 - 阵列基板以及显示面板 - Google Patents

阵列基板以及显示面板 Download PDF

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Publication number
WO2020124888A1
WO2020124888A1 PCT/CN2019/082394 CN2019082394W WO2020124888A1 WO 2020124888 A1 WO2020124888 A1 WO 2020124888A1 CN 2019082394 W CN2019082394 W CN 2019082394W WO 2020124888 A1 WO2020124888 A1 WO 2020124888A1
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Prior art keywords
connection terminals
along
regions
reference plane
array substrate
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Ceased
Application number
PCT/CN2019/082394
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English (en)
French (fr)
Inventor
袁朝煜
陈敏
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/496,455 priority Critical patent/US11043510B2/en
Publication of WO2020124888A1 publication Critical patent/WO2020124888A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays

Definitions

  • the present application relates to the field of display, in particular to an array substrate and a display panel.
  • An array substrate (also called a TFT substrate) formed with a driving circuit, such as a TFT circuit, is an indispensable part in a display device, and includes a display area, a binding area provided at one end of the display area, including a signal conversion area and connection terminals
  • the signal conversion area is provided with a signal conversion line
  • the connection terminal area is provided with a connection terminal.
  • the signal conversion line is correspondingly connected to the connection terminal, and the binding between the array substrate and the drive chip is realized based on the connection terminal.
  • the design of signal conversion lines and connection terminals in the bonding area will directly affect the yield of bonding.
  • the present application provides an array substrate and a display panel to solve the problem that the distance between the connection terminals of the existing array substrate is too small, and short-circuiting is likely to occur during bonding, resulting in poor bonding.
  • the array substrate includes:
  • the binding area is provided at one end of the display area and includes a signal conversion area and a connection terminal area; the signal conversion area is provided with a signal conversion line, the connection terminal area is provided with a connection terminal, and the signal conversion line is connected to the The connection terminals are correspondingly connected;
  • the signal conversion line extends along the first direction and connects two connection terminals of adjacent signal conversion lines, and projections on the reference plane along the second direction do not coincide, the reference plane is parallel to the first direction, And perpendicular to the connection terminal setting surface, the second direction is perpendicular to the reference plane.
  • connection terminal area includes at least two sub-regions, and projections of the connection terminals in the sub-regions along the second direction on the reference plane coincide.
  • connection terminals in the sub-regions have the same size.
  • connection terminals in the sub-regions are formed in the same process.
  • connection terminals in adjacent sub-regions are connected along the projection on the reference plane along the second direction.
  • connection terminals in the adjacent sub-regions are connected along the projection on the reference plane along the second direction.
  • the gaps between the projections of all the connection terminals in the adjacent sub-regions on the reference plane along the second direction are the same.
  • the gaps between the connection terminals of all adjacent sub-regions are the same.
  • the display panel includes an array substrate.
  • the array substrate includes:
  • the binding area is provided at one end of the display area and includes a signal conversion area and a connection terminal area; the signal conversion area is provided with a signal conversion line, the connection terminal area is provided with a connection terminal, and the signal conversion line is connected to the The connection terminals are correspondingly connected;
  • the signal conversion line extends along the first direction and connects two connection terminals of adjacent signal conversion lines, and projections on the reference plane along the second direction do not coincide, the reference plane is parallel to the first direction, And perpendicular to the connection terminal setting surface, the second direction is perpendicular to the reference plane.
  • connection terminal area includes at least two sub-regions, and projections of the connection terminals in the sub-regions along the second direction on the reference plane coincide.
  • connection terminals in the sub-areas have the same size.
  • connection terminals in the sub-regions are formed in the same process.
  • connection terminals in adjacent sub-regions are connected along the projection on the reference plane along the second direction.
  • connection terminals in the adjacent sub-regions are connected along the projection on the reference plane along the second direction.
  • the gaps between the projections of all the connection terminals in the adjacent sub-regions on the reference plane along the second direction are the same.
  • the gaps between the connection terminals of all adjacent sub-regions are the same.
  • the present application provides a new array substrate and a display panel.
  • the array substrate includes a display area and a binding area located at one end of the display area.
  • the binding area includes correspondingly connected signal conversion lines and connection terminals, wherein, The signal conversion line extends in the first direction and connects the two connection terminals of the adjacent signal conversion line, and the projections on the reference plane in the second direction do not overlap; in this way, the design of the adjacent connection terminals staggered can be increased
  • the spacing between the adjacent connection terminals solves the problem that the spacing of the connection terminals of the existing array substrate is too small, and short-circuiting is likely to occur during bonding, resulting in poor bonding.
  • FIG. 1 is a first schematic cross-sectional view of an array substrate provided by an embodiment of this application.
  • FIG. 2 is a second schematic cross-sectional view of an array substrate provided by an embodiment of the present application.
  • FIG. 3 is a third schematic cross-sectional view of an array substrate provided by an embodiment of the present application.
  • FIG. 4 is a fourth cross-sectional schematic diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 1 is a first schematic cross-sectional view of an array substrate 10 provided by an embodiment of the present application.
  • An embodiment of the present application provides an array substrate 10, including:
  • the display area 11 includes a plurality of display devices for performing display functions
  • the binding area 12 is provided at one end of the display area 11 and includes a signal conversion area and a connection terminal 122 area; the signal conversion area is provided with a signal conversion line 121 and the connection terminal 122 area is provided with a connection terminal 122, The signal conversion line 121 is correspondingly connected to the connection terminal 122.
  • the signal conversion line 121 connects the connection terminal 122 to the display device of the display area 11 for signal exchange.
  • connection terminal 122 of the binding area 12 is bound to the IC terminal on the flexible circuit board, so that the control signal on the flexible circuit board is transmitted to the display area through the connection terminal 122 11, and execute the corresponding signal instruction.
  • connection terminals 122 in the connection terminal area 122, and the smaller the spacing between adjacent connection terminals 122; accurate connection terminal 122 and IC terminals on the flexible circuit board The more difficult the binding, the lower the product yield. Therefore, this application proposes the following solutions to solve the above problems.
  • the signal conversion line 121 extends along the first direction X, connects the two connection terminals 122 of the adjacent signal conversion line 121, and the projections on the reference plane along the second direction Y do not coincide, and the reference plane is parallel to the
  • the first direction X is perpendicular to the installation surface of the connection terminal 122
  • the second direction Y is perpendicular to the reference plane.
  • connection terminals 122 By providing two connection terminals 122 for connecting adjacent signals, the projection on the reference plane along the second direction Y does not coincide, so that the two adjacent terminals along the first direction X are staggered, and then in the second direction Y
  • the distance between two adjacent connection terminals 122 is at least doubled, which reduces the density of the connection terminals 122 in the connection terminals 122 area, thereby improving the alignment fault tolerance rate of the connection terminals 122 and the IC terminals, and can improve the product yield.
  • FIG. 2 is a second schematic cross-sectional view of an array substrate 10 provided by an embodiment of the present application.
  • connection terminal 122 area includes at least two sub-regions 12a, and projections of the connection terminal 122 in the sub-region 12a along the second direction Y on the reference plane coincide.
  • connection terminals 122 Due to the restriction that the projections of the connection terminals 122 in the sub-region 12a along the second direction Y on the reference plane coincide, the connection terminals 122 can be regularly arranged in the connection terminal 122 area and lifted The manufacturing efficiency of the array substrate 10 is improved.
  • the connecting terminals 122 in the sub-region 12a have the same size.
  • connection terminals 122 in the sub-region 12a are formed in the same process. This embodiment can improve the binding of the connection terminals 122 and the IC terminals without increasing the process of the connection terminals 122 process Yield.
  • FIG. 3 is a third schematic cross-sectional view of a protective cover provided by an embodiment of the present application.
  • connection terminals 122 in the adjacent sub-regions 12a are connected along the projection of the second direction Y on the reference plane.
  • connection terminal 122 area includes two sub-regions 12a
  • the connection terminals 122 in adjacent sub-regions 12a overlap or connect along the projection direction of the second direction Y on the reference plane; when the connection terminal 122
  • the zone includes more than two sub-regions 12a, at least the connection terminals 122 in adjacent sub-regions 12a along the second direction Y project on the reference plane partially overlap or just connect.
  • connection terminals 122 in the adjacent sub-regions 12a are connected along the projection of the second direction Y on the reference plane.
  • connection terminal 122 includes two sub-regions 12a or more than two sub-regions 12a, all the connection terminals 122 in adjacent sub-regions 12a project along the second direction Y on the reference plane Overlap or connect.
  • FIG. 4 is a fourth cross-sectional schematic diagram of the array substrate 10 provided by an embodiment of the present application.
  • the application in order to further improve the error tolerance rate when the connection terminal 122 and the IC terminal are bound, the application is provided along the first direction X, and the connection terminal 122 in the adjacent sub-region 12a is along the first There is a gap between the projections of the two directions Y on the reference plane.
  • connection terminal 122 area When the connection terminal 122 area includes two sub-regions 12a, there is a gap between the projections of the connection terminals 122 in adjacent sub-regions 12a along the second direction Y on the reference plane; when the connection terminals 122 When the area includes more than two sub-regions 12a, at least there is a gap between the projections of the connection terminals 122 in the adjacent sub-regions 12a along the second direction Y on the reference plane, that is, there may also be adjacent sub-regions
  • the connection terminals 122 in 12a are partially overlapped or connected along the projection direction of the second direction Y on the reference plane. It can be set according to actual needs.
  • connection terminal 122 includes two sub-regions 12a or more than two sub-regions 12a, the projections of the connection terminals 122 in all adjacent sub-regions 12a along the second direction Y on the reference plane There are gaps between them.
  • the gaps between the projections of the connection terminals 122 in all adjacent sub-regions 12a on the reference plane along the second direction Y are the same.
  • the gaps between the connection terminals 122 of all adjacent sub-regions 12a are the same. That is, the connection terminals 122 of the adjacent sub-regions 12a are arranged equidistantly.
  • the array substrate 10 further includes an insulating layer, and the insulating layer covers the signal conversion line 121.
  • the insulating layer insulates the signal conversion line 121 to prevent the signal conversion line 121 from contacting other metals and causing a short circuit.
  • an embodiment of the present application provides a display panel, such as a liquid crystal display panel, etc.
  • the display panel includes an array substrate, and the array substrate includes:
  • the binding area is provided at one end of the display area and includes a signal conversion area and a connection terminal area; the signal conversion area is provided with a signal conversion line, the connection terminal area is provided with a connection terminal, and the signal conversion line is connected to the The connection terminals are correspondingly connected;
  • the signal conversion line extends along the first direction and connects two connection terminals of adjacent signal conversion lines, and projections on the reference plane along the second direction do not coincide, the reference plane is parallel to the first direction, And perpendicular to the connection terminal setting surface, the second direction is perpendicular to the reference plane.
  • connection terminal area includes at least two sub-regions, and projections of the connection terminals in the sub-regions on the reference plane along the second direction coincide.
  • connection terminals in the sub-regions have the same size.
  • connection terminals in the sub-regions are formed in the same process.
  • connection terminals in adjacent sub-regions are projected on the reference plane along the second direction along the projection.
  • connection terminals in the adjacent sub-regions are projected on the reference plane along the second direction along the projection direction.
  • connection terminals in the adjacent sub-regions have the same gap between projections on the reference plane along the second direction along the second direction .
  • the gaps between the connection terminals of all adjacent sub-regions are the same.
  • the present application provides a new array substrate and a display panel.
  • the array substrate includes a display area and a binding area located at one end of the display area.
  • the binding area includes correspondingly connected signal conversion lines and connection terminals, wherein, The signal conversion line extends along the first direction X, and connects the two connection terminals of the adjacent signal conversion line, and the projections on the reference plane along the second direction do not overlap; in this way, the design of adjacent connection terminals staggered can be increased
  • the large distance between adjacent connection terminals solves the problem that the connection distance between the connection terminals of the existing array substrate is too small, and short-circuiting is likely to occur during bonding, resulting in poor bonding.

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Abstract

本申请提供一种阵列基板以及显示面板，该阵列基板的信号转换线沿第一方向延伸，连接相邻信号转换线的两个连接端子，沿第二方向在参考平面上的投影不重合；这样，相邻连接端子交相错开的设计能够增大相邻连接端子之间的间距，解决了现有阵列基板连接端子间距过小，在绑定时易发生短路造成绑定不良的问题。

Description

阵列基板以及显示面板 技术领域
本申请涉及显示领域，尤其涉及一种阵列基板以及显示面板。
 背景技术
形成有驱动电路，如TFT电路的阵列基板（也称TFT基板），是显示装置内不可或缺的一部分，其包括显示区，设置于显示区一端的绑定区，包括信号转换区以及连接端子区，信号转换区设置有信号转换线，连接端子区设置有连接端子，信号转换线与连接端子对应连接，基于连接端子实现阵列基板与驱动芯片之间的绑定。
其中，绑定区中的信号转换线以及连接端子的设计会直接影响绑定的良率，产品的分辨率越高导致绑定区的连接端子和信号转换线越密集，相邻连接端子之间的间距越小，绑定工艺的精度要求越高。
因此，目前亟需一种阵列基板以解决上述问题。
 技术问题
本申请提供一种阵列基板以及显示面板，以解决现有阵列基板连接端子间距过小，在绑定时易发生短路造成绑定不良的问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供了一种阵列基板，所述阵列基板包括：
显示区；
绑定区，设置于所述显示区一端，包括信号转换区以及连接端子区；所述信号转换区设置有信号转换线，所述连接端子区设置有连接端子，所述信号转换线与所述连接端子对应连接；
其中，所述信号转换线沿第一方向延伸，连接相邻信号转换线的两个连接端子，沿第二方向在参考平面上的投影不重合，所述参考平面平行于所述第一方向、且垂直于所述连接端子设置面，所述第二方向垂直于所述参考平面。
在本申请的阵列基板中，所述连接端子区包括至少两个子区域，所述子区域内的连接端子沿所述第二方向在所述参考平面上的投影重合。
在本申请的阵列基板中，所述子区域内的连接端子尺寸相同。
在本申请的阵列基板中，所述子区域内的连接端子在同一道工艺中形成。
在本申请的阵列基板中，沿所述第一方向，相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影连接。
在本申请的阵列基板中，沿所述第一方向，所有相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影连接。
在本申请的阵列基板中，沿所述第一方向，相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影之间存在间隙。
在本申请的阵列基板中，沿所述第一方向，所有相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影之间存在间隙。
在本申请的阵列基板中，沿所述第一方向，所有相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影之间间隙大小相同。
在本申请的阵列基板中，沿所述第二方向，所有相邻子区域连接端子之间的间隙大小相同。
本申请实施例提供了一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括：
显示区；
绑定区，设置于所述显示区一端，包括信号转换区以及连接端子区；所述信号转换区设置有信号转换线，所述连接端子区设置有连接端子，所述信号转换线与所述连接端子对应连接；
其中，所述信号转换线沿第一方向延伸，连接相邻信号转换线的两个连接端子，沿第二方向在参考平面上的投影不重合，所述参考平面平行于所述第一方向、且垂直于所述连接端子设置面，所述第二方向垂直于所述参考平面。
在本申请的显示面板中，所述连接端子区包括至少两个子区域，所述子区域内的连接端子沿所述第二方向在所述参考平面上的投影重合。
在本申请的显示面板中，所述子区域内的连接端子尺寸相同。
在本申请的显示面板中，所述子区域内的连接端子在同一道工艺中形成。
在本申请的显示面板中，沿所述第一方向，相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影连接。
在本申请的显示面板中，沿所述第一方向，所有相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影连接。
在本申请的显示面板中，沿所述第一方向，相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影之间存在间隙。
在本申请的显示面板中，沿所述第一方向，所有相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影之间存在间隙。
在本申请的显示面板中，沿所述第一方向，所有相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影之间间隙大小相同。
在本申请的显示面板中，沿所述第二方向，所有相邻子区域连接端子之间的间隙大小相同。
 有益效果
本申请提供了一种新的阵列基板以及显示面板，该阵列基板包括显示区和位于所述显示区一端的绑定区，所述绑定区包括对应连接的信号转换线和连接端子，其中，所述信号转换线沿第一方向延伸，连接相邻信号转换线的两个连接端子，沿第二方向在参考平面上的投影不重合；这样，相邻连接端子交相错开的设计能够增大相邻连接端子之间的间距，解决了现有阵列基板连接端子间距过小，在绑定时易发生短路造成绑定不良的问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的阵列基板的第一种截面示意图。
图2为本申请实施例提供的阵列基板的第二种截面示意图。
图3为本申请实施例提供的阵列基板的第三种截面示意图。
图4为本申请实施例提供的阵列基板的第四种截面示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
针对现有阵列基板连接端子间距过小，在绑定时易发生短路造成绑定不良的问题，本申请实施例可以解决这个问题。
请参阅图1，图1为本申请实施例提供的阵列基板10的第一种截面示意图。
本申请实施例提供了一种阵列基板10，包括：
显示区11，包括多个用以执行显示功能的显示器件；
绑定区12，设置于所述显示区11一端，包括信号转换区以及连接端子122区；所述信号转换区设置有信号转换线121，所述连接端子122区设置有连接端子122，所述信号转换线121与所述连接端子122对应连接。
所述信号转换线121将所述连接端子122与所述显示区11的显示器件连接，用以进行信号交流。
在进行显示面板制作时，将所述绑定区12的连接端子122与柔性线路板上的IC端子进行绑定，使得柔性线路板上的控制信号通过所述连接端子122传输至所述显示区11，并执行相对应的信号指令。
现有产品的分辨率越高，所述连接端子122区的连接端子122数量越多，相邻连接端子122之间的间距越小；将连接端子122与柔性线路板上的IC端子的进行精准绑定的难度越大，产品的良品率降低。因此，本申请提出以下方案解决上述问题。
其中，所述信号转换线121沿第一方向X延伸，连接相邻信号转换线121的两个连接端子122，沿第二方向Y在参考平面上的投影不重合，所述参考平面平行于所述第一方向X、且垂直于所述连接端子122设置面，所述第二方向Y垂直于所述参考平面。
通过设置连接相邻信号的两个连接端子122，沿第二方向Y在参考平面上的投影不重合，使得沿第一方向X的两个相邻端子交相错开，进而在第二方向Y上相邻的两个连接端子122的间距至少增大一倍，降低了连接端子122区内连接端子122的密度，进而提高了连接端子122与IC端子的对位容错率，能够改善产品良率。
请参阅图2，图2为本申请实施例提供的阵列基板10的第二种截面示意图。
在本申请一种实施例中，所述连接端子122区包括至少两个子区域12a，所述子区域12a内的连接端子122沿所述第二方向Y在所述参考平面上的投影重合。
通过所述子区域12a内的连接端子122沿所述第二方向Y在所述参考平面上的投影重合的限制，能够将所述连接端子122在所述连接端子122区内规律排布，提升了阵列基板10的制作效率。
在本申请一种实施例中，所述子区域12a内的连接端子122尺寸相同。
在本申请一种实施例中，所述子区域12a内的连接端子122在同一道工艺中形成，本实施例能够在不增加连接端子122工艺制程的基础上提升连接端子122与IC端子绑定的良率。
请参阅图3，图3为本申请实施例提供的保护盖板的第三种截面示意图。
在本申请一种实施例中，沿所述第一方向X，相邻子区域12a内的连接端子122沿所述第二方向Y在所述参考平面上的投影连接。
当所述连接端子122区包括两个子区域12a时，相邻子区域12a内的连接端子122沿所述第二方向Y在所述参考平面上的投影部分重叠或连接；当所述连接端子122区包括两个以上子区域12a时，至少存在相邻子区域12a内的连接端子122沿所述第二方向Y在所述参考平面上的投影部分重叠或恰好连接。
在本申请一种实施例中，沿所述第一方向X，所有相邻子区域12a内的连接端子122沿所述第二方向Y在所述参考平面上的投影连接。
即无论所述连接端子122区包括两个子区域12a还是包括两个以上子区域12a时，所有相邻子区域12a内的连接端子122沿所述第二方向Y在所述参考平面上的投影部分重叠或连接。
请参阅图4，图4为本申请实施例提供的阵列基板10的第四种截面示意图。
在本申请一种实施例中，为了进一步提高连接端子122和IC端子绑定时的容错率，本申请设置沿所述第一方向X，相邻子区域12a内的连接端子122沿所述第二方向Y在所述参考平面上的投影之间存在间隙。
当所述连接端子122区包括两个子区域12a时，相邻子区域12a内的连接端子122沿所述第二方向Y在所述参考平面上的投影之间存在间距；当所述连接端子122区包括两个以上子区域12a时，至少存在相邻子区域12a内的连接端子122沿所述第二方向Y在所述参考平面上的投影之间存在间距，即也可能存在相邻子区域12a内的连接端子122沿所述第二方向Y在所述参考平面上的投影部分重叠或连接。具体可根据实际需求进行设置。
在本申请一种实施例中，沿所述第一方向X，所有相邻子区域12a内的连接端子122沿所述第二方向Y在所述参考平面上的投影之间存在间隙。
即无论所述连接端子122区包括两个子区域12a还是包括两个以上子区域12a时，所有相邻子区域12a内的连接端子122沿所述第二方向Y在所述参考平面上的投影之间均存在间隙。
在一种实施例中，沿所述第一方向X，所有相邻子区域12a内的连接端子122沿所述第二方向Y在所述参考平面上的投影之间间隙大小相同。
在一种实施例中，沿所述第二方向Y，所有相邻子区域12a连接端子122之间的间隙大小相同。即相邻子区域12a连接端子122之间等距设置。
在一种实施例中，所述阵列基板10还包括绝缘层，所述绝缘层覆盖所述信号转换线121。所述绝缘层对所述信号转换线121进行绝缘保护以避免所述信号转换线121与其它金属接触导致短路。
在一种实施例中，本申请实施例提供了一种显示面板，如液晶显示面板等，所述显示面板包括阵列基板，所述阵列基板包括：
显示区；
绑定区，设置于所述显示区一端，包括信号转换区以及连接端子区；所述信号转换区设置有信号转换线，所述连接端子区设置有连接端子，所述信号转换线与所述连接端子对应连接；
其中，所述信号转换线沿第一方向延伸，连接相邻信号转换线的两个连接端子，沿第二方向在参考平面上的投影不重合，所述参考平面平行于所述第一方向、且垂直于所述连接端子设置面，所述第二方向垂直于所述参考平面。
在一种实施例中，在本申请的显示面板中，所述连接端子区包括至少两个子区域，所述子区域内的连接端子沿所述第二方向在所述参考平面上的投影重合。
在一种实施例中，在本申请的显示面板中，所述子区域内的连接端子尺寸相同。
在一种实施例中，在本申请的显示面板中，所述子区域内的连接端子在同一道工艺中形成。
在一种实施例中，在本申请的显示面板中，沿所述第一方向，相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影连接。
在一种实施例中，在本申请的显示面板中，沿所述第一方向，所有相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影连接。
在一种实施例中，在本申请的显示面板中，沿所述第一方向，相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影之间存在间隙。
在一种实施例中，在本申请的显示面板中，沿所述第一方向，所有相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影之间存在间隙。
在一种实施例中，在本申请的显示面板中，沿所述第一方向，所有相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影之间间隙大小相同。
在一种实施例中，在本申请的显示面板中，沿所述第二方向，所有相邻子区域连接端子之间的间隙大小相同。
根据上述实施例可知：
本申请提供了一种新的阵列基板以及显示面板，该阵列基板包括显示区和位于所述显示区一端的绑定区，所述绑定区包括对应连接的信号转换线和连接端子，其中，所述信号转换线沿第一方向X延伸，连接相邻信号转换线的两个连接端子，沿第二方向在参考平面上的投影不重合；这样，相邻连接端子交相错开的设计能够增大相邻连接端子之间的间距，解决了现有阵列基板连接端子间距过小，在绑定时易发生短路造成绑定不良的问题。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，其包括：
    显示区；
    绑定区，设置于所述显示区一端，包括信号转换区以及连接端子区；所述信号转换区设置有信号转换线，所述连接端子区设置有连接端子，所述信号转换线与所述连接端子对应连接；
    其中，所述信号转换线沿第一方向延伸，连接相邻信号转换线的两个连接端子，沿第二方向在参考平面上的投影不重合，所述参考平面平行于所述第一方向、且垂直于所述连接端子设置面，所述第二方向垂直于所述参考平面。
  2. 根据权利要求1所述的阵列基板，其中，所述连接端子区包括至少两个子区域，所述子区域内的连接端子沿所述第二方向在所述参考平面上的投影重合。
  3. 根据权利要求2所述的阵列基板，其中，所述子区域内的连接端子尺寸相同。
  4. 根据权利要求2所述的阵列基板，其中，所述子区域内的连接端子在同一道工艺中形成。
  5. 根据权利要求2所述的阵列基板，其中，沿所述第一方向，相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影连接。
  6. 根据权利要求2所述的阵列基板，其中，沿所述第一方向，所有相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影连接。
  7. 根据权利要求2所述的阵列基板，其中，沿所述第一方向，相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影之间存在间隙。
  8. 根据权利要求2所述的阵列基板，其中，沿所述第一方向，所有相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影之间存在间隙。
  9. 根据权利要求8所述的阵列基板，其中，沿所述第一方向，所有相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影之间间隙大小相同。
  10. 根据权利要求2所述的阵列基板，其中，沿所述第二方向，所有相邻子区域连接端子之间的间隙大小相同。
  11. 一种显示面板，其包括阵列基板，所述阵列基板包括：
    显示区；
    绑定区，设置于所述显示区一端，包括信号转换区以及连接端子区；所述信号转换区设置有信号转换线，所述连接端子区设置有连接端子，所述信号转换线与所述连接端子对应连接；
    其中，所述信号转换线沿第一方向延伸，连接相邻信号转换线的两个连接端子，沿第二方向在参考平面上的投影不重合，所述参考平面平行于所述第一方向、且垂直于所述连接端子设置面，所述第二方向垂直于所述参考平面。
  12. 根据权利要求11所述的显示面板，其中，所述连接端子区包括至少两个子区域，所述子区域内的连接端子沿所述第二方向在所述参考平面上的投影重合。
  13. 根据权利要求12所述的显示面板，其中，所述子区域内的连接端子尺寸相同。
  14. 根据权利要求12所述的显示面板，其中，所述子区域内的连接端子在同一道工艺中形成。
  15. 根据权利要求12所述的显示面板，其中，沿所述第一方向，相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影连接。
  16. 根据权利要求12所述的显示面板，其中，沿所述第一方向，所有相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影连接。
  17. 根据权利要求12所述的显示面板，其中，沿所述第一方向，相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影之间存在间隙。
  18. 根据权利要求12所述的显示面板，其中，沿所述第一方向，所有相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影之间存在间隙。
  19. 根据权利要求18所述的显示面板，其中，沿所述第一方向，所有相邻子区域内的连接端子沿所述第二方向在所述参考平面上的投影之间间隙大小相同。
  20. 根据权利要求12所述的显示面板，其中，沿所述第二方向，所有相邻子区域连接端子之间的间隙大小相同。
PCT/CN2019/082394 2018-12-18 2019-04-12 阵列基板以及显示面板 Ceased WO2020124888A1 (zh)

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