WO2020124638A1 - 阵列基板、制备阵列基板的方法和显示终端 - Google Patents

阵列基板、制备阵列基板的方法和显示终端 Download PDF

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WO2020124638A1
WO2020124638A1 PCT/CN2018/123870 CN2018123870W WO2020124638A1 WO 2020124638 A1 WO2020124638 A1 WO 2020124638A1 CN 2018123870 W CN2018123870 W CN 2018123870W WO 2020124638 A1 WO2020124638 A1 WO 2020124638A1
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substrate
shielding metal
pixel electrode
array substrate
transparent conductive
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PCT/CN2018/123870
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English (en)
French (fr)
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姚宇
李敏
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惠科股份有限公司
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Publication of WO2020124638A1 publication Critical patent/WO2020124638A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a method of preparing the array substrate, and a display terminal.
  • liquid crystal display technology Liquid Crystal Display, referred to as LCD
  • CRT cathode Ray Tube
  • a liquid crystal display panel includes a color filter substrate and an array substrate facing the color filter substrate, and liquid crystal is provided between the color filter substrate and the array substrate.
  • the conventional array substrate generally includes a shielding metal and a pixel electrode provided on the shielding metal.
  • dark lines may be generated on the side of the pixel electrode close to the shielding metal, which affects the display effect.
  • an array substrate a method of preparing the array substrate, and a display terminal are provided.
  • An array substrate can be applied to a liquid crystal display panel.
  • the array substrate includes:
  • the substrate is provided with a thin film transistor
  • Shielding metal which is arranged on the substrate and blocks the channel of the thin film transistor
  • the pixel electrode is arranged on the shielding metal
  • a method for preparing an array substrate includes:
  • the shielding metal shields the channel of the thin film transistor
  • a display terminal including:
  • Equipment body including multiple functional devices
  • a display panel covering the device body and connected to the multiple functional devices
  • the display panel includes the array substrate according to any one of claims 1 to 4.
  • the display panel further includes a color filter substrate and a liquid crystal layer;
  • the color filter substrate and the array substrate are disposed on both sides of the liquid crystal layer.
  • FIG. 1 is a schematic structural diagram of an array substrate in an embodiment
  • FIG. 2 is a schematic structural diagram of an array substrate in conventional technology
  • FIG. 3 is a flowchart of a method for preparing an array substrate in an embodiment
  • 4 to 5 are schematic structural flowcharts of preparing an array substrate in an embodiment.
  • the array substrate may include at least a base provided with a thin film transistor, a shield metal, and a pixel electrode; wherein, the shield metal may be provided on the base and shield the channel of the thin film transistor, thereby avoiding light leakage current.
  • the pixel electrode may be disposed above the shielding metal.
  • the shielding metal and the pixel electrode should be located in different film layers and are offset from each other, that is, there should be a gap of a predetermined size between the projection of the shielding metal on the substrate and the projection of the pixel electrode on the substrate.
  • the substrate, the shielding metal, and the pixel electrode are only for the minimum film structure required by the array substrate in the process of achieving the purpose of the present application.
  • the above embodiments The array substrate in can also add other functional film structures or functional devices according to actual needs.
  • the pixel electrode needs to be disposed above the shielding metal, and it is ensured that the pixel electrode and the shielding metal are located in different film structures.
  • other film layer structures such as an insulating layer may be provided between the pixel electrode and the shielding metal.
  • the pixel electrode may also be formed in the upper layer of the shielding metal.
  • the non-overlap ensures that the shielding metal and the pixel electrode cannot form a capacitive structure, which makes there is no electric field line distribution between the shielding metal and the pixel electrode when the array substrate is powered on, which greatly eliminates the edge effect of the electric field, thus making The edge part of the pixel electrode does not cause dark lines.
  • the preset gap between the projection of the shielding metal on the substrate and the projection of the pixel electrode on the substrate may be represented by D, obviously D is greater than or equal to 0 ⁇ m, in order to ensure that the gap does not reach There is a problem of light leakage, so D can also be set to 10 ⁇ m or less.
  • a metal material may be used to prepare the shielding film layer.
  • the shielding properties of metals such as molybdenum, copper, and silver are better than other metals, so pure metal or alloys of molybdenum, copper, and silver can be used to prepare the shielding film.
  • it is a better choice to use copper to prepare the shielding film layer because copper is more readily available than other metals, and it is relatively cheaper to use copper to prepare the shielding metal. Has a better economic effect.
  • the material of the pixel electrode may be indium tin oxide (ITO).
  • ITO indium tin oxide
  • the pixel electrode can have higher conductivity, higher visible light transmittance, higher mechanical hardness, and good chemical stability.
  • the material of the pixel electrode may also be indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO).
  • the array substrate may further include an insulating layer disposed on the shielding metal; the pixel electrode may be disposed on the insulating layer.
  • the shielding metal may also be a ring-shaped structure in which there is a hollow area.
  • the pixel electrode may be disposed at a position above the shielding metal corresponding to the hollow region, that is, the projection of the pixel electrode on the substrate may pass through the hollow region.
  • This embodiment provides a method for preparing an array substrate, which can be used to prepare the array substrate in the above embodiments.
  • the above method may include the following steps:
  • Step S1 providing a substrate provided with a thin film transistor.
  • the substrate may be prepared first, so as to form each film layer structure on the substrate later.
  • Step S2 preparing a shielding metal on the substrate; the shielding metal shields the channel of the thin film transistor.
  • a shielding metal may be formed on the substrate, and the shielding metal may shield the channel of the thin film transistor to prevent light leakage current.
  • this step specifically includes but is not limited to: forming the shielding metal directly on the substrate, forming the shielding metal and other devices on the substrate together, and the shielding metal and the other device are in the same film structure in.
  • Step S3 preparing a transparent conductive film on the shielding metal.
  • a transparent conductive thin film may be prepared in any film layer located above the shielding metal.
  • the transparent conductive film and the shielding metal are located in different film structures, and there may be one, two, or multiple other film structures between the transparent conductive film and the shielding metal.
  • Step S4 preparing a pixel electrode according to the transparent conductive film.
  • an etching process including but not limited to wet etching may be used to etch the transparent conductive film, and the portion of the transparent conductive film that overlaps with the shielding metal is removed, and Finally, the remaining transparent conductive film, that is, the projection of the pixel electrode on the substrate and the projection of the shielding metal on the substrate have a predetermined gap.
  • This embodiment provides another method for preparing an array substrate, which may specifically include: preparing a substrate provided with a thin film transistor; preparing a shielding metal on the substrate, the shielding metal is a ring structure having a hollow region, and the channel of the thin film transistor Block it; prepare a pixel electrode above the shielding metal.
  • a preset gap may be provided between the projection of the shielding metal on the substrate and the projection of the pixel electrode on the substrate by increasing the inner diameter of the hollow area and/or reducing the size of the pixel electrode.
  • the conventional photomask used to form the shielding metal can be enlarged so that the formed shielding metal has a larger hollow area than the conventional shielding metal, which makes the vertical In the direction of the substrate, the pixel electrode can be located in the hollow area, which ensures that there is no overlap between the pixel electrode and the shielding metal.
  • the pixel electrode can be located in the hollow area on the shielding metal, ensuring that there is no overlap between the pixel electrode and the shielding metal.
  • FIG. 1 is a schematic structural diagram of an array substrate in an embodiment. As shown in FIG. 1, this embodiment provides an array substrate for use in a liquid crystal display panel.
  • the array substrate may include thin film transistors (not shown in the figure). ) Of the substrate 10, the shielding metal 11, and the pixel electrode 12.
  • the shielding metal 11 may be disposed on the substrate 10, and the pixel electrode 12 may be disposed above the shielding metal 11.
  • the shielding metal 11 may be directly coated on the substrate 10 over the entire surface, or it may be located in the same film layer structure as other devices such as black shading blocks (not shown).
  • the pixel electrode 12 and the shielding metal 11 are located in different film structures, and the projection of the pixel electrode 12 on the substrate 10 and the shielding metal 11 on the substrate 10 in a direction perpendicular to the extension of the substrate 10 There is a gap of a preset size between the projections of, that is, when the array substrate is powered on, the shielding metal 11 does not form a capacitive structure with the pixel electrode 12.
  • a buffer layer (not shown in the figure), an insulating layer (not shown in the figure) and other film layer structures may be provided between the pixel electrode 12 and the shielding metal 11 as long as the shielding metal 11 It is not necessary to form a capacitive structure with the pixel electrode 12, that is, when electric current is applied, no electric field lines are formed between the shielding metal 11 and the pixel electrode 12.
  • FIG. 2 is a schematic structural diagram of an array substrate in the conventional technology.
  • the array substrate may include a shield metal 20 and a pixel electrode 21 located above the shield metal.
  • the shielding metal 20 and the pixel electrode 21 there is an overlap between the shielding metal 20 and the pixel electrode 21, that is, the shielding metal and the pixel electrode form a capacitive structure, which causes an electric field to be generated between the shielding film layer and the pixel electrode after the array substrate is powered on line.
  • the electric field lines at the edge of the pixel electrode 21 will change the original linear shape into a curved shape, which makes the liquid crystal distributed at the curved electric field lines (not shown in the figure)
  • the tilt direction of the liquid crystal that is distributed at the linear electric field line is inconsistent, resulting in a difference between light and dark, that is, dark lines are generated at the edge.
  • the preset gap D between the projection of the shielding metal 11 on the substrate 10 and the projection of the pixel electrode 12 on the substrate 10 It should be as large as possible. However, if the predetermined gap is too large, the problem of light leakage is likely to occur. Therefore, D can be set to be greater than or equal to 0 ⁇ m and less than or equal to 10 ⁇ m; for example, 0, 2 ⁇ m, 4 ⁇ m, 6 ⁇ m, 8 ⁇ m, or 10 ⁇ m.
  • the shielding metal 11 may be a metal material such as molybdenum, copper, silver, etc. so that the shielding metal 11 can better perform a shielding function.
  • the material of the pixel electrode 12 may also be ITO.
  • FIG. 3 is a flowchart of a method for preparing an array substrate in an embodiment. As shown in FIG. 3, based on the array substrate in the above embodiment, this embodiment provides a method for preparing an array substrate. The method may include the following steps:
  • Step S1 providing a substrate provided with a thin film transistor.
  • FIGS. 4 to 5 are schematic structural flow diagrams of fabricating an array substrate in an embodiment.
  • the base 40 may be made of materials such as glass, metal, or polyethylene terephthalate (PET). ), polyethylene naphthalate (PEN), polyimide, or other plastic material is formed of a suitable material, and a thin film transistor (not shown) may be provided on the substrate.
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • polyimide polyimide
  • a thin film transistor not shown
  • Step S2 preparing a shielding metal on the substrate; the shielding metal shields the channel of the thin film transistor.
  • a shielding metal 41 can be formed on the substrate 40 by a PVD (physical vapor deposition, including evaporation and sputtering, etc.), and the shielding metal 41 should be able to shield the channel of the thin film transistor to avoid light generation Leakage current.
  • PVD physical vapor deposition, including evaporation and sputtering, etc.
  • Step S3 preparing a transparent conductive film on the shielding metal.
  • a device film layer such as a buffer layer 42 and an insulating layer 43 may be sequentially formed on the shielding metal 41, and then a transparent conductive film 44 is formed on the insulating layer 43.
  • the transparent conductive film 44 may use a transparent conductive metal material such as indium tin oxide (ITO), so that the transparent conductive film has high conductivity, high visible light transmittance, high mechanical hardness, and good chemical stability.
  • the material of the transparent conductive film 44 may also be indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO).
  • Step S4 preparing a pixel electrode according to the transparent conductive film.
  • a passivation layer 45 may be formed on the transparent conductive film 44, wherein, in a direction parallel to the substrate 40, the projection of the passivation layer 45 on the substrate 40 and the projection of the shielding metal 41 on the substrate 40 There is a preset gap between them.
  • the transparent conductive film 44 may be wet-etched to etch away the portion of the transparent conductive film 44 that is not covered by the passivation layer 45, thereby forming the pixel electrode 50 as shown in FIG. Further, the passivation layer 45 can be removed. Thus, in the direction parallel to the substrate 40, the above-mentioned predetermined gap is provided between the projection of the shielding metal 41 on the substrate 40 and the projection of the pixel electrode 50 on the substrate 40.
  • the shielding metal and the pixel electrode are formed successively so that there is a predetermined gap between the projection of the shielding metal on the substrate and the projection of the pixel electrode on the substrate in a direction parallel to the substrate, that is, there is no overlap , To ensure that there is no electric field line distribution between the shielding metal and the pixel electrode, which greatly eliminates the edge effect of the electric field, so that no dark lines will occur at the edge of the pixel electrode.
  • a liquid crystal display panel which may specifically include: an array substrate, a color film substrate, and a liquid crystal layer; wherein the color film substrate and the array substrate are disposed on both sides of the liquid crystal layer.
  • the array substrate may further specifically include: a base, provided with a thin film transistor; a shielding metal, provided on the base, and shielding the channel of the thin film transistor; a pixel electrode, provided on the shielding metal; wherein, the shielding metal is on the base There is a preset gap between the projection of the pixel and the projection of the pixel electrode on the substrate.
  • the display terminal may be an electronic device with a display function such as a mobile phone, a computer, or a watch. Further, the display terminal may specifically include: a device body including multiple functional devices; a liquid crystal display panel, Covered on the device body and connected with multiple functional devices. Specifically, the liquid crystal display panel can be overlaid on the device body for displaying pictures; the device body can also be provided with functional devices such as a brightness adjustment key and a power key, and can be connected with the liquid crystal display panel to control the display brightness of the liquid crystal display panel , Switches, etc.
  • the liquid crystal display panel may specifically include: an array substrate, a color filter substrate, and a liquid crystal layer; wherein, the color filter substrate and the array substrate are disposed on both sides of the liquid crystal layer.
  • the array substrate may further specifically include: a base provided with a thin film transistor; a shield metal provided on the base and shielding the channel of the thin film transistor; a pixel electrode provided on the shield metal; wherein the shield metal is provided on the base There is a preset gap between the projection of the pixel and the projection of the pixel electrode on the substrate.

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Abstract

一种阵列基板，所述阵列基板包括：基底，设置有薄膜晶体管；屏蔽金属，设置于所述基底上，且对所述薄膜晶体管的沟道予以遮挡；像素电极，设置于所述屏蔽金属之上；其中，所述屏蔽金属在所述基底上的投影与所述像素电极在所述基底上的投影之间具有预设间隙。

Description

阵列基板、制备阵列基板的方法和显示终端 技术领域
本申请涉及显示技术领域，特别是涉及一种阵列基板、制备阵列基板的方法和显示终端。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成示例性技术。
随着社会不断发展，液晶显示技术(Liquid Crystal Display，简称LCD)已代替阴极射线显像技术(Cathode Ray Tube，简称CRT)成为主流。
一般地，液晶显示面板包括彩膜基板和与该彩膜基板对盒的阵列基板，在该彩膜基板与阵列基板之间设置有液晶。
传统的阵列基板一般包括屏蔽金属和设置于屏蔽金属之上的像素电极，然而，在阵列基板通电后，在像素电极靠近屏蔽金属的一侧可能产生暗纹，影响显示效果。
发明内容
根据本申请的各种实施例，提供一种阵列基板、制备阵列基板的方法和显示终端。
一种阵列基板，可应用于液晶显示面板中，所述阵列基板包括：
基底，设置有薄膜晶体管；
屏蔽金属，设置于所述基底上，且对所述薄膜晶体管的沟道予以遮挡；
像素电极，设置于所述屏蔽金属之上；
其中，所述屏蔽金属在所述基底上的投影与所述像素电极在所述基底上的投影之间具有预设间隙。
一种制备阵列基板的方法，包括：
提供设置有薄膜晶体管的基底；
于所述基底上方制备屏蔽金属；所述屏蔽金属对所述薄膜晶体管的沟道予以遮挡；
于所述屏蔽金属上方制备像素电极；
其中，所述屏蔽金属在所述基底上的投影与所述像素电极在所述基底上的投影之间具有预设间隙。
一种显示终端，包括：
设备本体，包括多个功能器件；
显示面板，覆盖在所述设备本体上，并与所述多个功能器件连接；
其中，所述显示面板包括如权利要求1至4任意一项所述的阵列基板。
在其中一个实施例中，所述显示面板还包括彩膜基板和液晶层；
其中，所述彩膜基板与所述阵列基板设置在所述液晶层的两侧。
在上述阵列基板、制备阵列基板的方法和显示终端中，通过改变屏蔽金属与像素电极的相对位置，使得在平行于基底的方向上，屏蔽金属在基底上的投影与像素电极在基底上的投影之间具有预设间隙，也即不重叠，确保了屏蔽金属与像素电极之间不会有电场线分布，极大地消除了电场的边缘效应，从而使像素电极边缘处不会产生暗纹问题。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或示例性技术中的技术方案，下面将对实施例或示例性技术描述中所需要使用的附图作简单地介绍，显而易见地， 下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一个实施例中阵列基板的结构示意图；
图2为传统技术中阵列基板的结构示意图；
图3为一个实施例中制备阵列基板的方法的流程图；
图4至图5为一个实施例中制备阵列基板的结构流程示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本实施例提供一种阵列基板，尤其是一种设置在液晶显示面板中的阵列基板。具体地，该阵列基板可以至少包括设置有薄膜晶体管的基底、屏蔽金属和像素电极；其中，屏蔽金属可以是设置在基底上并对薄膜晶体管的沟道予以遮挡，从而避免产生光照漏电流。像素电极可以是设置在屏蔽金属上方。特别地，屏蔽金属和像素电极应位于不同的膜层结构中且相互错开，也即屏蔽金属在基底上的投影与像素电极在基底上的投影之间应具有一预设大小的间隙。
本领域技术人员可以理解，基底、屏蔽金属和像素电极仅是为了实现本申请目的过程中，阵列基板所需具有的最少膜层结构，然而，为了使得阵列基板具有更丰富的功能，上述实施例中的阵列基板还可以依据实际需要而增加其他功能性的膜层结构或者是功能器件。
在上述实施例中，像素电极需要设置在屏蔽金属上方，并且保证像素电极和屏蔽金属位于不同的膜层结构中。然而，可以理解的是，像素电极与屏蔽金属之间可以设置有如绝缘层等其他膜层结构。在一个实施例中，也可以是将像素电极形成于屏蔽金属的上一层膜层中，此时，应当理解，为了保证 像素电极在基底上的投影与屏蔽膜层在基底上的投影之间有预设间隙，屏蔽金属应与其他器件位于同一膜层结构中，且像素电极可以是形成在该其他器件上。
在上述阵列基板中，通过改变屏蔽金属与像素电极的相对位置，使得在平行于基底的方向上，屏蔽金属在基底上的投影与像素电极在基底上的投影之间具有预设间隙，也即不重叠，确保了屏蔽金属与像素电极无法构成电容结构，这就使得当阵列基板通电后，在屏蔽金属与像素电极之间不会有电场线分布，极大地消除了电场的边缘效应，从而使像素电极的边缘部分不会产生暗纹问题。
在一个实施例中，可以将屏蔽金属在基底上的投影与像素电极在基底上的投影之间的预设间隙用D进行表示，显然D是大于等于0μm的，为了保证在该间隙出不至于产生漏光问题，故还可以设置D小于等于10μm。
在一个实施例中，为了使得屏蔽膜层能够具备良好的屏蔽特性，可以采用金属材料制备屏蔽膜层。一般而言，钼、铜、银等金属的屏蔽特性相对其他金属而言要更好，故可以采用钼、铜、银的纯金属或者是合金制备屏蔽膜层。然而，在一个优选的实施例中，采用铜制备屏蔽膜层是一个较佳的选择，这是因为铜相对其他金属更为易得，且才用铜制备屏蔽金属相对而言要更为廉价，具有更好的经济效应。
在一个实施例中，为了使像素电极能够透光，像素电极的材质可以是铟锡氧化物(ITO)。当像素电极的材质为铟锡氧化物时，像素电极可以具备更高的导电率、更高的可见光透过率、更高的机械硬度和良好的化学稳定性。当然，在其他实施例中，像素电极的材质也可以为氧化铟锌(IZO)、氧化锌(ZnO)、氧化铟(In2O3)、氧化铟镓(IGO)或氧化铝锌(AZO)等。
在一个实施例中，阵列基板还可以包括设置于屏蔽金属上的绝缘层；像素电极可以设置在该绝缘层上。屏蔽金属还可以是环形结构，在该环形结构中有一中空区域。像素电极可以设置屏蔽金属上方对应该中空区域的位置处，也即使得像素电极在基底上的投影可以穿过该中空区域。
本实施例提供一种制备阵列基板的方法，该方法可以用于制备上述实施例中的阵列基板。上述方法可以包括如下的步骤：
步骤S1:提供设置有薄膜晶体管的基底。
具体地，可以先制备基底，以便于后续再该基底上形成各膜层结构。
步骤S2：于基底上制备屏蔽金属；屏蔽金属对薄膜晶体管的沟道予以遮挡。
具体地，在制备基底后，可以在基底上形成屏蔽金属，并且，该屏蔽金属可以对薄膜晶体管的沟道予以遮挡以防止产生光照漏电流。本领域技术人员可以理解，本步骤具体包括但不限于：将屏蔽金属直接整面形成于基底上、将屏蔽金属与其他器件共同形成在基底上且该屏蔽金属与该其他器件位于同一膜层结构中。
步骤S3：于屏蔽金属上方制备透明导电薄膜。
具体地，在形成屏蔽金属之后，可以在位于屏蔽金属上方的任一膜层中制备透明导电薄膜。本领域技术人员可以理解，透明导电薄膜和屏蔽金属是位于不同的膜层结构中的，并且，透明导电薄膜与屏蔽金属之间可以设置有一层、两层或多层其他膜层结构。
步骤S4：根据透明导电薄膜制备像素电极。
具体地，在形成了透明导电薄膜后，可以采用包括但不限于湿法刻蚀等刻蚀工艺对透明导电薄膜进行刻蚀，并将透明导电薄膜中与屏蔽金属相互重叠的部分予以去除，并最终使得剩余的透明导电薄膜，也即像素电极在基底上的投影与屏蔽金属在基底上的投影之间具有预设间隙。
在上述制备阵列基板的方法中，通过改变屏蔽金属与像素电极的相对位置，使得在平行于基底的方向上，屏蔽金属在基底上的投影与像素电极在基底上的投影之间具有预设间隙，也即不重叠，确保了屏蔽金属与像素电极无法构成电容结构，这就使得当阵列基板通电后，在屏蔽金属与像素电极之间不会有电场线分布，极大地消除了电场的边缘效应，从而使像素电极的边缘部分不会产生暗纹问题。
本实施例提供另一种制备阵列基板的方法，可以具体包括：制备设置有薄膜晶体管的基底；于基底上制备屏蔽金属，屏蔽金属为具有中空区域的环状结构，且对薄膜晶体管的沟道予以遮挡；于屏蔽金属上方制备像素电极。在本实施例中，可以通过增大中空区域的内径和/或减小像素电极的尺寸来使得屏蔽金属在基底上的投影与像素电极在基底上的投影之间具有预设间隙。
具体地，在一个实施例中，可以通过加大传统的用于形成屏蔽金属的光罩，使得形成的屏蔽金属相对传统的屏蔽金属而言具有更大内径的中空区域，这就使得在垂直于基底的方向上，像素电极可以位于该中空区域内，保证了像素电极和屏蔽金属之间不会有重叠。在其他实施例中，也可以通过减小传统的用于形成像素电极的光罩，使得形成的像素电极相对传统的像素电极而言具有更小的尺寸，这就使得在垂直于基底的方向上，像素电极可以位于屏蔽金属上的中空区域内，保证了像素电极和屏蔽金属之间不会有重叠。
为了使本领域技术人员充分理解本申请，以下结合附图对本申请进行进一步解释说明。
图1为一个实施例中阵列基板的结构示意图，如图1所示，本实施例提供一种阵列基板，应用在液晶显示面板中，该阵列基板可以包括设置有薄膜晶体管(图中未示出)的基底10、屏蔽金属11和像素电极12。其中，屏蔽金属11可以设置在基底10上，像素电极12可以设置在屏蔽金属11上方。
在一个实施例中，屏蔽金属11可以直接整面涂覆在基底10上，也可以同例如黑色遮光块(图中未示出)等其他器件位于同一膜层结构中。
在一个实施例中，像素电极12与屏蔽金属11位于不同的膜层结构中，并且，在垂直于基板10延展的方向上，像素电极12在基板10上的投影与屏蔽金属11在基板10上的投影之间具有预设大小的间隙，也即，在阵列基板通电时，屏蔽金属11不与像素电极12形成电容结构。然而，本领域技术人员应当知晓，像素电极12与屏蔽金属11之间还可以设置有缓冲层(图中未示出)、绝缘层(图中未示出)等膜层结构，只要屏蔽金属11不与像素电极12形成电容结构，也即在通电时，屏蔽金属11与像素电极12之间无电场线 形成即可。
如图2为传统技术中阵列基板的结构示意图。如图2所示，在传统技术中，阵列基板可以包括屏蔽金属20和位于屏蔽金属上方的像素电极21。具体地，屏蔽金属20与像素电极21之间具有重叠部分，也就是说，屏蔽金属与像素电极形成了电容结构，这就使得在阵列基板通电后，屏蔽膜层与像素电极之间会生成电场线。然而，由于电场的边缘效应，位于像素电极21边缘处的电场线将改变原有的直线状，变成弯曲状，这就使得分布在该弯曲状电场线处的液晶(图中未示出)与分布在直线状电场线处的液晶倾倒方向不一致，从而造成亮暗差异，也即在该边缘处产生暗纹。
而如图1所示，在上述实施例中，通过改变屏蔽金属与像素电极的相对位置，使得在垂直于所述基底延展的方向上，屏蔽金属在基底上的投影与像素电极在基底上的投影之间具有预设间隙，也即不重叠，确保了屏蔽金属与像素电极之间不会有电场线分布，极大地消除了电场的边缘效应，从而使像素电极边缘处不会产生暗纹问题。
在一个实施例中，为了尽可能消除电场的边缘效应，于平行于基板10的方向上，屏蔽金属11在基底10上的投影与像素电极12在基底10上的投影之间的预设间隙D应尽可能的大。然而，若该预设间隙过大，又容易产生漏光的问题。故可以设置D大于等于0μm，且小于等于10μm；例如，0、2μm、4μm、6μm、8μm或10μm等。
在一个实施例中，屏蔽金属11可以是钼、铜、银等金属材质以使得屏蔽金属11能更好地起到屏蔽作用。在其他实施例中，像素电极12的材质也可以是ITO。
图3为一个实施例中制备阵列基板的方法的流程图。如图3所示，基于上述实施例中的阵列基板，本实施例提供一种制备阵列基板的方法，该方法可以包括如下步骤：
步骤S1：提供设置有薄膜晶体管的基底。
具体地，图4至图5为一个实施例中制备阵列基板的结构流程示意图， 如图4所示，基底40可以由诸如玻璃材料、金属材料或包括聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)或聚酰亚胺等的塑胶材料中合适的材料形成，且在基底上可以设置有薄膜晶体管(图中未示出)。
步骤S2：于基底上制备屏蔽金属；屏蔽金属对所述薄膜晶体管的沟道予以遮挡。
具体地，可以通过PVD(物理汽相沉积，包括蒸镀和溅镀等)方法在基底40上形成屏蔽金属41，且该屏蔽金属41应能够对薄膜晶体管的沟道予以遮挡，以避免产生光照漏电流。
步骤S3：于屏蔽金属上方制备透明导电薄膜。
在一些实施例中，在形成屏蔽金属41后，可以在屏蔽金属41上先依次形成缓冲层42、绝缘层43等器件膜层，再在绝缘层43上形成透明导电薄膜44。其中，透明导电薄膜44可以采用透明导电金属材料如铟锡氧化物(ITO)，以使得透明导电薄膜具有高的导电率、高的可见光透过率、高的机械硬度和良好的化学稳定性。在其他实施例中，透明导电薄膜44的材质也可以为氧化铟锌(IZO)、氧化锌(ZnO)、氧化铟(In2O3)、氧化铟镓(IGO)或氧化铝锌(AZO)。
步骤S4：根据透明导电薄膜制备像素电极。
在一个实施例中，可以在透明导电薄膜44上形成钝化层45，其中，在平行于基底40的方向上，钝化层45在基底40上的投影与屏蔽金属41在基底40上的投影之间有一预设间隙。
在一个实施例中，可以对透明导电薄膜44进行湿法刻蚀，从而将透明导电薄膜44上未被钝化层45覆盖的部分刻蚀掉，从而形成如图5所示的像素电极50。进一步地，可以将钝化层45去除。由此，在平行于基底40的方向上，屏蔽金属41在基底40上的投影与像素电极50在基底40上的投影之间具有上述的预设间隙。
在上述实施例中，通过先后形成屏蔽金属与像素电极，使得在平行于基底的方向上，屏蔽金属在基底上的投影与像素电极在基底上的投影之间具有预设间隙，也即不重叠，确保了屏蔽金属与像素电极之间不会有电场线分布， 极大地消除了电场的边缘效应，从而使像素电极边缘处不会产生暗纹问题。
本实施例提供一种液晶显示面板，可以具体包括：阵列基板、彩膜基板和液晶层；其中，彩膜基板与阵列基板设置在液晶层的两侧。该阵列基板还可以具体包括：基底，设置有薄膜晶体管；屏蔽金属，设置于基底上，且对薄膜晶体管的沟道予以遮挡；像素电极，设置于屏蔽金属之上；其中，屏蔽金属在基底上的投影与像素电极在基底上的投影之间具有预设间隙。
本实施例提供一种显示终端，该显示终端可以是手机、电脑、手表等具有显示功能的电子设备，进一步地，该显示终端可以具体包括：设备本体，包括多个功能器件；液晶显示面板，覆盖在设备本体上，并与多个功能器件连接。具体地，液晶显示面板可以覆盖在设备本体上用于显示画面；设备本体上还可以设置有亮度调节键、电源键等功能器件，并且可以与液晶显示面板连接，以控制液晶显示面板的显示亮度、开关等。在本实施例中，液晶显示面板可以具体包括：阵列基板、彩膜基板和液晶层；其中，彩膜基板与阵列基板设置在液晶层的两侧。该阵列基板还可以具体包括：基底，设置有薄膜晶体管；屏蔽金属，设置于基底上，且对薄膜晶体管的沟道予以遮挡；像素电极，设置于屏蔽金属之上；其中，屏蔽金属在基底上的投影与像素电极在基底上的投影之间具有预设间隙。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种阵列基板，所述阵列基板包括：
    基底，设置有薄膜晶体管；
    屏蔽金属，设置于所述基底上，且对所述薄膜晶体管的沟道予以遮挡；
    像素电极，设置于所述屏蔽金属上方；
    其中，所述屏蔽金属在所述基底上的投影与所述像素电极在所述基底上的投影之间具有预设间隙。
  2. 根据权利要求1所述的阵列基板，其中所述屏蔽金属和所述像素电极位于不同的膜层结构中。
  3. 根据权利要求1所述的阵列基板，其中，0≤D≤10μm，D为所述预设间隙。
  4. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括设置于所述屏蔽金属上的绝缘层；所述像素电极设置于所述绝缘层上；
    其中，所述屏蔽金属为环形结构，所述像素电极穿过所述环形结构的中空区域投影至所述基底上。
  5. 根据权利要求1所述的阵列基板，其中，所述屏蔽金属的材质包括钼、铜和银中的至少一种。
  6. 根据权利要求1所述的阵列基板，其中，所述像素电极的材质为铟锡氧化物。
  7. 根据权利要求1所述的阵列基板，其中，所述像素电极的材质为氧化铟锌、氧化锌、氧化铟、氧化铟镓以及氧化铝锌中的任意一种。
  8. 一种制备阵列基板的方法，包括：
    提供设置有薄膜晶体管的基底；
    于所述基底上方制备屏蔽金属；所述屏蔽金属对所述薄膜晶体管的沟道予以遮挡；
    于所述屏蔽金属上方制备像素电极；其中，所述屏蔽金属在所述基底上的投影与所述像素电极在所述基底上的投影之间具有预设间隙。
  9. 根据权利要求8所述的方法，其中，通过物理气相沉积方法实现所述于所述基底上方制备屏蔽金属的步骤。
  10. 根据权利要求8所述的方法，其中，所述于所述基底上方制备屏蔽金属的步骤，包括：
    将所述屏蔽金属直接整面形成于基底上。
  11. 根据权利要求8所述的方法，其中，所述于所述屏蔽金属上方制备像素电极的步骤，包括：
    于所述屏蔽金属上方制备透明导电薄膜；
    根据所述透明导电薄膜制备所述像素电极。
  12. 根据权利要求11所述的方法，其中，所述于所述屏蔽金属上方制备透明导电薄膜的步骤，包括：
    在形成所述屏蔽金属之后，在位于所述屏蔽金属上方的任一膜层中制备所述透明导电薄膜；
    其中，所述透明导电薄膜和所述屏蔽金属位于不同的膜层结构中；以及
    所述透明导电薄膜与所述屏蔽金属之间设置有一层、两层或多层其他膜层结构。
  13. 根据权利要求11所述的方法，其中，所述透明导电薄膜在所述基底上的投影与所述像素电极在所述基底上的投影部分重叠，所述根据所述透明导电薄膜制备像素电极的步骤，包括：
    采用刻蚀工艺去除所述透明导电薄膜中与所述屏蔽金属重叠的部分，以获得所述像素电极。
  14. 根据权利要求13所述的方法，其中，所述刻蚀工艺包括湿法刻蚀。
  15. 根据权利要求8所述的方法，其中，所述屏蔽金属为具有中空区域的环状结构；
    其中，所述预设间隙为通过增大所述中空区域的内径和/或减小所述像素电极的尺寸形成。
  16. 一种显示终端，包括：
    设备本体，包括多个功能器件；
    显示面板，覆盖在所述设备本体上，并与所述多个功能器件连接；
    其中，所述显示面板包括如权利要求1至7任意一项所述的阵列基板。
  17. 根据权利要求16所述的显示终端，其中，所述设备本体上设置有与所述显示面板连接的亮度调节键和电源键，所述亮度调节键用于控制所述显示面板的显示亮度，所述电源键用于控制所述显示面板的开关状态。
  18. 根据权利要求17所述的显示终端，其中，所述显示面板还包括彩膜基板和液晶层；
    其中，所述彩膜基板与所述阵列基板设置在所述液晶层的两侧。
PCT/CN2018/123870 2018-12-18 2018-12-26 阵列基板、制备阵列基板的方法和显示终端 WO2020124638A1 (zh)

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