WO2020118942A1 - 一种用以连续快速产生闪存接口讯号序列的方法 - Google Patents

一种用以连续快速产生闪存接口讯号序列的方法 Download PDF

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WO2020118942A1
WO2020118942A1 PCT/CN2019/078234 CN2019078234W WO2020118942A1 WO 2020118942 A1 WO2020118942 A1 WO 2020118942A1 CN 2019078234 W CN2019078234 W CN 2019078234W WO 2020118942 A1 WO2020118942 A1 WO 2020118942A1
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flash memory
instruction
flash
queue
continuously
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陈育鸣
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江苏华存电子科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

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  • the invention relates to the technical field of flash memory, in particular to a method for continuously and rapidly generating a sequence of flash memory interface signals.
  • Flash memory is a kind of long-life non-volatile (can retain the stored data information in case of power failure), data deletion is not a single byte but a fixed block.
  • the block size is generally 256KB to 20MB.
  • Flash memory is a variant of electronically erasable read-only memory. Unlike flash memory and EEPROM, EEPROM can be deleted and rewritten at the byte level rather than the entire chip erase and write, and most of the chips of flash memory require block erase. Because it can still save data when the power is off, flash memory is usually used to save setting information, such as saving information in the computer's BIOS (basic program), PDA, digital camera, etc.
  • BIOS basic program
  • the design of the current flash memory master control device requires the processor to perform multiple read and write operations on the registers of the flash memory master control module to complete the operation code control required by the flash memory instruction sequence when the read or write command is issued. Before the next round of instruction operations, you must first wait for the completion of the previous round of instructions. This method is not only time-consuming and inefficient, but also takes up a lot of processor resources. When you need to do frequent operations on flash memory, you cannot effectively improve the performance of the operation.
  • An object of the present invention is to provide a method for continuously and quickly generating a sequence of flash memory interface signals to solve the problems mentioned in the background art.
  • a method for continuously and rapidly generating a flash memory interface signal sequence including a main control chip, a flash memory storage controller and a flash memory control physical layer are provided in the main control chip,
  • the flash memory storage controller is provided with a flash memory control register and a flash memory interface controller, the flash memory control register is connected to the flash memory interface controller, the flash memory interface controller is connected to the flash memory control physical layer, and the flash memory control physical layer is also connected to multiple external Flash storage components.
  • the plurality of flash storage components include a first flash storage component, a second flash storage component, a third flash storage component, and an N-th flash storage component, where N is an integer greater than 3.
  • an instruction queue manager is also provided in the flash memory storage controller, and the instruction queue manager is connected to the flash memory control register.
  • the processor can write the next group of instruction groups to the queue.
  • the hardware directly calls the flash memory instruction sequence in the queue to quickly and freely issue arbitrary instructions to the flash memory component. sequence.
  • the beneficial effect of the present invention is that the present invention configures the flash memory instruction queue manager so that the main control end does not need to wait for the previous round of instructions when it needs to issue any commands such as read or write to the flash memory component.
  • the processor To complete, it is only necessary for the processor to continuously write multiple sets of register information in the instruction queue to the instruction queue manager until the queue is full.
  • the flash controller takes the next group from the queue Instruction group to run. After the instruction group in the queue is taken out, the processor can write the next group of instruction groups to the queue.
  • the hardware directly calls the instruction sequence of the flash memory in the queue to quickly and accurately The component issues any command sequence to effectively improve the working efficiency of the flash memory control module.
  • FIG. 1 is a schematic diagram of a flash memory control unit in the main control unit of the present invention without a flash memory instruction instruction queue manager;
  • FIG. 2 is a schematic diagram of a flash memory instruction unit configured with a flash memory instruction command queue manager in the main control of the present invention
  • FIG. 3 is a schematic diagram of the status of the flash memory control unit in the main control of the present invention without a flash memory instruction queue manager;
  • FIG 4 is another schematic diagram of the status of the flash memory control unit in the main control of the present invention without the configuration of the flash memory instruction queue manager;
  • FIG. 5 is a schematic diagram of the status of the flash memory control unit in the main control of the present invention, configured with a flash memory instruction queue manager;
  • FIG. 6 is another schematic diagram of the status of the flash memory control unit in the main control of the present invention and the configuration of the flash memory instruction queue manager.
  • the present invention provides a technical solution: a method for continuously and rapidly generating a flash memory interface signal sequence, including a main control chip 1, a flash memory storage controller 2 and a flash memory are provided in the main control chip 1 Controlling the physical layer 3, the flash memory storage controller 2 is provided with a flash memory control register 4 and a flash memory interface controller 5, the flash memory control register 4 is connected to the flash memory interface controller 5, and the flash memory interface controller 5 is connected to the flash memory control physics Layer 3, the flash control physical layer 3 is also connected to multiple external flash storage components; the multiple flash storage components include a first flash storage component 6, a second flash storage component 7, a third flash storage component 8, and an N-th flash storage Component, N is an integer greater than 3.
  • the flash memory storage controller 2 is also provided with an instruction queue manager 9, which is connected to the flash memory control register 4.
  • a method for continuously and rapidly generating a flash memory interface signal sequence is characterized by comprising the following steps:
  • the processor can write the next group of instruction groups to the queue.
  • the hardware directly calls the flash memory instruction sequence in the queue to quickly and freely issue arbitrary instructions to the flash memory component. sequence.
  • the present invention configures the flash memory instruction queue manager so that the main control end does not need to wait for the previous round of instructions to complete when it needs to issue any instructions such as read or write to the flash memory component, only the processor continuously
  • the instruction queue manager continues to write multiple sets of register information in the instruction queue until the queue is full.
  • the flash controller takes the next group of instructions from the queue to run.
  • the processor can write the next set of instruction sets to the queue. In this way, the hardware directly calls the flash instruction sequence in the queue, and quickly issues any instruction sequence to the flash component quickly and effectively, thereby effectively improving The working efficiency of the flash memory control module.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
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Abstract

一种用以连续快速产生闪存接口讯号序列的方法，配置闪存指令队列管理器,使主控端在需要对闪存组件发出读取或写入等任意指令时，不须等待前一轮指令完成，只需要由处理器连续对指令队列管理器持续写入多组寄存器信息于指令队列中直到队列全满；待前一轮闪存接口指令完成时，闪存控制器再由队列中取出下一组指令组来运行，当队列里的指令组被取出后，处理器便可以再向队列写入下一组指令组，如此藉由硬件直接调用队列里的闪存指令序列，快速无误的对闪存组件发出任意指令序列，藉以有效提升闪存主控模块之工作效能。

Description

一种用以连续快速产生闪存接口讯号序列的方法 技术领域
本发明涉及闪存技术领域，具体为一种用以连续快速产生闪存接口讯号序列的方法。
背景技术
闪存是一种长寿命的非易失性(在断电情况下仍能保持所存储的数据信息)的存储器，数据删除不是以单个的字节为单位而是以固定的区块为单位，区块大小一般为256KB到20MB。闪存是电子可擦除只读存储器的变种，闪存与EEPROM不同的是，EEPROM能在字节水平上进行删除和重写而不是整个芯片擦写，而闪存的大部分芯片需要块擦除。由于其断电时仍能保存数据，闪存通常被用来保存设置信息，如在电脑的BIOS(基本程序)、PDA、数码相机中保存资料等。
现行闪存主控装置设计在进行发出读取或写入指令操作时,需要由处理器对闪存主控模块之寄存器做多次读写动作以完成闪存指令序列所需之操作代码控制,并且在进行下一轮指令操作前,必须先等待前一轮指令完成.此方式不但耗时没效率,对于处理器资源之占用也非常巨大.在需要对闪存做频繁操作时无法有效提升操作性能。
发明内容
本发明的目的在于提供一种用以连续快速产生闪存接口讯号序 列的方法，以解决上述背景技术中提出的问题。
为实现上述目的，本发明提供如下技术方案：一种用以连续快速产生闪存接口讯号序列的方法，包括主控芯片,所述主控芯片内设置闪存储存控制器和闪存控制物理层，所述闪存储存控制器内设有闪存控制寄存器和闪存接口控制器，所述闪存控制寄存器连接闪存接口控制器，所述闪存接口控制器连接闪存控制物理层，所述闪存控制物理层还连接外部多个闪存储存组件。
优选的，多个闪存储存组件包括第一闪存储存组件、第二闪存储存组件、第三闪存储存组件、第N闪存储存组件，N为大于3的整数。
优选的，所述闪存储存控制器内还设有指令队列管理器，所述指令队列管理器连接闪存控制寄存器。
优选的，包括以下步骤：
A、配置闪存指令队列管理器,使主控端在需要对闪存组件发出读取或写入等任意指令时,不须等待前一轮指令完成；
B、只需要由处理器连续对指令队列管理器持续写入多组寄存器信息于指令队列中直到队列全满；
C、待前一轮闪存接口指令完成时,闪存控制器再由队列中取出下一组指令组来运行；
D、当队列里的指令组被取出后,处理器便可以再向队列写入下一组指令组.，如此藉由硬件直接调用队列里的闪存指令序列,快速无误的对闪存组件发出任意指令序列。
与现有技术相比，本发明的有益效果是：本发明配置闪存指令队列管理器,使主控端在需要对闪存组件发出读取或写入等任意指令时,不须等待前一轮指令完成,只需要由处理器连续对指令队列管理器持续写入多组寄存器信息于指令队列中直到队列全满.待前一轮闪存接口指令完成时,闪存控制器再由队列中取出下一组指令组来运行.，当队列里的指令组被取出后,处理器便可以再向队列写入下一组指令组.，如此藉由硬件直接调用队列里的闪存指令序列,快速无误的对闪存组件发出任意指令序列,藉以有效提升闪存主控模块之工作效能。
附图说明
图1为本发明主控内部的闪存控制单元,未配置闪存指令指令队列管理器示意图；
图2为本发明主控内部的闪存控制单元,配置闪存指令指令队列管理器示意图；
图3为本发明主控内部的闪存控制单元,未配置闪存指令指令队列管理器的状况示意图；
图4为本发明主控内部的闪存控制单元,未配置闪存指令指令 队列管理器的状况另一示意图；
图5为本发明主控内部的闪存控制单元,配置闪存指令指令队列管理器的状况示意图；
图6为本发明主控内部的闪存控制单元,配置闪存指令指令队列管理器的状况另一示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1-6，本发明提供一种技术方案：一种用以连续快速产生闪存接口讯号序列的方法,包括主控芯片1,所述主控芯片1内设置闪存储存控制器2和闪存控制物理层3，所述闪存储存控制器2内设有闪存控制寄存器4和闪存接口控制器5，所述闪存控制寄存器4连接闪存接口控制器5，所述闪存接口控制器5连接闪存控制物理层3，所述闪存控制物理层3还连接外部多个闪存储存组件；多个闪存储存组件包括第一闪存储存组件6、第二闪存储存组件7、第三闪存储存组件8、第N闪存储存组件，N为大于3的整数。
本发明中，闪存储存控制器2内还设有指令队列管理器9，所 述指令队列管理器9连接闪存控制寄存器4。
本发明中，一种用以连续快速产生闪存接口讯号序列的方法，其特征在于：包括以下步骤：
A、配置闪存指令队列管理器,使主控端在需要对闪存组件发出读取或写入等任意指令时,不须等待前一轮指令完成；
B、只需要由处理器连续对指令队列管理器持续写入多组寄存器信息于指令队列中直到队列全满；
C、待前一轮闪存接口指令完成时,闪存控制器再由队列中取出下一组指令组来运行；
D、当队列里的指令组被取出后,处理器便可以再向队列写入下一组指令组.，如此藉由硬件直接调用队列里的闪存指令序列,快速无误的对闪存组件发出任意指令序列。
综上所述，本发明配置闪存指令队列管理器,使主控端在需要对闪存组件发出读取或写入等任意指令时,不须等待前一轮指令完成,只需要由处理器连续对指令队列管理器持续写入多组寄存器信息于指令队列中直到队列全满.待前一轮闪存接口指令完成时,闪存控制器再由队列中取出下一组指令组来运行.，当队列里的指令组被取出后,处理器便可以再向队列写入下一组指令组.，如此藉由硬件直接调用队列里的闪存指令序列,快速无误的对闪存组件发出任意指令序列,藉以有效提升闪存主控模块之工作效能。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。

Claims (4)

  1. 一种用以连续快速产生闪存接口讯号序列的方法,包括主控芯片(1),其特征在于：所述主控芯片(1)内设置闪存储存控制器(2)和闪存控制物理层(3)，所述闪存储存控制器(2)内设有闪存控制寄存器(4)和闪存接口控制器(5)，所述闪存控制寄存器(4)连接闪存接口控制器(5)，所述闪存接口控制器(5)连接闪存控制物理层(3)，所述闪存控制物理层(3)还连接外部多个闪存储存组件。
  2. 根据权利要求1所述的一种用以连续快速产生闪存接口讯号序列的方法，其特征在于：多个闪存储存组件包括第一闪存储存组件(6)、第二闪存储存组件(7)、第三闪存储存组件(8)、第N闪存储存组件，N为大于3的整数。
  3. 根据权利要求1所述的一种用以连续快速产生闪存接口讯号序列的方法，其特征在于：所述闪存储存控制器(2)内还设有指令队列管理器(9)，所述指令队列管理器(9)连接闪存控制寄存器(4)。
  4. 根据权利要求1所述的一种用以连续快速产生闪存接口讯号序列的方法，其特征在于：包括以下步骤：
    A、配置闪存指令队列管理器,使主控端在需要对闪存组件发出读取或写入等任意指令时,不须等待前一轮指令完成；
    B、只需要由处理器连续对指令队列管理器持续写入多组寄存器 信息于指令队列中直到队列全满；
    C、待前一轮闪存接口指令完成时,闪存控制器再由队列中取出下一组指令组来运行；
    D、当队列里的指令组被取出后,处理器便可以再向队列写入下一组指令组.，如此藉由硬件直接调用队列里的闪存指令序列,快速无误的对闪存组件发出任意指令序列。
PCT/CN2019/078234 2018-12-09 2019-03-15 一种用以连续快速产生闪存接口讯号序列的方法 WO2020118942A1 (zh)

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