WO2020114435A1 - 数据处理方法、装置及存储介质 - Google Patents

数据处理方法、装置及存储介质 Download PDF

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Publication number
WO2020114435A1
WO2020114435A1 PCT/CN2019/123081 CN2019123081W WO2020114435A1 WO 2020114435 A1 WO2020114435 A1 WO 2020114435A1 CN 2019123081 W CN2019123081 W CN 2019123081W WO 2020114435 A1 WO2020114435 A1 WO 2020114435A1
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Prior art keywords
predistortion
data
input
control signal
data sequence
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English (en)
French (fr)
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刘欢
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Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H04B1/401—Circuits for selecting or indicating operating mode
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B2001/0408—Circuits with power amplifiers
    • H04B2001/0425—Circuits with power amplifiers with linearisation using predistortion

Definitions

  • the present disclosure relates to the technical field of wireless communication, for example, to a data processing method and device.
  • the above method solidifies the hardware of the predistortion circuit, and can only perform predistortion processing on the fixed frequency band data sequence input by the fixed channel, that is to say, the number of supported channels and the frequency band width are fixed, and it is impossible to achieve multi-channel input.
  • the pre-distortion processing of the data sequence of the data and to achieve the pre-distortion processing of the single-channel input data sequence to increase the bandwidth of the data sequence.
  • An embodiment of the present application provides a data processing apparatus.
  • the apparatus includes:
  • the control unit is set to determine the mode of operation, when it is determined to operate in the first mode, a first control signal is generated, and when it is determined to operate in the second mode, a second control signal is generated;
  • the first filter unit is configured to, in response to the first control signal, filter the input data sequence based on a sampling rate N times the sampling rate of the data sequence input from the first input channel to obtain data of multiple branches Sequence, and in response to the second control signal, stop filtering the data sequence input by the first input channel, where N is a positive integer;
  • a predistortion calculation unit configured to perform predistortion processing based on the first predistortion coefficients on the data sequences of the plurality of branches, respectively, to obtain a plurality of predistortion processed first data sequences, or, through multiple input channels
  • the input multi-channel data sequences are respectively subjected to pre-distortion processing based on second pre-distortion coefficients to obtain a plurality of pre-distorted processed second data sequences;
  • the second filter unit is configured to, in response to the first control signal, filter the plurality of pre-distorted first data sequences based on the sampling rate of the data sequence input from the first input channel, A plurality of filtered first data sequences are obtained, and in response to the second control signal, the filtering processing of the plurality of pre-distorted processed first data sequences is stopped.
  • An embodiment of the present application provides a data processing method.
  • the method includes:
  • the input data sequence is filtered based on a sampling rate N times the sampling rate of the input data sequence of the channel to obtain a plurality of branched data sequences, and in response to the second control signal, stop Filtering processing of the data sequence input by the first input channel, where N is a positive integer;
  • Performing predistortion processing based on the first predistortion coefficients on the data sequences of the plurality of branches, respectively, to obtain a plurality of predistorted first data sequences, or, respectively, multiple data sequences input through multiple input channels Perform pre-distortion processing based on the second pre-distortion coefficients to obtain multiple second data sequences after pre-distortion processing;
  • a data sequence In response to the first control signal, based on the sampling rate of the data sequence input from the first input channel, performing filtering processing on the plurality of pre-distortion processed first data sequences respectively to obtain multiple filtering processed first data sequences A data sequence, in response to the second control signal, stops filtering the first data sequence after the plurality of predistortion processes.
  • FIG. 1 is a schematic structural diagram of a data processing device according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of the composition structure of the data processing system according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram 1 of a composition of a digital predistortion processing module according to an embodiment of the present application
  • FIG. 4 is a schematic structural diagram 2 of a digital predistortion processing module according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a specific implementation process of a data processing method according to an embodiment of this application.
  • FIG. 6 is a schematic flowchart 1 of an implementation process of a data processing method according to an embodiment of the present application
  • FIG. 7 is a second schematic flowchart of an implementation process of a data processing method according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a data processing device according to an embodiment of the present application.
  • the peak-to-average ratio of the current communication standard signals is getting larger and larger, while the power amplifier (referred to as the power amplifier in the following description) has a certain nonlinear region, and the peak-to-average ratio signal passes through the power amplifier It is easier to make the power amplifier enter a nonlinear state.
  • the non-linear state of the power amplifier will cause the signal to spread the spectrum outside the band, causing channel interference and intermodulation distortion, causing distortion of the transmitted signal in the band, causing the bit error rate to rise, and ultimately causing a decline in communication performance.
  • the power back-off method can be used to reduce the signal power of the input power amplifier, so that the power amplifier always works in the linear state.
  • the first disadvantage is that it is more difficult to find the linear limit point of the power amplifier that meets the requirements; the second is that the efficiency of the power amplifier is reduced and the cost is increased; the third is that when the power returns to a certain level, continuing to fall back will not improve the linearity of the power amplifier. Therefore, in the occasions with high linearity requirements, it is not enough to adopt the power back-off technique.
  • DPD Digital Pre-Distortion
  • DPD Digital Pre-Distortion
  • the control unit in the data processing apparatus judges the mode of operation, generates a first control signal when it is determined to operate in the first mode, and generates it when it is determined to operate in the second mode A second control signal;
  • the first filter unit in the data processing device responds to the first control signal based on the sampling rate N times the sampling rate of the data sequence input to the first input channel Performing filtering to obtain a plurality of branched data sequences, and in response to the second control signal, stopping the filtering process of the data sequence input to the first input channel, where N is a positive integer;
  • the distortion calculation unit respectively performs predistortion processing based on the first predistortion coefficients on the data sequences of the plurality of branches to obtain a plurality of predistortion processed first data sequences, or, for multiple channels input through multiple input channels
  • the data sequence is separately subjected to predistortion processing based on the second predistortion coefficients to obtain a plurality of predistortion processed
  • An embodiment of the present application provides a data processing apparatus. As shown in FIG. 1, the apparatus includes:
  • the control unit 11 is set to determine the operation mode, when it is determined to work in the first mode, a first control signal is generated, and when it is determined to work in the second mode, a second control signal is generated;
  • the first filter unit 12 is configured to, in response to the first control signal, filter the input data sequence based on a sampling rate N times the sampling rate of the data sequence input from the first input channel to obtain multiple branches The data sequence, and in response to the second control signal, stopping the filtering process of the data sequence input by the first input channel, where N is a positive integer;
  • the predistortion calculation unit 13 is configured to perform predistortion processing based on the first predistortion coefficients on the data sequences of the plurality of branches, respectively, to obtain a plurality of predistortion processed first data sequences, or
  • the multi-channel data sequences input by the channels are respectively subjected to pre-distortion processing based on the second pre-distortion coefficients to obtain multiple second data sequences after pre-distortion processing;
  • the second filter unit 14 is configured to, in response to the first control signal, filter the plurality of pre-distorted first data sequences based on the sampling rate of the data sequence input from the first input channel, respectively To obtain a plurality of filtered first data sequences, and in response to the second control signal, stop filtering the plurality of pre-distorted processed first data sequences.
  • the first mode may be a single-channel high-band mode
  • the second mode may be a multi-channel mode.
  • the single-channel high-band mode not only can the pre-distortion processing be performed on the single-channel input data sequence, but also the bandwidth of the data sequence to be pre-distorted can be increased.
  • pre-distortion processing can be performed on the data sequence input by the multi-channel.
  • control unit 11 may be implemented by a processor such as a digital signal processor (Digital Signal Processor, DSP) or a field programmable gate array (Field Programmable Gate Array, FPGA), so that the software can be configured by software programming
  • DSP Digital Signal Processor
  • FPGA Field Programmable Gate Array
  • the data sequence of the single-channel input 1 times the sampling rate can be converted into the data sequence of the N-fold sampling rate, so that the sampling rate of the data sequence can be increased, and thus the pre-distortion can be increased The bandwidth of the processed data sequence.
  • B is the bandwidth of a data sequence of a single channel input
  • F s is the sampling rate of a data sequence of a single channel input.
  • N usually takes the smallest positive integer that satisfies Expression (2), which can simplify hardware design and reduce equipment costs.
  • the first filter unit 12 includes a plurality of sub-filtering units.
  • the input data sequence can be filtered by the plurality of sub-filtering units to obtain a plurality of branched data sequences.
  • the pre-distortion calculation unit 13 may include a plurality of sub-calculation units, and the pre-distortion processing is performed on the data sequence output by the corresponding sub-filter unit through the corresponding sub-calculation unit.
  • the first filter unit 12 includes N sub-filter units, the coefficients of each sub-filter may be different, and the predistortion calculation unit 13 may include M sub-calculation units.
  • N and M are positive integers, and N is less than or equal to M.
  • the N sub-filtering units correspond to the M sub-computing units one-to-one; when N is less than M, the N sub-filtering units correspond to the N sub-computing units of the M sub-computing units Correspondingly, and the remaining MN sub-calculation units of the M sub-calculation units are not used.
  • the sub-calculation unit 1 may perform pre-distortion processing on the first branch data sequence obtained by filtering a data sequence input from the first input channel, and the sub-calculation unit 2
  • the data sequence of the second branch may be pre-distorted, and so on, the sub-calculation unit M may perform pre-distortion processing on the data sequence of the Nth branch.
  • M and N are positive integers greater than 1, and N is equal to M. It should be noted that when N is less than M, the extra (M-N) sub-calculation units may not be used.
  • the sub-unit 1 can perform pre-distortion processing on the data sequence input from channel 1
  • the sub-calculation unit 2 can perform pre-distortion processing on the data sequence input from channel 2
  • the sub-calculation unit M can Pre-distortion the data sequence input to channel P.
  • M and P are positive integers greater than 1, and P is equal to M.
  • the data sequences of multiple branches obtained by filtering the data sequence input from the first input channel and the multi-channel data sequences input from the multiple input channels may be simultaneously input to the predistortion calculation unit 13.
  • the predistortion calculation unit 13 needs to perform predistortion processing on the data sequences of the plurality of branches; when working in the second mode, the predistortion calculation unit 13 13 Pre-distortion processing needs to be performed on the multiple data sequence.
  • the device may further include a front routing unit.
  • the front routing unit is configured to, in response to the first control signal, turn on the first filter unit 12 and the predistortion calculation unit 13 to output the plurality of outputs from the first filter unit
  • the branched data sequence is input to the predistortion calculation unit 13, and in response to the second control signal, the plurality of input channels and the predistortion calculation unit 13 are turned on to output the multi-channel data sequence.
  • the front routing unit may be implemented by multiple two-way selectors, and the input of each two-way selector may be connected to each sub-filter unit in the first filter unit 12 and one of the multiple input channels
  • the input channels are connected, and the output of each two-way selector can be connected to the corresponding sub-calculation unit in the predistortion calculation unit 13.
  • each two-way selector turns on the sub-filter unit and the corresponding sub-calculation unit to output the data sequence of one branch of the data sequences of the plurality of branches, in the first
  • each two-way selector turns on the multiple input channels and the corresponding sub-calculation unit to output one data sequence of the multiple data sequences.
  • the data sequence processed by the predistortion calculation unit 13 needs to be sent to a digital-to-analog converter for the digital-to-analog converter to perform digital-to-analog conversion processing.
  • the device may further include a combiner.
  • the combiner is configured to combine multiple filtered first data sequences to obtain a third data sequence.
  • analog sequence obtained through the digital-to-analog conversion process can be sent to the power amplifier.
  • the device may further include a rear routing unit.
  • the rear routing unit is configured to, in response to the first control signal, connect the second filter unit 14 and the first output channel through the combiner to output the third data sequence on the current channel, Output a zero sequence on other channels, and in response to the second control signal, turn on the predistortion calculation unit 13 and a plurality of output channels to output the corresponding predistortion processed second data sequence on the corresponding channel.
  • the second filter unit 14 includes N sub-filter units, and the coefficients of each sub-filter may be different.
  • the current channel may refer to the first channel, or, according to actual conditions, one channel is selected from the P channels as the current channel.
  • the function models may include a Wiener model, a parallel Wiener model, and a neural network model. and many more.
  • the device may further include a predistortion function coefficient calculation unit.
  • the predistortion function coefficient calculation unit is configured to output the first predistortion coefficient to the predistortion calculation unit 13 in response to the first control signal, and to the predistortion in response to the second control signal
  • the calculation unit 13 outputs the second predistortion coefficient.
  • the input data of the power amplifier is processed through the predistortion technology, so that the power amplifier working in the nonlinear region can still meet the linearization requirements of the wireless communication system.
  • the data sequence processed by the predistortion calculation unit 13 can be used as input data of the power amplifier, and the data sequence processed by the predistortion calculation unit 13 can be subjected to digital-to-analog conversion and power amplification processing to obtain output data, and It can make the output data of the power amplifier and the input data satisfy the linear relationship.
  • the device may further include a power amplification unit.
  • the power amplification unit is configured to perform digital-to-analog conversion processing on the second data sequence to obtain a second data sequence after digital-to-analog conversion processing; perform power amplification processing on the second data sequence after digital-analog conversion processing to obtain The first output sequence, or performing digital-to-analog conversion processing on the third data sequence to obtain a third data sequence after digital-to-analog conversion processing; performing power amplification on the third data sequence after digital-to-analog conversion processing to obtain the first Two output sequences.
  • the first output sequence and the second data sequence satisfy a linear relationship
  • the second output sequence and the third data sequence satisfy a linear relationship.
  • the data processing device provided in the embodiments of the present application can realize pre-distortion processing of a single-channel input data sequence when working in the first mode; and can realize multi-channel data input for multi-channel input when working in the second mode Pre-distortion processing of the sequence.
  • the solution of the embodiment of the present application not only supports pre-distortion processing of multi-channel input multi-channel data sequences, but also supports pre-distortion processing of single-channel input one-channel data sequences, and can also improve the data sequence to be pre-distorted. Bandwidth.
  • the predistortion calculation unit 13 does not fixedly correspond to a certain channel, but performs predistortion processing on the single-channel input data sequence in the first mode, and at the same time improves the data sequence to be predistorted In the second mode, the multi-channel input multi-channel data sequence is pre-distorted.
  • the number of channels and the bandwidth that can be supported are not fixed. It can support multi-channel pre-distortion processing and single-channel wide-band pre-distortion processing, which can save hardware overhead and improve product competitiveness.
  • the digital processing system includes: a digital predistortion processing module, a control unit, a digital-to-analog converter, an up-converter, a power amplifier, a digital predistortion function coefficient calculation unit, and an analog-to-digital conversion Converter, downconverter, and attenuator.
  • the digital predistortion processing module includes: an N-fold interpolation polyphase filter, a front routing unit, a digital predistortion calculation unit 1 to a digital predistortion calculation unit N, an N-fold extraction polyphase filter, and Rear routing unit. As shown in FIG.
  • the digital predistortion processing module includes: an N-fold interpolation polyphase filter, a front routing unit, a digital predistortion calculation unit 1 to a digital predistortion calculation unit N, an N-fold extraction polyphase filter, and a post Routing unit and adder.
  • the N-fold interpolation polyphase filter includes N sub-filters, and coefficients of each sub-filter may be different, and the N-fold decimation polyphase filter includes N sub-filters, and coefficients of each sub-filter may be different.
  • the single-channel wideband mode corresponds to the above-mentioned first mode
  • the multi-channel mode corresponds to the above-mentioned second mode
  • the control unit corresponds to the above-mentioned control unit 11
  • the N-fold interpolation polyphase filter corresponds to the above-mentioned first filter unit 12
  • the N-fold decimation polyphase filter corresponds to the above-mentioned second filter unit 14
  • the predistortion calculation unit 1 to the digital predistortion calculation unit M correspond to the sub-calculation unit 1 to the sub-calculation unit M in the predistortion calculation unit 13 described above
  • the adder corresponds to the above-described combiner.
  • the application scenario in this application embodiment is: when working in the single-channel wideband mode, through the control unit, the N-fold interpolation polyphase filter, the front routing unit, the digital predistortion calculation unit 1 to the digital predistortion calculation unit N , N times decimation polyphase filter, and post-routing unit, pre-distortion processing of single-channel input data sequence.
  • the single-channel wideband mode and the multi-channel mode are configured through software.
  • control unit may be implemented by a processor such as DSP, FPGA, etc.
  • the working mode supported by the digital predistortion module may be configured through software programming.
  • the digital predistortion module When the digital predistortion module is required to support predistortion processing of a single-channel input data sequence and can increase the bandwidth, it can be configured as a single-channel wideband mode; when the digital predistortion module is required to support multi-channel input When the data sequence is pre-distorted, it can be configured in multi-channel mode.
  • control unit determines the operating mode, and when it is determined to operate in the single-channel broadband mode, generates the first control signal.
  • the first control signal may control the N-fold interpolation polyphase filter, the front routing unit, the N-fold extraction polyphase filter, and the rear routing unit.
  • the N-fold interpolation polyphase filter responds to the first control signal, and converts a data sequence of 1-fold sampling rate input from channel 1 into a data sequence of N-fold sampling rate through N-fold interpolation to obtain multiple branches Is the data sequence of the first phase (the first branch) to the Nth phase (the Nth branch).
  • the front routing unit in response to the first control signal, turns on the N-fold interpolation polyphase filter and the corresponding digital predistortion calculation unit to perform interpolation processing on the output of the N-fold interpolation polyphase filter
  • the data sequence of N branches is input to the corresponding digital predistortion calculation unit.
  • the digital predistortion calculation unit 1 to the digital predistortion calculation unit M perform predistortion processing on the interpolated N branch data sequences.
  • the digital predistortion calculation unit 1 performs predistortion processing on the first phase data sequence
  • the digital predistortion calculation unit 2 performs predistortion processing on the second phase data sequence
  • the digital predistortion calculation unit M performs the Nth phase
  • M and N are positive integers greater than 1, and N is equal to M. It should be noted that when N is less than M, the additional (M-N) digital predistortion calculation units may not be used.
  • the N-fold decimation polyphase filter responds to the first control signal and filters the N-phase data sequence after interpolation and predistortion processing to obtain a plurality of filtered first data sequences.
  • the adder multiple filter-processed first data sequences are combined to obtain a third data sequence.
  • the above-mentioned adder is the aforementioned combiner.
  • the adder can be set after the N-fold decimation polyphase filter, and multiple filters on the N branches of the N-fold decimation polyphase filter.
  • the processed first data sequence is combined to obtain a third data sequence, as shown in FIG. 4.
  • a seventh step in response to the first control signal, switches the second filter unit and a single output channel, such as channel 1, through the adder to output the third data sequence on channel 1,
  • the zero sequence is output on channels other than channel 1.
  • the pre-distortion processing is performed on the multi-channel data sequences input by the multi-channel through the control unit, the front routing unit, the digital predistortion calculation unit 1 to the digital predistortion calculation unit N, and the rear routing unit.
  • the single-channel wideband mode and the multi-channel mode are configured through software.
  • control unit may be implemented by a processor such as DSP, FPGA, etc.
  • the working mode supported by the digital predistortion module may be configured through software programming.
  • the digital predistortion module When the digital predistortion module is required to support predistortion processing of a single-channel input data sequence and can increase the bandwidth, it can be configured as a single-channel wideband mode; when the digital predistortion module is required to support multi-channel input When the data sequence is pre-distorted, it can be configured in multi-channel mode.
  • control unit determines the operation mode, and when it is determined that the operation is in the multi-channel mode, generates a second control signal.
  • the second control signal may control the front routing unit and the rear routing unit.
  • the front routing unit turns on multiple input channels and corresponding digital predistortion calculation units to output multiple data sequences input by P channels.
  • the digital predistortion calculation unit 1 to the digital predistortion calculation unit M perform predistortion processing on the multi-path data sequence to obtain a second data sequence.
  • the digital predistortion calculation unit 1 performs predistortion processing on a data sequence input from channel 1
  • the digital predistortion calculation unit 2 performs predistortion processing on a data sequence input from channel 2, and so on, the digital predistortion calculation unit M
  • M and P are positive integers greater than 1, and P is equal to M. It should be noted that when P is less than M, the additional (M-P) digital predistortion calculation units may not be used.
  • the post-routing unit in response to the second control signal, turns on the digital predistortion calculation unit and multiple output channels to output corresponding multiple predistortion processed second data sequences on the corresponding channels.
  • the second data sequence processed by the digital predistortion calculation unit 1 is output on channel 1
  • the second data sequence processed by the digital predistortion calculation unit 2 is output on channel 2, and so on
  • the digital predistortion calculation is output on channel M
  • the second data sequence processed by unit M is output on channel 1
  • the N-fold interpolation filter 12 when working in the second mode, the N-fold interpolation filter 12, the front routing unit, the N digital predistortion calculation units 13, the N-fold decimation filter 14, and the rear routing Data processing between units is independent.
  • FIG. 5 is a schematic diagram of an implementation process of a data processing method according to an embodiment of the present application, combined with the structural schematic diagram of the digital predistortion processing module described above, as shown in FIG. 5, the method includes:
  • Step 501 The control unit determines whether it is currently operating in the single-channel broadband mode. When it is determined to operate in the single-channel wideband mode, step 502 is performed; when it is determined to operate in the multi-channel mode, step 507 is performed.
  • Step 502 The N-fold interpolation polyphase filter filters the input data sequence according to the N-fold sampling rate of the one-channel data sequence input from channel 1, to obtain multiple branched data sequences, and executes step 503.
  • Step 503 The front routing unit turns on the N-fold interpolation polyphase filter and the corresponding digital predistortion calculation unit to output the data sequence of the multiple branches, and executes step 504.
  • Step 504 The digital predistortion calculation unit 1 to the digital predistortion calculation unit M respectively perform predistortion processing on the data sequences of the multiple branches based on the first predistortion coefficients to obtain multiple predistortion processed first data sequences And execute step 505.
  • Step 505 The N-fold interpolation polyphase filter performs filtering processing on the plurality of pre-distorted first data sequences based on the sampling rate of the one-way data sequence to obtain a plurality of filtered first data sequences; by addition The third data sequence obtained by combining the first data sequences after filtering is combined, and step 506 is performed.
  • Step 506 The post-routing unit turns on the N-fold decimation polyphase filter and multiple output channels, outputs a third data sequence on channel 1, and outputs a zero sequence on other channels, ending.
  • Step 507 The front routing unit connects the input channel and the corresponding digital predistortion calculation unit to output the multi-channel data sequence, and executes step 508.
  • Step 508 The digital predistortion calculation unit 1 to the digital predistortion calculation unit M respectively perform predistortion processing on the multi-channel data sequence input through multiple channels based on the second predistortion coefficients to obtain multiple predistortion processed second data Sequence and execute step 509.
  • Step 509 The post-routing unit connects the digital predistortion calculation unit and multiple output channels to output the corresponding predistortion-processed second data sequence on the corresponding channel, and ends.
  • an embodiment of the present application also provides a data processing method. As shown in FIG. 6, the method includes:
  • Step 601 The control unit in the data processing device judges the mode of operation, generates a first control signal when it is determined to operate in the first mode, and generates a second control signal when it is determined to operate in the second mode.
  • Step 602 In response to the first control signal, the first filter unit in the data processing device filters the input data sequence based on the sampling rate of N times the sampling rate of the data sequence input from the first input channel To obtain data sequences of multiple branches, and in response to the second control signal, stop filtering the data sequence input by the first input channel, where N is a positive integer.
  • Step 603 The predistortion calculation unit in the data processing apparatus performs predistortion processing based on the first predistortion coefficients on the data sequences of the multiple branches, respectively, to obtain a plurality of predistortion processed first data sequences, or , Performing predistortion processing based on the second predistortion coefficients on the multiple data sequences input through the multiple input channels, respectively, to obtain multiple second data sequences after the predistortion processing.
  • Step 604 The second filter unit in the data processing device responds to the first control signal and based on the sampling rate of the data sequence input from the first input channel, The data sequence is filtered to obtain a plurality of filtered first data sequences, and in response to the second control signal, the filtering of the plurality of pre-distorted processed first data sequences is stopped.
  • the first mode may be a single-channel high-band mode
  • the second mode may be a multi-channel mode.
  • the single-channel high-band mode not only can the pre-distortion processing be performed on the single-channel input data sequence, but also the bandwidth of the data sequence to be pre-distorted can be increased; in the multi-channel mode, multiple The data sequence of the channel input is pre-distorted.
  • control unit may be implemented by a processor such as DSP, FPGA, etc.
  • the first mode and the second mode may be configured through software programming.
  • a single-input data sequence with a sampling rate of 1 can be converted into a data sequence with an sampling rate of N, so that the sampling rate of the data sequence can be increased, and further processing to be predistorted can be increased The bandwidth of the data sequence.
  • the first filter unit includes a plurality of sub-filter units.
  • the predistortion calculation unit may include a plurality of sub-calculation units, and the pre-distortion processing is performed on the data sequence output by the corresponding sub-filtering unit through the corresponding sub-calculation unit.
  • the first filter unit includes N sub-filter units, and the predistortion calculation unit may include M sub-calculation units.
  • N and M are positive integers, and N is less than or equal to M.
  • the N sub-filtering units correspond to the M sub-computing units one-to-one; when N is less than M, the N sub-filtering units correspond to the N sub-computing units of the M sub-computing units Correspondingly, and the remaining MN sub-calculation units of the M sub-calculation units are not used.
  • the sub-calculation unit 1 may perform pre-distortion processing on the first branch of the data sequence obtained by filtering a data sequence input from the first input channel, and the sub-calculation unit 2
  • the data sequence of the second branch may be pre-distorted, and so on, the sub-calculation unit M may perform pre-distortion processing on the data sequence of the Nth branch.
  • M and N are positive integers greater than 1, and N is equal to M. It should be noted that when N is less than M, the extra (M-N) sub-calculation units may not be used.
  • the sub-unit 1 can perform pre-distortion processing on the data sequence input from channel 1
  • the sub-calculation unit 2 can perform pre-distortion processing on the data sequence input from channel 2
  • the sub-calculation unit M can Pre-distortion the data sequence input to channel P.
  • M and P are positive integers greater than 1, and P is equal to M.
  • the data sequences of multiple branches obtained by filtering the data sequence input from the first input channel and the multi-channel data sequences input from the multiple input channels may be simultaneously input to the predistortion calculation unit.
  • the predistortion calculation unit needs to perform predistortion processing on the data sequences of the plurality of branches; when working in the second mode, the predistortion calculation unit needs Perform pre-distortion processing on the multiple data sequence.
  • the method further includes: in response to the first control signal, the front routing unit in the data processing device turns on the first filter unit and the predistortion calculation unit, To input the data sequences of the plurality of branches output by the first filter unit to the predistortion calculation unit; in response to the second control signal, turn on a plurality of input channels and the predistortion calculation unit, To output the multiple data sequence.
  • the front routing unit may be implemented by multiple two-way selectors, and the input of each two-way selector may be input to each sub-filter unit in the first filter unit and one input of the multiple input channels
  • the channels are connected, and the output of each two-way selector can be connected to the corresponding sub-calculation unit in the predistortion calculation unit.
  • each two-way selector turns on the sub-filter unit and the corresponding sub-calculation unit to output the data sequence of one branch among the data sequences of the plurality of branches, in the first
  • each two-way selector turns on the input channel and the corresponding sub-calculation unit to output one way of the multi-way data sequence.
  • the data sequence processed by the predistortion calculation unit may be subjected to digital-to-analog conversion processing to obtain an analog sequence, which is used as an input sequence of a power amplifier.
  • the method further includes: a combiner in the data processing device combines multiple filtered first data sequences to obtain a third data sequence.
  • analog sequence obtained through the digital-to-analog conversion process can be sent to the power amplifier.
  • the method further includes: in response to the first control signal, the rear routing unit in the data processing device turns on the second filter unit and the first through the combiner An output channel to output the third data sequence on the current channel and a zero sequence on other channels; in response to the second control signal, turn on the predistortion calculation unit and multiple output channels to output on the corresponding channel The corresponding second data sequence after predistortion processing.
  • the current channel may refer to the first channel, or, according to actual conditions, one channel is selected from the P channels as the current channel.
  • the function models may include a Wiener model, a parallel Wiener model, and a neural network model. and many more.
  • the method further includes: the predistortion function coefficient calculation unit of the data processing device outputs the first predistortion coefficient to the predistortion calculation unit in response to the first control signal ; In response to the second control signal, output the second predistortion coefficient to the predistortion calculation unit.
  • the input data of the power amplifier is processed through the predistortion technology, so that the power amplifier working in the nonlinear region can still meet the linearization requirements of the wireless communication system.
  • the data sequence processed by the predistortion calculation unit can be used as input data of the power amplifier; the data sequence processed by the predistortion calculation unit can be subjected to digital-to-analog conversion and power amplification processing to obtain output data, and can Make the output data of the power amplifier and the input data satisfy the linear relationship.
  • the method further includes: the power amplifying unit in the data processing device performs digital-to-analog conversion processing on the second data sequence to obtain a second data sequence after digital-to-analog conversion processing; Performing power amplification processing on the second data sequence after the digital-analog conversion processing to obtain a first output sequence, or performing digital-analog conversion processing on the third data sequence to obtain a third data sequence after digital-analog conversion processing; The third data sequence after the digital-to-analog conversion process is subjected to power amplification processing to obtain a second output sequence.
  • the first output sequence and the second data sequence satisfy a linear relationship
  • the second output sequence and the third data sequence satisfy a linear relationship.
  • the method includes:
  • Step 701 Determine the working mode.
  • Step 702 When it is determined to work in the first mode, generate a first control signal, and when it is determined to work in the second mode, generate a second control signal;
  • the first control signal is used to control the N-fold interpolation polyphase filter to filter the one-channel data sequence according to the N-fold sampling rate of the one-channel data sequence input rate of the current channel to obtain data of multiple branches sequence.
  • the data sequences of the plurality of branches are used for the predistortion calculation unit to perform predistortion processing based on the first predistortion coefficients to obtain a plurality of predistortion processed first data sequences.
  • the first control signal is also used for the N-fold decimation polyphase filter to perform filtering processing on a plurality of pre-distorted processed first data sequences according to the sampling rate of the one-way data sequence to obtain a plurality of filtered processing The first data sequence.
  • the second control signal is used to control the N-fold interpolation polyphase filter to stop filtering the one-way data sequence, and the N-fold extraction polyphase filter to stop processing the first data after the plurality of predistortion processes Filtering the sequence so that the predistortion calculation unit performs predistortion processing based on the second predistortion coefficients on the multiple data sequences input through the multiple input channels to obtain multiple predistortion processed second data sequences.
  • the second control signal is also used to control the post-routing unit to output the corresponding pre-distorted second data sequence on the corresponding channel.
  • the first mode may be a single-channel high-band mode
  • the second mode may be a multi-channel mode.
  • the single-channel high-band mode not only can the pre-distortion processing be performed on the single-channel input data sequence, but also the bandwidth of the data sequence to be pre-distorted can be increased; in the multi-channel mode, multiple The multi-channel data sequence of the channel input is pre-distorted separately.
  • the N-way interpolation polyphase filter, the front routing unit, the N-time decimation polyphase filter, and the rear routing unit can be used to filter a single-channel input data sequence To obtain the data sequence of multiple branches; through the front routing unit, connect the first filter unit and the predistortion calculation unit to input the data sequence of the multiple branches output by the first filter unit To the predistortion calculation unit; through the predistortion calculation unit, perform a predistortion process based on the first predistortion coefficients on the data sequences of the multiple branches, respectively, to obtain a plurality of predistortion processed first data sequences; N times decimated polyphase filter, according to the sampling rate of the one-way data sequence, filter the multiple pre-distorted first data sequences to obtain multiple filtered first data sequences; through the post-routing unit , Using the combiner to connect the second filter unit and the first output channel to output a third data sequence on the current channel and a zero sequence on other channels
  • the second control signal can control the front routing unit and the rear routing unit.
  • the pre-distortion unit outputs the multi-path data sequence to the pre-distortion calculation unit; the pre-distortion calculation unit respectively performs pre-distortion processing based on the second pre-distortion coefficient on the multi-path data sequence input through multiple input channels To obtain multiple pre-distorted second data sequences; through the post-routing unit, the pre-distortion calculation unit and multiple output channels are turned on to output the corresponding pre-distorted second data sequences on the corresponding channels.
  • the data processing device 80 includes a processor 81 and a memory 82 for storing a computer program that can be run on the processor 81.
  • the processor 81 is configured to run the computer program to implement the steps in the data processing method provided in the above embodiment.
  • the data processing device 80 further includes a bus 83, which is used to connect the processor 81 and the memory 82 and perform data transmission.
  • an embodiment of the present application further provides a storage medium, that is, a computer storage medium, for example, a computer-readable storage medium, for example, including a memory 82 that stores a computer program, and the above computer program may be stored by the data processing device 80.
  • the processor 81 executes to complete the steps of the aforementioned corresponding methods.
  • Computer-readable storage media can be Ferromagnetic Random Access Memory (FRAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), and movable routes Demonstrates Erasable Programmable Read-Only Memory (EPROM), electrically movable routes demonstrating Programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), flash memory (Flash) Memory, magnetic surface Memory, compact disc, or read-only compact disc (Compact Disc Read-Only Memory, CD-ROM) and other memories.
  • FRAM Ferromagnetic Random Access Memory
  • ROM Read Only Memory
  • PROM Programmable Read-Only Memory
  • EPROM Electrically movable routes demonstrating Programmable Read-Only Memory
  • Flash Flash Memory
  • magnetic surface Memory compact disc
  • CD-ROM Compact Disc Read-Only Memory

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Abstract

本公开提供了一种数据处理方法、装置及存储介质，该装置包括：控制单元，设置为判断工作的模式；第一滤波器单元，设置为对输入的数据序列进行滤波，得到多个分支的数据序列，以及停止对输入的数据序列的滤波处理；预失真计算单元，设置为对多个分支的数据序列分别进行基于第一预失真系数的预失真处理，得到多个预失真处理后的第一数据序列，或对通过多个输入通道输入的多路数据序列分别进行基于第二预失真系数的预失真处理，得到多个预失真处理后的第二数据序列；第二滤波器单元，设置为对多个预失真处理后的第一数据序列分别进行滤波处理，得到多个滤波处理后的第一数据序列，以及停止对多个预失真处理后的第一数据序列的滤波处理。

Description

数据处理方法、装置及存储介质
本申请要求在2018年12月4日提交中国专利局、申请号为201811474907.6的中国专利申请的优先权，以上申请的全部内容通过引用结合在本申请中。
技术领域
本公开涉及无线通信技术领域，例如涉及一种数据处理方法及装置。
背景技术
随着无线通信技术的发展，为了提高通信性能，如何使功率放大器始终工作在线性状态成为行业热门问题。相关技术中，通过固定的一个非线性函数模型，对预失真电路的硬件进行固化，以使功率放大器工作在线性状态。
上述方式对预失真电路的硬件进行固化，仅能对固定通道输入的固定频带的数据序列进行预失真处理，也就是说，支持的通道数量和频带宽度是固定的，无法既实现对多通道输入的数据序列进行预失真处理，又实现在对单通道输入的数据序列进行预失真处理时提高数据序列的频带宽度。
发明内容
本申请实施例提供一种数据处理装置，所述装置包括：
控制单元，设置为判断工作的模式，当确定工作在第一模式时，生成第一控制信号，当确定工作在第二模式时，生成第二控制信号；
第一滤波器单元，设置为响应所述第一控制信号，基于第一输入通道输入的数据序列的采样率的N倍采样率，对所述输入的数据序列进行滤波，得到多个分支的数据序列，以及响应所述第二控制信号，停止对所述第一输入通道输 入的数据序列的滤波处理，其中N为正整数；
预失真计算单元，设置为对所述多个分支的数据序列分别进行基于第一预失真系数的预失真处理，得到多个预失真处理后的第一数据序列，或者，对通过多个输入通道输入的多路数据序列分别进行基于第二预失真系数的预失真处理，得到多个预失真处理后的第二数据序列；
第二滤波器单元，设置为响应所述第一控制信号，基于所述第一输入通道输入的数据序列的采样率，对所述多个预失真处理后的第一数据序列分别进行滤波处理，得到多个滤波处理后的第一数据序列，以及响应所述第二控制信号，停止对所述多个预失真处理后的第一数据序列的滤波处理。
本申请实施例提供一种数据处理方法，所述方法包括：
判断工作的模式，当确定工作在第一模式时，生成第一控制信号，当确定工作在第二模式时，生成第二控制信号；
响应所述第一控制信号，基于通道输入的数据序列的采样率的N倍采样率，对所述输入的数据序列进行滤波，得到多个分支的数据序列，响应所述第二控制信号，停止对所述第一输入通道输入的数据序列的滤波处理，其中N为正整数；
对所述多个分支的数据序列分别进行基于第一预失真系数的预失真处理，得到多个预失真处理后的第一数据序列，或者，对通过多个输入通道输入的多路数据序列分别进行基于第二预失真系数的预失真处理，得到多个预失真处理后的第二数据序列；
响应所述第一控制信号，基于所述第一输入通道输入的数据序列的采样率，对所述多个预失真处理后的第一数据序列分别进行滤波处理，得到多个滤波处理后的第一数据序列，响应所述第二控制信号，停止对所述多个预失真处理后 的第一数据序列的滤波处理。
附图说明
图1为本申请实施例数据处理装置的组成结构示意图；
图2为本申请实施例数据处理系统的组成结构示意图；
图3为本申请实施例数字预失真处理模块的组成结构示意图一；
图4为本申请实施例数字预失真处理模块的组成结构示意图二；
图5为本申请实施例数据处理方法的具体实现流程示意图；
图6为本申请实施例数据处理方法的实现流程示意图一；
图7为本申请实施例数据处理方法的实现流程示意图二；
图8为本申请实施例数据处理装置的组成结构示意图。
具体实施方式
下面结合附图及实施例对本申请进行详细描述。
目前，随着无线通信技术的不断发展，当前所采用的通信制式信号的峰均比越来越大，而功率放大器(以下描述中简称功放)具有一定的非线性区域，高峰均比信号通过功放时更易使得功率放大器进入非线性状态。而功放的非线性状态会使得信号在带外引起频谱扩展，导致临道干扰和互调失真，在带内引起传输信号的失真，令误码率上升，最终造成通信性能的下降。
目前，为了使功放始终工作在线性状态，可以采用功率回退法，将输入功放的信号功率降低，令功放始终工作在线性状态。但缺点一是找到满足要求的功放线性极限点比较困难；二是降低了功放的效率，增加成本；三是当功率回退到一定程度时，继续回退将不再改善功放的线性度。因此在线性度要求很高 的场合，仅采用功率回退技术是不够的。
另外，还可以采用数字预失真(Digital Pre-Distortion，DPD)技术使功放始终工作在线性状态。例如，对功放的输入信号和输出信号进行数据采集，通过分析采集数据进而分析功放的非线性数学模型，制作相应的DPD数字预失真电路。通信信号先通过DPD数字预失真电路，再进入功放时无需回退功率就可以减少功放在非线性区域运行时产生的失真，功放效率可以大幅度提升。但由于传统的DPD数字预失真电路一旦硬件固化，其能够支持的通道数量、功率放大器(Power Amplifier，PA)数量和频段宽度是固定的。而随着第五代移动通信技术(5th-Generation，5G)的不断发展，无线运营商的通信网络呈现出多频段并存格局，采用传统数字预失真电路的DPD装置已经无法满足多通道DPD和宽频段DPD兼容的需求。
基于此，在本公开的每种实施例中，数据处理装置中的控制单元判断工作的模式，当确定工作在第一模式时，生成第一控制信号，当确定工作在第二模式时，生成第二控制信号；所述数据处理装置中的第一滤波器单元响应所述第一控制信号，基于第一输入通道输入的数据序列的采样率的N倍采样率，对所述输入的数据序列进行滤波，得到多个分支的数据序列，以及响应所述第二控制信号，停止对所述第一输入通道输入的数据序列的滤波处理，其中N为正整数；所述数据处理装置中的预失真计算单元对所述多个分支的数据序列分别进行基于第一预失真系数的预失真处理，得到多个预失真处理后的第一数据序列，或者，对通过多个输入通道输入的多路数据序列分别进行基于第二预失真系数的预失真处理，得到多个预失真处理后的第二数据序列；所述数据处理装置中的第二滤波器单元响应所述第一控制信号，基于所述第一输入通道输入的数据序列的采样率，对所述多个预失真处理后的第一数据序列分别进行滤波处理， 得到多个滤波处理后的第一数据序列，以及响应所述第二控制信号，停止对所述多个预失真处理后的第一数据序列的滤波处理。
本申请实施例提供一种数据处理装置，如图1所示，该装置包括：
控制单元11，设置为判断工作的模式，当确定工作在第一模式时，生成第一控制信号，当确定工作在第二模式时，生成第二控制信号；
第一滤波器单元12，设置为响应所述第一控制信号，基于第一输入通道输入的数据序列的采样率的N倍采样率，对所述输入的数据序列进行滤波，得到多个分支的数据序列，以及响应所述第二控制信号，停止对所述第一输入通道输入的数据序列的滤波处理，其中N为正整数；
预失真计算单元13，设置为对所述多个分支的数据序列分别进行基于第一预失真系数的预失真处理，得到多个预失真处理后的第一数据序列，或者，对通过多个输入通道输入的多路数据序列分别进行基于第二预失真系数的预失真处理，得到多个预失真处理后的第二数据序列；
第二滤波器单元14，设置为响应所述第一控制信号，基于所述第一输入通道输入的数据序列的采样率，对所述多个预失真处理后的第一数据序列分别进行滤波处理，得到多个滤波处理后的第一数据序列，以及响应所述第二控制信号，停止对所述多个预失真处理后的第一数据序列的滤波处理。
其中，所述第一模式可以为单通道高频带模式，所述第二模式可以为多通道模式。在所述单通道高频带模式下，不仅能够对单通道输入的数据序列进行预失真处理，而且可以提高待预失真处理的数据序列的频带宽度。在所述多通道模式下，可以对多通道输入的数据序列进行预失真处理。
实际应用时，所述控制单元11可以由数字信号处理器(Digital Signal Processor，DSP)、或现场可编程门阵列(Field Programmable Gate Array，FPGA) 等处理器实现，这样，可以通过软件编程配置所述第一模式和第二模式。
这里，通过所述第一滤波器单元12，可以将单通道输入的1倍采样率的数据序列转换为N倍采样率的数据序列，从而可以提高数据序列的采样率，进而能够增加待预失真处理的数据序列的频带宽度。
对于N的取值，假设单通道输入的数据序列的采样率为F s，奈奎斯特区间为[-Fs/2,Fs/2]，数据序列的带宽为B，频域范围为[-B/2，B/2]。通过N倍插值滤波器，对单通道输入的数据序列进行N倍插值处理后，2N+1阶频谱分量以N×Fs为周期在频域进行复制，如果保证在[-Fs/2，Fs/2]的奈奎斯特区间内没有第2N+1阶频谱分量的混叠，那么N必须满足的条件表达式如(1)所示：
Figure PCTCN2019123081-appb-000001
将上述条件表达式进行变换后，得到表达式(2)：
Figure PCTCN2019123081-appb-000002
其中，B为单通道输入的一路数据序列的带宽，F s为单通道输入的一路数据序列的采样率。
需要说明的是，在硬件实现时，N值通常取满足表达式(2)的最小正整数，这样可以简化硬件设计，降低设备成本。
实际应用时，所述第一滤波器单元12包括多个子滤波单元，这样，可以通过多个子滤波单元对所述输入的数据序列分别进行滤波，得到多个分支的数据序列。预失真计算单元13可以包括多个子计算单元，通过相应的子计算单元对相应子滤波单元输出的数据序列进行预失真处理。
基于此，在一实施例中，所述第一滤波器单元12包括N个子滤波单元，每个子滤波器的系数可以不同，所述预失真计算单元13可以包括M个子计算单元。 其中，N和M均为正整数，且N小于或等于M。当N等于M时，所述N个子滤波单元与所述M个子计算单元一一对应；当N小于M时，所述N个子滤波单元与所述M个子计算单元中的N个子计算单元一一对应，并且所述M个子计算单元中剩余的M-N个子计算单元不使用。
在一实施方式中，在所述第一模式下，子计算单元1可以对所述第一输入通道输入的一路数据序列滤波得到的第1个分支的数据序列进行预失真处理，子计算单元2可以对第2个分支的数据序列进行预失真处理，以此类推，子计算单元M可以对第N个分支的数据序列进行预失真处理。其中，M、N均为大于1的正整数，且N等于M。需要说明的是，当N小于M时，多出的(M-N)个子计算单元可以不使用。
在所述第二模式下，子单元1可以对通道1输入的数据序列进行预失真处理，子计算单元2可以对通道2输入的数据序列进行预失真处理，以此类推，子计算单元M可以对通道P输入的数据序列进行预失真处理。其中，M、P均为大于1的正整数，且P等于M。
实际应用时，对所述第一输入通道输入的数据序列滤波得到的多个分支的数据序列和所述多个输入通道输入的多路数据序列可以同时输入到所述预失真计算单元13。这样，当工作在所述第一模式时，所述预失真计算单元13需要对所述多个分支的数据序列进行预失真处理；当工作在所述第二模式时，所述预失真计算单元13需要对所述多路数据序列进行预失真处理。
基于此，在一实施例中，所述装置还可以包括前路由单元。
所述前路由单元，设置为响应所述第一控制信号，接通所述第一滤波器单元12与所述预失真计算单元13，以将所述第一滤波器单元输出的所述多个分支的数据序列输入至所述预失真计算单元13，以及响应所述第二控制信号，接通 所述多个输入通道与所述预失真计算单元13，以输出所述多路数据序列。
这里，所述前路由单元可由多个二路选择器实现，每个二路选择器的输入可以与所述第一滤波器单元12中的每个子滤波单元以及所述多个输入通道中的一个输入通道相连，每个二路选择器的输出可以与所述预失真计算单元13中对应的子计算单元相连。在所述第一控制信号作用下，每个二路选择器接通子滤波单元与相应的子计算单元，以输出所述多个分支的数据序列中的一个分支的数据序列，在所述第二控制信号作用下，每个二路选择器接通所述多个输入通道与相应的子计算单元，以输出所述多路数据序列中的一路数据序列。
实际应用时，经过所述预失真计算单元13处理后的数据序列需要送入数模转换器，以供数模转换器进行数模转换处理。
基于此，在一实施例中，所述装置可以还包括合路器。
所述合路器，设置为对多个滤波处理后的第一数据序列进行合路，得到第三数据序列。
实际应用时，经过数模转换处理得到的模拟序列，可以送入功放。
基于此，在一实施例中，所述装置还可以包括后路由单元。
所述后路由单元，设置为响应所述第一控制信号，通过所述合路器接通所述第二滤波器单元14与第一输出通道，以在当前通道输出所述第三数据序列，在其他通道输出零序列，以及响应所述第二控制信号，接通所述预失真计算单元13与多个输出通道，以在相应通道输出对应的预失真处理后的第二数据序列。
其中，所述第二滤波器单元14包括N个子滤波单元，每个子滤波器的系数可以不同。
这里，当通道的数量为P个时，所述当前通道可以是指第一个通道，或者，根据实际情况，从P个通道中选取一个通道作为所述当前通道。
实际应用时，确定预失真系数的函数模型可以有多种，因而可以使用不同的函数模型分别确定两种模式对应的预失真系数，所述函数模型可以包括Wiener模型、并联Wiener模型、神经网络模型等等。
基于此，在一实施例中，所述装置还可以包括预失真函数系数计算单元。
所述预失真函数系数计算单元，设置为响应所述第一控制信号，向所述预失真计算单元13输出所述第一预失真系数，以及响应所述第二控制信号，向所述预失真计算单元13输出所述第二预失真系数。
实际应用时，通过预失真技术对功率放大器的输入数据进行处理，可以使工作在非线性区域的功率放大器仍能满足无线通信系统对线性化的要求。这样，可以将所述预失真计算单元13处理后的数据序列作为功放的输入数据，并对所述预失真计算单元13处理后的数据序列进行数模转换、功率放大处理，得到输出数据，且能够使功放的输出数据与输入数据满足线性关系。
基于此，在一实施例中，所述装置还可以包括功率放大单元。
所述功率放大单元，设置为对所述第二数据序列进行数模转换处理，得到数模转换处理后的第二数据序列；对数模转换处理后的第二数据序列进行功率放大处理，得到第一输出序列，或者，对所述第三数据序列进行数模转换处理，得到数模转换处理后的第三数据序列；对数模转换处理后的第三数据序列进行功率放大处理，得到第二输出序列。其中，所述第一输出序列与所述第二数据序列满足线性关系，所述第二输出序列与所述第三数据序列满足线性关系。
本申请实施例提供的数据处理装置，当工作在第一模式时，可以实现对单通道输入的数据序列的预失真处理；当工作在第二模式时，可以实现对多通道输入的多路数据序列的预失真处理。采用本申请实施例的方案，既支持对多通道输入的多路数据序列进行预失真处理，又支持对单通道输入的一路数据序列 进行预失真处理，还能提高待预失真处理的数据序列的频带宽度。
另外，本申请实施例中，所述预失真计算单元13不是固定对应某一个通道，而是在第一模式下对单通道输入的数据序列进行预失真处理，同时提高待预失真处理的数据序列的频带宽度，在第二模式下，对多通道输入的多路数据序列分别进行预失真处理。显然，能够支持的通道数量和频带宽度不是固定的，既可以支持多通道的预失真处理，又可以支持单通道宽频带的预失真处理，进而能节省硬件开销，提高产品的竞争力。
下面结合应用实施例对本公开再作详细描述。
在本应用实施例中，如图2所示，数字处理系统包括：数字预失真处理模块、控制单元、数模转换器、上变频器、功率放大器、数字预失真函数系数计算单元、模数转换器、下变频器、以及衰减器。如图3所示，所述数字预失真处理模块包括：N倍插值多相滤波器、前路由单元、数字预失真计算单元1至数字预失真计算单元N、N倍抽取多相滤波器、以及后路由单元。如图4所示，所述数字预失真处理模块包括：N倍插值多相滤波器、前路由单元、数字预失真计算单元1至数字预失真计算单元N、N倍抽取多相滤波器、后路由单元、以及加法器。所述N倍插值多相滤波器包括N个子滤波器，每个子滤波器的系数可以不同，所述N倍抽取多相滤波器包括N个子滤波器，每个子滤波器的系数可以不同。
其中，单通道宽频带模式对应上述的第一模式，多通道模式对应上述的第二模式。所述控制单元对应上述的控制单元11，所述N倍插值多相滤波器对应上述的第一滤波器单元12，所述N倍抽取多相滤波器对应上述的第二滤波器单元14，数字预失真计算单元1至数字预失真计算单元M对应上述的预失真计算单元13中的子计算单元1至子计算单元M，加法器对应上述的合路器。
另外，本应用实施例中的应用场景为：工作在单通道宽频带模式时，通过控制单元、N倍插值多相滤波器、前路由单元、数字预失真计算单元1至数字预失真计算单元N、N倍抽取多相滤波器、以及后路由单元，对单通道输入的数据序列进行预失真处理。
第一步，通过软件配置所述单通道宽频带模式和多通道模式。
这里，所述控制单元可以由DSP、FPGA等处理器实现，这样，可以通过软件编程配置所述数字预失真模块支持的工作模式。当需要所述数字预失真模块支持对单通道输入的数据序列进行预失真处理且能够提高频带宽度时，可以配置为单通道宽频带模式；当需要所述数字预失真模块支持对多通道输入的数据序列进行预失真处理时，可以配置为多通道模式。
第二步，所述控制单元判断工作的模式，当确定工作在单通道宽频带模式时，生成第一控制信号。
这里，所述第一控制信号可以对N倍插值多相滤波器、前路由单元、N倍抽取多相滤波器及后路由单元进行控制。
第三步，N倍插值多相滤波器响应所述第一控制信号，将通道1输入的1倍采样率的一路数据序列通过N倍插值转换为N倍采样率的数据序列，得到多个分支的数据序列，即第1相(第1分支)至第N相(第N分支)的数据序列。
第四步，前路由单元响应所述第一控制信号，接通所述N倍插值多相滤波器与对应的数字预失真计算单元，以将N倍插值多相滤波器输出的经过插值处理后的N个分支的数据序列输入至对应的数字预失真计算单元。
第五步，数字预失真计算单元1至数字预失真计算单元M对经过插值后的N个分支的数据序列进行预失真处理。
其中，数字预失真计算单元1对第1相数据序列进行预失真处理，数字预 失真计算单元2对第2相数据序列进行预失真处理，以此类推，数字预失真计算单元M对第N相数据序列进行预失真处理。其中，M、N均为大于1的正整数，且N等于M。需要说明的是，当N小于M时，多出的(M-N)个数字预失真计算单元可以不使用。
第六步，N倍抽取多相滤波器响应所述第一控制信号，对经过插值、预失真处理后的N相数据序列进行滤波，得到多个滤波处理后的第一数据序列。通过加法器，对多个滤波处理后的第一数据序列进行合路，得到第三数据序列。在本实施例中，上述的加法器即为前述的合路器，该加法器可以设置于N倍抽取多相滤波器之后，对N倍抽取多相滤波器的N个分支输出的多个滤波处理后的第一数据序列进行合路，以得到第三数据序列，如图4所示。
第七步，后路由单元响应所述第一控制信号，通过所述加法器接通所述第二滤波器单元与单个输出通道，例如通道1，以在通道1输出所述第三数据序列，在除通道1以外的其他通道输出零序列。
需要说明的是，本应用实施例中，当工作在单通道宽频带模式时，N倍插值多相滤波器、前路由单元、数字预失真计算单元1至数字预失真计算单元M、N倍抽取多相滤波器、以及后路由单元之间的数据处理是有关联而非独立的。
工作在多通道模式时，通过控制单元、前路由单元、数字预失真计算单元1至数字预失真计算单元N、以及后路由单元，对多通道输入的多路数据序列分别进行预失真处理。
第一步，通过软件配置所述单通道宽频带模式和多通道模式。
这里，所述控制单元可以由DSP、FPGA等处理器实现，这样，可以通过软件编程配置所述数字预失真模块支持的工作模式。当需要所述数字预失真模块支持对单通道输入的数据序列进行预失真处理且能够提高频带宽度时，可以配 置为单通道宽频带模式；当需要所述数字预失真模块支持对多通道输入的数据序列进行预失真处理时，可以配置为多通道模式。
第二步，所述控制单元判断工作的模式，当确定工作在多通道模式时，生成第二控制信号。
这里，所述第二控制信号可以对前路由单元、后路由单元进行控制。
第三步，前路由单元响应所述第二控制信号，接通多个输入通道与对应的数字预失真计算单元，以输出P个通道输入的多路数据序列。
第四步，数字预失真计算单元1至数字预失真计算单元M对所述多路数据序列进行预失真处理，得到第二数据序列。
其中，数字预失真计算单元1对通道1输入的一路数据序列进行预失真处理，数字预失真计算单元2对通道2输入的一路数据序列进行预失真处理，以此类推，数字预失真计算单元M对通道P输入的一路数据序列进行预失真处理。其中，M、P均为大于1的正整数，且P等于M。需要说明的是，当P小于M时，多出的(M-P)个数字预失真计算单元可以不使用。
第五步，后路由单元响应所述第二控制信号，接通数字预失真计算单元与多个输出通道，以在相应通道输出对应的多个预失真处理后的第二数据序列。
这里，在通道1输出数字预失真计算单元1处理后的第二数据序列，在通道2输出数字预失真计算单元2处理后的第二数据序列，以此类推，在通道M输出数字预失真计算单元M处理后的第二数据序列。
需要说明的是，在本应用实施例中，当工作在第二模式时，N倍插值滤波器12、前路由单元、N个数字预失真计算单元13、N倍抽取滤波器14、以及后路由单元之间的数据处理是独立的。
图5是本申请实施例数据处理方法的实现流程示意图，结合上述的数字预 失真处理模块的结构示意图，如图5所示，所述方法包括：
步骤501：控制单元判断当前是否工作在单通道宽频带模式。当确定工作在单通道宽频带模式时，执行步骤502；当确定工作在多通道模式时，执行步骤507。
步骤502：N倍插值多相滤波器按照通道1输入的一路数据序列的采样率的N倍采样率，对所述输入的数据序列进行滤波，得到多个分支的数据序列，并执行步骤503。
步骤503：前路由单元接通所述N倍插值多相滤波器与对应的数字预失真计算单元，以输出所述多个分支的数据序列，并执行步骤504。
步骤504：数字预失真计算单元1至数字预失真计算单元M基于第一预失真系数，对所述多个分支的数据序列分别进行预失真处理，得到多个预失真处理后的第一数据序列，并执行步骤505。
步骤505：N倍插值多相滤波器基于所述一路数据序列的采样率，对多个预失真处理后的第一数据序列进行滤波处理，得到多个滤波处理后的第一数据序列；通过加法器对多个滤波处理后的第一数据序列进行合路得到的第三数据序列，并执行步骤506。
步骤506：后路由单元接通所述N倍抽取多相滤波器与多个输出通道，在通道1输出第三数据序列，在其他通道输出零序列，结束。
步骤507：前路由单元接通输入通道与对应的数字预失真计算单元，以输出所述多路数据序列，并执行步骤508。
步骤508：数字预失真计算单元1至数字预失真计算单元M基于第二预失真系数，对通过多通道输入的多路数据序列分别进行预失真处理，得到多个预失真处理后的第二数据序列，并执行步骤509。
步骤509：后路由单元接通数字预失真计算单元与多个输出通道，以在相应通道输出对应的预失真处理后的第二数据序列，结束。
基于上述数据处理装置，本申请实施例还提供了一种数据处理方法，如图6所示，该方法包括：
步骤601：数据处理装置中的控制单元判断工作的模式，当确定工作在第一模式时，生成第一控制信号，当确定工作在第二模式时，生成第二控制信号。
步骤602：所述数据处理装置中的第一滤波器单元响应所述第一控制信号，基于第一输入通道输入的数据序列的采样率的N倍采样率，对所述输入的数据序列进行滤波，得到多个分支的数据序列，响应所述第二控制信号，停止对所述第一输入通道输入的数据序列的滤波处理，其中N为正整数。
步骤603：所述数据处理装置中的预失真计算单元对所述多个分支的数据序列分别进行基于第一预失真系数的预失真处理，得到多个预失真处理后的第一数据序列，或者，对通过多个输入通道输入的多路数据序列分别进行基于第二预失真系数的预失真处理，得到多个预失真处理后的第二数据序列。
步骤604：所述数据处理装置中的第二滤波器单元响应所述第一控制信号，基于所述第一输入通道输入的数据序列的采样率，对所述多个预失真处理后的第一数据序列进行滤波处理，得到多个滤波处理后的第一数据序列，响应所述第二控制信号，停止对所述多个预失真处理后的第一数据序列的滤波处理。
其中，所述第一模式可以为单通道高频带模式，所述第二模式可以为多通道模式。在所述单通道高频带模式下，不仅能够对单通道输入的数据序列进行预失真处理，而且可以提高待预失真处理的数据序列的频带宽度；在所述多通道模式下，可以对多通道输入的数据序列进行预失真处理。
实际应用时，所述控制单元可以由DSP、FPGA等处理器实现，这样，可以 通过软件编程配置所述第一模式和第二模式。
这里，通过所述第一滤波器单元，可以将单通道输入的1倍采样率的数据序列转换为N倍采样率的数据序列，从而可以提高数据序列的采样率，进而能够增加待预失真处理的数据序列的频带宽度。
实际应用时，所述第一滤波器单元包括多个子滤波单元，这样，可以通过多个子滤波单元对所述输入的数据序列分别进行滤波，得到多个分支的数据序列。预失真计算单元可以包括多个子计算单元，通过相应的子计算单元对相应子滤波单元输出的数据序列进行预失真处理。
基于此，在一实施例中，所述第一滤波器单元包括N个子滤波单元，所述预失真计算单元可以包括M个子计算单元。其中，N和M均为正整数，且N小于或等于M。当N等于M时，所述N个子滤波单元与所述M个子计算单元一一对应；当N小于M时，所述N个子滤波单元与所述M个子计算单元中的N个子计算单元一一对应，并且所述M个子计算单元中剩余的M-N个子计算单元不使用。
在一实施方式中，在所述第一模式下，子计算单元1可以对所述第一输入通道输入的一路数据序列滤波得到的第1个分支的数据序列进行预失真处理，子计算单元2可以对第2个分支的数据序列进行预失真处理，以此类推，子计算单元M可以对第N个分支的数据序列进行预失真处理。其中，M、N均为大于1的正整数，且N等于M。需要说明的是，当N小于M时，多出的(M-N)个子计算单元可以不使用。
在所述第二模式下，子单元1可以对通道1输入的数据序列进行预失真处理，子计算单元2可以对通道2输入的数据序列进行预失真处理，以此类推，子计算单元M可以对通道P输入的数据序列进行预失真处理。其中，M、P均 为大于1的正整数，且P等于M。
实际应用时，对所述第一输入通道输入的数据序列滤波得到的多个分支的数据序列和所述多个输入通道输入的多路数据序列可以同时输入到所述预失真计算单元。这样，当工作在所述第一模式时，所述预失真计算单元需要对所述多个分支的数据序列进行预失真处理；当工作在所述第二模式时，所述预失真计算单元需要对所述多路数据序列进行预失真处理。
基于此，在一实施例中，所述方法还包括：所述数据处理装置中的前路由单元响应所述第一控制信号，接通所述第一滤波器单元与所述预失真计算单元，以将所述第一滤波器单元输出的所述多个分支的数据序列输入到所述预失真计算单元；响应所述第二控制信号，接通多个输入通道与所述预失真计算单元，以输出所述多路数据序列。
这里，所述前路由单元可由多个二路选择器实现，每个二路选择器的输入可以与所述第一滤波器单元中的每个子滤波单元以及所述多个输入通道中的一个输入通道相连，每个二路选择器的输出可以与所述预失真计算单元中对应的子计算单元相连。在所述第一控制信号作用下，每个二路选择器接通子滤波单元与相应的子计算单元，以输出所述多个分支的数据序列中的一个分支的数据序列，在所述第二控制信号作用下，每个二路选择器接通输入通道与相应的子计算单元，以输出所述多路数据序列中的一路数据序列。
实际应用时，经过所述预失真计算单元处理后的数据序列可以进行数模转换处理，得到模拟序列，以作为功放的输入序列。
基于此，在一实施例中，所述方法还包括：所述数据处理装置中的合路器对多个滤波处理后的第一数据序列进行合路，得到第三数据序列。
实际应用时，经过数模转换处理得到的模拟序列，可以送入功放。
基于此，在一实施例中，所述方法还包括：所述数据处理装置中的后路由单元响应所述第一控制信号，通过所述合路器接通所述第二滤波器单元与第一输出通道，以在当前通道输出所述第三数据序列，在其他通道输出零序列；响应所述第二控制信号，接通所述预失真计算单元与多个输出通道，以在相应通道输出对应的预失真处理后的第二数据序列。
这里，当通道的数量为P个时，所述当前通道可以是指第一个通道，或者，根据实际情况，从P个通道中选取一个通道作为所述当前通道。
实际应用时，确定预失真系数的函数模型可以有多种，因而可以使用不同的函数模型分别确定两种模式对应的预失真系数，所述函数模型可以包括Wiener模型、并联Wiener模型、神经网络模型等等。
基于此，在一实施例中，所述方法还包括：所述数据处理装置的预失真函数系数计算单元响应所述第一控制信号，向所述预失真计算单元输出所述第一预失真系数；响应所述第二控制信号，向所述预失真计算单元输出所述第二预失真系数。
实际应用时，通过预失真技术对功率放大器的输入数据进行处理，可以使工作在非线性区域的功率放大器仍能满足无线通信系统对线性化的要求。这样，可以将所述预失真计算单元处理后的数据序列作为功率放大器的输入数据；并对所述预失真计算单元处理后的数据序列进行数模转换、功率放大处理，得到输出数据，且能够使功率放大器的输出数据与输入数据满足线性关系。
基于此，在一实施例中，所述方法还包括：所述数据处理装置中的功率放大单元对所述第二数据序列进行数模转换处理，得到数模转换处理后的第二数据序列；对数模转换处理后的第二数据序列进行功率放大处理，得到第一输出序列，或者，对所述第三数据序列进行数模转换处理，得到数模转换处理后的 第三数据序列；对数模转换处理后的第三数据序列进行功率放大处理，得到第二输出序列。其中，所述第一输出序列与所述第二数据序列满足线性关系，所述第二输出序列与所述第三数据序列满足线性关系。
那么从控制单元的角度来说，如图7所示，该方法包括：
步骤701：判断工作的模式。
步骤702：当确定工作在第一模式时，生成第一控制信号，当确定工作在第二模式时，生成第二控制信号；
这里，所述第一控制信号用于控制N倍插值多相滤波器按照当前通道输入的一路数据序列的采样率的N倍采样率，对所述一路数据序列进行滤波，得到多个分支的数据序列。所述多个分支的数据序列用于供预失真计算单元进行基于第一预失真系数的预失真处理，得到多个预失真处理后的第一数据序列。所述第一控制信号还用于供N倍抽取多相滤波器按照所述一路数据序列的采样率，对多个预失真处理后的第一数据序列进行滤波处理，得到多个滤波处理后的第一数据序列。
所述第二控制信号用于控制N倍插值多相滤波器停止对所述一路数据序列的滤波处理，并控制N倍抽取多相滤波器停止对所述多个预失真处理后的第一数据序列的滤波处理，以便于预失真计算单元对通过多个输入通道输入的多路数据序列分别进行基于第二预失真系数的预失真处理，得到多个预失真处理后的第二数据序列。所述第二控制信号还用于控制后路由单元在相应通道输出对应的预失真处理后的第二数据序列。
这里，所述第一模式可以为单通道高频带模式，所述第二模式可以为多通道模式。在所述单通道高频带模式下，不仅能够对单通道输入的数据序列进行预失真处理，而且可以提高待预失真处理的数据序列的频带宽度；在所述多通 道模式下，可以对多通道输入的多路数据序列分别进行预失真处理。
这里，当工作在所述第一模式时，可以通过N倍插值多相滤波器、前路由单元、N倍抽取多相滤波器、以及后路由单元，实现对单通道输入的一路数据序列进行滤波，得到多个分支的数据序列；通过前路由单元，接通所述第一滤波器单元与所述预失真计算单元，以将所述第一滤波单元输出的所述多个分支的数据序列输入至所述预失真计算单元；通过预失真计算单元，对所述多个分支的数据序列分别进行基于第一预失真系数的预失真处理，得到多个预失真处理后的第一数据序列；通过N倍抽取多相滤波器，按照所述一路数据序列的采样率，对多个预失真处理后的第一数据序列进行滤波处理，得到多个滤波处理后的第一数据序列；通过后路由单元，利用所述合路器接通所述第二滤波器单元与第一输出通道，以在当前通道输出第三数据序列，在其他通道输出零序列，所述第三数据序列为对多个滤波处理后的第一数据序列进行合路得到的数据序列。
当工作在所述第二模式时，所述第二控制信号可以对前路由单元、后路由单元进行控制。通过前路由单元，向所述预失真计算单元输出所述多路数据序列；通过预失真计算单元，对通过多个输入通道输入的多路数据序列分别进行基于第二预失真系数的预失真处理，得到多个预失真处理后的第二数据序列；通过后路由单元，接通所述预失真计算单元与多个输出通道，以在相应通道输出对应的预失真处理后的第二数据序列。
基于前述的实施例，本申请实施例提供一种数据处理装置80。如图8所示，所述数据处理装置80包括处理器81和用于存储能够在处理器81上运行的计算机程序的存储器82。其中，所述处理器81用于设置为运行所述计算机程序时，以实现上述实施例中提供的数据处理方法中的步骤。所述数据处理装置80还包 括总线83，所述总线83用于连接所述处理器81和所述存储器82，并进行数据的传输。
在示例性实施例中，本申请实施例还提供了一种存储介质，即计算机存储介质，例如为计算机可读存储介质，例如包括存储计算机程序的存储器82，上述计算机程序可由数据处理装置80的处理器81执行，以完成前述相应方法所述步骤。计算机可读存储介质可以是磁性随机存取存储器(Ferromagnetic Random Access Memory，FRAM)、只读存储器Read Only Memory，ROM)、可编程只读存储器(Programmable Read-Only Memory，PROM)、可运动路线的展示可编程只读存储器(Erasable Programmable Read-Only Memory，EPROM)、电可运动路线的展示可编程只读存储器(Electrically Erasable Programmable Read-Only Memory，EEPROM)、快闪存储器(Flash Memory)、磁表面存储器、光盘、或只读光盘(Compact Disc Read-Only Memory，CD-ROM)等存储器。
另外，本申请实施例所记载的技术方案之间，在不冲突的情况下，可以任意组合。
需要说明的是：“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。

Claims (13)

  1. 一种数据处理装置，包括：
    控制单元，设置为判断工作的模式，当确定工作在第一模式时，生成第一控制信号，当确定工作在第二模式时，生成第二控制信号；
    第一滤波器单元，设置为响应所述第一控制信号，基于第一输入通道输入的数据序列的采样率的N倍采样率，对所述输入的数据序列进行滤波，得到多个分支的数据序列，以及响应所述第二控制信号，停止对所述第一输入通道输入的数据序列的滤波处理，其中N为正整数；
    预失真计算单元，设置为对所述多个分支的数据序列分别进行基于第一预失真系数的预失真处理，得到多个预失真处理后的第一数据序列，或者，对通过多个输入通道输入的多路数据序列分别进行基于第二预失真系数的预失真处理，得到多个预失真处理后的第二数据序列；
    第二滤波器单元，设置为响应所述第一控制信号，基于所述第一输入通道输入的数据序列的采样率，对所述多个预失真处理后的第一数据序列分别进行滤波处理，得到多个滤波处理后的第一数据序列，以及响应所述第二控制信号，停止对所述多个预失真处理后的第一数据序列的滤波处理。
  2. 根据权利要求1所述的装置，还包括：
    前路由单元，设置为响应所述第一控制信号，接通所述第一滤波器单元与所述预失真计算单元，以将所述第一滤波器单元输出的所述多个分支的数据序列输入至所述预失真计算单元，以及响应所述第二控制信号，接通所述多个输入通道与所述预失真计算单元，以输出所述多路数据序列。
  3. 根据权利要求1所述的装置，所述装置还包括：
    合路器，设置为对所述多个滤波处理后的第一数据序列进行合路，得到第 三数据序列。
  4. 根据权利要求3所述的装置，还包括：
    后路由单元，设置为响应所述第一控制信号，通过所述合路器接通所述第二滤波器单元与第一输出通道，以输出所述第三数据序列，以及响应所述第二控制信号，接通所述预失真计算单元与多个输出通道，以输出对应的所述多个预失真处理后的第二数据序列。
  5. 根据权利要求1所述的装置，还包括：
    预失真函数系数计算单元，设置为响应所述第一控制信号，向所述预失真计算单元输出所述第一预失真系数，以及响应所述第二控制信号，向所述预失真计算单元输出所述第二预失真系数。
  6. 根据权利要求1所述的装置，其中，
    所述第一滤波器单元包括N个子滤波单元，所述预失真计算单元包括M个子计算单元，其中，N和M均为正整数，且N小于或等于M；
    当N等于M时，所述N个子滤波单元与所述M个子计算单元一一对应；
    当N小于M时，所述N个子滤波单元与所述M个子计算单元中的N个子计算单元一一对应，并且所述M个子计算单元中剩余的M-N个子计算单元不使用。
  7. 一种数据处理方法，包括：
    判断工作的模式，当确定工作在第一模式时，生成第一控制信号，当确定工作在第二模式时，生成第二控制信号；
    响应所述第一控制信号，基于第一输入通道输入的数据序列的采样率的N倍采样率，对所述输入的数据序列进行滤波，得到多个分支的数据序列，响应所述第二控制信号，停止对所述第一输入通道输入的数据序列的滤波处理，其 中N为正整数；
    对所述多个分支的数据序列分别进行基于第一预失真系数的预失真处理，得到多个预失真处理后的第一数据序列，或者，对通过多个输入通道输入的多路数据序列分别进行基于第二预失真系数的预失真处理，得到多个预失真处理后的第二数据序列；
    响应所述第一控制信号，基于所述第一输入通道输入的数据序列的采样率，对所述多个预失真处理后的第一数据序列分别进行滤波处理，得到多个滤波处理后的第一数据序列，响应所述第二控制信号，停止对所述多个预失真处理后的第一数据序列的滤波处理。
  8. 根据权利要求7所述的方法，还包括：
    响应所述第一控制信号，接通第一滤波器单元与预失真计算单元，以将所述第一滤波器单元输出的所述多个分支的数据序列输入至所述预失真计算单元；
    响应所述第二控制信号，接通所述多个输入通道与所述预失真计算单元，以输出所述多路数据序列。
  9. 根据权利要求7所述的方法，还包括：
    对所述多个滤波处理后的第一数据序列进行合路，得到第三数据序列。
  10. 根据权利要求9所述的方法，还包括：
    响应所述第一控制信号，通过所述合路器接通所述第二滤波器单元与第一输出通道，以输出所述第三数据序列；
    响应所述第二控制信号，接通预失真计算单元与多个输出通道，以输出对应的所述多个预失真处理后的第二数据序列。
  11. 根据权利要求7所述的方法，还包括：
    响应所述第一控制信号，向预失真计算单元输出所述第一预失真系数；
    响应所述第二控制信号，向所述预失真计算单元输出所述第二预失真系数。
  12. 一种数据处理装置，包括处理器和用于存储能够在处理器上运行的计算机程序的存储器；其中，所述处理器用于运行所述计算机程序时，执行权利要求7-11中任一项所述的数据处理方法中的步骤。
  13. 一种计算机可读存储介质，其上存储有计算机程序，其中，该计算机程序被处理器执行时实现权利要求7-11中任一项所述的数据处理方法中的步骤。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116938161A (zh) * 2022-04-08 2023-10-24 中国移动通信有限公司研究院 一种带限数字预失真系统和方法
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102361476A (zh) * 2011-07-29 2012-02-22 上海交通大学 宽带多频段功放数字预失真装置及其方法
CN102571657A (zh) * 2010-12-10 2012-07-11 中兴通讯股份有限公司 一种变换采样率的数字预失真处理系统和方法
CN103609018A (zh) * 2011-05-12 2014-02-26 安德鲁有限责任公司 基于插值的数字预失真结构
CN104580044A (zh) * 2014-12-29 2015-04-29 大唐移动通信设备有限公司 一种预失真处理方法和系统
US20150381220A1 (en) * 2014-06-27 2015-12-31 Freescale Semiconductor, Inc. Adaptive high-order nonlinear function approximation using time-domain volterra series to provide flexible high performance digital pre-distortion

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101257481B (zh) * 2008-04-22 2012-09-05 中兴通讯股份有限公司 一种预处理不连续配置多载波的削峰系统和方法
US8560592B2 (en) * 2010-07-30 2013-10-15 National Instruments Corporation Performing multiplication for a multi-channel notch rejection filter
CN103685099B (zh) * 2012-09-25 2017-05-24 京信通信系统（中国）有限公司 一种对信号进行变频调整的方法和设备
CN104301268B (zh) * 2013-07-19 2019-05-21 中兴通讯股份有限公司 多通道预失真方法及装置
TWI536731B (zh) * 2013-08-20 2016-06-01 瑞昱半導體股份有限公司 預失真方法、預失真裝置以及機器可讀媒體
CN103929388B (zh) * 2014-04-23 2017-10-03 大唐移动通信设备有限公司 一种数据处理系统及处理方法
US9768985B2 (en) * 2016-01-26 2017-09-19 Nxp B.V. Equalization from presence change transients
CN106506417B (zh) * 2017-01-03 2020-01-24 电子科技大学 一种窄带反馈的数字预失真系统与方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102571657A (zh) * 2010-12-10 2012-07-11 中兴通讯股份有限公司 一种变换采样率的数字预失真处理系统和方法
CN103609018A (zh) * 2011-05-12 2014-02-26 安德鲁有限责任公司 基于插值的数字预失真结构
CN102361476A (zh) * 2011-07-29 2012-02-22 上海交通大学 宽带多频段功放数字预失真装置及其方法
US20150381220A1 (en) * 2014-06-27 2015-12-31 Freescale Semiconductor, Inc. Adaptive high-order nonlinear function approximation using time-domain volterra series to provide flexible high performance digital pre-distortion
CN104580044A (zh) * 2014-12-29 2015-04-29 大唐移动通信设备有限公司 一种预失真处理方法和系统

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