WO2020113841A1 - 低温多晶硅显示面板制造方法 - Google Patents

低温多晶硅显示面板制造方法 Download PDF

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WO2020113841A1
WO2020113841A1 PCT/CN2019/078291 CN2019078291W WO2020113841A1 WO 2020113841 A1 WO2020113841 A1 WO 2020113841A1 CN 2019078291 W CN2019078291 W CN 2019078291W WO 2020113841 A1 WO2020113841 A1 WO 2020113841A1
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layer
forming
silicon oxide
oxide layer
silicon
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PCT/CN2019/078291
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French (fr)
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江艺
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武汉华星光电半导体显示技术有限公司
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Priority to US16/349,657 priority Critical patent/US20200203398A1/en
Publication of WO2020113841A1 publication Critical patent/WO2020113841A1/zh

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Definitions

  • the present invention relates to a method for manufacturing a low-temperature polysilicon display panel, which can avoid the amorphous silicon (a-Si) layer before the excimer laser annealing (Excimer-Laser Annealing, ELA) process, the amorphous Particles or metal ions adhered to the air remain on the silicon layer, which causes defects in the crystal lattice of the polycrystalline silicon formed by the amorphous silicon layer and reduces the yield of the display panel.
  • a-Si amorphous silicon
  • ELA excimer laser annealing
  • LTPS Low Temperature Poly-silicon
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the biggest difference between the technology and the traditional amorphous silicon display is that the LTPS reaction speed is relatively fast, and has the advantages of high brightness, high resolution, and low power consumption.
  • the excimer laser annealing (Excimer-Laser Annealing, ELA) process is required to generate polysilicon (Poly-Si) on the amorphous silicon (a-Si) layer.
  • Amorphous Silicon (a-Si) surface is cleaned to improve TFT electrical properties.
  • the excimer laser annealing process of the prior art is performed by exposure to general atmospheric environment and cannot prevent the air flow from causing particles or metal ions to adhere to the amorphous silicon layer. Therefore, hydrofluoric acid plus ozone must be used in the process HF+O3) Clean the surface of the amorphous silicon layer to avoid residual particles or metal ions.
  • the surface of the amorphous silicon layer is not completely clean and particles or metal ions remain, the surface of the amorphous silicon layer is easily oxidized, and when the amorphous silicon layer is laser crystallized to form polysilicon, the amorphous silicon layer remains in the amorphous The particles or metal ions of the silicon layer absorb laser energy, causing many defects in the polycrystalline silicon lattice formed on the amorphous silicon layer, which affects the electrical uniformity of the finished low-temperature polycrystalline silicon.
  • the natural oxide layer on the surface of the amorphous silicon layer has uneven structural defects.
  • the structural defects are also removed by the aforementioned hydrofluoric acid (HF), and then O3 is used on the surface of the cleaned amorphous silicon layer.
  • a silicon oxide (SiO) coating layer is formed.
  • the step of cleaning with hydrofluoric acid is performed in a general atmospheric environment, the problem of particles or metal ions remaining on the surface of the amorphous silicon layer after cleaning cannot be avoided, and the use of hydrofluoric acid is likely to cause product pollution and the environment Pollution.
  • the present invention provides a method for manufacturing a low-temperature polysilicon display panel, which can avoid the process of excimer-laser annealing (ELA) on an amorphous silicon (a-Si) layer. Particles or metal ions attached to the air remain on the amorphous silicon layer, which causes defects in the crystal lattice of the polycrystalline silicon formed by the amorphous silicon layer and reduces the yield of the display panel.
  • ELA excimer-laser annealing
  • the main object of the present invention is to provide a method for manufacturing a low-temperature polysilicon display panel, including:
  • Vacuum environment providing steps including providing a vacuum environment
  • the step of providing a substrate includes providing a glass substrate
  • the next silicon oxide layer forming step includes forming a silicon oxide (SiO) layer on the glass substrate;
  • the step of forming a silicon nitride layer includes forming a silicon nitride layer on the next silicon oxide layer;
  • the step of forming an upper silicon oxide layer includes forming an upper silicon oxide layer on the silicon nitride layer;
  • the step of forming an amorphous silicon layer includes forming an amorphous silicon layer on the upper silicon oxide layer in the vacuum environment;
  • the step of forming a protective layer includes forming a protective layer on the amorphous silicon layer;
  • the annealing step includes excimer laser annealing the amorphous silicon layer to form poly-Si on the amorphous silicon layer.
  • the step of forming the protective layer is performed in the vacuum environment.
  • the annealing step is performed in the vacuum environment.
  • the substrate providing step, the next silicon oxide layer forming step, the silicon nitride layer forming step, the upper silicon oxide layer forming step, and the annealing step At least one is performed in the vacuum environment.
  • the substrate providing step, the next silicon oxide layer forming step, the silicon nitride layer forming step, and the upper silicon oxide layer forming step are all in the vacuum environment Execution.
  • the vacuum environment is a vacuum chamber.
  • a vacuum pump is connected to the vacuum chamber, and the vacuum pump is used to evacuate the vacuum chamber.
  • the amorphous silicon layer is washed with hydrofluoric acid and ozone, and then the step of forming the protective layer is performed.
  • the protective layer is silicon monoxide.
  • Another object of the present invention is to provide a method for manufacturing a low-temperature polysilicon display panel, including:
  • Vacuum environment providing steps including providing a vacuum environment
  • the step of providing a substrate includes providing a glass substrate
  • the step of forming the next silicon oxide layer includes forming the next silicon oxide layer on the glass substrate;
  • the step of forming a silicon nitride layer includes forming a silicon nitride layer on the next silicon oxide layer;
  • the step of forming an upper silicon oxide layer includes forming an upper silicon oxide layer on the silicon nitride layer;
  • the step of forming an amorphous silicon layer includes forming an amorphous silicon layer onto the upper silicon oxide layer in the vacuum environment;
  • the step of forming a protective layer includes forming a protective layer on the amorphous silicon layer;
  • the annealing step includes excimer laser annealing the amorphous silicon layer to form polysilicon on the amorphous silicon layer;
  • the step of forming the protective layer is performed in the vacuum environment
  • the annealing step is performed in the vacuum environment
  • At least one of the substrate providing step, the next silicon oxide layer forming step, the silicon nitride layer forming step, the upper silicon oxide layer forming step, and the annealing step are in the Perform in a vacuum environment.
  • the substrate providing step, the next silicon oxide layer forming step, the silicon nitride layer forming step, and the upper silicon oxide layer forming step are all in the vacuum environment Execution.
  • the vacuum environment is a vacuum chamber.
  • a vacuum pump is connected to the vacuum chamber, and the vacuum pump is used to evacuate the vacuum chamber.
  • the amorphous silicon layer is washed with hydrofluoric acid and ozone, and then the step of forming the protective layer is performed.
  • the protective layer is silicon monoxide.
  • the method for manufacturing a low-temperature polysilicon display panel of the present invention can avoid the atmospheric atmosphere by performing at least the step of forming the amorphous silicon layer in the vacuum environment instead of the general atmospheric environment. Dust particles and metal ions remain on the amorphous silicon layer. Particles or metal ions attached to the air remain on the amorphous silicon layer, which causes defects in the lattice of polysilicon formed by the a-Si layer and reduces the yield of the display panel.
  • the polycrystalline silicon layer generated by the excimer laser annealing step of the method for manufacturing a low-temperature polycrystalline silicon display panel of the present invention has a better lattice arrangement structure than the prior art, avoiding lattice defects, thereby improving the display panel Yield and quality.
  • the step of cleaning the amorphous silicon with hydrofluoric acid and ozone becomes Necessary steps to improve the efficiency of the display panel manufacturing process and reduce environmental pollution.
  • FIG. 1 is a schematic diagram of a method for manufacturing a low-temperature polysilicon display panel of the present invention performed in a vacuum environment.
  • FIG. 2 is a flow chart of the steps of the method for manufacturing a low-temperature polysilicon display panel of the present invention.
  • the method for manufacturing a low-temperature polysilicon display panel of the present invention includes: a vacuum environment providing step S01, a substrate providing step S02, a next silicon oxide layer forming step S03, a silicon nitride layer forming step S04, a previous oxidation
  • the vacuum environment providing step S01 includes providing a vacuum environment 100.
  • the vacuum environment 100 is a vacuum chamber.
  • a vacuum pump 110 is connected to the vacuum chamber, and the vacuum pump 110 is used to evacuate the vacuum chamber.
  • the vacuum pump 110 can evacuate the vacuum chamber throughout to maintain the vacuum degree in the vacuum chamber.
  • the vacuum pump 110 may selectively evacuate the vacuum chamber only when specific steps are performed, so as to more efficiently maintain the vacuum conditions of the vacuum chamber and avoid excessive power consumption due to continuous vacuuming problem.
  • the substrate providing step S02 includes providing a glass substrate 10.
  • the next silicon oxide layer forming step S03 includes forming the next silicon oxide layer 20 onto the glass substrate 10.
  • the silicon nitride layer forming step S04 includes forming a silicon nitride layer 30 onto the next silicon oxide layer 20.
  • the upper silicon oxide layer forming step S05 includes forming an upper silicon oxide layer 40 onto the silicon nitride layer 30.
  • the protective layer forming step S07 is performed in the vacuum environment 100.
  • the step S06 of forming the amorphous silicon layer includes forming an amorphous silicon layer 50 on the upper silicon oxide layer 40 in the vacuum environment 100.
  • the protective layer forming step S07 includes forming a protective layer 60 on the amorphous silicon layer 50.
  • the protective layer 60 is silicon monoxide.
  • the annealing step S08 includes performing excimer-laser annealing (ELA) on the amorphous silicon layer 50 to form poly-silicon (Poly-Si) on the amorphous silicon layer 50.
  • ELA excimer-laser annealing
  • the annealing step S08 is performed in the vacuum environment 100.
  • the amorphous silicon layer forming step S06 the amorphous silicon layer 50 is washed with hydrofluoric acid and ozone, and then the protective layer forming step S07 is performed.
  • the substrate provides step S02, the next silicon oxide layer forming step S03, the silicon nitride layer forming step S04, the upper silicon oxide layer forming step S05, and all At least one of the annealing steps S08 is performed in the vacuum environment 100.
  • the substrate providing step S02, the next silicon oxide layer forming step S03, the silicon nitride layer forming step S04, and the upper silicon oxide layer forming step S05 are all in The vacuum environment 100 is executed.
  • the method for manufacturing a low-temperature polysilicon display panel of the present invention can avoid the atmosphere by performing at least the amorphous silicon layer forming step S06 in the vacuum environment 100 instead of the general atmospheric environment Dust particles and metal ions remain in the amorphous silicon layer 50.
  • the polycrystalline silicon layer generated by the excimer laser annealing step S08 in the method for manufacturing a low-temperature polysilicon display panel of the present invention has a better lattice arrangement structure than the prior art, to avoid lattice defects, and Improve the yield and quality of the display panel.
  • the step of cleaning the amorphous silicon with hydrofluoric acid and ozone It becomes an unnecessary step to improve the efficiency of the display panel process and reduce environmental pollution.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Electroluminescent Light Sources (AREA)
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Abstract

一种低温多晶硅显示面板制造方法,包括:真空环境提供步骤,包括提供一真空环境;基板提供步骤,包括提供一玻璃基板;下一氧化硅层形成步骤,包括形成一下一氧化硅层到所述玻璃基板上;氮化硅层形成步骤,包括形成一氮化硅层到所述下一氧化硅层上;上一氧化硅层形成步骤,包括形成一上一氧化硅层到所述氮化硅层上;非晶硅层形成步骤,包括在所述真空环境中,形成一非晶硅层到所述上一氧化硅层上;保护层形成步骤,包括形成一保护层到所述非晶硅层上;退火步骤,包括对所述非晶硅层进行准分子雷射退火以在所述非晶硅层上形成多晶硅。本发明可避免所述非晶硅层上因残留有空气中粒子或金属离子而使生成的多晶硅晶格产生缺陷的问题。

Description

低温多晶硅显示面板制造方法 技术领域
本发明是有关于一种低温多晶硅显示面板制造方法,其可避免在对一非晶硅(a-Si)层实施准分子激光退火(Excimer-Laser Annealing, ELA)的工艺之前,所述非晶硅层上残留有自空气中附着的粒子或是金属离子,导致所述非晶硅层所形成的多晶硅的晶格产生缺陷而降低显示面板良率的问题。
背景技术
低温多晶硅(Low Temperature Poly-silicon, LTPS)为新一代薄膜晶体管液晶显示器((Thin Film Transistor Liquid Crystal Display, TFT-LCD)技术,所述技术与传统非晶硅显示器最大差异在于LTPS 反应速度相对较快,且有高亮度、高解析度、以及低耗电量等优点。
在制造低温多晶硅显示面板的工艺中,需要通过准分子激光退火(Excimer-Laser Annealing, ELA)工艺来在非晶硅(a-Si)层上生成多晶硅(Poly-Si),此前需要对非晶硅(Amorphous Silicon, a-Si)表面做清洁处理,以改善TFT电性。
现有技术的准分子激光退火工艺是暴露在一般大气环境下而进行而无法防止气流流动导致粒子或金属离子附着在非晶硅层上,因此在所述工艺中必须采用氢氟酸加臭氧(HF+O3) 对所述非晶硅层的表面进行清洁,避免粒子或金属离子残留。若是非晶硅层表面未完全清洁而残留有粒子或金属离子,则所述非晶硅层表面容易氧化,在对所述非晶硅层进行激光结晶而形成多晶硅时,残留在所述非晶硅层的粒子或金属离子会吸收激光能量,导致所述非晶硅层上形成的多晶硅晶格产生许多缺陷,而影响低温多晶硅成品电性均匀性。
此外,非晶硅层表面的自然氧化层存在凹凸不平的结构缺陷,所述结构缺陷亦是通过上述的氢氟酸(HF)去除,接着用O3在所述清洁过的非晶硅层表面再形成氧化硅(SiO)覆盖层。然而,由于用氢氟酸进行清洁的步骤在一般大气环境下进行,无法避免清洁后又有粒子或是金属离子残留于非晶硅层表面的问题,且使用氢氟酸容易造成产品污染与环境污染。
故,有必要提供一种低温多晶硅显示面板制造方法,以解决现有技术所存在的问题。
技术问题
有鉴于此,本发明提供一种低温多晶硅显示面板制造方法,其可避免在对一非晶硅(a-Si)层实施准分子激光退火(Excimer-Laser Annealing, ELA)的工艺之前,所述非晶硅层上残留有自空气中附着的粒子或是金属离子,导致所述非晶硅层所形成的多晶硅的晶格产生缺陷而降低显示面板良率的问题。
技术解决方案
本发明的主要目的在于提供一种低温多晶硅显示面板制造方法,包括:
真空环境提供步骤,包括提供一真空环境;
基板提供步骤,包括提供一玻璃基板;
下一氧化硅层形成步骤,包括形成一下一氧化硅(SiO)层到所述玻璃基板上;
氮化硅层形成步骤,包括形成一氮化硅层到所述下一氧化硅层上;
上一氧化硅层形成步骤,包括形成一上一氧化硅层到所述氮化硅层上;
非晶硅层形成步骤,包括在所述真空环境中,形成一非晶硅层到所述上一氧化硅层上;
保护层形成步骤,包括形成一保护层到所述非晶硅层上;以及
退火步骤,包括对所述非晶硅层进行准分子雷射退火以在所述非晶硅层上形成多晶硅(Poly-Si)。
在本发明的一实施例中,所述保护层形成步骤是在所述真空环境中执行。
在本发明的一实施例中,所述退火步骤是在所述真空环境中执行。
在本发明的一实施例中,所述基板提供步骤、所述下一氧化硅层形成步骤、所述氮化硅层形成步骤、所述上一氧化硅层形成步骤、以及所述退火步骤的至少一者是在所述真空环境中执行。
在本发明的一实施例中,所述基板提供步骤、所述下一氧化硅层形成步骤、所述氮化硅层形成步骤、以及所述上一氧化硅层形成步骤均在所述真空环境中执行。
在本发明的一实施例中,所述真空环境为一真空室。
在本发明的一实施例中,所述真空室连接有一真空泵,所述真空泵用于对所述真空室抽真空。
在本发明的一实施例中,在所述非晶硅层形成步骤之后,以氢氟酸及臭氧对所述非晶硅层进行清洗,再执行所述保护层形成步骤。
在本发明的一实施例中,所述保护层为一氧化硅。
本发明的另一目的在于提供一种低温多晶硅显示面板制造方法,包括:
真空环境提供步骤,包括提供一真空环境;
基板提供步骤,包括提供一玻璃基板;
下一氧化硅层形成步骤,包括形成一下一氧化硅层到所述玻璃基板上;
氮化硅层形成步骤,包括形成一氮化硅层到所述下一氧化硅层上;
上一氧化硅层形成步骤,包括形成一上一氧化硅层到所述氮化硅层上;
非晶硅层形成步骤,包括在所述真空环境中,形成一非晶硅层到所述上一氧化硅层上;
保护层形成步骤,包括形成一保护层到所述非晶硅层上;以及
退火步骤,包括对所述非晶硅层进行准分子雷射退火以在所述非晶硅层上形成多晶硅;
其中,所述保护层形成步骤是在所述真空环境中执行;
其中,所述退火步骤是在所述真空环境中执行;
其中,所述基板提供步骤、所述下一氧化硅层形成步骤、所述氮化硅层形成步骤、所述上一氧化硅层形成步骤、以及所述退火步骤的至少一者是在所述真空环境中执行。
在本发明的一实施例中,所述基板提供步骤、所述下一氧化硅层形成步骤、所述氮化硅层形成步骤、以及所述上一氧化硅层形成步骤均在所述真空环境中执行。
在本发明的一实施例中,所述真空环境为一真空室。
在本发明的一实施例中,所述真空室连接有一真空泵,所述真空泵用于对所述真空室抽真空。
在本发明的一实施例中,在所述非晶硅层形成步骤之后,以氢氟酸及臭氧对所述非晶硅层进行清洗,再执行所述保护层形成步骤。
在本发明的一实施例中,所述保护层为一氧化硅。
有益效果
与现有技术相比较,本发明的低温多晶硅显示面板制造方法,通过至少将所述非晶硅层形成步骤在所述真空环境中执行,而非在一般大气环境中执行,可避免大气中的尘埃粒子以及金属离子残留在所述非晶硅层上残留有自空气中附着的粒子或是金属离子,导致所述a-Si层所形成的多晶硅的晶格产生缺陷而降低显示面板良率的问题,因此,本发明低温多晶硅显示面板制造方法通过准分子激光退火步骤所生成的多晶硅层具有相较于现有技术具有较好的晶格排列结构,避免晶格缺陷,进而提升了显示面板的良率以及品质。此外,在形成所述非晶硅层后,由于所述非晶硅层表面所残留的粒子及金属离子显著减少,因此,以氢氟酸及臭氧对所述非晶硅的清洗的步骤成为非必要的步骤,藉此提升显示面板制程的效率并减少环境污染。
为让本发明的上述内容能更明显易懂,下文特举优选实施例,并配合所附图式,作详细说明如下:
附图说明
图1是一本发明低温多晶硅显示面板制造方法在一真空环境下执行的的示意图。
图2是本发明低温多晶硅显示面板制造方法的步骤流程图。
本发明的实施方式
请参照图1及图2,本发明低温多晶硅显示面板制造方法,包括:真空环境提供步骤S01、基板提供步骤S02、下一氧化硅层形成步骤S03、氮化硅层形成步骤S04、上一氧化硅层形成步骤S05、非晶硅层形成步骤S06、保护层形成步骤S07、以及退火步骤S08。
所述真空环境提供步骤S01包括提供一真空环境100。在本发明的一实施例中,所述真空环境100为一真空室。所述真空室连接有一真空泵110,所述真空泵110用于对所述真空室抽真空。所述真空泵110可全程对所述真空室抽真空以维持真空室内的真空度。或者,所述真空泵110也可选择性在特定的步骤执行时才对所述真空室抽真空,以较有效率地维持所述真空室的真空条件,并避免因持续抽真空而过于耗电的问题。
所述基板提供步骤S02包括提供一玻璃基板10。
所述下一氧化硅层形成步骤S03包括形成一下一氧化硅层20到所述玻璃基板10上。
所述氮化硅层形成步骤S04包括形成一氮化硅层30到所述下一氧化硅层20上。
所述上一氧化硅层形成步骤S05包括形成一上一氧化硅层40到所述氮化硅层30上。在本发明的一实施例中,所述保护层形成步骤S07是在所述真空环境100中执行。
所述非晶硅层形成步骤S06包括在所述真空环境100中,形成一非晶硅层50到所述上一氧化硅层40上。
所述保护层形成步骤S07包括形成一保护层60到所述非晶硅层50上。在本发明的一实施例中,所述保护层60为一氧化硅。
所述退火步骤S08包括对所述非晶硅层50进行准分子雷射退火(Excimer-Laser Annealing, ELA)以在所述非晶硅层50上形成多晶硅(Poly-Si)。在本发明的一实施例中,所述退火步骤S08是在所述真空环境100中执行。在本发明的一实施例中,在所述非晶硅层形成步骤S06之后,以氢氟酸及臭氧对所述非晶硅层50进行清洗,再执行所述保护层形成步骤S07。
在本发明的一实施例中,所述基板提供步骤S02、所述下一氧化硅层形成步骤S03、所述氮化硅层形成步骤S04、所述上一氧化硅层形成步骤S05、以及所述退火步骤S08的至少一者是在所述真空环境100中执行。
在本发明的一实施例中,所述基板提供步骤S02、所述下一氧化硅层形成步骤S03、所述氮化硅层形成步骤S04、以及所述上一氧化硅层形成步骤S05均在所述真空环境100中执行。
与现有技术相比较,本发明的低温多晶硅显示面板制造方法,通过至少将所述非晶硅层形成步骤S06在所述真空环境100中执行,而非在一般大气环境中执行,可避免大气中的尘埃粒子以及金属离子残留在所述非晶硅层50上残留有自空气中附着的粒子或是金属离子,导致所述非晶硅层50所形成的多晶硅的晶格产生缺陷而降低显示面板良率的问题,因此,本发明低温多晶硅显示面板制造方法通过准分子激光退火步骤S08所生成的多晶硅层具有相较于现有技术具有较好的晶格排列结构,避免晶格缺陷,进而提升了显示面板的良率以及品质。此外,在形成所述非晶硅层50后,由于所述非晶硅层50表面所残留的粒子及金属离子显著减少,因此,以氢氟酸及臭氧对所述非晶硅的清洗的步骤成为非必要的步骤,藉此提升显示面板制程的效率并减少环境污染。

Claims (15)

  1. 一种低温多晶硅显示面板制造方法,包括:
    真空环境提供步骤,包括提供一真空环境;
    基板提供步骤,包括提供一玻璃基板;
    下一氧化硅层形成步骤,包括形成一下一氧化硅层到所述玻璃基板上;
    氮化硅层形成步骤,包括形成一氮化硅层到所述下一氧化硅层上;
    上一氧化硅层形成步骤,包括形成一上一氧化硅层到所述氮化硅层上;
    非晶硅层形成步骤,包括在所述真空环境中,形成一非晶硅层到所述上一氧化硅层上;
    保护层形成步骤,包括形成一保护层到所述非晶硅层上;以及
    退火步骤,包括对所述非晶硅层进行准分子雷射退火以在所述非晶硅层上形成多晶硅。
  2. 如权利要求1所述低温多晶硅显示面板制造方法,其中:所述保护层形成步骤是在所述真空环境中执行。
  3. 如权利要求1所述低温多晶硅显示面板制造方法,其中:所述退火步骤是在所述真空环境中执行。
  4. 如权利要求1所述低温多晶硅显示面板制造方法,其中:所述基板提供步骤、所述下一氧化硅层形成步骤、所述氮化硅层形成步骤、所述上一氧化硅层形成步骤、以及所述退火步骤的至少一者是在所述真空环境中执行。
  5. 如权利要求1所述低温多晶硅显示面板制造方法,其中: 所述基板提供步骤、所述下一氧化硅层形成步骤、所述氮化硅层形成步骤、以及所述上一氧化硅层形成步骤均在所述真空环境中执行。
  6. 如权利要求1所述低温多晶硅显示面板制造方法,其中:所述真空环境为一真空室。
  7. 如权利要求1所述低温多晶硅显示面板制造方法,其中:所述真空室连接有一真空泵,所述真空泵用于对所述真空室抽真空。
  8. 如权利要求1所述低温多晶硅显示面板制造方法,其中:在所述非晶硅层形成步骤之后,以氢氟酸及臭氧对所述非晶硅层进行清洗,再执行所述保护层形成步骤。
  9. 如权利要求1所述低温多晶硅显示面板制造方法,其中:所述保护层为一氧化硅。
  10. 一种低温多晶硅显示面板制造方法,包括:
    真空环境提供步骤,包括提供一真空环境;
    基板提供步骤,包括提供一玻璃基板;
    下一氧化硅层形成步骤,包括形成一下一氧化硅层到所述玻璃基板上;
    氮化硅层形成步骤,包括形成一氮化硅层到所述下一氧化硅层上;
    上一氧化硅层形成步骤,包括形成一上一氧化硅层到所述氮化硅层上;
    非晶硅层形成步骤,包括在所述真空环境中,形成一非晶硅层到所述上一氧化硅层上;
    保护层形成步骤,包括形成一保护层到所述非晶硅层上;以及
    退火步骤,包括对所述非晶硅层进行准分子雷射退火以在所述非晶硅层上形成多晶硅;
    其中,所述保护层形成步骤是在所述真空环境中执行;
    其中,所述退火步骤是在所述真空环境中执行;
    其中,所述基板提供步骤、所述下一氧化硅层形成步骤、所述氮化硅层形成步骤、所述上一氧化硅层形成步骤、以及所述退火步骤的至少一者是在所述真空环境中执行。
  11. 如权利要求10所述低温多晶硅显示面板制造方法,其中: 所述基板提供步骤、所述下一氧化硅层形成步骤、所述氮化硅层形成步骤、以及所述上一氧化硅层形成步骤均在所述真空环境中执行。
  12. 如权利要求10所述低温多晶硅显示面板制造方法,其中:所述真空环境为一真空室。
  13. 如权利要求10所述低温多晶硅显示面板制造方法,其中:所述真空室连接有一真空泵,所述真空泵用于对所述真空室抽真空。
  14. 如权利要求10所述低温多晶硅显示面板制造方法,其中:在所述非晶硅层形成步骤之后,以氢氟酸及臭氧对所述非晶硅层进行清洗,再执行所述保护层形成步骤。
  15. 如权利要求10所述低温多晶硅显示面板制造方法,其中:所述保护层为一氧化硅。
PCT/CN2019/078291 2018-12-03 2019-03-15 低温多晶硅显示面板制造方法 WO2020113841A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1577773A (zh) * 2003-07-29 2005-02-09 三菱电机株式会社 薄膜晶体管及其制造方法
JP3942853B2 (ja) * 2001-08-28 2007-07-11 株式会社半導体エネルギー研究所 半導体材料製造装置
CN103646871A (zh) * 2013-11-18 2014-03-19 上海和辉光电有限公司 一种提高非晶硅表面氧化层均匀性的方法
CN104658898A (zh) * 2013-11-22 2015-05-27 上海和辉光电有限公司 低温多晶硅薄膜的制作方法
CN107452749A (zh) * 2016-04-08 2017-12-08 群创光电股份有限公司 显示装置及其制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3942853B2 (ja) * 2001-08-28 2007-07-11 株式会社半導体エネルギー研究所 半導体材料製造装置
CN1577773A (zh) * 2003-07-29 2005-02-09 三菱电机株式会社 薄膜晶体管及其制造方法
CN103646871A (zh) * 2013-11-18 2014-03-19 上海和辉光电有限公司 一种提高非晶硅表面氧化层均匀性的方法
CN104658898A (zh) * 2013-11-22 2015-05-27 上海和辉光电有限公司 低温多晶硅薄膜的制作方法
CN107452749A (zh) * 2016-04-08 2017-12-08 群创光电股份有限公司 显示装置及其制造方法

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