WO2020108467A1 - 网络设备及转换装置 - Google Patents

网络设备及转换装置 Download PDF

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Publication number
WO2020108467A1
WO2020108467A1 PCT/CN2019/120843 CN2019120843W WO2020108467A1 WO 2020108467 A1 WO2020108467 A1 WO 2020108467A1 CN 2019120843 W CN2019120843 W CN 2019120843W WO 2020108467 A1 WO2020108467 A1 WO 2020108467A1
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WIPO (PCT)
Prior art keywords
message
cpu
packet
header
private information
Prior art date
Application number
PCT/CN2019/120843
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English (en)
French (fr)
Inventor
李跃武
Original Assignee
新华三技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 新华三技术有限公司 filed Critical 新华三技术有限公司
Priority to JP2021518774A priority Critical patent/JP7116255B2/ja
Priority to EP19889431.3A priority patent/EP3890258B1/en
Priority to US17/293,179 priority patent/US11765102B2/en
Publication of WO2020108467A1 publication Critical patent/WO2020108467A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/103—Packet switching elements characterised by the switching fabric construction using a shared central buffer; using a shared memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9047—Buffering arrangements including multiple buffers, e.g. buffer pools
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/06—Notations for structuring of protocol data, e.g. abstract syntax notation one [ASN.1]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/22—Parsing or analysis of headers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/26—Special purpose or proprietary protocols or architectures

Definitions

  • Network equipment generally includes a switching chip and a CPU.
  • the switch chip When the switch chip sends a message to the CPU, it will first add a private message header to the Ethernet header of the message according to the private protocol, and then send the message carrying the private message header to the CPU, so that the CPU can read the private message header from the message. Get message characteristics.
  • the information related to the packet characteristics may include: the VLAN to which the packet belongs, the QoS of the packet, and the interface information of the peripheral interface that received the packet, and so on.
  • the private protocols adopted by different switching chips may be different. In this way, after the CPU receives the packet, the Ethernet header of the packet carries the private information header, so the packet cannot be recognized normally, which affects the CPU's traffic distribution.
  • FIG. 1 is a structural diagram of a network device provided by the present disclosure.
  • FIG. 2 is a schematic diagram of a private information header provided at a specified position provided by the present disclosure.
  • FIG. 3 is a structural diagram of a network device provided by Embodiment 1 of the present disclosure.
  • FIG. 4 is a schematic diagram of a format of a message carrying a private information header provided by the present disclosure.
  • FIG 5 is a structural diagram of a network device provided by Embodiment 2 of the present disclosure.
  • FIG. 6 is a structural diagram of a network device provided in Embodiment 3 of the present disclosure.
  • FIG. 7 is a structural diagram of a network device according to Embodiment 4 of the present disclosure.
  • FIG. 8 is a structural diagram of a conversion device provided by the present disclosure.
  • FIG. 9 is another structural diagram of a conversion device provided by the present disclosure.
  • the network device may include: a switching chip 101, a CPU 102, and a conversion device 103.
  • the conversion device 103 may be implemented by software or hardware.
  • the conversion device 103 can be applied to a device that includes a processor and a storage medium, and the function of the conversion device 103 is realized by the processor reading machine executable code in the storage medium.
  • the conversion device 103 may be an FPGA chip.
  • the present disclosure does not specifically limit the implementation of the conversion device 103.
  • the switching chip 101 has a CPU interface 101_1 through which messages can be sent to and received from the CPU 102.
  • the CPU 102 includes at least: a media access controller (MAC: Media Access Controller) 102_1 and a buffer (Buffer) 102_2.
  • MAC Media Access Controller
  • Buffer buffer
  • the conversion device 103 receives the first message sent by the switching chip 101 through the CPU interface 101_1 and needs to be sent to the CPU 102, and migrates the private information header in the Ethernet header of the first message to all Obtain the second message from the specified position of the first message, calculate the CRC (Cyclic Redundancy Check) code of the second message, and use the calculated CRC code to replace the CRC code already carried in the second message
  • the third message, the third message is sent to the buffer on the CPU for buffering. It should be noted that the above-mentioned first message to third message are only named for convenience of distinction, and are not used for limitation.
  • the packet is usually identified by analyzing the Ethernet header of the packet.
  • the Ethernet header may include: a data link layer header (also called a layer 2 header), an IP header (also called a layer 3 header), and a TCP/UDP header (also called a layer 4 header).
  • the above-mentioned designated position may be a position other than the ether head.
  • the above specified location may be exemplified by the last N free bytes in the payload of the message, where N is the byte occupied by the private information header Quantity.
  • FIG. 2 shows an example of a private information header at a specified position.
  • the conversion apparatus 103 migrates the private information header originally carried in the packet Ethernet header to a position other than the Ethernet header in the packet, In this way, even if the message carries a private information header, it will not affect the CPU's identification of the message, and thus will not affect the normal distribution of the message by the CPU.
  • FIG. 3 is a structural diagram of a network device provided by an embodiment of the present disclosure.
  • the network device may include: a switching chip 301, a CPU 302, and a conversion device 303.
  • the network device shown in this embodiment takes an exchange chip as an example.
  • the switching chip 301 may include a CPU interface 301_1 and a peripheral interface 301_2.
  • the number of peripheral interfaces 301_2 is greater than or equal to 1.
  • the peripheral interface is used to receive messages outside the switching chip 301 and to send messages outside the switching chip 301.
  • the CPU 302 includes at least: a media access controller 302_1, a buffer 302_2, a memory 302_3, a CPU core 302_4, and a shunt module 302_5.
  • the number of CPU cores 302_4 is greater than or equal to 1.
  • the conversion device 303 is connected between the CPU interface 301_1 and the media access controller 302_1.
  • One interface Port303_1 of the conversion device 303 is connected to the CPU interface 301_1, and the other interface Port303_2 is connected to the media access controller 302_1.
  • the switching chip 301 receives the message through the peripheral interface Port301_2.
  • the message here can be recorded as message 31.
  • the switching chip 301 determines that the message 31 needs to be sent to the CPU 302, it adds a private information header to the Ethernet header of the message 31 according to the set private message header addition method.
  • the private information header can be added after the destination MAC address and the source MAC address.
  • the private information header here contains the following message characteristic information: the VLAN to which the message 31 belongs, the QoS of the message 31, the interface information of Port301_2, and so on.
  • the message 31 with the added private information header is denoted as the message 32.
  • the switching chip 301 sends a message 32 through the CPU interface 301_1.
  • the interface Port303_1 of the conversion device 303 is connected to the CPU interface 301_1.
  • the switching chip 301 sends the message 32 through the CPU interface 301_1
  • the conversion device 303 receives the message 32 through the interface Port303_1.
  • the conversion device 303 receives the message 32 through the interface Port303_1, recognizes the private information header from the Ethernet header of the message 32 according to the locally recorded private information header identification method, and then performs the following processing on the message 32: the identified The private information header is migrated from the Ethernet header to the designated position of the message 32, and after the private information header is migrated, the CRC code of the message 32 is recalculated, and the CRC code carried in the message 32 is updated to the recalculated CRC code.
  • the identification method of the private information header corresponds to the way that the exchange chip 301 adds the private information header, and it may be pre-configured in the conversion device 303; or, the conversion device 303 determines the chip identifier of the exchange chip 301.
  • the last N idle bytes in the payload of the designated message 32 are taken as an example, and N is the number of bytes occupied by the private information header.
  • the message 32 processed by the conversion device 303 is recorded as the message 33.
  • the conversion device 303 sends a message 33 through the interface Port303_2.
  • the interface Port303_2 of the conversion device 303 is connected to the media access controller 302_1 of the CPU 302, when the conversion device 303 sends the message 33 through the interface Port303_2, the media access controller 302_1 of the CPU 302 will receive the message 33.
  • the media access controller 302_1 When the media access controller 302_1 receives the message 33, it processes the message 33.
  • the media access controller 302_1 can process the message 33 according to the definition of the Ethernet MAC standard, which mainly includes: subcontracting the message 33 according to the definition of the Ethernet MAC standard, which is not specifically limited in this disclosure.
  • the processed message 33 is denoted as message 34 here.
  • the media access controller 302_1 caches the message 34 to the buffer 302_2.
  • the private information header in the message 34 cached by the buffer 302_2 is at the end of the payload of the message 34.
  • the CPU core 302_4 when the message characteristic information in the private information header in the message 34 needs to be obtained, the CPU core 302_4 will read the instruction code from the memory 302_3, and run the instruction code to obtain the private information in the message 34 Message feature information in the header.
  • the memory 302_3 stores the above instruction code in advance.
  • the message feature information here is as described above, mainly: the VLAN to which the message 31 belongs, the QoS of the message 31, the interface information of Port301_2, and so on.
  • the CPU core 302_4 After the CPU core 302_4 acquires the message feature information, it can set a message control strategy based on the acquired message feature information.
  • the operation performed after acquiring the message feature information is not specifically limited.
  • the distribution module 302_5 when the packet 34 needs to be distributed, the distribution module 302_5 will obtain the packet 34 from the buffer 302_2, because the private information header of the packet 34 is at the end of the payload of the packet 34 (Payload The last N idle bytes) will not affect the identification and distribution of the packet 34 by the distribution module 302_5. Therefore, the distribution module 302_5 can normally divide the packet 34 according to the existing distribution method to distribute the packet 34 to the corresponding In the message queue. Specifically, the offloading module 302_5 offloads the packet 34 may include: the offloading module 302_5 may determine the priority of the packet 34 according to the information in the ether header of the packet 34, and place the packet 34 in the packet corresponding to the priority Text queue. In this embodiment, different message queues can be scheduled by the same CPU core or by different CPU cores, and this embodiment is not specifically limited.
  • the conversion device 303 transfers the private information header that was originally carried in the Ethernet header of the message to a specified position in the message that does not affect the identification of the message except the Ethernet header, thereby achieving even
  • the message carries a private information header, because the private information header is in a position in the message that does not affect message identification, and it does not affect the CPU's (specifically, the offload module 302_5) identification and normal offload of the message.
  • Embodiment 1 So far, the description of Embodiment 1 is completed.
  • FIG. 5 is a structural diagram of a network device according to Embodiment 2 of the present disclosure.
  • the network device may include: a switching chip 501, a CPU 502, and a conversion device 503.
  • the network device shown in this embodiment takes an exchange chip as an example.
  • the switching chip 501 may include a CPU interface 501_1 and a peripheral interface 501_2.
  • the CPU 502 includes at least: a media access controller 502_1, a buffer 502_2, a memory 502_3, a CPU core 502_4, and a shunt module 502_5.
  • the CPU interface 501_1 of the switching chip 501 is connected to the media access controller 502_1 of the CPU 502.
  • the conversion device 503 is connected between the media access controller 502_1 and the buffer 502_2.
  • the switching chip 501 receives the message through the peripheral interface Port501_2.
  • the message here can be recorded as message 51.
  • a private information header is added to the Ethernet header of the message 51 according to a processing method similar to the above-mentioned switching chip 301.
  • the added private information header is shown in Figure 4. For ease of description, here the message 51 with the added private information header is recorded as the message 52.
  • the switching chip 501 sends a message 52 through the CPU interface 501_1.
  • the CPU interface 501_1 of the switching chip 501 is connected to the media access controller 502_1 of the CPU 502.
  • the switching chip 501 sends a message 52 through the CPU interface 501_1, the media access controller 502_1 of the CPU 502 will receive the message 52.
  • the media access controller 502_1 When the media access controller 502_1 receives the message 52, it processes the message 52.
  • the media access controller 502_1 processes the message 52 in a manner similar to the message processing method of the media access controller 302_1 in Embodiment 1.
  • the processed message 52 is denoted as message 53 here.
  • the media access controller 502_1 sends a message 53 to the buffer 502_2.
  • the conversion device 503 is connected between the media access controller 502_1 and the buffer 502_2.
  • the conversion device 503 between the media access controller 502_1 and the buffer 502_2 will Message 53 is received before buffer 502_2.
  • the conversion device 503 When the conversion device 503 receives the message 53, it recognizes the private information header from the Ethernet header of the message 53 according to the locally recorded private information header identification method, and then performs the following processing on the message 53: the identified private
  • the information header is migrated from the Ethernet header to the designated position of the message 53, and the CRC code of the message 53 is recalculated after the private information header is migrated, and the CRC code carried in the message 53 is updated to the recalculated CRC code.
  • the last N idle bytes in the payload of the designated message 53 are used as an example, and N is the number of bytes occupied by the private information header.
  • the message 53 processed by the conversion device 503 is recorded as the message 54.
  • the conversion device 503 buffers the message 54 to the buffer 502_2. So far, the private information header in the packet 54 buffered by the buffer 502_2 is at the end of the payload of the packet 54.
  • the CPU core 502_4 when the message feature information in the private information header in the message 54 needs to be obtained, the CPU core 502_4 performs the operation as performed by the CPU core 302_4 to obtain the message feature in the private information header in the message 54 information.
  • the offload module 502_5 when the message 54 needs to be offloaded, the offload module 502_5 performs the operation as performed by the offload module 302_5 to offload the message 54.
  • the conversion device 503 transfers the private information header originally carried in the Ethernet header of the message to a specified position in the message that does not affect the identification of the message except the Ethernet header.
  • the message carries a private information header, because the private information header is in a position in the message that does not affect message identification, and it does not affect the CPU's (specifically, the offload module 302_5) identification and normal offload of the message.
  • Embodiment 2 So far, the description of Embodiment 2 is completed.
  • FIG. 6 is a structural diagram of a network device according to Embodiment 3 of the present disclosure.
  • the network device may include: a switching chip 601 and a CPU 602.
  • the network device shown in Embodiment 3 takes an exchange chip as an example.
  • the structure of the exchange chip 601 is similar to the structure of the exchange chip 301 and the exchange chip 501, and will not be described in detail.
  • the CPU 602 at least includes: a module 600, a buffer 602_1, a memory 602_2, a CPU core 602_3, and a shunt module 602_4.
  • the module 600 is composed of a media access controller 600_1 and a conversion device 600_2.
  • the media access controller 600_1 and the conversion device 600_2 may be provided in the module 600 according to the following principle 1.
  • Principle 1 is to require the conversion device 600_2 to receive the message from the switching chip 601 before the media access controller 600_1.
  • the conversion device 600_2 when the conversion device 600_2 receives the message from the switching chip 601, it will process the message in the same manner as the conversion device in Embodiment 1 processes the message.
  • the private information header in the message finally cached in the buffer 602_1 is at the specified position of the message (such as the end of the payload).
  • the CPU core 602_3 and the shunt module 602_4 will be processed in the same manner as the CPU core and the shunt module in Embodiment 1 or 2, respectively.
  • the media access controller 600_1 and the conversion device 600_2 may also be provided in the module 600 according to the following principle 2.
  • Principle 2 is to require the media access controller 600_1 to receive the message from the switching chip 601 before the conversion device 600_2.
  • the conversion device 600_2 when the conversion device 600_2 receives the message from the switching chip 601, it will process the message according to the manner in which the conversion device processes the message in Embodiment 2.
  • the private information header in the message finally cached in the buffer 602_1 is at the specified position of the message (such as the end of the payload).
  • the above embodiments 1 to 3 take the network device including one switching chip as an example, and when there are M switching chips in the network device, M is greater than 1, and the processing method is similar to the case where there is one switching chip in the network device. 4 Description:
  • FIG. 7 is a structural diagram of a network device according to Embodiment 4 of the present disclosure.
  • the network device may include: a switching chip 701a, a switching chip 701b, a CPU 702, and a conversion device 703.
  • the structures of the switching chip 701a and the switching chip 701b are similar, and both include a CPU interface and a peripheral interface.
  • the CPU interface on the switching chip 701a is denoted as CPU interface 701_a1
  • the CPU interface on the switching chip 701b is denoted as CPU interface 701_b1.
  • the CPU 702 includes at least: a media access controller 702_1, a buffer 702_2, a memory 702_3, a CPU core 702_4, and a shunt module 702_5.
  • the conversion device 703 is connected between the switching chip and the CPU as an example.
  • the CPU interface 701_a1 of the switching chip 701a is connected to one end interface (denoted Port703_1) of the conversion device 703, and the other end interface (denoted Port703_2) of the conversion device 703 is connected to the media access controller 702_1 of the CPU 702.
  • the CPU interface 701_b1 of the switching chip 701b is connected to one end interface (denoted Port703_3) of the conversion device 703, and the other end interface (denoted Port703_4) of the conversion device 703 is connected to the media access controller 702_1 of the CPU 702.
  • the conversion device 703 when the conversion device 703 receives the message from the switching chip 701a through the interface Port703_1, it will recognize the private from the Ethernet header of the message according to the locally recorded private information header identification method corresponding to the interface Port703_1 Message header, and then process the message according to the message processing method of the conversion device in Embodiment 1. Finally, the private information header in the message from the switching chip 701a buffered by the buffer 702_2 on the CPU 702 is at the designated position of the message (except for the Ethernet header, which does not affect the message identification position, such as the end of the payload). The conversion device 703 receives the message from the switching chip 701b through the interface Port703_3 in a similar manner.
  • the final conversion device 203 will uniformly migrate the private information header of the message from each switching chip from the Ethernet header to the packet divided by the Ethernet header It does not affect the designated position of the message identification, even if the message carries a private information header, because the private information header is in the message does not affect the position of the message identification, it will not affect the CPU (specifically, the offload module 302_5) Message identification and normal distribution.
  • the conversion device 703 is connected between the switching chip and the CPU as an example.
  • the location of the conversion device may also be as described in Embodiment 2 and Embodiment 3. This disclosure is not specifically limited.
  • FIG. 8 is a structural diagram of a conversion device provided by the present disclosure.
  • the conversion device (denoted as 800) shown in FIG. 8 is applied to a network device, where the network device may include a switching chip 801 and a CPU 802. As shown in FIG. 8, the conversion device 800 is connected between the switching chip 801 and the CPU 802.
  • the conversion device 800 may include:
  • the first receiving unit 800_1 is configured to receive a first message; the first message is a message sent by the switching chip 801 to the CPU 802.
  • the first processing unit 800_2 is configured to migrate the private information header in the Ethernet header of the first message to a designated position of the first message, obtain a second message, and calculate the cyclic redundancy correction of the second message Verify the CRC code, replace the CRC code already carried in the second message with the CRC code to obtain a third message, and send the third message to the CPU; the specified position is divided by the first message Position outside the etheric head.
  • the first processing unit 800_2 migrating the private information header in the Ethernet header of the first packet to the specified location of the first packet includes:
  • the designated position is the last N bytes in the Ethernet payload of the packet; the N is the number of bytes occupied by the private information header.
  • FIG. 9 is a structural diagram of another conversion device provided by the present disclosure.
  • the conversion device (denoted as 900) shown in FIG. 9 is applied to a network device, where the network device may include a switching chip 901 and a CPU 902.
  • the switching chip 901 includes at least a CPU interface 901_1, and the CPU 902 includes at least a media access controller 902_1 and a buffer 902_2.
  • the conversion device 900 is connected between the media access controller 902_1 and the buffer 902_2.
  • the conversion device 900 may include:
  • the second receiving unit 900_1 is configured to receive a first message, which is a message sent by the switching chip 901 to the CPU 902 through the CPU interface 901_1 and processed by the media access controller 902_1;
  • the second processing unit 900_2 is configured to migrate the private information header in the Ethernet header of the first message to a specified position of the first message, obtain a second message, and calculate the cyclic redundancy of the second message I check the CRC code, use the CRC code to replace the CRC code already carried in the second message to obtain a third message, and send the third message to the Buffer for buffering; Position outside the ether head.
  • the second processing unit 900_2 migrating the private information header in the Ethernet header of the first packet to the specified location of the first packet includes:
  • the designated position is the last N bytes in the Ethernet payload of the packet; the N is the number of bytes occupied by the private information header.

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Computing Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)

Abstract

一种网络设备包括：交换芯片、CPU，所述交换芯片至少包括：CPU接口，所述CPU至少包括：媒体访问控制器、缓存器Buffer。所述网络设备还包括：转换装置。所述转换装置，接收所述交换芯片通过所述CPU接口向所述CPU上送的第一报文，将所述第一报文的以太头部中的私有信息头迁移至所述第一报文的指定位置得到第二报文，计算第二报文的循环冗余校验CRC码，利用所述CRC码替换第二报文已携带的CRC码得到第三报文，将所述第三报文发送至所述CPU上的Buffer进行缓存；所述指定位置为所述第一报文的除所述以太头部之外的位置。

Description

网络设备及转换装置 背景技术
网络设备一般包括交换芯片和CPU。当交换芯片向CPU发送报文时，会按照私有协议先在报文的以太头部增加私有信息头然后将携带了私有信息头的报文发送给CPU，以便CPU从报文的私有信息头中获取报文特征。报文特征相关的信息可包括：报文所属VLAN、报文的QoS、收到报文的外围接口的接口信息等。
由于不同交换芯片所采用的私有协议可能会不同，这样，CPU收到报文后，会因报文的以太头部携带私有信息头而无法正常识别报文，影响CPU对报文的分流。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。
图1为本公开提供的网络设备的结构图。
图2为本公开提供的私有信息头在指定位置的示意图。
图3为本公开实施例1提供的网络设备的结构图。
图4为本公开提供的报文携带私有信息头的格式示意图。
图5为本公开实施例2提供的网络设备的结构图。
图6为本公开实施例3提供的网络设备的结构图。
图7为本公开实施例4提供的网络设备的结构图。
图8为本公开提供的转换装置的结构图。
图9为本公开提供的转换装置的另一结构图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面结合附图和具体实施例对本公开进行详细描述。
如图1所示，本公开提供的网络设备的结构图中，该网络设备可包括：交换芯片101、 CPU102和转换装置103。这里，转换装置103可通过软件实现，也可通过硬件实现。当转换装置103通过软件实现时，该转换装置103可以应用于一个包括处理器以及存储介质的装置，通过处理器读取存储介质中的机器可执行代码来实现转换装置103的功能。当转换装置103通过硬件实现时，比如该转换装置103可以是FPGA芯片。本公开对转换装置103的实现方式并不具体限定。
如图1所示，交换芯片101上具有CPU接口101_1，通过该接口可以向CPU 102上送报文以及接收来自CPU 102的报文。CPU102至少包括：媒体访问控制器(MAC：Media Access Controller)102_1和缓存器(Buffer)102_2。
在图1中，转换装置103，接收交换芯片101通过CPU接口101_1发送的、需上送至CPU102的第一报文，将所述第一报文的以太头部中的私有信息头迁移至所述第一报文的指定位置得到第二报文，计算第二报文的循环冗余校验(CRC：Cyclic Redundancy Check)码，利用计算的CRC码替换第二报文已携带的CRC码得到第三报文，将所述第三报文发送至所述CPU上的Buffer进行缓存。需要说明的是，上述的第一报文至第三报文只是为便于区分而进行的命名，并非用于限定。
在应用中，通常通过分析报文的以太头部来识别报文。其中，以太头部可包括：数据链路层头部(也称二层头部)、IP头部(也称三层头部)、TCP/UDP头部(也称四层头部)。基于此，在本实施例中，上述指定位置可为除以太头部之外的位置。
作为一个实施例，在不影响报文原有内容的前提下，上述的指定位置可举例为报文的以太载荷(Payload)中的最后N个空闲字节，N为私有信息头占用的字节数量。图2举例示出了私有信息头在指定位置的示意图。
至此，完成图1所示的网络设备的结构描述。
通过图1所示网络设备的结构可以看出，本公开实施例中，由转换装置103将原本携带在报文以太头部中的私有信息头迁移至报文中以太头部之外的位置，这样，即使报文携带私有信息头，也不会影响CPU对报文的识别，进而也不会影响CPU对报文的正常分流。
下面通过四个具体实施例对本公开实施例提供的网络设备的结构进行描述：
实施例1：
参见图3，图3为本公开实施例提供的网络设备的结构图。如图3所示，该网络设备可包括：交换芯片301、CPU302、转换装置303。本实施例所示的网络设备以包括一 个交换芯片为例。
如图3所示，交换芯片301可包括CPU接口301_1和外围接口301_2。这里，外围接口301_2的数量大于等于1。外围接口用于接收交换芯片301外部的报文，以及用于向交换芯片301外部发送报文。
如图3所示，CPU302至少包括：媒体访问控制器302_1、缓存器302_2、内存302_3、CPU核302_4、分流模块302_5。CPU核302_4的数量大于等于1。
在本实施例中，如图3所示，转换装置303连接在CPU接口301_1和媒体访问控制器302_1之间。转换装置303的一个接口Port303_1与CPU接口301_1相连，另一个接口Port303_2与媒体访问控制器302_1相连。
基于上述结构，下面描述报文如何从交换芯片301传输至CPU302：
如图3所示，交换芯片301通过外围接口Port301_2接收到报文。为便于描述，这里的报文可记为报文31。
交换芯片301在确定报文31需上送CPU302时，则按照已设置的私有信息头添加方式在报文31的以太头部中增加私有信息头。如图4所示，该私有信息头可以添加在目的MAC地址和源MAC地址之后。这里的私有信息头包含以下报文特征信息：报文31所属的VLAN、报文31的QoS、Port301_2的接口信息等。为便于描述，这里将增加了私有信息头的报文31记为报文32。
交换芯片301通过CPU接口301_1发送报文32。
转换装置303的接口Port303_1与CPU接口301_1相连，当交换芯片301通过CPU接口301_1发送报文32，则转换装置303会通过接口Port303_1接收到报文32。
转换装置303通过接口Port303_1接收到报文32，根据本地已记录的私有信息头识别方式从报文32的以太头部中识别出私有信息头，然后对报文32进行以下处理：将识别出的私有信息头从以太头部迁移至报文32的指定位置，并在迁移私有信息头后重新计算报文32的CRC码，将报文32已携带的CRC码更新为该重新计算的CRC码。这里，私有信息头识别方式与交换芯片301添加私有信息头的方式相对应，其可预先配置在转换装置303；或者，是由转换装置303依据交换芯片301的芯片标识确定。
本实施例以指定位置为报文32的Payload中的最后N个空闲字节为例，N为私有信息头占用的字节数量。
为便于描述，将经由转换装置303处理后的报文32记为报文33。
转换装置303通过接口Port303_2发送报文33。
由于转换装置303的接口Port303_2与CPU302的媒体访问控制器302_1连接，则当转换装置303通过接口Port303_2发送报文33后，CPU302的媒体访问控制器302_1会接收到报文33。
当媒体访问控制器302_1接收到报文33后，对报文33进行处理。这里，媒体访问控制器302_1可按照Ethernet MAC标准定义对报文33进行处理，主要包括：按照Ethernet MAC标准定义将报文33进行分包等，本公开并不具体限定。为便于描述，这里将处理后的报文33记为报文34。
媒体访问控制器302_1将报文34缓存至缓存器302_2。
至此，缓存器302_2缓存的报文34中的私有信息头在报文34的Payload的最后。
在本实施例中，当需要获取报文34中私有信息头内的报文特征信息时，CPU核302_4会从内存302_3中读取指令代码，通过运行该指令代码以获取报文34中私有信息头内的报文特征信息。内存302_3预先存储上述指令代码。这里的报文特征信息如上所述，主要为：报文31所属的VLAN、报文31的QoS、Port301_2的接口信息等。
当CPU核302_4获取报文特征信息后，可基于该获取的报文特征信息设定报文控制策略等。本实施例中，获取报文特征信息后执行的操作并不具体限定。
在本实施例中，当需要对报文34进行分流时，分流模块302_5会从缓存器302_2中获取报文34，因为此时报文34的私有信息头在报文34的Payload的最后(Payload中的最后N个空闲字节)，不会影响分流模块302_5对报文34的识别和分流，因此，分流模块302_5可按照现有分流方式正常对报文34进行分流以将报文34分配到对应的报文队列中。具体地，分流模块302_5对报文34进行分流可包括：分流模块302_5可依据报文34的以太头部中的信息确定报文34的优先级，将报文34放入该优先级对应的报文队列。在本实施例中，不同报文队列可由同一个CPU核调度，也可由不同CPU核调度，本实施例并不具体限定。
可以看出，本实施例中，转换装置303通过将原本携带在报文以太头部中的私有信息头迁移至报文中除以太头部之外不影响报文识别的指定位置，实现了即使报文携带私有信息头，因为该私有信息头处于报文中不影响报文识别的位置，其不会影响CPU(具体是分流模块302_5)对报文的识别和正常分流。
至此，完成实施例1的描述。
实施例2：
参见图5，图5为本公开实施例2提供的网络设备的结构图。如图5所示，该网络设备可包括：交换芯片501、CPU502、转换装置503。本实施例所示的网络设备以包括一个交换芯片为例。
如图5所示，交换芯片501可包括CPU接口501_1和外围接口501_2。
CPU502至少包括：媒体访问控制器502_1、缓存器502_2、内存502_3、CPU核502_4、分流模块502_5。
本实施例中，交换芯片501的CPU接口501_1与CPU502的媒体访问控制器502_1相连。
本实施例中，转换装置503连接在媒体访问控制器502_1和缓存器502_2之间。
基于上述结构，下面描述报文如何从交换芯片501传输至CPU502：
如图5所示，交换芯片501通过外围接口Port501_2接收到报文。为便于描述，这里的报文可记为报文51。
交换芯片501在确定报文51需上送CPU502时，按照类似上述交换芯片301的处理方式在报文51的以太头部中增加私有信息头。该增加的私有信息头如图4所示。为便于描述，这里将增加了私有信息头的报文51记为报文52。
交换芯片501通过CPU接口501_1发送报文52。
交换芯片501的CPU接口501_1与CPU502的媒体访问控制器502_1连接，当交换芯片501通过CPU接口501_1发送报文52，CPU502的媒体访问控制器502_1会接收到报文52。
当媒体访问控制器502_1接收到报文52后，对报文52进行处理。这里，媒体访问控制器502_1对报文52的处理方式类似实施例1中媒体访问控制器302_1的报文处理方式。为便于描述，这里将处理后的报文52记为报文53。
媒体访问控制器502_1向缓存器502_2发送报文53。
转换装置503连接在媒体访问控制器502_1和缓存器502_2之间，当媒体访问控制器502_1向缓存器502_2发送报文53时，处于媒体访问控制器502_1和缓存器502_2 之间的转换装置503会先于缓存器502_2收到报文53。
当转换装置503接收到报文53时，根据本地已记录的私有信息头识别方式从报文53的以太头部中识别出私有信息头，然后对报文53进行以下处理：将识别出的私有信息头从以太头部迁移至报文53的指定位置，并在迁移私有信息头后重新计算报文53的CRC码，将报文53已携带的CRC码更新为该重新计算的CRC码。本实施例以指定位置为报文53的Payload中的最后N个空闲字节为例，N为私有信息头占用的字节数量。
为便于描述，将转换装置503处理后的报文53记为报文54。
转换装置503将报文54缓存至缓存器502_2。至此，缓存器502_2缓存的报文54中的私有信息头在报文54的Payload的最后。
在本实施例中，当需要获取报文54中私有信息头内的报文特征信息时，CPU核502_4执行如CPU核302_4执行的操作，以获取报文54中私有信息头内的报文特征信息。
在本实施例中，当需要对报文54进行分流时，分流模块502_5执行如分流模块302_5执行的操作，以对报文54进行分流。
可以看出，本实施例中，转换装置503通过将原本携带在报文以太头部中的私有信息头迁移至报文中除以太头部之外不影响报文识别的指定位置，实现了即使报文携带私有信息头，因为该私有信息头处于报文中不影响报文识别的位置，其不会影响CPU(具体是分流模块302_5)对报文的识别和正常分流。
至此，完成实施例2的描述。
实施例3：
参见图6，图6为本公开实施例3提供的网络设备的结构图。如图6所示，该网络设备可包括：交换芯片601、CPU602。本实施例3所示的网络设备以包括一个交换芯片为例。
在本实施例3中，交换芯片601的结构与交换芯片301、交换芯片501的结构类似，不再赘述。
在本实施例3中，CPU602至少包括：模块600、缓存器602_1、内存602_2、CPU核602_3、分流模块602_4。其中，模块600由媒体访问控制器600_1和转换装置600_2组成。
在本实施例3中，可以按照如下原则1在模块600设置媒体访问控制器600_1、转 换装置600_2。原则1是要求转换装置600_2先于媒体访问控制器600_1接收到来自交换芯片601的报文。
基于此，当转换装置600_2接收到来自交换芯片601的报文时，会按照实施例1中转换装置处理报文的方式处理报文。最终缓存至缓存器602_1的报文中的私有信息头在报文的指定位置(比如Payload的最后)。
本实施例3中，CPU核602_3、分流模块602_4会分别按照实施例1或2中CPU核、分流模块处理报文的方式处理。
至此，完成实施例3的描述。
需要说明的是，在本实施例中，也可以按照如下原则2在模块600设置媒体访问控制器600_1、转换装置600_2。原则2是要求媒体访问控制器600_1先于转换装置600_2接收到来自交换芯片601的报文。此种情况下，当转换装置600_2接收到来自交换芯片601的报文时，会按照实施例2中转换装置处理报文的方式处理报文。最终缓存至缓存器602_1的报文中的私有信息头在报文的指定位置(比如Payload的最后)。
上述实施例1至实施例3以网络设备包括一个交换芯片为例，而当网络设备存在M个交换芯片时，M大于1，其处理方式类似网络设备存在一个交换芯片的情况，下文通过实施例4进行描述：
实施例4：
本实施例4以网络设备存在2个交换芯片为例。参见图7，图7为本公开实施例4提供的网络设备的结构图。在图7所示的网络设备的结构图中，该网络设备可包括：交换芯片701a、交换芯片701b、CPU702、转换装置703。
在本实施例4中，交换芯片701a、交换芯片701b的结构类似，均包括CPU接口和外围接口。其中，交换芯片701a上的CPU接口记为CPU接口701_a1，交换芯片701b上的CPU接口记为CPU接口701_b1。
如图7所示，CPU702至少包括：媒体访问控制器702_1、缓存器702_2、内存702_3、CPU核702_4、分流模块702_5。
本实施例4以转换装置703连接在交换芯片与CPU之间为例。如图7所示，交换芯片701a的CPU接口701_a1与转换装置703的一端接口(记为Port703_1)相连，转换装置703的另一端接口(记为Port703_2)与CPU702的媒体访问控制器702_1相连。 交换芯片701b的CPU接口701_b1与转换装置703的一端接口(记为Port703_3)相连，转换装置703的另一端接口(记为Port703_4)与CPU702的媒体访问控制器702_1相连。
如图7所示，转换装置703通过接口Port703_1接收到来自交换芯片701a的报文时，会依据本地已记录的与接口Port703_1对应的私有信息头识别方式从报文的以太头部中识别出私有信息头，然后按照实施例1中转换装置的报文处理方式处理报文。最终，CPU702上的缓存器702_2缓存的来自交换芯片701a的报文中的私有信息头处于报文的指定位置(除以太头部之外不影响报文识别的位置，比如为Payload的最后)。转换装置703通过接口Port703_3接收到来自交换芯片701b的报文的处理方式类似。
可以看出，本实施例4中，不管网络设备包括多少交换芯片，最终转换装置203都会将来自各个交换芯片的报文的私有信息头从以太头部统一迁移至报文中除以太头部之外不影响报文识别的指定位置，实现了即使报文携带私有信息头，因为该私有信息头处于报文中不影响报文识别的位置，其不会影响CPU(具体是分流模块302_5)对报文的识别和正常分流。
至此，完成实施例4的描述。
需要说明的是，实施例4中只是以转换装置703连接在交换芯片与CPU之间为例，转换装置的位置也可如实施例2、实施例3描述，本公开并不具体限定。
以上对本公开进行了描述。下面对本公开提供的转换装置进行描述：
参见图8，图8为本公开提供的转换装置的结构图。图8所示的转换装置(记为800)应用于网络设备中，这里的网络设备可包括交换芯片801、CPU802。如图8所示，转换装置800连接在交换芯片801和CPU802之间。
如图8所示，转换装置800可包括：
第一接收单元800_1，用于接收第一报文；第一报文为交换芯片801向CPU802上送的报文。
第一处理单元800_2，用于将第一报文的以太头部中的私有信息头迁移至所述第一报文的指定位置，得到第二报文，计算第二报文的循环冗余校验CRC码，利用所述CRC码替换第二报文已携带的CRC码得到第三报文，向所述CPU发送所述第三报文；所述指定位置为所述第一报文中除所述以太头部之外的位置。
作为一个实施例，第一处理单元800_2将第一报文的以太头部中的私有信息头迁移至第一报文的指定位置包括：
根据本地已记录的私有信息头识别方式从所述第一报文的以太头部中识别出所述私有信息头；
将所述私有信息头从所述第一报文的以太头部迁移至所述第一报文的指定位置。
作为一个实施例，所述指定位置为所述报文的以太载荷Payload中的最后N个字节；所述N为所述私有信息头占用的字节数量。
至此，完成图8所示转换装置的结构图。
参见图9，图9为本公开提供的另一转换装置的结构图。图9所示的转换装置(记为900)应用于网络设备中，这里的网络设备可包括交换芯片901、CPU902。其中，交换芯片901至少包括：CPU接口901_1，CPU902至少包括：媒体访问控制器902_1、缓存器902_2。
如图9所示，转换装置900连接在媒体访问控制器902_1和缓存器902_2之间。
如图9所示，转换装置900可包括：
第二接收单元900_1，用于接收第一报文，第一报文为交换芯片901通过CPU接口901_1向CPU902上送的且经由媒体访问控制器902_1处理的报文；
第二处理单元900_2，用于将所述第一报文的以太头部中的私有信息头迁移至所述第一报文的指定位置，得到第二报文，计算第二报文的循环冗余校验CRC码，利用所述CRC码替换第二报文已携带的CRC码得到第三报文，将所述第三报文发送至所述Buffer进行缓存；所述指定位置为除所述以太头部之外的位置。
作为一个实施例，第二处理单元900_2将第一报文的以太头部中的私有信息头迁移至第一报文的指定位置包括：
根据本地已记录的私有信息头识别方式从所述第一报文的以太头部中识别出所述私有信息头；
将所述私有信息头从所述第一报文的以太头部迁移至所述第一报文的指定位置。
作为一个实施例，所述指定位置为所述报文的以太载荷Payload中的最后N个字节；所述N为所述私有信息头占用的字节数量。
至此，完成图9所示转换装置的结构图。
以上所述仅为本公开的较佳实施例而已，并不用以限制本公开，凡在本公开的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本公开保护的范围之内。

Claims (12)

  1. 一种网络设备，包括：交换芯片、中央处理单元CPU，所述交换芯片至少包括：CPU接口，所述CPU至少包括：媒体访问控制器、缓存器Buffer；其特征在于，
    所述网络设备还包括：转换装置；
    所述转换装置，接收所述交换芯片通过所述CPU接口向所述CPU上送的第一报文，将所述第一报文的以太头部中的私有信息头迁移至所述第一报文的指定位置得到第二报文，计算第二报文的循环冗余校验CRC码，利用所述CRC码替换第二报文已携带的CRC码得到第三报文，将所述第三报文发送至所述CPU上的Buffer进行缓存；所述指定位置为所述第一报文的除所述以太头部之外的位置。
  2. 根据权利要求1所述的网络设备，其特征在于，所述转换装置连接在所述CPU接口和所述媒体访问控制器之间；
    所述将所述第三报文发送至所述CPU上的Buffer进行缓存包括：
    向所述媒体访问控制器发送所述第三报文，以由所述媒体访问控制器对接收的所述第三报文进行处理并缓存至所述Buffer。
  3. 根据权利要求1所述的网络设备，其特征在于，所述转换装置连接在所述媒体访问控制器和所述Buffer之间；
    所述第一报文为所述交换芯片通过所述CPU接口向所述CPU上送的且经由所述媒体访问控制器处理的报文。
  4. 根据权利要求1至3任一所述的网络设备，其特征在于，所述转换装置和所述媒体访问控制器集成在同一模块。
  5. 根据权利要求1所述的网络设备，其特征在于，所述转换装置将第一报文的以太头部中的私有信息头迁移至第一报文的指定位置包括：
    根据本地已记录的私有信息头识别方式从所述第一报文的以太头部中识别出所述私有信息头；
    将所述私有信息头从所述第一报文的以太头部迁移至所述第一报文的指定位置。
  6. 根据权利要求5所述的网络设备，其特征在于，所述私有信息头识别方式预先配置在所述转换装置；或者，
    所述私有信息头识别方式是由所述转换装置依据所述交换芯片的芯片标识确定的。
  7. 根据权利要求1所述的网络设备，其特征在于，所述指定位置为所述报文的以太载荷Payload中的最后N个字节；
    所述N为所述私有信息头占用的字节数量。
  8. 根据权利要求1至7任一所述的网络设备，其特征在于，所述CPU还包括：内存和CPU核；
    所述内存，用于存储指令代码，
    所述CPU核，用于在获取所述私有信息头中的信息时，从所述内存读取和运行所述指令代码以实现从所述第三报文的指定位置获取所述私有信息头中的信息。
  9. 一种转换装置，其特征在于，所述转换装置应用于网络设备，所述网络设备包括交换芯片、CPU；所述转换装置连接在所述交换芯片和所述CPU之间；所述转换装置被配置为：
    接收第一报文；所述第一报文为交换芯片向所述CPU上送的报文；
    将所述第一报文的以太头部中的私有信息头迁移至所述第一报文的指定位置，得到第二报文，计算第二报文的循环冗余校验CRC码，利用所述CRC码替换第二报文已携带的CRC码得到第三报文，向所述CPU发送所述第三报文；所述指定位置为所述第一报文的除所述以太头部之外的位置。
  10. 根据权利要求9所述的转换装置，其特征在于，将第一报文的以太头部中的私有信息头迁移至第一报文的指定位置包括：
    根据本地已记录的私有信息头识别方式从所述第一报文的以太头部中识别出所述私有信息头；
    将所述私有信息头从所述第一报文的以太头部迁移至所述第一报文的指定位置。
  11. 一种转换装置，其特征在于，所述转换装置应用于网络设备，所述网络设备包括交换芯片、CPU，所述交换芯片至少包括：CPU接口，所述CPU至少包括：媒体访问控制器、缓存器Buffer；
    所述转换装置连接在所述媒体访问控制器和所述Buffer之间；
    所述转换装置被配置为：
    接收第一报文，所述第一报文为所述交换芯片通过所述CPU接口向所述CPU上送的且经由所述媒体访问控制器处理的报文；
    将所述第一报文的以太头部中的私有信息头迁移至所述第一报文的指定位置，得到第二报文，计算第二报文的循环冗余校验CRC码，利用所述CRC码替换第二报文已携带的CRC码得到第三报文，将所述第三报文发送至所述Buffer进行缓存；所述指定位置为所述第一报文的除所述以太头部之外的位置。
  12. 根据权利要求11所述的转换装置，其特征在于，将第一报文的以太头部中的私有信息头迁移至第一报文的指定位置包括：
    根据本地已记录的私有信息头识别方式从所述第一报文的以太头部中识别出所述私有信息头；
    将所述私有信息头从所述第一报文的以太头部迁移至所述第一报文的指定位置。
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