WO2020107754A1 - 一种提高GaN增强型MOSFET阈值电压的外延层结构及器件制备 - Google Patents

一种提高GaN增强型MOSFET阈值电压的外延层结构及器件制备 Download PDF

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WO2020107754A1
WO2020107754A1 PCT/CN2019/079417 CN2019079417W WO2020107754A1 WO 2020107754 A1 WO2020107754 A1 WO 2020107754A1 CN 2019079417 W CN2019079417 W CN 2019079417W WO 2020107754 A1 WO2020107754 A1 WO 2020107754A1
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王茂俊
陶明
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Peking University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates

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  • the invention belongs to the technical field of microelectronics, and relates to the field of power electronic devices and power switches based on compound semiconductor materials.
  • GaN Because of its outstanding material properties, such as high breakdown field strength, high electron saturation mobility, etc., wide band gap semiconductor GaN is considered to be a very promising competitor in the field of next-generation high-efficiency power switches.
  • 2DEG two-dimensional electron gas
  • 2DEG two-dimensional electron gas
  • this advantage allows GaN power electronic devices based on AlGaN/GaN heterojunction to have faster switching speed, but it also means that the conventional heterojunction high mobility transistor (HEMT) is a depletion type device, That is, at zero gate voltage, the device is normally open and the device threshold voltage is negative.
  • GaN-based devices there are two main ways to realize the enhanced operation of GaN-based devices.
  • One is to integrate a low-voltage enhanced silicon-based MOSFET and a high-voltage depletion-mode GaN device into a cascode structure to achieve an enhanced operation. System; the second is to directly use enhanced high-voltage GaN power devices.
  • the advantage of the cascode structure is that the gate is controlled on the silicon-based MOSFET, and the gate of the GaN-based device is not directly controlled, so that the system has no operating current at zero bias and is forward-biased above the threshold voltage When pressing, it can use the normally open GaN-based device to quickly open.
  • the gate control does not directly affect the GaN-based device, and the conversion efficiency control of the power switch is not very good, and this will greatly affect the safe operation of the system and the pulsating noise. Therefore, the direct gate-controlled high-voltage enhanced GaN power device It is still very necessary.
  • the present invention focuses on the design of the AlGaN/GaN heterojunction epitaxial layer structure, and proposes a new epitaxial layer structure that uses a simple and easy to implement traditional dry etching process By removing the AlGaN barrier layer, an enhanced GaN power device with a very positive threshold voltage can be prepared.
  • the novel epitaxial layer structure proposed by the present invention includes: a substrate, a GaN buffer layer, an intrinsic GaN layer, an Mg-doped P-type GaN layer, an intrinsic GaN channel layer, and an intrinsic AlGaN barrier layer, as shown in the figure 1 shown.
  • the new epitaxial layer structure inserts a layer of Mg-doped P-type GaN into the intrinsic GaN layer under 2DEG.
  • the gate is etched below the Mg-doped P-type GaN layer to form a gate
  • the lower channel compared with the channel formed by removing the AlGaN barrier layer in the traditional epitaxial layer structure, the structure has more P-type GaN channels on both sides, that is, the device is fully turned on.
  • the inversion of the GaN layer the inversion of the P-type GaN channel is also required, so that the threshold voltage of the device will be larger than that of the enhanced device prepared by the traditional epitaxial layer structure.
  • the p-type GaN inversion channel is located on the side, and its effective width is very narrow, which is determined by the thickness of the p-type GaN, which avoids facing a long lateral P-type GaN trench when only etching the upper layer of intrinsic GaN Road. Since the carrier mobility of the inversion channel on p-type GaN is less than that of the accumulation channel on intrinsic GaN, this etching scheme can effectively avoid the lateral p-type GaN inversion channel The problem of large on-resistance improves the output current capability of the device.
  • the formation of passivation layer, groove gate, plane isolation, insulating gate dielectric layer, ohmic contact, and gate and source-drain ohmic metal electrodes on the above new epitaxial layer structure using traditional groove gate process can form the enhancement of high threshold voltage Type GaN MOSFET.
  • the channel inversion region After inserting a P-type GaN layer into the intrinsic GaN layer and completely etching it, the channel inversion region has a P-type GaN layer in addition to the intrinsic GaN layer, which can greatly increase the threshold voltage of the device and help solve The reliability of GaN-enhanced devices in practical applications has broadened their application in the field of power switching.
  • the present invention uses the Sentaurus TCAD simulation tool to simulate and verify a simple MOS gate trench type device based on the new epitaxial layer structure (as shown in FIG. 2).
  • the resulting transfer characteristics of the device are shown in FIG. 3. It is seen that the threshold voltage is about 5V (extracted by linear extrapolation), which is greatly improved compared with the gate-groove device under the traditional structure, and preliminary simulation verification confirms the feasibility of the present invention.
  • the inserted Mg-doped P-type GaN layer needs to be designed with a reasonable thickness and doping concentration.
  • composition and material types of the key layers of the new epitaxial layer structure are as follows:
  • the substrate material is preferably one of the following materials: Si, SiC, sapphire.
  • the doping concentration of the Mg-doped P-type GaN layer is preferably: 5E16 ⁇ 2E18cm -3 .
  • the thickness of the Mg-doped P-type GaN layer is preferably 50 nm to 300 nm.
  • the thickness of the intrinsic GaN channel layer on the Mg-doped P-type GaN layer is preferably: 100 nm to 300 nm.
  • the present invention provides a simple and easy-to-implement process based on the new GaN epitaxial layer structure to prepare GaN enhanced MOSFET, including the following steps:
  • a GaN buffer layer, an intrinsic GaN layer, an Mg-doped P-type GaN layer, an intrinsic GaN channel layer, and an intrinsic AlGaN barrier layer are sequentially grown on the substrate;
  • the gate pattern is lithographically etched, the dielectric passivation layer is etched first, and then the intrinsic GaN channel layer is etched until the Mg-doped P-type GaN layer is completely etched to form a groove, and then preferably at 650 °C ⁇ 800 °C Anneal in N 2 protective gas for 15 minutes to activate P-type GaN;
  • the area of the gate electrode is etched, the gate electrode material is grown by electron beam evaporation or magnetron sputtering, then the device is subjected to a stripping process to form the gate electrode, and finally the entire wafer is annealed under a nitrogen atmosphere to complete the entire device Of preparation.
  • the material of the dielectric passivation layer in the above process method may be any one of the following materials: Si 3 N 4 , SiO 2 , AlN, Al 2 O 3 , SiON.
  • step 3) the method of etching to form the groove may be any one of the following methods: ICP etching, wet etching.
  • the materials of the source electrode and the drain electrode in the above process method are: one or more alloys of titanium, aluminum, nickel, gold, platinum, iridium, molybdenum, tantalum, niobium, cobalt, zirconium, tungsten and the like.
  • the insulating gate dielectric layer in the above process method may be any one of the following materials: Si 3 N 4 , Al 2 O 3 , AlN, HfO 2 , SiO 2 , HfTiO, Sc 2 O 3 , Ga 2 O 3 , MgO, SiON.
  • the gate electrode material in the above process method is one or a combination of the following conductive materials: platinum, iridium, nickel, gold, molybdenum, palladium, selenium, beryllium, TiN, polysilicon, ITO.
  • the present invention proposes a new type of AlGaN/GaN heterojunction structure, on which the enhanced device with larger threshold voltage can be realized by the simplest gate trench etching process. This guarantees the absolute off-state of the device under zero bias and is expected to solve the related reliability problems of GaN devices in practical applications.
  • FIG. 1 is a schematic cross-sectional structure diagram of a novel epitaxial layer structure proposed by the present invention.
  • FIG. 2 is a schematic diagram of a cross-sectional structure of a simple MOS gate trench type GaN enhanced device based on the novel epitaxial layer structure of the present invention (sentaurus TCAD device simulation structure).
  • Fig. 3 is a comparison diagram of the device transfer characteristic curve obtained by computer simulation of the device structure shown in Fig. 2 with the use of Sentaurus TCAD simulation software and an ordinary device without a pGaN insertion layer. It can be seen that the threshold voltage of the device is greatly increased.
  • FIGS. 4 to 9 are schematic diagrams of device cross-sectional structures corresponding to each step of the process of preparing a trench-type GaN enhanced device based on the epitaxial layer structure proposed by the present invention, and reflect a specific implementation example of the present invention.
  • FIG. 1 shows the novel epitaxial layer structure proposed by the present invention.
  • the heterojunction structure smoothly includes the substrate, the GaN buffer layer, the intrinsic GaN layer, the Mg-doped P-type GaN layer, and the intrinsic GaN channel Layer and intrinsic AlGaN barrier layer.
  • a specific implementation example of preparing a GaN enhanced device using a gate trench etching process based on the structure includes the following specific steps:
  • the active region is formed, and the GaN wafer that has been annealed to activate the P-type GaN at the channel is photolithographic and etched (or ion implanted) to form the active region mesa;
  • step (4) On the basis of step (4), an Al 2 O 3 insulating gate dielectric layer is grown on the wafer surface to form the structure shown in FIG. 7;
  • the Al 2 O 3 covering the source-drain ohmic contact is removed by wet etching (as shown in FIG. 8), and then Ni is grown by electron beam evaporation in the gate region /Au alloy, and then continue to use the stripping process to form the gate metal electrode to form a T-gate structure, as shown in Figure 9. Finally, the entire wafer was annealed under N 2 atmosphere and annealed at 400°C for 10 min.
  • the enhanced GaN prepared by the above process steps has a larger threshold voltage, which can ensure the absolute off state under zero bias.

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Abstract

一种提高GaN增强型MOSFET阈值电压的外延层结构及基于该结构的器件制备方法，涉及电力电子器件及功率开关领域。该外延层结构自下而上依次为衬底、GaN缓冲层、本征GaN层、Mg掺杂P型GaN层、GaN沟道层和AlGaN势垒层。在该结构上用凹槽栅工艺形成钝化层、凹槽栅、平面隔离、绝缘栅介质层、欧姆接触以及栅和源漏欧姆金属电极即可制备出高阈值电压增强型GaN MOSFET。本发明在本征GaN层中插入P型GaN层，将其完全刻蚀后，沟道反型区域除了本征GaN层还有P型GaN层，由此可以极大提高器件的阈值电压。有利于解决GaN增强型器件在实际应用中的可靠性问题，扩宽了其在功率开关领域的应用。

Description

一种提高GaN增强型MOSFET阈值电压的外延层结构及器件制备 技术领域
本发明属于微电子技术领域，涉及基于化合物半导体材料的电力电子器件及功率开关领域。
背景技术
宽禁带半导体GaN因其突出的材料性能，例如高击穿场强、高电子饱和迁移率等，而被认为是下一代高效率功率开关领域十分有前景的竞争者。此外，由于极强的自发极化效应，在常规的AlGaN/GaN异质结界面天然存在着浓度可高达10 13cm -2的二维电子气(2DEG)，2DEG的迁移率可高达2000cm 2/V·S，这一优势使得基于AlGaN/GaN异质结的GaN电力电子器件能有更快的开关速度，但同时也意味着常规异质结高迁移率晶体管(HEMT)为耗尽型器件，即在零栅压下，器件处于常开态，器件阈值电压为负值。然而在实际应用中，对于功率电子系统的安全操作而言，为了确保只加正栅压偏置时器件才有工作电流，增强型器件是必不可缺的。因此，国内外众多研究人员一直在致力于实现高性能的增强型GaN HEMT。
目前主要有两种方式来实现GaN基器件的增强型操作，一是将一个低压增强型硅基MOSFET和一个高压耗尽型GaN器件采用共源共栅结构集成封装成一个能实现增强型操作的系统；二是直接采用增强型高压GaN功率器件。共源共栅结构的优势主要是栅控在硅基MOSFET上，而GaN基器件的栅并没有被直接控制，这样使得该系统在零偏压时没有工作电流，在阈值电压以上的正向偏压时，又能利用常开的GaN基器件快速开启。然而毕竟栅控没有直接作用在GaN基器件上，功率开关的转换效率控制就不太好，而这又会极大地影响系统的安全操作以及脉动噪声，因此直接栅控的高压增强型GaN功率器件依然十分有必要。
增强型GaN功率器件的实现主要有以下两种方法：1.在AlGaN/GaN异质结表面生长一层P-type GaN层，合理地设计该层的厚度以及掺杂即可有效地耗尽异质结界面处的2DEG，从而实现常关型GaN功率器件，P-Type GaN栅结构虽然能够得到阈值电压一致性很好的增强型器件，但是由于P型GaN生长困难，材料质量差导致栅可靠性并不好。2.减薄栅区域的AlGaN层厚度，消除栅下的固有正极化电荷，从而耗尽异质结界面处的2DEG，实现常关型GaN功率器件，该法制得的金属-绝缘栅结构(MIS)器件虽然能得到不错的栅可靠性器件且工艺简单，但该器件的阈值电压很难做得很正，换言之很难保证零偏压下的绝对关断状态。
发明内容
为了解决上述方法2实现增强型GaN功率器件技术的缺点，本发明着眼于AlGaN/GaN 异质结外延层结构的设计，提出一种新型外延层结构，采用简单易于实现的传统干法刻蚀工艺去除AlGaN势垒层，即可制备得到阈值电压很正的增强型GaN功率器件。
本发明提出的新型外延层结构自下而上包括：衬底、GaN缓冲层、本征GaN层、Mg掺杂P型GaN层、本征GaN沟道层以及本征AlGaN势垒层，如图1所示。该新型外延层结构在2DEG下方的本征GaN层中插入了一层Mg掺杂P型GaN层，采用传统栅槽刻蚀工艺，栅下方刻蚀到Mg掺杂P型GaN层以下，形成栅下方的沟道，相比于传统外延层结构去除AlGaN势垒层后形成的沟道，该结构中多出了两侧的P-type GaN沟道，也就是说，器件完全开启，不仅需要本征GaN层的反型，还需要P-type GaN沟道的反型，由此器件的阈值电压将会比传统外延层结构制备出来的增强型器件要大。与此同时，p-type GaN反型沟道位于侧面，其有效宽度很窄，由p-type GaN的厚度决定，避免了仅刻蚀上层本征GaN时面临较长的横向P-type GaN沟道。由于p-type GaN上反型沟道的载流子迁移率要小于本征GaN上的积累沟道中载流子迁移率，因此这种刻蚀方案可以有效回避横向p-type GaN反型沟道导通电阻大的问题，从而提高器件的输出电流能力。
在上述新型外延层结构上用传统的凹槽栅工艺形成钝化层、凹槽栅、平面隔离、绝缘栅介质层、欧姆接触以及栅和源漏欧姆金属电极，即可形成高阈值电压的增强型GaN MOSFET。在本征GaN层中插入P型GaN层，将其完全刻蚀后，沟道反型区域除了本征GaN层还有P型GaN层，由此可以极大提高器件的阈值电压，有利于解决GaN增强型器件在实际应用中的可靠性问题，扩宽了其在功率开关领域的应用。
本发明依据上述技术思路，借助sentaurus TCAD仿真工具，对基于该新型外延层结构的简单MOS栅槽型器件(如图2所示)进行仿真验证，得到的器件转移特性如图3所示，可以看到阈值电压约为5V(线性外推法提取)，这相比于传统结构下的栅槽型器件有了极大的提高，初步仿真验证证实了本发明的可行性。为了实现该新型外延层的生长且保证器件的性能，插入的Mg掺杂P型GaN层需要合理地设计其厚度、掺杂浓度，此外，为了避免P-type GaN对GaN沟道层的影响，其与GaN沟道层的距离也应该合理地设计。综合考虑以上各项影响，该新型外延层结构关键层成分组成及材料种类如下所示：
所述衬底材料优选为以下材料中的一种：Si、SiC、蓝宝石。
所述Mg掺杂P型GaN层掺杂浓度优选为：5E16～2E18cm -3。
所述Mg掺杂P型GaN层厚度优选为50nm～300nm。
所述Mg掺杂P型GaN层上面的本征GaN沟道层厚度优选为：100nm～300nm。
本发明提供了基于该GaN新型外延层结构的一种简单易于实现的工艺方法来制备GaN增强型MOSFET，包括以下步骤：
(1)在所述衬底上依次生长GaN缓冲层、本征GaN层、Mg掺杂P型GaN层、本征GaN沟道层以及本征AlGaN势垒层；
(2)在AlGaN势垒层上用PECVD、ICPCVD或者LPCVD生长介质钝化层；
(3)光刻出栅极图形，首先刻蚀介质钝化层，再刻蚀本征GaN沟道层直至Mg掺杂P型GaN层全部刻蚀干净形成凹槽，然后优选在650℃～800℃之间于N 2保护气体中退火15分钟，激活P-type GaN；
(4)对已经退火激活沟道处P-type GaN的GaN晶圆片进行光刻和刻蚀(或者离子注入)形成有源区台面；
(5)对制备好有源区台面的GaN晶圆片进行光刻，刻蚀出源漏欧姆电极区域，通过电子束蒸发或者磁控溅射制备多层金属形成源极和漏极，并在800℃到900℃之间于保护气体中退火30秒，形成欧姆接触；
(6)形成欧姆接触之后，将晶圆片放入原子层淀积设备中，在其表面生长绝缘栅介质层，随后光刻出源漏区域欧姆接触孔，去除掉欧姆接触孔的绝缘栅介质层，使得源漏欧姆接触露出来；
(7)光刻栅电极区域，用电子束蒸发或者磁控溅射生长栅电极材料，随后对器件进行剥离工艺处理形成栅电极，最后在氮气环境下对整个晶圆进行退火处理，完成整体器件的制备。
以上工艺方法中所述介质钝化层的材料可为以下材料中的任意一种：Si 3N 4、SiO 2、AlN、Al 2O 3、SiON。
以上工艺方法中，步骤3)刻蚀形成凹槽的方法可以是以下方法的任意一种：ICP刻蚀、湿法腐蚀。
以上工艺方法中所述源极和漏极的材料为：钛、铝、镍、金、铂、铱、钼、钽、铌、钴、锆、钨等中的一种或多种的合金。
以上工艺方法中所述绝缘栅介质层可为以下材料中的任意一种：Si 3N 4、Al 2O 3、AlN、HfO 2、SiO 2、HfTiO、Sc 2O 3、Ga 2O 3、MgO、SiON。
以上工艺方法中所述栅电极材料为以下导电材料中的一种或多种的组合：铂、铱、镍、金、钼、钯、硒、铍、TiN、多晶硅、ITO。
本发明从化合物半导体的材料结构设计角度出发，提出一种新型的AlGaN/GaN异质结结构，在该结构上用最简单的栅槽刻蚀工艺即可实现较大阈值电压的增强型器件，保证了器件在零偏压下的绝对关断状态从而有望解决GaN器件在实际应用中的相关可靠性问题。
附图说明
附图将会更加详细地阐述本发明提出的新型外延层结构以及基于该外延层结构的GaN增强型器件制备示例。附图说明如下：
图1是本发明提出的新型外延层结构剖面结构示意图。
图2是基于本发明新型外延层结构的简单MOS栅槽型GaN增强型器件的剖面结构示意图(sentaurus TCAD器件仿真结构)。
图3是借助sentaurus TCAD仿真软件对图2所示器件结构计算机模拟得到的器件转移特性曲线和没有pGaN插入层的普通器件的对比图，可以看出器件阈值电压大幅度提升。
图4～图9是基于本发明提出的外延层结构，在其上制备栅槽型GaN增强型器件每一步工艺后对应的器件剖面结构示意图，反映了本发明的一个具体实施示例。
具体实施方式
在下文中，将参照附图详细地阐述基于本发明提出的新型外延层结构制备栅槽型GaN增强型器件，以使本发明的具体实施方法、工艺流程、核心技术要点更加易于明白了解。该示例仅为本发明的一种实现方法，即本发明提出的结构不应该局限于在此阐述的示例。基于该示例，将本发明的范围充分地传达给本领域技术人员。
图1展示了本发明提出的新型外延层结构，该异质结结构从下向上的顺利依次包括衬底、GaN缓冲层、本征GaN层、Mg掺杂P型GaN层、本征GaN沟道层以及本征AlGaN势垒层。基于该结构利用栅槽刻蚀工艺制备GaN增强型器件的一个具体实施示例包括以下具体步骤：
(1)在图1所示的AlGaN/GaN异质结结构晶圆上用PECVD、ICPCVD或者LPCVD生长一层Si 3N 4钝化层，用来提高最终器件的可靠性，形成的结构剖面图如图4所示；
(2)在图4所示结构的基础上，首先用RIE刻蚀机去除栅槽区域的Si 3N 4，然后用ICP刻蚀机去除栅槽区域的GaN，栅下方刻蚀到Mg掺杂P型GaN层以下，形成栅下方的沟道，最后在650℃～800℃之间于N 2保护气体中退火15分钟，激活P-type GaN，形成的结构剖面图如图5所示；
(3)接下来形成有源区域，对已经退火激活沟道处P-type GaN的GaN晶圆片进行光刻和刻蚀(或者离子注入)形成有源区台面；
(4)然后在有源区区域中光刻出源漏欧姆图形，首先用RIE刻蚀机去除覆盖其上的Si 3N 4，然后通过电子束蒸发Ti/Al/Ni/Au四种金属，采用剥离工艺制备出源漏欧姆金属电极，最后在870℃氮气氛围中进行快速退火30秒，形成欧姆接触，其剖面结构示意图如图6所示；
(5)在步骤(4)的基础上，在晶圆表面生长Al 2O 3绝缘栅介质层，形成如图7所示的结构；
(6)在图7所示结构的基础上用湿法腐蚀的方法去除覆盖在源漏欧姆接触上面的Al 2O 3(如图8所示)，接下来在栅区用电子束蒸发生长Ni/Au合金，随后继续用剥离工艺形成栅金属电极，形成一个T型栅结构，如图9所示。最后在N 2氛围下对整个晶圆进行退火处理，在400℃下退火10min。
通过以上工艺步骤制备得到的增强型GaN MOSHEMT相比于常规的增强型器件，阈值电压更大，能确保零偏压下的绝对关断状态。

Claims (14)

  1. 一种提高GaN增强型MOSFET阈值电压的外延层结构，自下而上依次为衬底、GaN缓冲层、本征GaN层、Mg掺杂P型GaN层、本征GaN沟道层和本征AlGaN势垒层。
  2. 根据权利要求1所述的提高GaN增强型MOSFET阈值电压的外延层结构，其特征在于：所述衬底的材料为Si、SiC或蓝宝石。
  3. 根据权利要求1所述的提高GaN增强型MOSFET阈值电压的外延层结构，其特征在于：所述Mg掺杂P型GaN层的掺杂浓度为5E16～2E18cm -3。
  4. 根据权利要求1所述的提高GaN增强型MOSFET阈值电压的外延层结构，其特征在于：所述Mg掺杂P型GaN层的厚度为50nm～300nm。
  5. 根据权利要求1所述的提高GaN增强型MOSFET阈值电压的外延层结构，其特征在于：所述本征GaN沟道层的厚度为100nm～300nm。
  6. 一种GaN增强型MOSFET，为栅槽型器件，其特征在于，该器件具有权利要求1～5任一所述的提高GaN增强型MOSFET阈值电压的外延层结构，栅槽刻蚀至所述Mg掺杂P型GaN层以下。
  7. 一种GaN增强型MOSFET的制备方法，首先在衬底上依次生长GaN缓冲层、本征GaN层、Mg掺杂P型GaN层、本征GaN沟道层和本征AlGaN势垒层，得到权利要求1～5任一所述的提高GaN增强型MOSFET阈值电压的外延层结构，然后在其上用凹槽栅工艺形成GaN增强型MOSFET。
  8. 根据权利要求7所述的制备方法，其特征在于，该制备方法包括以下步骤：
    1)在衬底上依次生长GaN缓冲层、本征GaN层、Mg掺杂P型GaN层、本征GaN沟道层和本征AlGaN势垒层；
    2)在本征AlGaN势垒层上生长介质钝化层；
    3)光刻出栅极图形，先刻蚀介质钝化层，再刻蚀本征GaN沟道层直至Mg掺杂P型GaN层全部刻蚀干净，形成凹槽，然后退火激活P型GaN；
    4)光刻和刻蚀或者离子注入形成有源区台面；
    5)在有源区台面光刻和刻蚀出源漏欧姆电极区域，通过电子束蒸发或者磁控溅射制备金属源极和漏极，并退火形成欧姆接触；
    6)利用原子层淀积设备在表面生长绝缘栅介质层，随后光刻出源漏区域欧姆接触孔，去除掉欧姆接触孔的绝缘栅介质层，使得源漏欧姆接触露出来；
    7)光刻栅电极区域，用电子束蒸发或者磁控溅射生长栅电极材料，随后对器件进行剥离工艺处理形成栅电极，最后退火处理，完成整体器件的制备。
  9. 根据权利要求8所述的制备方法，其特征在于：所述介质钝化层的材料为以下材料中的任意一种：Si 3N 4、AlN、Al 2O 3、SiO 2、SiON。
  10. 根据权利要求8所述的制备方法，其特征在于：步骤3)通过ICP刻蚀或湿法腐蚀形成凹槽。
  11. 根据权利要求8所述的制备方法，其特征在于：步骤3)中在650℃～800℃于N 2保护气体中退火15分钟，激活P型GaN。
  12. 根据权利要求8所述的制备方法，其特征在于：步骤6)中所述绝缘栅介质层为以下材料中的任意一种：Si 3N 4、Al 2O 3、AlN、HfO 2、SiO 2、HfTiO、Sc 2O 3、Ga 2O 3、MgO、SiNO。
  13. 根据权利要求8所述的制备方法，其特征在于：所述源极和漏极的材料选自钛、铝、镍、金、铂、铱、钼、钽、铌、钴、锆和钨中的一种或多种的合金。
  14. 根据权利要求8所述的制备方法，其特征在于：所述栅电极材料为以下导电材料中的一种或多种的组合：铂、铱、镍、金、钼、钯、硒、铍、TiN、多晶硅、ITO。
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