WO2020107478A1

WO2020107478A1 - Voltage equalization circuit, voltage equalization method and device

Info

Publication number: WO2020107478A1
Application number: PCT/CN2018/118776
Authority: WO
Inventors: 张书浩; 邹桐
Original assignee: 北京比特大陆科技有限公司
Priority date: 2018-11-30
Filing date: 2018-11-30
Publication date: 2020-06-04
Also published as: CN112889198B; CN112889198A

Abstract

A voltage equalization circuit, a voltage equalization method and a device. The voltage equalization circuit comprises: a driver (11), a variable resistance unit (12) and a calculation unit (13). The driver (11) is connected to the variable resistance unit (12) and the calculation unit (13), and the variable resistance unit (12) is also connected to the calculation unit (13). The driver (11) is configured to acquire the voltage across the calculation unit (13), and adjust the resistance of the variable resistance unit (12) according to the voltage across the calculation unit (13), so that the voltage across the calculation unit (13) is within a preset voltage range. By means of said method and device, the reliability of a circuit is improved.

Description

Voltage balancing circuit, voltage balancing method and equipment

Technical field

The present disclosure relates to the field of circuit technology, and in particular, to a voltage balancing circuit, voltage balancing method, and equipment.

Background technique

Currently, a plurality of components (such as chips, etc.) are usually provided in the circuit. Among the plurality of components, some components are in a parallel relationship and some components are in a series relationship.

In the actual application process, the multiple components may be powered by the same power source. When the same power source supplies multiple serially connected components, the voltage shared by each component may be different from the actual voltage required by the component, causing the component to fail jobs. For example, when the voltage actually shared by the component is less than the starting voltage of the component, the component cannot start working. When the voltage actually shared by the component is greater than the maximum voltage that the component can withstand, the component may be burned out. It can be seen from the above that the reliability of the circuit in the prior art is poor.

Summary of the invention

The present disclosure provides a voltage balancing circuit, a voltage balancing method and equipment, which improves the reliability of the circuit.

In a first aspect, an embodiment of the present disclosure provides a voltage equalization circuit, including: a driver, a variable resistance unit, and a calculation unit, the driver being respectively connected to the variable resistance unit and the calculation unit, the variable resistance The unit is also connected to the computing unit, wherein,

In a second aspect, an embodiment of the present disclosure provides a circuit board, including the voltage equalization circuit described in the first aspect.

In a third aspect, an embodiment of the present disclosure provides a supercomputing device, including the circuit board described in the second aspect.

According to a fourth aspect, an embodiment of the present disclosure provides a voltage equalization method, which is applied to a voltage equalization circuit. The voltage equalization circuit includes a driver, a variable resistance unit, and a calculation unit. The driver and the variable resistance unit are respectively The calculation unit is connected, and the variable resistance unit is also connected to the calculation unit, wherein the method includes:

The driver obtains the voltage across the calculation unit;

The driver adjusts the resistance of the variable resistance unit according to the voltage across the calculation unit, so that the voltage across the calculation unit is within a preset voltage range.

According to a fifth aspect, an embodiment of the present disclosure provides a driver, which is characterized by being applied to a voltage equalization circuit, the voltage equalization circuit including the driver, a variable resistance unit, and a calculation unit. A resistance unit is connected to the calculation unit, and the variable resistance unit is also connected to the calculation unit, wherein the driver includes an acquisition module and an adjustment module, wherein,

The obtaining module is used to obtain the voltage across the computing unit;

The adjustment module is used to adjust the resistance of the variable resistance unit according to the voltage across the calculation unit, so that the voltage across the calculation unit is within a preset voltage range.

According to a sixth aspect, an embodiment of the present disclosure provides an electronic device, which includes:

At least one processor; and

A memory communicatively connected to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor. When the instructions are executed by the at least one processor, the at least one processor is caused to perform the method of the fourth aspect.

According to a seventh aspect, an embodiment of the present disclosure provides a computer-readable storage medium, characterized in that computer-executable instructions are stored, and the computer-executable instructions are configured to perform the method of the fourth aspect.

In an eighth aspect, an embodiment of the present disclosure provides a computer program product, characterized in that the computer program product includes a computer program stored on a computer-readable storage medium, and the computer program includes program instructions, when the program instructions When executed by a computer, the computer is caused to perform the method of the fourth aspect.

The voltage equalization circuit, the voltage equalization method and the equipment provided by the embodiments of the present disclosure include a driver, a variable resistance unit and a calculation unit in the voltage equalization circuit. The driver is respectively connected to the variable resistance unit and the calculation unit The unit is connected, and the driver is used to collect the voltage across the computing unit, and adjust the resistance of the variable resistance unit according to the voltage across the computing unit, so that the voltage across the computing unit is within the preset voltage range, thereby improving the reliability of the circuit.

BRIEF DESCRIPTION

One or more embodiments are exemplified by the corresponding drawings. These exemplary descriptions and the drawings do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a proportional limitation, and among them:

1 is a schematic structural diagram of a first voltage balancing circuit provided by an embodiment of the present disclosure;

2 is a schematic diagram of the voltage correspondence relationship provided by an embodiment of the present disclosure;

3 is a schematic structural diagram of a second voltage equalization circuit provided by an embodiment of the present disclosure;

4 is a schematic structural diagram of a third voltage equalization circuit provided by an embodiment of the present disclosure;

5 is a schematic structural diagram of a fourth voltage equalization circuit provided by an embodiment of the present disclosure;

6 is a schematic structural diagram of a fifth voltage equalization circuit provided by an embodiment of the present disclosure;

7 is a schematic flowchart of a voltage balancing method provided by an embodiment of the present disclosure;

8 is a schematic structural diagram of a driver provided by an embodiment of the present disclosure;

9 is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure.

detailed description

In order to understand the features and technical contents of the embodiments of the present disclosure in more detail, the following describes the implementation of the embodiments of the present disclosure in detail with reference to the drawings. The accompanying drawings are for reference only and are not intended to limit the embodiments of the present disclosure. In the following technical description, for convenience of explanation, various details are provided to provide a sufficient understanding of the disclosed embodiments. However, without these details, one or more embodiments can still be implemented. In other cases, to simplify the drawings, well-known structures and devices can be simplified.

The circuit includes multiple computing units (such as chips, etc.). Normally, when the voltages across the computing units are balanced (the voltages across the components are within the preset voltage range), the computing units can be guaranteed to work properly. In order to equalize the voltage at both ends of the calculation unit in the circuit, an embodiment of the present disclosure provides a voltage equalization circuit in which a driver and a variable resistance unit can be provided, and the driver adjusts the resistance of the variable resistance unit so that The voltage across the calculation unit in the voltage equalization circuit is within a preset voltage range, thereby improving the reliability of the circuit.

The technical solutions shown in the present disclosure will be described in detail below through specific embodiments. The following specific embodiments may exist alone or may be combined with each other. For the same or similar content, repeated description will not be repeated in different embodiments.

FIG. 1 is a schematic structural diagram of a first voltage equalization circuit provided by an embodiment of the present disclosure. Referring to FIG. 1, the voltage equalization circuit may include: a driver 11, a variable resistance unit 12 and a calculation unit 13, the driver 11 is respectively connected to the variable resistance unit 12 and the calculation unit 13, and the variable resistance unit 12 is also connected to the calculation unit 13 Connection, wherein the driver 11 is used to collect the voltage across the computing unit 13 and adjust the resistance (ie, equivalent resistance) of the variable resistance unit 12 according to the voltage across the computing unit 13 so that the voltage across the computing unit 13 is Set voltage range.

In some possible embodiments, the driver 11 may also collect the current flowing through the calculation unit 13 and adjust the resistance of the variable resistance unit 12 according to the current flowing through the calculation unit 13 so that the voltage across the calculation unit 13 is preset Within the voltage range, there is no limit.

In some possible implementations, the driver 11 may generally be any driving device capable of realizing voltage collection and adjusting the resistance of the variable resistance unit 12, and its implementation may also include hardware implementation and software implementation. When the implementation of the driver 11 is a hardware implementation, the driver 11 can usually be a driving circuit, a controller, a processor, a CPU (Central Processing Unit), an MCU (Microcontroller Unit), or an AP (Application Processor, application processor, etc., as long as the voltage across the computing unit 13 can be collected and the actual equivalent resistance of the variable resistance unit 12 can be adjusted; when the implementation of the driver 11 is a software implementation, the driver 11 is usually It may be software code or program code, which is not limited in the embodiments of the present disclosure.

In some possible embodiments, the variable resistance unit 12 may be a transistor.

For example, the transistor may be a MOS (Metal Oxide Semiconductor), such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The transistor may also be a transistor, for example, an NPN transistor, a PNP transistor, or the like.

In some possible implementation manners, the calculation unit 13 may be a device such as a chip.

The computing unit 13 may also be a controller, a processor, or other components in the chip, such as a computing core and a processing core in the chip, which are not specifically limited in the embodiments of the present disclosure.

In some possible implementations, the calculation unit 13 has its corresponding preset voltage range, and the preset voltage range may also be referred to as the working voltage range of the calculation unit 13.

It should be noted that the preset voltage range can usually be flexibly set according to the actual situation, for example, it can be set to 0.8V, 1V, 1.5V, 2V, or 2.5V, etc., without any limitation.

For example, when the computing unit 13 is a chip in the computing board of the supercomputing device, the preset voltage range may generally be the normal range of the core voltage of the chip, such as 0.8V or 1.5V, which will not be repeated here.

In the actual application process, when the voltage across the calculation unit 13 is within the preset voltage range, the calculation unit 13 can work normally. When the voltage across the calculation unit 13 is not within the preset voltage range, the calculation unit 13 cannot work normally.

For example, when the voltage across the computing unit 13 is less than the minimum voltage in the preset voltage range, the computing unit 13 may fail to start working. When the voltage across the computing unit 13 is greater than the maximum voltage in the preset voltage range, the computing unit 13 may be burned out.

In a possible implementation manner, the drivers 11 may be connected to both ends of the computing unit 13 respectively.

During the operation of the voltage equalization circuit, the driver 11 can collect the voltage across the calculation unit 13 and adjust the resistance of the variable resistance unit 12 according to the voltage across the calculation unit 13. Since the variable resistance unit 12 is connected to the calculation unit 13, the change in the resistance of the variable resistance unit 12 will affect the change in the voltage across the calculation unit 13. During the adjustment of the resistance of the variable resistance unit 12 by the driver 11, when the driver 11 detects that the voltage across the calculation unit 13 is within the preset voltage range, the adjustment of the resistance of the variable resistance unit 12 is suspended, so that the variable resistance unit The resistance of 12 remains unchanged, so that the voltage across the computing unit 13 remains unchanged, and the voltage across the computing unit 13 is within a preset voltage range.

In some possible implementation manners, after the driver 11 acquires the voltage across the calculation unit 13, the driver 11 may first determine whether the voltage across the calculation unit 13 is within a preset voltage range. When the voltage across the calculation unit 13 is within the preset voltage range, the driver 11 does not adjust the resistance of the variable resistance unit 12, that is, does not perform any operation. When the voltage across the calculation unit 13 is not within the preset voltage range, the driver 11 then adjusts the resistance of the variable resistance unit 12

In some possible implementations, the driver 11 may determine the driving signal according to the voltage across the computing unit 13 and the preset voltage range, and adjust the resistance of the variable resistance unit 12 according to the driving signal, so that the voltage across the computing unit 13 is Within the preset voltage range.

Optionally, when the variable resistance unit 12 is a transistor, the driving signal may be a voltage signal between the control terminal and the output terminal (or input terminal) of the transistor.

Optionally, the voltage between the two ends of the calculation unit 13 and the first voltage of the transistor (the voltage between the control terminal and the output terminal of the transistor, or the voltage between the control terminal and the input terminal of the transistor) may be preset For the corresponding relationship, the driver 11 may determine the voltage between the control terminal and the output terminal of the transistor according to the preset voltage range and the corresponding relationship.

For example, when the transistor is a MOS tube, the correspondence may be the correspondence between the voltage across the calculation unit 13 and the gate-source voltage of the MOS tube (the voltage between the gate and source of the MOS tube), for example, The voltage between _core and V _GS ; when the transistor is a triode, the corresponding relationship can be the voltage between the two ends of the calculation unit 13 and the base-emitter voltage of the triode (the voltage between the base and the emitter of the triode) Correspondence.

For example, if the variable resistance unit 12 is a MOS tube and the calculation unit 13 is a chip, the correspondence between the voltage across the calculation unit 13 and the variable voltage of the variable resistance unit 12 can be the voltage across the chip and the MOS tube The corresponding relationship between the gate-source voltages of can be shown in Figure 2.

Referring to FIG. 2, the horizontal axis represents the voltage across the computing unit 13 (ie, the chip), the vertical axis represents the gate-source voltage of the MOS tube, and V _off is the turn-off voltage of the MOS tube.

It should be noted that when the computing unit is a series of multiple chips, the voltage across the computing unit may also be the voltage across the multiple series chips, such as nV _core (n is the number of chips in series), which will not be repeated here. .

As can be seen from FIG. 2, the larger the gate-source voltage of the MOS transistor, the smaller the voltage across the calculation unit 13. Therefore, when the voltage across the calculation unit 13 needs to be reduced, the gate-source voltage of the MOS tube can be increased, so that the equivalent resistance of the MOS tube increases, and the equivalent resistance of the calculation unit 13 and the MOS tube decreases, thereby reducing the calculation The voltage across unit 13 decreases.

When the voltage across the calculation unit 13 needs to be increased, the gate-source voltage of the MOS transistor needs to be reduced. However, in practical applications, the actual voltage will only decrease and not increase after the MOS transistors are connected in parallel. Therefore, the other computing units 13 (other over-voltage computing units) connected in series with the computing unit 13 can be adjusted at this time. The voltage at the terminal makes the calculation unit 13 on the entire link within the normal voltage range.

FIG. 2 merely illustrates the correspondence between the voltage across the calculation unit 13 and the gate-source voltage of the MOS transistor in an example form, and does not limit the correspondence.

The voltage equalization circuit provided by an embodiment of the present disclosure includes a driver 11, a variable resistance unit 12, and a calculation unit 13, the driver 11 is connected to the variable resistance unit 12 and the calculation unit 13, respectively, and the variable resistance unit 12 is also connected to the calculation unit 13 The driver 11 is used to collect the voltage across the computing unit 13 and adjust the resistance of the variable resistance unit 12 according to the voltage across the computing unit 13 so that the voltage across the computing unit 13 is within a preset voltage range, thereby improving the circuit reliability.

Based on the embodiment shown in FIG. 1, in some possible implementation manners, the voltage equalization circuit may further include a power supply, the power supply is connected to the variable resistance unit 12 and the calculation unit 13, and the power supply is used to connect the variable resistance unit 12 and The computing unit 13 supplies power.

In some possible embodiments, the variable resistance unit 12 may be a MOS transistor. Among them, the gate of the MOS tube is connected to the driver 11, and the source and drain of the MOS tube are respectively connected to the computing unit 13.

Optionally, the calculation unit 13 may include a chip. Alternatively, the calculation unit 13 may include at least two chips in parallel. Alternatively, the calculation unit 13 may include at least two chips connected in series. Alternatively, the computing unit 13 may include at least two chipsets connected in parallel, and each chipset includes at least two chips connected in series.

Next, taking the variable resistance unit 12 as a MOS tube as an example, the above three cases will be described in detail with reference to FIGS. 3 to 5.

FIG. 3 is a schematic structural diagram of a second voltage equalization circuit provided by an embodiment of the present disclosure. Referring to FIG. 3, the variable resistance unit 12 is a MOS tube, and the calculation unit 13 is a chip IC. The driver 11 is respectively connected to the gate and the chip of the MOS tube, and the source and drain of the MOS tube are respectively connected to the chip.

In some possible implementations, the drivers 11 are respectively connected to both ends of the chip.

In some possible implementations, the source of the MOS tube is connected to one end of the chip, and the drain of the MOS tube is connected to the other end of the chip.

In the actual application process, the driver 11 can collect the voltage across the chip in real time. When the voltage across the chip is within the preset voltage range, the driver 11 does nothing, the MOS is equivalent to an open circuit, and the equivalent resistance is infinite.

When the voltage across the chip is not within the preset voltage range, the driver 11 determines the gate-source voltage of the MOS tube according to the preset voltage range, and outputs a new voltage to the gate of the MOS tube, so that the MOS works in the variable resistance area, and The equivalent resistance of the MOS tube is changed. After the equivalent resistance of the MOS tube is changed, the equivalent resistance of the MOS tube and the chip in parallel is also changed. This can change the voltage across the chip, until The voltage is within the preset voltage range.

It should be noted that at this time, the gate-source voltage output by the driver 11 to the MOS transistor needs to be kept constant to ensure that the voltage across the chip continues within the preset voltage range.

4 is a schematic structural diagram of a third voltage equalization circuit provided by an embodiment of the present disclosure. Referring to FIG. 4, the variable resistance unit 12 is a MOS tube, and the calculation unit 13 includes multiple parallel chips (IC1, IC2, ..., ICn). The driver 11 is respectively connected to the gate of the MOS tube and each chip, and the source and drain of the MOS tube are respectively connected to each chip.

In some possible embodiments, the driver 11 may be connected to both ends of each chip in the computing unit 13. Alternatively, the driver 11 may be connected to both ends of any one or more chips in the computing unit 13.

In some possible implementations, the source of the MOS tube is connected to one end of each chip, and the drain of the MOS tube is connected to the other end of each chip.

In some possible implementation manners, the preset voltage ranges corresponding to multiple parallel chips included in the calculation unit 13 may be the same.

In actual application, the driver 11 can collect the voltage across the chip in real time. When the voltage across the chip is within the preset voltage range, the driver 11 does not change the voltage output to the gate of the MOS tube, so that the resistance of the MOS tube remains constant. When the voltage across the chip is not within the preset voltage range, the driver 11 determines the gate-source voltage of the MOS tube according to the preset voltage range, and outputs a new voltage to the gate of the MOS tube, so that the equivalent resistance of the MOS tube changes. After the equivalent resistance of the MOS tube changes, the equivalent resistance of the MOS tube and multiple chips changes. Because the power supply supplies power to the multiple chips and MOS tubes, the power supply also supplies power to other components connected in series with the multiple chips. Therefore, when the equivalent resistance of the transistor and the multiple chips changes, the voltage division of the MOS tube and the multiple chips changes, which in turn causes the voltage across each chip to change, so that the voltage across each chip can be Within the preset voltage range.

FIG. 5 is a schematic structural diagram of a fourth voltage equalization circuit provided by an embodiment of the present disclosure. Referring to FIG. 5, the variable resistance unit 12 is a transistor, and the calculation unit 13 includes a plurality of chips (IC1, IC2, ..., ICn) connected in series. The driver 11 is respectively connected to the gate of the MOS tube and a plurality of chips connected in series, and the source and drain of the MOS tube are connected to each chip respectively.

In some possible implementations, one end of the driver 11 is connected to the first chip (for example, IC1) in the computing unit 13, and the other end of the driver 11 is connected to the last chip (for example, ICn) in the computing unit 13.

In some possible implementations, the drain of the MOS transistor is connected to the first chip (eg, IC1) in the calculation unit 13, and the source of the transistor is connected to the last chip (eg, ICn) in the calculation unit 13.

In the actual application process, the driver 11 can collect the voltage across the n chips in real time (the sum of the voltage across each chip of the n chips), when the voltage across the n chips is within the voltage range corresponding to the n chips , The voltage across each chip of the n chips is usually within the respective operating voltage range, that is, each chip of the n chips can normally work normally, in this case, the driver 11 does not change the The voltage output by the gate keeps the resistance of the MOS tube constant. When the voltage across the n chips is not within the voltage range corresponding to the n chips, the driver 11 determines the gate-source voltage of the MOS tube according to the voltage range corresponding to the n chips, and outputs a new voltage to the gate of the MOS tube, The equivalent resistance of the MOS tube changes. After the equivalent resistance of the MOS tube changes, the equivalent resistance of the MOS tube and multiple chips changes. Because the power supply to the multiple chips and MOS tubes, the power supply also The other components connected in series with the multiple chips supply power. Therefore, when the equivalent resistance of the MOS tube and the multiple chips changes, the partial voltage of the MOS tube and the multiple chips changes, so that the total voltage across the multiple chips Within the voltage range corresponding to the n chips, the voltage across each chip is changed, so that the voltage across each chip is within the respective operating voltage range.

In the actual application process, the circuit usually includes multiple chips. In the multiple chips, some chips are connected in series and some chips are connected in parallel. In order to make each chip work normally, multiple drivers 11 and multiple MOS tubes can be added to the circuit. Moreover, one MOS tube can correspond to one voltage domain (the voltage difference of the voltage domain is V _core ). At this time, one voltage domain includes one chip or multiple parallel chips; in addition, one MOS tube can also correspond to n voltage domains. (The voltage difference of the voltage domain is nV _core ). Each voltage domain includes n chips connected in series, or n chipsets connected in series, and each chip set includes m chips connected in parallel. Wherein, both n and m can be positive integers.

Next, the structure of the voltage equalization circuit will be described in detail with reference to FIG. 6.

6 is a schematic structural diagram of a fifth voltage equalization circuit provided by an embodiment of the present disclosure. Please refer to FIG. 6, which includes a power supply DC and multiple sets of voltage balancing circuits. Each set of voltage balancing resistors includes a driver 11, a MOS tube, and n chips in series. For each group of voltage equalization circuits, the driver 11 is respectively connected to the gate of the MOS tube and each chip, and the source and drain of the MOS tube are respectively connected to each chip.

In some possible implementation manners, the preset voltage ranges corresponding to multiple chips in each group of voltage balancing resistors may be the same.

The working process of each group of voltage balancing resistors is the same. The following will take the working process of any voltage balancing circuit as an example for description.

In the actual application process, the driver 111 can collect the voltage across the chip (IC1-1 to IC1-n) in real time. When the voltage across the chip (IC1-1 to IC1-n) is within the preset voltage range, the driver 111 does not change The voltage output to the gate of the MOS tube keeps the resistance of the MOS tube constant. When the voltage across the chip is not within the preset voltage range, the driver 11 determines the gate-source voltage of the transistor according to the preset voltage range, and outputs a new voltage to the gate of the MOS tube, so that the equivalent resistance of the MOS tube changes. After the equivalent resistance of the MOS tube changes, the equivalent resistance of the MOS tube and multiple chips (IC1-1 to IC1-n) changes. Since the chips in multiple sets of voltage equalization circuits are connected in series, when the equivalent resistance of the MOS tube and the chip (IC1-1 to IC1-n) changes, the division of the MOS tube and the chip (IC1-1 to IC1-n) The voltage changes, so that the voltage across each chip (IC1-1 to IC1-n) changes, so that the voltage across each chip (IC1-1 to IC1-n) can be within a preset voltage range.

In any of the above embodiments, when a chip fails, the driver 11 can adjust the resistance of the corresponding transistor according to the collected voltage, thereby avoiding the impact of the voltage on the other chip when a chip fails, improving the circuit Reliability.

Based on the voltage equalization circuit shown in any of the above embodiments, the method for the driver to equalize the voltage in the circuit will be described in detail below, please refer to the embodiment shown in FIG. 7.

7 is a schematic flowchart of a voltage balancing method provided by an embodiment of the present disclosure. The method is applied to a voltage equalization circuit. The voltage equalization circuit includes a driver, a variable resistance unit, and a calculation unit. The driver is connected to the variable resistance unit and the calculation unit, and the variable resistance unit is also connected to the calculation unit. Please refer to FIG. 7, the method may include:

S701. The driver obtains the voltage across the calculation unit.

Optionally, the voltage across the computing unit may be the absolute value of the difference between the voltage at one end of the computing unit and the voltage at the other end. That is, the voltage across the computing unit may be the pressure difference of the voltage across the computing unit.

In some possible implementations, the driver may obtain the first voltage at one end of the calculation unit and the second voltage at the other end of the calculation unit, and determine the voltage across the calculation unit according to the first voltage and the second voltage.

For example, the absolute value of the difference between the first voltage and the second voltage may be determined as the voltage across the calculation unit.

S702. The driver adjusts the resistance of the variable resistance unit according to the voltage across the calculation unit, so that the voltage across the calculation unit is within a preset voltage range.

In some possible implementations, the driver determines whether the voltage across the computing unit is within a preset voltage range, if it is, the driver does not adjust the resistance of the variable resistance unit, if not, the driver adjusts the variable according to the voltage across the computing unit The resistance of the resistance unit so that the voltage across the calculation unit is within a preset voltage range.

In some possible implementations, when the variable resistance unit is a transistor, the driver may determine the control terminal and the output terminal of the transistor according to the correspondence between the voltage across the calculation unit and the first voltage of the transistor and the preset voltage range Voltage, the first voltage of the transistor is the voltage between the control terminal and the output terminal of the transistor; the driver adjusts the resistance of the variable resistance unit according to the voltage between the control terminal and the output terminal of the transistor The voltage at the terminal is within the preset voltage range.

In some possible implementation manners, when the transistor is a MOS tube, the correspondence between the voltage across the calculation unit and the gate-source voltage of the MOS tube can be referred to FIG. 2 and will not be repeated here.

In the voltage equalization method provided by the embodiments of the present disclosure, the driver is connected to the variable resistance unit and the calculation unit, and the variable resistance unit is also connected to the calculation unit. The driver can collect the voltage across the calculation unit and adjust the voltage according to the voltage across the calculation unit. The resistance of the variable resistance unit is adjusted so that the voltage across the calculation unit is within a preset voltage range, thereby improving the reliability of the circuit.

8 is a schematic structural diagram of a driver provided by an embodiment of the present disclosure. The driver is applied to a voltage equalization circuit, and the voltage equalization circuit includes the driver, a variable resistance unit, and a calculation unit, and the driver is connected to the variable resistance unit and the calculation unit, respectively, and the variable resistance unit It is also connected to the calculation unit, wherein the driver 11 includes an acquisition module 111 and an adjustment module 112, wherein,

The obtaining module 111 is configured to obtain the voltage across the calculation unit;

The adjustment module 112 is configured to adjust the resistance of the variable resistance unit according to the voltage across the calculation unit, so that the voltage across the calculation unit is within a preset voltage range.

The driver shown in the embodiment of the present disclosure can execute the technical solution shown in the embodiment of FIG. 7, and its implementation principles and beneficial effects are similar, and will not be repeated here.

In a possible implementation manner, the adjustment module 112 is specifically configured to:

Determine whether the voltage across the calculation unit is within the preset voltage range;

When the voltage across the calculation unit is not within the preset voltage range, adjust the resistance of the variable resistance unit according to the voltage across the calculation unit, so that the voltage across the calculation unit is within the preset voltage range Inside.

In a possible implementation manner, the variable resistance unit is a transistor, and the adjustment module is specifically used to:

Determine the voltage between the control terminal and the output terminal of the transistor according to the correspondence between the voltage across the computing unit and the first voltage of the transistor and the preset voltage range, the first voltage of the transistor being the control terminal of the transistor And the output voltage;

The resistance of the variable resistance unit is adjusted according to the voltage between the control terminal and the output terminal of the transistor, so that the voltage across the calculation unit is within a preset voltage range.

In some possible implementations, the chip in the computing unit 13 may generally be an AI (Artificial Intelligence) processing chip, a digital credential processing chip, an ASIC (Application Specific Integrated Circuit) chip, etc. Any limitation.

An embodiment of the present disclosure also provides a circuit board, including the voltage equalization circuit shown in the above embodiment.

It should be noted that the circuit board may generally include one or more than two sets of voltage equalization circuits, which is not limited in any way.

An embodiment of the present disclosure also provides a supercomputing device, including the circuit board shown in the above embodiment.

In some possible implementations, the supercomputing device may generally include one or more than two circuit boards to serve as an arithmetic board or a computing power board in the supercomputing device.

It should be noted that the supercomputing device can generally be an AI supercomputing device, a digital certificate supercomputing device, etc., and there is no limitation on this.

An embodiment of the present disclosure also provides a computer-readable storage medium that stores computer-executable instructions that are configured to perform the above-described voltage balancing method.

An embodiment of the present disclosure also provides a computer program product. The computer program product includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by a computer, the The computer executes the voltage balancing method described above.

The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

An embodiment of the present disclosure also provides an electronic device, whose structure is shown in FIG. 9, the electronic device includes:

At least one processor (processor) 901, one processor 902 is taken as an example in FIG. 9; and the memory (memory) 902 may further include a communication interface (Communication Interface) 903 and a bus 904. The processor 901, the communication interface 903, and the memory 902 can complete communication with each other through the bus 904. The communication interface 903 can be used for information transmission. The processor 901 may call logic instructions in the memory 902 to perform the voltage balancing method of the above embodiment.

In addition, the logic instructions in the aforementioned memory 902 may be implemented in the form of software functional units and sold or used as an independent product, and may be stored in a computer-readable storage medium.

The memory 902 is a computer-readable storage medium that can be used to store software programs and computer-executable programs, such as program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 901 executes functional applications and data processing by running software programs, instructions, and modules stored in the memory 902, that is, implementing the voltage balancing method in the foregoing method embodiments.

The memory 902 may include a storage program area and a storage data area, where the storage program area may store an operating system and application programs required by at least one function; the storage data area may store data created according to the use of a terminal device, and the like. In addition, the memory 902 may include a high-speed random access memory, and may also include a non-volatile memory.

The technical solutions of the embodiments of the present disclosure may be embodied in the form of software products, which are stored in a storage medium and include one or more instructions to make a computer device (which may be a personal computer, server, or network) Equipment, etc.) to perform all or part of the steps of the method described in the embodiments of the present disclosure. The aforementioned storage medium may be a non-transitory storage medium, including: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk, etc. A medium that can store program codes may also be a transient storage medium.

When used in this disclosure, although the terms "first", "second", etc. may be used in this disclosure to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without changing the meaning of the description, the first element can be called the second element, and likewise, the second element can be called the first element, as long as all occurrences of the "first element" are consistently renamed and all occurrences of The "second component" can be renamed consistently. The first element and the second element are both elements, but they may not be the same element.

The terms used in this disclosure are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "said" are intended to include plural forms as well . Similarly, the term "and/or" as used in this disclosure is meant to include any and all possible combinations of one or more associated lists. In addition, when used in this disclosure, the term "comprise" and its variations "comprises" and/or includes etc. refer to the stated features, wholes, steps, operations, elements, and/or The presence of components does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and/or groups of these.

The various aspects, implementations, implementations or features in the described embodiments can be used alone or in any combination. Various aspects in the described embodiments may be implemented by software, hardware, or a combination of software and hardware. The described embodiments may also be embodied by a computer-readable medium that stores computer-readable code including instructions executable by at least one computing device. The computer-readable medium can be associated with any data storage device capable of storing data, which can be read by a computer system. Computer-readable media used for examples may include read-only memory, random access memory, CD-ROM, HDD, DVD, magnetic tape, optical data storage devices, and the like. The computer-readable medium may also be distributed in computer systems connected through a network, so that computer-readable codes can be stored and executed in a distributed manner.

The above technical description may refer to the accompanying drawings, which form a part of the present disclosure, and the description shows an implementation according to the described embodiments in the drawings. Although these embodiments are described in sufficient detail to enable those skilled in the art to implement these embodiments, these embodiments are non-limiting; so that other embodiments can be used without departing from the scope of the described embodiments Changes can also be made under circumstances. For example, the sequence of operations described in the flowchart is non-limiting, so the sequence of two or more operations explained in the flowchart and described according to the flowchart may be changed according to several embodiments. As another example, in several embodiments, one or more operations illustrated in the flowchart and described in accordance with the flowchart are optional or may be deleted. In addition, certain steps or functions may be added to the disclosed embodiments, or two or more steps may be replaced in sequence. All these changes are considered to be included in the disclosed embodiments and claims.

In addition, terminology is used in the above technical description to provide a thorough understanding of the described embodiments. However, no excessively detailed details are required to implement the described embodiments. Therefore, the above description of the embodiments is presented for explanation and description. The embodiments presented in the above description and the examples disclosed in accordance with these embodiments are provided separately to add context and help to understand the described embodiments. The above description is not intended to be without omission or to limit the described embodiments to the precise form of this disclosure. Based on the above teachings, several modifications, choices and changes are possible. In some cases, well-known processing steps are not described in detail to avoid unnecessarily affecting the described embodiments.

Claims

A voltage equalization circuit is characterized by comprising: a driver, a variable resistance unit and a calculation unit, the driver is respectively connected to the variable resistance unit and the calculation unit, the variable resistance unit is also connected to the The computing unit is connected, where,

The driver is used to collect the voltage across the calculation unit, and adjust the resistance of the variable resistance unit according to the voltage across the calculation unit, so that the voltage across the calculation unit is within a preset voltage range.
The voltage equalization circuit according to claim 1, wherein the circuit further comprises a power supply, the power supply is connected to the variable resistance unit and the calculation unit, and the power supply is used to supply the variable resistance The unit and the computing unit are powered.
The voltage equalization circuit according to claim 1, wherein the variable resistance unit is a transistor.
The voltage equalization circuit according to claim 3, wherein a control terminal of the transistor is connected to the driver, and an input terminal and an output terminal of the transistor are respectively connected to both ends of the calculation unit.
The voltage equalization circuit according to claim 1, wherein the variable resistance unit is a transistor or a field effect transistor.
The voltage equalization circuit according to any one of claims 1 to 5, wherein the calculation unit includes a chip.
The voltage equalization circuit according to any one of claims 1 to 5, wherein the calculation unit includes at least two chips connected in parallel.
The voltage equalization circuit according to any one of claims 1 to 5, wherein the calculation unit includes at least two chips connected in series.
The voltage equalization circuit according to any one of claims 1 to 5, wherein the calculation unit includes at least two chipsets connected in parallel, and each chipset includes at least two chips connected in series.
The voltage balancing circuit according to any one of claims 1-9, characterized in that

The driver is specifically configured to adjust the resistance of the variable resistance unit according to the voltage across the calculation unit when the driver determines that the voltage across the calculation unit is outside the preset voltage range.
The voltage equalization circuit according to any one of claims 1-10, wherein

The driver is specifically configured to determine a driving signal according to the voltage across the calculation unit and the preset voltage range, and adjust the resistance of the variable resistance unit according to the driving signal.
The voltage equalization circuit according to claim 11, wherein the variable resistance unit is a transistor, and the drive signal is a voltage signal between a control terminal and an output terminal of the transistor.
A circuit board, characterized by comprising the voltage equalization circuit according to any one of claims 1 to 12.
A supercomputing device, characterized by comprising the circuit board according to claim 13.
A voltage equalization method is characterized in that it is applied to a voltage equalization circuit. The voltage equalization circuit includes a driver, a variable resistance unit, and a calculation unit, and the driver is connected to the variable resistance unit and the calculation unit, The variable resistance unit is also connected to the calculation unit, wherein the method includes:

The driver obtains the voltage across the calculation unit;

The driver adjusts the resistance of the variable resistance unit according to the voltage across the calculation unit, so that the voltage across the calculation unit is within a preset voltage range.
The method according to claim 15, wherein the driver adjusts the resistance of the variable resistance unit according to the voltage across the calculation unit, so that the voltage across the calculation unit is within a preset voltage range, include:

The driver determines whether the voltage across the calculation unit is within the preset voltage range;

When the voltage across the calculation unit is not within the preset voltage range, the driver adjusts the resistance of the variable resistance unit according to the voltage across the calculation unit, so that the voltage across the calculation unit is Set voltage range.
The method according to claim 15 or 16, wherein the variable resistance unit is a transistor, and the driver adjusts the resistance of the variable resistance unit according to the voltage across the calculation unit to enable the calculation The voltage across the unit is within the preset voltage range, including:

The driver determines the voltage between the control terminal and the output terminal of the transistor according to the correspondence between the voltage across the computing unit and the first voltage of the transistor and the preset voltage range, the first voltage of the transistor is a transistor The voltage between the control terminal and the output terminal;

The driver adjusts the resistance of the variable resistance unit according to the voltage between the control terminal and the output terminal of the transistor, so that the voltage across the calculation unit is within a preset voltage range.
A driver is characterized in that it is applied to a voltage equalization circuit including the driver, a variable resistance unit and a calculation unit, and the driver is connected to the variable resistance unit and the calculation unit, The variable resistance unit is also connected to the calculation unit, wherein the driver includes an acquisition module and an adjustment module, wherein,

The obtaining module is used to obtain the voltage across the computing unit;

The adjustment module is used to adjust the resistance of the variable resistance unit according to the voltage across the calculation unit, so that the voltage across the calculation unit is within a preset voltage range.
The driver according to claim 18, wherein the adjustment module is specifically used to:

Determine whether the voltage across the calculation unit is within the preset voltage range;

When the voltage across the calculation unit is not within the preset voltage range, adjust the resistance of the variable resistance unit according to the voltage across the calculation unit, so that the voltage across the calculation unit is within the preset voltage range Inside.
The driver according to claim 18 or 19, wherein the variable resistance unit is a transistor, and the adjustment module is specifically used to:

Determine the voltage between the control terminal and the output terminal of the transistor according to the correspondence between the voltage across the computing unit and the first voltage of the transistor and the preset voltage range, the first voltage of the transistor being the control terminal of the transistor And the output voltage;

The resistance of the variable resistance unit is adjusted according to the voltage between the control terminal and the output terminal of the transistor, so that the voltage across the calculation unit is within a preset voltage range.
An electronic device, characterized in that it includes:

At least one processor; and

A memory communicatively connected to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, causes the at least one processor to perform the method of any one of claims 15-17 .
A computer-readable storage medium, characterized in that computer-executable instructions are stored, and the computer-executable instructions are configured to perform the method of any one of claims 15-17.
A computer program product, characterized in that the computer program product includes a computer program stored on a computer-readable storage medium, and the computer program includes program instructions, which when executed by a computer causes Performing the method of any of claims 15-17.