CN112889198B - Voltage equalization circuit, voltage equalization method and equipment - Google Patents
Voltage equalization circuit, voltage equalization method and equipment Download PDFInfo
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- CN112889198B CN112889198B CN201880098300.4A CN201880098300A CN112889198B CN 112889198 B CN112889198 B CN 112889198B CN 201880098300 A CN201880098300 A CN 201880098300A CN 112889198 B CN112889198 B CN 112889198B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
Abstract
A voltage equalization circuit, a voltage equalization method and a device, the voltage equalization circuit comprising: the device comprises a driver (11), a variable resistance unit (12) and a calculation unit (13), wherein the driver (11) is respectively connected with the variable resistance unit (12) and the calculation unit (13), the variable resistance unit (12) is further connected with the calculation unit (13), the driver (11) is used for collecting voltages at two ends of the calculation unit (13) and adjusting the resistance of the variable resistance unit (12) according to the voltages at two ends of the calculation unit (13), so that the voltages at two ends of the calculation unit (13) are within a preset voltage range. The method and the device improve the reliability of the circuit.
Description
Technical Field
The present disclosure relates to the field of circuit technologies, and in particular, to a voltage equalization circuit, a voltage equalization method, and a device.
Background
Conventionally, a circuit is generally provided with a plurality of components (for example, chips) in which some of the components are connected in parallel and some of the components are connected in series.
In practical applications, the same power supply may supply power to the multiple components, and when the same power supply supplies power to multiple components connected in series, the voltage shared by each component may be different from the voltage actually required by the component, so that the component may not work normally. For example, when the voltage actually shared by a component is less than the starting voltage of the component, the component cannot start to operate, and when the voltage actually shared by the component is greater than the maximum sustainable voltage of the component, the component may be burned out. As can be seen from the above, the reliability of the circuit in the prior art is poor.
Disclosure of Invention
The present disclosure provides a voltage equalization circuit, a voltage equalization method, and a device, which improve reliability of a circuit.
In a first aspect, an embodiment of the present disclosure provides a voltage equalization circuit, including: a driver, a variable resistance unit and a calculation unit, the driver being connected to the variable resistance unit and the calculation unit, respectively, the variable resistance unit being further connected to the calculation unit, wherein,
in a second aspect, an embodiment of the present disclosure provides a circuit board, including the voltage equalization circuit described in the first aspect.
In a third aspect, the present disclosure provides a supercomputing apparatus including the circuit board described in the second aspect.
In a fourth aspect, an embodiment of the present disclosure provides a voltage equalization method applied to a voltage equalization circuit, where the voltage equalization circuit includes a driver, a variable resistance unit, and a calculation unit, the driver is connected to the variable resistance unit and the calculation unit, and the variable resistance unit is further connected to the calculation unit, where the method includes:
the driver acquires the voltage at two ends of the computing unit;
the driver adjusts the resistance of the variable resistance unit according to the voltage at the two ends of the computing unit so that the voltage at the two ends of the computing unit is within a preset voltage range.
In a fifth aspect, the disclosed embodiments provide a driver, which is applied to a voltage equalization circuit, where the voltage equalization circuit includes the driver, a variable resistance unit, and a calculation unit, the driver is connected to the variable resistance unit and the calculation unit, respectively, and the variable resistance unit is further connected to the calculation unit, where the driver includes an acquisition module and an adjustment module, where,
the acquisition module is used for acquiring the voltage at two ends of the calculation unit;
the adjusting module is used for adjusting the resistance of the variable resistance unit according to the voltage at the two ends of the calculating unit so as to enable the voltage at the two ends of the calculating unit to be within a preset voltage range.
In a sixth aspect, an embodiment of the present disclosure provides an electronic device, including:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein, the first and the second end of the pipe are connected with each other,
the memory stores instructions executable by the at least one processor, which when executed by the at least one processor, cause the at least one processor to perform the method of the fourth aspect.
In a seventh aspect, an embodiment of the present disclosure provides a computer-readable storage medium, where computer-executable instructions are stored, and the computer-executable instructions are configured to perform the method described in the fourth aspect.
In an eighth aspect, the disclosed embodiments provide a computer program product, wherein the computer program product comprises a computer program stored on a computer-readable storage medium, the computer program comprising program instructions that, when executed by a computer, cause the computer to perform the method of the fourth aspect.
The voltage equalization circuit comprises a driver, a variable resistance unit and a calculation unit, wherein the driver is respectively connected with the variable resistance unit and the calculation unit, the variable resistance unit is also connected with the calculation unit, the driver is used for collecting voltages at two ends of the calculation unit and adjusting the resistance of the variable resistance unit according to the voltages at the two ends of the calculation unit, so that the voltages at the two ends of the calculation unit are within a preset voltage range, and the reliability of the circuit is further improved.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the accompanying drawings and not in limitation thereof, in which elements having the same reference numeral designations are shown as like elements and not in limitation thereof, and wherein:
fig. 1 is a schematic structural diagram of a first voltage equalization circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a voltage correspondence relationship provided by the embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a second voltage equalization circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a third voltage equalization circuit according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a fourth voltage equalization circuit provided in the embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a fifth voltage equalization circuit according to an embodiment of the present disclosure;
fig. 7 is a schematic flow chart of a voltage equalization method according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a driver provided in an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.
Detailed Description
So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.
In a circuit including a plurality of computing units (e.g., chips, etc.), normally, the computing units are guaranteed to operate properly when the voltages across the computing units are balanced (the voltage across the components is within a predetermined voltage range). In order to equalize voltages at two ends of a computing unit in a circuit, the embodiment of the disclosure provides a voltage equalization circuit, in which a driver and a variable resistance unit may be disposed, and the driver adjusts the resistance of the variable resistance unit to make the voltages at two ends of the computing unit in the voltage equalization circuit within a preset voltage range, thereby improving the reliability of the circuit.
Hereinafter, the technical means shown in the present disclosure will be described in detail by specific examples. The following embodiments may exist alone or in combination with one another, and the description of the same or similar matters will not be repeated in different embodiments.
Fig. 1 is a schematic structural diagram of a first voltage equalization circuit according to an embodiment of the present disclosure. Referring to fig. 1, the voltage equalization circuit may include: the driver 11 is connected with the variable resistance unit 12 and the calculation unit 13, the variable resistance unit 12 is further connected with the calculation unit 13, wherein the driver 11 is used for collecting voltages at two ends of the calculation unit 13, and adjusting the resistance (i.e., equivalent resistance) of the variable resistance unit 12 according to the voltages at two ends of the calculation unit 13, so that the voltages at two ends of the calculation unit 13 are within a preset voltage range.
In some possible embodiments, the driver 11 may further collect the current flowing through the calculating unit 13, and adjust the resistance of the variable resistance unit 12 according to the current flowing through the calculating unit 13, so that the voltage across the calculating unit 13 is within a preset voltage range, which is not limited in any way.
In some possible embodiments, the driver 11 may be generally any driving device capable of implementing voltage acquisition and adjusting the resistance of the variable resistance unit 12, and the implementation manner thereof may also include a hardware implementation manner and a software implementation manner. When the driver 11 is implemented in a hardware implementation manner, the driver 11 may be a driving circuit, a controller, a Processor, a CPU (Central Processing Unit), an MCU (micro controller Unit), an AP (Application Processor), or the like, as long as the voltage across the calculating Unit 13 can be acquired and the actual equivalent resistance of the variable resistance Unit 12 can be adjusted; when the driver 11 is implemented as a software implementation, the driver 11 may be generally a software code or a program code, which is not limited in this respect by the embodiments of the present disclosure.
In some possible embodiments, the variable resistance unit 12 may be a transistor.
For example, the Transistor may be a MOS (Metal Oxide Semiconductor), such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The transistor may also be a transistor, such as an NPN-type transistor, a PNP-type transistor, and the like.
In some possible embodiments, the computing unit 13 may be a chip or the like.
The computing unit 13 may also be a controller, a processor, or other components in a chip, such as a computing core, a processing core, and the like in the chip, which is not specifically limited in this disclosure.
In some possible embodiments, the computing unit 13 has a corresponding preset voltage range, which may also be referred to as an operating voltage range of the computing unit 13.
It should be noted that the preset voltage range can be flexibly set according to actual situations, for example, the preset voltage range can be set to 0.8V, 1V, 1.5V, 2V, or 2.5V, and the like, which is not limited in any way.
For example, when the calculating unit 13 is a chip in an operation board of a super-calculating device, the predetermined voltage range may be a normal range of core voltage of the chip, such as 0.8V or 1.5V, which is not described herein again.
In practical applications, when the voltage across the computing unit 13 is within the preset voltage range, the computing unit 13 can work normally. When the voltage across the computing unit 13 is not within the preset voltage range, the computing unit 13 cannot work normally.
For example, when the voltage across the calculation unit 13 is less than the minimum voltage in the preset voltage range, the calculation unit 13 may not start the operation. When the voltage across the computing unit 13 is greater than the maximum voltage in the preset voltage range, the computing unit 13 may be burned out.
In one possible embodiment, the drivers 11 may be connected to both ends of the computing unit 13.
During the operation of the voltage balancing circuit, the driver 11 may collect the voltage across the computing unit 13, and adjust the resistance of the variable resistance unit 12 according to the voltage across the computing unit 13. Since the variable resistance unit 12 is connected to the calculation unit 13, a change in the resistance of the variable resistance unit 12 affects a change in the voltage across the calculation unit 13. In the process of adjusting the resistance of the variable resistance unit 12 by the driver 11, when the driver 11 detects that the voltage across the computing unit 13 is within the preset voltage range, the driver 11 suspends adjusting the resistance of the variable resistance unit 12, so that the resistance of the variable resistance unit 12 is kept unchanged, further the voltage across the computing unit 13 is kept unchanged, and the voltage across the computing unit 13 is within the preset voltage range.
In some possible embodiments, after the driver 11 acquires the voltage across the computing unit 13, the driver 11 may first determine whether the voltage across the computing unit 13 is within a preset voltage range. When the voltage across the calculation unit 13 is in the preset voltage range, the driver 11 does not adjust the resistance of the variable resistance unit 12, i.e., does nothing. When the voltage across the computing unit 13 is not within the preset voltage range, the driver 11 adjusts the resistance of the variable resistance unit 12 again
In some possible embodiments, the driver 11 may determine the driving signal according to the voltage across the calculating unit 13 and a preset voltage range, and adjust the resistance of the variable resistance unit 12 according to the driving signal, so that the voltage across the calculating unit 13 is within the preset voltage range.
Alternatively, when the variable resistance unit 12 is a transistor, the driving signal may be a voltage signal between a control terminal and an output terminal (or an input terminal) of the transistor.
Alternatively, a corresponding relationship between the voltage at the two ends of the calculating unit 13 and the first voltage of the transistor (the voltage between the control end and the output end of the transistor, or the voltage between the control end and the input end of the transistor) may be preset, and the driver 11 may determine the voltage between the control end and the output end of the transistor according to a preset voltage range and the corresponding relationship.
For example, when the transistor is a MOS transistor, the corresponding relationship may be a corresponding relationship between a voltage across the computing unit 13 and a gate-source voltage of the MOS transistor (a voltage between a gate and a source of the MOS transistor), for example, V core And V GS A voltage in between; when the transistor is a triode, the correspondence relationship may be a correspondence relationship between a voltage across the calculation unit 13 and a base-emitter voltage of the triode (a voltage between the base and the emitter of the triode).
For example, if the variable resistance unit 12 is a MOS transistor and the calculating unit 13 is a chip, the corresponding relationship between the voltage across the calculating unit 13 and the variable voltage of the variable resistance unit 12 may be the corresponding relationship between the voltage across the chip and the gate-source voltage of the MOS transistor, which may be specifically as shown in fig. 2.
Referring to fig. 2, the horizontal axis represents the voltage across the computing unit 13 (i.e., the chip), and the vertical axis represents the gate-source voltage of the MOS transistor, V off Is the turn-off voltage of the MOS tube.
It should be noted that, when the computing unit is formed by serially connecting a plurality of chips, the voltage across the computing unit may also be the voltage across the plurality of chips connected in series, such as nV core (n is the number of chips connected in series), which will not be described in detail.
As can be seen from fig. 2, the larger the gate-source voltage of the MOS transistor is, the smaller the voltage across the calculation unit 13 is. Therefore, when the voltage across the computing unit 13 needs to be reduced, the gate-source voltage of the MOS transistor can be increased, so that the equivalent resistance of the MOS transistor is increased, the equivalent resistance of the computing unit 13 and the MOS transistor is reduced, and the reduction of the voltage across the computing unit 13 is reduced.
When the voltage across the computing unit 13 needs to be increased, the gate-source voltage of the MOS transistor needs to be decreased. However, in practical applications, since the actual voltage is only decreased and not increased after the MOS transistors are connected in parallel, the voltages at two ends of the other calculating units 13 (overvoltage other calculating units) connected in series with the calculating unit 13 can be adjusted at this time, so that the calculating unit 13 on the whole link is within the normal voltage range.
Fig. 2 illustrates the correspondence between the voltage across the computing unit 13 and the gate-source voltage of the MOS transistor by way of example only, and the correspondence is not limited.
The voltage equalization circuit provided by the embodiment of the disclosure comprises a driver 11, a variable resistance unit 12 and a calculation unit 13, wherein the driver 11 is respectively connected with the variable resistance unit 12 and the calculation unit 13, the variable resistance unit 12 is further connected with the calculation unit 13, the driver 11 is used for collecting voltages at two ends of the calculation unit 13 and adjusting the resistance of the variable resistance unit 12 according to the voltages at two ends of the calculation unit 13, so that the voltages at two ends of the calculation unit 13 are within a preset voltage range, and the reliability of the circuit is further improved.
On the basis of the embodiment shown in fig. 1, in some possible implementations, the voltage equalization circuit may further include a power supply connected to the variable resistance unit 12 and the calculation unit 13, and configured to supply power to the variable resistance unit 12 and the calculation unit 13.
In some possible embodiments, the variable resistance unit 12 may be a MOS transistor. The gate of the MOS transistor is connected to the driver 11, and the source and the drain of the MOS transistor are respectively connected to the computing unit 13.
Alternatively, the calculation unit 13 may include one chip. Alternatively, the calculation unit 13 may comprise at least two chips connected in parallel. Alternatively, the calculation unit 13 may comprise at least two chips connected in series. Alternatively, the computing unit 13 may include at least two series-parallel chip sets, each chip set including at least two chips connected in series.
The three cases will be described in detail below with reference to fig. 3 to 5, taking the variable resistance unit 12 as a MOS transistor as an example.
Fig. 3 is a schematic structural diagram of a second voltage equalization circuit according to an embodiment of the present disclosure. Referring to fig. 3, the variable resistance unit 12 is a MOS transistor, and the calculating unit 13 is a chip IC. The driver 11 is respectively connected with the grid electrode of the MOS tube and the chip, and the source electrode and the drain electrode of the MOS tube are respectively connected with the chip.
In some possible embodiments, the drivers 11 are connected to both ends of the chip, respectively.
In some possible embodiments, the source of the MOS transistor is connected to one end of the chip, and the drain of the MOS transistor is connected to the other end of the chip.
In the practical application process, the driver 11 can acquire the voltages at the two ends of the chip in real time, when the voltages at the two ends of the chip are within a preset voltage range, the driver 11 does not perform any operation, the MOS is equivalent to an open circuit, and the equivalent resistance is infinite.
When the voltages at the two ends of the chip are not within the preset voltage range, the driver 11 determines the gate-source voltage of the MOS transistor according to the preset voltage range, and outputs a new voltage to the gate of the MOS transistor, so that the MOS transistor works in the variable resistance region, the equivalent resistance of the MOS transistor changes, and after the equivalent resistance of the MOS transistor changes, the equivalent resistance of the MOS transistor and the chip connected in parallel changes accordingly, which can change the voltages at the two ends of the chip until the voltages at the two ends of the chip are within the preset voltage range.
It should be noted that, at this time, the gate-source voltage output to the MOS transistor by the driver 11 needs to be kept constant to ensure that the voltage across the chip is continuously within the preset voltage range.
Fig. 4 is a schematic structural diagram of a third voltage equalization circuit according to an embodiment of the disclosure. Referring to fig. 4, the variable resistance unit 12 is a MOS transistor, and the computing unit 13 includes a plurality of parallel chips (IC 1, IC2, i.e., ICn). The driver 11 is respectively connected with the grid electrode of the MOS tube and each chip, and the source electrode and the drain electrode of the MOS tube are respectively connected with each chip.
In some possible embodiments, the driver 11 may be connected to both ends of each chip in the computing unit 13. Alternatively, the driver 11 may be connected to both ends of any one or more chips in the calculation unit 13.
In some possible embodiments, the source of the MOS transistor is connected to one end of each chip, and the drain of the MOS transistor is connected to the other end of each chip.
In some possible embodiments, the preset voltage ranges corresponding to the plurality of parallel chips included in the calculating unit 13 may be the same.
In the practical application process, the driver 11 can acquire the voltages at the two ends of the chip in real time, and when the voltages at the two ends of the chip are within the preset voltage range, the driver 11 does not change the voltage output to the gate of the MOS transistor, so that the resistance of the MOS transistor is kept constant. When the voltage at the two ends of the chip is not in the preset voltage range, the driver 11 determines the gate-source voltage of the MOS transistor according to the preset voltage range, and outputs a new voltage to the gate of the MOS transistor, so that the equivalent resistance of the MOS transistor changes, and after the equivalent resistance of the MOS transistor changes, the equivalent resistance of the MOS transistor and the chips changes.
Fig. 5 is a schematic structural diagram of a fourth voltage equalization circuit according to an embodiment of the present disclosure. Referring to fig. 5, the variable resistance unit 12 is a transistor, and the calculating unit 13 includes a plurality of chips (IC 1, IC2, i.e., ICn) connected in series. The driver 11 is respectively connected with the grid electrode of the MOS tube and a plurality of chips connected in series, and the source electrode and the drain electrode of the MOS tube are respectively connected with each chip.
In some possible embodiments, one end of the driver 11 is connected to the first chip (e.g., IC 1) in the computing unit 13, and the other end of the driver 11 is connected to the last chip (e.g., ICn) in the computing unit 13.
In some possible embodiments, the drain of the MOS transistor is connected to the first chip (e.g., IC 1) in the computing unit 13, and the source of the transistor is connected to the last chip (e.g., ICn) in the computing unit 13.
In an actual application process, the driver 11 may collect voltages at two ends of n chips (a sum of voltages at two ends of each chip in the n chips) in real time, and when the voltages at two ends of the n chips are within a voltage range corresponding to the n chips, the voltages at two ends of each chip in the n chips are usually within a respective working voltage range, that is, each chip in the n chips can normally work, in which case, the driver 11 does not change the voltage output to the gate of the MOS transistor, so that the resistance of the MOS transistor is kept constant. When the voltages at the two ends of the n chips are not in the voltage range corresponding to the n chips, the driver 11 determines the gate-source voltage of the MOS transistor according to the voltage range corresponding to the n chips, and outputs a new voltage to the gate of the MOS transistor, so that the equivalent resistance of the MOS transistor changes, and after the equivalent resistance of the MOS transistor changes, the equivalent resistance of the MOS transistor and the chips changes.
In practical applications, the circuit usually includes a plurality of chips, and some of the chips are connected in series and some of the chips are connected in parallel. In order to enable each chip to work normally, a plurality of drivers 11 and a plurality of MOS transistors may be added to the circuit. Moreover, one MOS transistor can correspond to one voltage domain (the voltage difference of the voltage domain is V) core ) At this time, one voltage domain includes 1 chip or a plurality of chips connected in parallel; in addition, one MOS tube can also correspond to n voltage domains (the voltage difference of the voltage domains is nV) core ) Each voltage domain comprises n chips connected in series, or n chip groups connected in series, each chip group comprises m chips connected in parallel. Wherein n and m can be positive integers.
Next, the structure of the voltage equalization circuit will be described in detail with reference to fig. 6.
Fig. 6 is a schematic structural diagram of a fifth voltage equalization circuit according to an embodiment of the present disclosure. Referring to fig. 6, the voltage balancing circuit includes a power supply DC and a plurality of groups of voltage balancing circuits, each group of voltage balancing resistors includes a driver 11, a MOS transistor and n chips connected in series. For each group of voltage equalization circuits, the driver 11 is respectively connected with the grid electrode of the MOS tube and each chip, and the source electrode and the drain electrode of the MOS tube are respectively connected with each chip.
In some possible embodiments, the preset voltage ranges corresponding to the plurality of chips in each group of voltage balancing resistors may be the same.
The working process of each group of voltage balancing resistors is the same, and the working process of any one voltage balancing circuit is taken as an example for explanation.
In the practical application process, the driver 111 may collect the voltages at the two ends of the chips (IC 1-1 to IC 1-n) in real time, and when the voltages at the two ends of the chips (IC 1-1 to IC 1-n) are within the preset voltage range, the driver 111 does not change the voltage output to the gate of the MOS transistor, so that the resistance of the MOS transistor is kept constant. When the voltage at the two ends of the chip is not in the preset voltage range, the driver 11 determines the gate-source voltage of the triode according to the preset voltage range and outputs new voltage to the gate of the MOS tube, so that the equivalent resistance of the MOS tube is changed, and after the equivalent resistance of the MOS tube is changed, the equivalent resistance of the MOS tube and the plurality of chips (IC 1-1 to IC 1-n) is changed. Due to the fact that the chips in the multiple groups of voltage equalizing circuits are connected in series, when equivalent resistances of the MOS tube and the chips (IC 1-1 to IC 1-n) are changed, partial voltages of the MOS tube and the chips (IC 1-1 to IC 1-n) are changed, and then voltages at two ends of each chip (IC 1-1 to IC 1-n) are changed, so that voltages at two ends of each chip (IC 1-1 to IC 1-n) can be within a preset voltage range.
In any of the above embodiments, when one chip fails, the driver 11 may adjust the resistance of the corresponding transistor according to the acquired voltage, thereby avoiding the influence on the voltages at the two ends of other chips when one chip fails, and improving the reliability of the circuit.
On the basis of the voltage equalization circuit shown in any of the above embodiments, a method for equalizing the voltage in the circuit by the driver will be described in detail below, with reference to the embodiment shown in fig. 7.
Fig. 7 is a schematic flow chart of a voltage equalization method according to an embodiment of the present disclosure. The method is applied to a voltage equalization circuit, the voltage equalization circuit comprises a driver, a variable resistance unit and a calculation unit, the driver is respectively connected with the variable resistance unit and the calculation unit, and the variable resistance unit is also connected with the calculation unit. Referring to fig. 7, the method may include:
s701, the driver acquires voltages at two ends of the computing unit.
Alternatively, the voltage across the computing unit may be an absolute value of a difference between the voltage at one end of the computing unit and the voltage at the other end. That is, the voltage across the computing unit may be the voltage difference across the computing unit.
In some possible embodiments, the driver may obtain a first voltage at one end of the computing unit and a second voltage at the other end of the computing unit, and determine the voltage across the computing unit from the first voltage and the second voltage.
For example, the absolute value of the difference of the first voltage and the second voltage may be determined as the voltage across the calculation unit.
S702, the driver adjusts the resistance of the variable resistance unit according to the voltage at the two ends of the calculation unit, so that the voltage at the two ends of the calculation unit is within a preset voltage range.
In some possible embodiments, the driver determines whether the voltage across the computing unit is within a preset voltage range, if so, the driver does not adjust the resistance of the variable resistance unit, and if not, the driver adjusts the resistance of the variable resistance unit according to the voltage across the computing unit, so that the voltage across the computing unit is within the preset voltage range.
In some possible embodiments, when the variable resistance unit is a transistor, the driver may determine a voltage between the control terminal and the output terminal of the transistor according to a correspondence between a voltage across the calculation unit and a first voltage of the transistor, which is a voltage between the control terminal and the output terminal of the transistor, and a preset voltage range; and the driver adjusts the resistance of the variable resistance unit according to the voltage between the control end and the output end of the transistor, so that the voltage at the two ends of the calculation unit is in a preset voltage range.
In some possible embodiments, when the transistor is an MOS transistor, reference may be made to fig. 2 for a corresponding relationship between voltages at two ends of the computing unit and a gate-source voltage of the MOS transistor, and details are not repeated here.
According to the voltage balancing method provided by the embodiment of the disclosure, the driver is respectively connected with the variable resistance unit and the calculation unit, the variable resistance unit is also connected with the calculation unit, the driver can collect voltages at two ends of the calculation unit, and the resistance of the variable resistance unit is adjusted according to the voltages at the two ends of the calculation unit, so that the voltages at the two ends of the calculation unit are within a preset voltage range, and the reliability of the circuit is further improved.
Fig. 8 is a schematic structural diagram of a driver according to an embodiment of the disclosure. The driver is applied to a voltage equalization circuit, the voltage equalization circuit comprises the driver, a variable resistance unit and a calculation unit, the driver is respectively connected with the variable resistance unit and the calculation unit, the variable resistance unit is also connected with the calculation unit, wherein the driver 11 comprises an acquisition module 111 and an adjustment module 112, wherein,
the obtaining module 111 is configured to obtain voltages at two ends of the computing unit;
the adjusting module 112 is configured to adjust the resistance of the variable resistance unit according to the voltage across the computing unit, so that the voltage across the computing unit is within a preset voltage range.
The driver shown in the embodiment of the present disclosure may implement the technical solution shown in the embodiment of fig. 7, and the implementation principle and the beneficial effects are similar, which are not described herein again.
In a possible implementation, the adjusting module 112 is specifically configured to:
judging whether the voltages at two ends of the computing unit are within the preset voltage range or not;
and when the voltage at the two ends of the calculation unit is not in the preset voltage range, adjusting the resistance of the variable resistance unit according to the voltage at the two ends of the calculation unit so as to enable the voltage at the two ends of the calculation unit to be in the preset voltage range.
In a possible implementation manner, the variable resistance unit is a transistor, and the adjusting module is specifically configured to:
determining the voltage between the control end and the output end of the transistor according to the corresponding relation between the voltages at the two ends of the computing unit and the first voltage of the transistor and the preset voltage range, wherein the first voltage of the transistor is the voltage between the control end and the output end of the transistor;
and adjusting the resistance of the variable resistance unit according to the voltage between the control end and the output end of the transistor, so that the voltage at two ends of the calculation unit is in a preset voltage range.
The driver shown in the embodiment of the present disclosure may implement the technical solution shown in the embodiment of fig. 7, and the implementation principle and the beneficial effect are similar, which are not described herein again.
In some possible embodiments, the chip in the computing unit 13 may be an AI (Artificial Intelligence) processing chip, a digital certificate processing chip, an ASIC (Application Specific Integrated Circuit) chip, and the like, which is not limited in any way.
The embodiment of the disclosure also provides a circuit board which comprises the voltage balancing circuit shown in the embodiment.
It should be noted that, the circuit board may generally include one or more than two sets of voltage equalization circuits, which is not limited in any way.
The embodiment of the disclosure also provides a super computing device, which comprises the circuit board shown in the embodiment.
In some possible embodiments, one or more than two circuit boards can be included in the super computing device to be used as an operation board or an operation board in the super computing device.
It should be noted that the super computing device may be an AI super computing device, a digital certificate super computing device, etc., and is not limited in any way.
Embodiments of the present disclosure also provide a computer-readable storage medium storing computer-executable instructions configured to perform the above voltage equalization method.
Embodiments of the present disclosure also provide a computer program product comprising a computer program stored on a computer-readable storage medium, the computer program comprising program instructions that, when executed by a computer, cause the computer to perform the above-mentioned voltage equalization method.
The computer readable storage medium described above may be a transitory computer readable storage medium or a non-transitory computer readable storage medium.
An embodiment of the present disclosure further provides an electronic device, a structure of which is shown in fig. 9, where the electronic device includes:
at least one processor (processor) 901, exemplified by processor 902 in fig. 9; and a memory (memory) 902, and may also include a Communication Interface 903 and a bus 904. The processor 901, the communication interface 903 and the memory 902 can communicate with each other through the bus 904. The communication interface 903 may be used for information transmission. The processor 901 may call logic instructions in the memory 902 to perform the voltage equalization method of the above-described embodiment.
Furthermore, the logic instructions in the memory 902 may be implemented in software functional units and stored in a computer readable storage medium when sold or used as a stand-alone product.
The memory 902, which is a computer-readable storage medium, can be used for storing software programs, computer-executable programs, such as program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 901 executes the software programs, instructions and modules stored in the memory 902, so as to execute the functional applications and data processing, that is, implement the voltage equalization method in the above method embodiment.
The memory 902 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal device, and the like. Further, memory 902 may include high speed random access memory and may also include non-volatile memory.
The technical solution of the embodiments of the present disclosure may be embodied in the form of a software product, where the computer software product is stored in a storage medium and includes one or more instructions to enable a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method of the embodiments of the present disclosure. And the aforementioned storage medium may be a non-transitory storage medium comprising: a U-disk, a portable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other media capable of storing program codes, and may also be a transient storage medium.
When used in this disclosure, the terms "first," "second," and the like, although may be used in this disclosure to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, unless the meaning of the description changes, so long as all occurrences of the "first element" are renamed consistently and all occurrences of the "second element" are renamed consistently. The first and second elements are both elements, but may not be the same element.
The words used in this disclosure are used only to describe embodiments and not to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this disclosure is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, the terms "comprises" and/or "comprising," when used in this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Various aspects, implementations, or features of the described embodiments can be used alone or in any combination. Aspects of the described embodiments may be implemented by software, hardware, or a combination of software and hardware. The described embodiments may also be embodied by a computer-readable medium having computer-readable code stored thereon, the computer-readable code comprising instructions executable by at least one computing device. The computer readable medium can be associated with any data storage device that can store data which can be read by a computer system. Exemplary computer readable media can include read-only memory, random-access memory, CD-ROMs, HDDs, DVDs, magnetic tape, and optical data storage devices, among others. The computer readable medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.
The above description of the technology may refer to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration embodiments in which the embodiments are described. While these embodiments are described in sufficient detail to enable those skilled in the art to practice them, they are not limiting; other embodiments may be utilized and changes may be made without departing from the scope of the described embodiments. For example, the order of operations described in a flowchart is non-limiting, and thus the order of two or more operations illustrated in and described in accordance with the flowchart may be altered in accordance with several embodiments. As another example, in several embodiments, one or more operations illustrated in and described with respect to the flowcharts may be optional or may be deleted. In addition, certain steps or functions may be added to the disclosed embodiments, or a sequence of two or more steps may be substituted. All such variations are considered to be encompassed by the disclosed embodiments and the claims.
Additionally, terminology is used in the foregoing description of the technology to provide a thorough understanding of the described embodiments. However, no unnecessary detail is required to implement the described embodiments. Accordingly, the foregoing description of the embodiments has been presented for purposes of illustration and description. The embodiments presented in the foregoing description and the examples disclosed in accordance with these embodiments are provided solely to add context and aid in the understanding of the described embodiments. The above description is not intended to be exhaustive or to limit the described embodiments to the precise form disclosed. Many modifications, alternative uses, and variations are possible in light of the above teaching. In some instances, well known process steps have not been described in detail in order to avoid unnecessarily obscuring the described embodiments.
Claims (19)
1. A voltage equalization circuit, comprising: a driver, a variable resistance unit and a calculation unit, the driver being connected to the variable resistance unit and the calculation unit, respectively, the variable resistance unit being further connected to the calculation unit, wherein,
the driver is used for collecting voltages at two ends of the computing unit and adjusting the resistance of the variable resistance unit according to the voltages at the two ends of the computing unit so as to enable the voltages at the two ends of the computing unit to be within a preset voltage range; the variable resistance unit is a transistor;
the driver is specifically configured to determine a voltage between the control end and the output end of the transistor according to a corresponding relationship between the voltages at the two ends of the computing unit and a first voltage of the transistor and the preset voltage range when the resistance of the variable resistance unit is adjusted according to the voltages at the two ends of the computing unit so that the voltages at the two ends of the computing unit are within the preset voltage range, where the first voltage of the transistor is a voltage between the control end and the output end of the transistor; and adjusting the resistance of the variable resistance unit according to the voltage between the control end and the output end of the transistor so as to enable the voltage at two ends of the calculation unit to be within a preset voltage range.
2. The voltage equalizing circuit of claim 1, further comprising a power supply coupled to the variable resistance unit and the calculating unit, the power supply configured to supply power to the variable resistance unit and the calculating unit.
3. The voltage equalizing circuit of claim 1, wherein a control terminal of the transistor is connected to the driver, and an input terminal and an output terminal of the transistor are respectively connected to two terminals of the computing unit.
4. The voltage equalizing circuit of claim 1, wherein the variable resistance unit is a triode or a field effect transistor.
5. The voltage equalizing circuit of any one of claims 1-4, wherein the computing unit comprises a chip.
6. The voltage equalizing circuit of any one of claims 1-4, wherein the computing unit comprises at least two chips connected in parallel.
7. The voltage equalizing circuit of any one of claims 1-4, wherein the computing unit comprises at least two chips connected in series.
8. The voltage equalizing circuit of any one of claims 1-4, wherein the computing unit comprises at least two parallel chip sets, each chip set comprising at least two chips connected in series.
9. Voltage equalizing circuit according to one of claims 1 to 8,
the driver is specifically configured to adjust the resistance of the variable resistance unit according to the voltage at the two ends of the calculation unit when the driver determines that the voltage at the two ends of the calculation unit is outside the preset voltage range.
10. Voltage equalizing circuit according to one of claims 1 to 9,
the driver is specifically configured to determine a driving signal according to the voltage at the two ends of the computing unit and the preset voltage range, and adjust the resistance of the variable resistance unit according to the driving signal.
11. The voltage equalizing circuit of claim 10, wherein the variable resistance unit is a transistor, and the driving signal is a voltage signal between a control terminal and an output terminal of the transistor.
12. A circuit board comprising the voltage equalizing circuit according to any one of claims 1 to 11.
13. A supercomputing device, characterized in that it comprises a circuit board according to claim 12.
14. A voltage equalization method applied to a voltage equalization circuit including a driver, a variable resistance unit, and a calculation unit, the driver being connected to the variable resistance unit and the calculation unit, respectively, and the variable resistance unit being further connected to the calculation unit, wherein the method includes:
the driver acquires the voltage at two ends of the computing unit;
the driver adjusts the resistance of the variable resistance unit according to the voltage at the two ends of the computing unit so as to enable the voltage at the two ends of the computing unit to be within a preset voltage range;
the variable resistance unit is a transistor, and the driver adjusts the resistance of the variable resistance unit according to the voltage at two ends of the computing unit, so that the voltage at two ends of the computing unit is within a preset voltage range, and the method comprises the following steps:
the driver determines the voltage between the control end and the output end of the transistor according to the corresponding relation between the voltages at the two ends of the computing unit and the first voltage of the transistor and the preset voltage range, wherein the first voltage of the transistor is the voltage between the control end and the output end of the transistor;
the driver adjusts the resistance of the variable resistance unit according to the voltage between the control end and the output end of the transistor, so that the voltage at two ends of the calculation unit is within a preset voltage range.
15. The method of claim 14, wherein the driver adjusts the resistance of the variable resistance unit according to the voltage across the computing unit so that the voltage across the computing unit is within a preset voltage range, comprising:
the driver judges whether the voltage at two ends of the computing unit is within the preset voltage range;
when the voltage at the two ends of the computing unit is not within the preset voltage range, the driver adjusts the resistance of the variable resistance unit according to the voltage at the two ends of the computing unit so as to enable the voltage at the two ends of the computing unit to be within the preset voltage range.
16. A driver is applied to a voltage equalization circuit, the voltage equalization circuit comprises the driver, a variable resistance unit and a calculation unit, the driver is respectively connected with the variable resistance unit and the calculation unit, the variable resistance unit is also connected with the calculation unit, the driver comprises an acquisition module and an adjustment module, wherein,
the acquisition module is used for acquiring the voltage at two ends of the calculation unit;
the adjusting module is used for adjusting the resistance of the variable resistance unit according to the voltage at the two ends of the calculating unit so as to enable the voltage at the two ends of the calculating unit to be within a preset voltage range;
the variable resistance unit is a transistor, and the adjusting module is specifically configured to:
determining the voltage between the control end and the output end of the transistor according to the corresponding relation between the voltage at the two ends of the computing unit and the first voltage of the transistor and the preset voltage range, wherein the first voltage of the transistor is the voltage between the control end and the output end of the transistor;
and adjusting the resistance of the variable resistance unit according to the voltage between the control end and the output end of the transistor so as to enable the voltage at two ends of the calculation unit to be within a preset voltage range.
17. The driver according to claim 16, wherein the adjustment module is specifically configured to:
judging whether the voltages at two ends of the computing unit are within the preset voltage range or not;
and when the voltage at the two ends of the calculation unit is not in the preset voltage range, adjusting the resistance of the variable resistance unit according to the voltage at the two ends of the calculation unit so as to enable the voltage at the two ends of the calculation unit to be in the preset voltage range.
18. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein, the first and the second end of the pipe are connected with each other,
the memory stores instructions executable by the at least one processor, which when executed by the at least one processor, cause the at least one processor to perform the method of claim 14 or 15.
19. A computer-readable storage medium having stored thereon computer-executable instructions configured to perform the method of claim 14 or 15.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2018/118776 WO2020107478A1 (en) | 2018-11-30 | 2018-11-30 | Voltage equalization circuit, voltage equalization method and device |
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| CN112889198A CN112889198A (en) | 2021-06-01 |
| CN112889198B true CN112889198B (en) | 2023-01-20 |
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| CN201880098300.4A Active CN112889198B (en) | 2018-11-30 | 2018-11-30 | Voltage equalization circuit, voltage equalization method and equipment |
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| CN (1) | CN112889198B (en) |
| WO (1) | WO2020107478A1 (en) |
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| CN201726162U (en) * | 2010-05-12 | 2011-01-26 | 北京天路能源有限公司 | Lithium ion power battery guard plate |
| CN202463682U (en) * | 2012-03-29 | 2012-10-03 | 宁波精华电子科技有限公司 | Multi-rotation speed control circuit of automobile front lighting light-dimming device |
| CN103683358A (en) * | 2012-09-20 | 2014-03-26 | 株式会社理光 | Battery voltage balancing device |
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| CN101986508A (en) * | 2010-12-03 | 2011-03-16 | 安徽力高新能源技术有限公司 | Battery equalizing device |
| CN102938574A (en) * | 2012-11-09 | 2013-02-20 | 谢亚平 | Voltage equalization circuit of lithium-ion battery pack |
| CN104347898A (en) * | 2013-08-02 | 2015-02-11 | 株式会社电装 | Equalization device for assembled battery |
| CN106100078A (en) * | 2016-08-30 | 2016-11-09 | 山东得普达电机股份有限公司 | A kind of non-dissipative equalizing controls device and control method |
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| Publication number | Publication date |
|---|---|
| WO2020107478A1 (en) | 2020-06-04 |
| CN112889198A (en) | 2021-06-01 |
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