WO2020103800A1 - 视频解码方法和视频解码器 - Google Patents

视频解码方法和视频解码器

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Publication number
WO2020103800A1
WO2020103800A1 PCT/CN2019/119213 CN2019119213W WO2020103800A1 WO 2020103800 A1 WO2020103800 A1 WO 2020103800A1 CN 2019119213 W CN2019119213 W CN 2019119213W WO 2020103800 A1 WO2020103800 A1 WO 2020103800A1
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Prior art keywords
matrix
dct2
transformation
pair
target
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PCT/CN2019/119213
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English (en)
French (fr)
Inventor
林永兵
郑建铧
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华为技术有限公司
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Publication of WO2020103800A1 publication Critical patent/WO2020103800A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/124—Quantisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/186—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/625—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using discrete cosine transform [DCT]

Definitions

  • the present application relates to the technical field of video encoding and decoding, and more specifically, to a video decoding method and decoder.
  • Digital video capabilities can be incorporated into a variety of devices, including digital TVs, digital live broadcast systems, wireless broadcast systems, personal digital assistants (PDAs), laptop or desktop computers, tablet computers, electronics Book readers, digital cameras, digital recording devices, digital media players, video game devices, video game consoles, cellular or satellite radio phones (so-called "smart phones"), video teleconferencing devices, video streaming devices And the like.
  • Digital video devices implement video compression techniques, for example, in the standards defined by MPEG-2, MPEG-4, ITU-T H.263, ITU-T H.264 / MPEG-4 Part 10 Advanced Video Coding (AVC), The video coding standard H.265 / high efficiency video coding (HEVC) standard and the video compression technology described in the extension of such standards.
  • Video devices can more efficiently transmit, receive, encode, decode, and / or store digital video information by implementing such video compression techniques.
  • Video compression techniques perform spatial (intra-image) prediction and / or temporal (inter-image) prediction to reduce or remove redundancy inherent in video sequences.
  • a video slice ie, a video frame or a portion of a video frame
  • the image block in the to-be-intra-coded (I) slice of the image is encoded using spatial prediction regarding reference samples in adjacent blocks in the same image.
  • An image block in an inter-coded (P or B) slice of an image may use spatial prediction relative to reference samples in neighboring blocks in the same image or temporal prediction relative to reference samples in other reference images.
  • the image may be referred to as a frame, and the reference image may be referred to as a reference frame.
  • the image block In the process of encoding an image block, the image block needs to be predicted to obtain residual coefficients, and then the residual coefficients are transformed, quantized, and entropy encoded to obtain an encoded code stream. Among them, in the process of transformation, it may try to transform the residual coefficients by using different transformation matrix pairs, and then select an appropriate transformation matrix to transform the residual coefficients according to the coding cost.
  • the DCT matrix 8 and the DCT7 matrix may also be used for transformation.
  • the calculation complexity is high.
  • the present application provides a video decoding method, a video encoding method, a video decoder, and a video encoder to simplify the computational complexity during inverse transformation / transformation.
  • an inverse video encoding method includes: parsing a code stream to obtain an index value of a target transform matrix pair for inverse transform processing of a current block and a quantization coefficient of the current block; Inverse quantization of the quantization coefficients of the current block to obtain the inverse quantization coefficients of the current block; according to the target transformation matrix pair index value and the correspondence between the target transformation matrix pair index value and the candidate transformation matrix pair, from all A target transformation matrix pair is determined among the candidate transformation matrix pairs, wherein the candidate transformation matrix pair includes a horizontal transformation matrix and a vertical transformation matrix, and the horizontal transformation matrix and the vertical transformation matrix are preset two One of the transformation matrices, the first one of the preset two transformation matrices is a DCT2 'matrix, where the DCT2' matrix is a transposed matrix of the DCT2 matrix; according to the inverse quantization coefficients of the current block Inverse transform processing is performed to obtain the reconstructed residual block of the current block; and the
  • inverse quantization may also be referred to as inverse quantization
  • inverse transform may also be referred to as inverse transform
  • the fast algorithm can be used when the DCT2 'is used for the inverse transformation, which can reduce the calculation complexity of the inverter process degree.
  • DCT2' since the DCT2 'matrix is a transpose of the DCT2 matrix, in the process of inverse transformation, DCT2' can reuse the inverse transformation realization circuit of DCT2, which can reduce the hardware implementation cost.
  • the DCT2 'matrix is derived from the DCT2 matrix.
  • the matrix coefficients of the DCT2' matrix can be derived from the matrix coefficients of the DCT2 matrix without additional storage of the matrix coefficients of the DCT2 'matrix, which can reduce storage overhead.
  • the second one of the preset two transformation matrices is derived from a DCT2 matrix.
  • the second one of the preset two transformation matrices can be derived from the DCT2 matrix, it is not necessary to additionally store the matrix coefficients of the second transformation matrix, which can reduce storage overhead.
  • the second one of the preset two transformation matrices is a DCT2'FS matrix or a DCT2'F matrix.
  • F in the DCT2'FS matrix and DCT2'F matrix represent mirror images
  • S in the DCT2'FS matrix represents symbol transformation
  • the DCT2'F matrix is a matrix obtained by mirroring the DCT2 'matrix
  • the DCT2'FS matrix is a matrix obtained by mirroring the DCT2' matrix and then performing symbol conversion on the mirrored matrix.
  • the DCT2'FS matrix or the DCT2'F matrix can be derived from a DCT matrix of a corresponding size.
  • a 16x16 DCT2'FS matrix or a 16x16 DCT2'F matrix can be derived from a 16x16 DCT2'F matrix.
  • the above-mentioned mirror image is a left-right mirror image.
  • Flipping a mirror image to the right and left of a matrix may refer to mirroring the matrix coefficients on the left side of the matrix to the right and mirroring the matrix coefficients on the right side of the matrix to the left.
  • the above-mentioned symbol transformation means that only the matrix coefficients of the even rows of the matrix are inverted, and the matrix coefficients of the odd rows of the matrix remain unchanged.
  • the above-mentioned symbol transformation means that only the matrix coefficients of the odd rows of the matrix are inverted, while the matrix coefficients of the even rows of the matrix remain unchanged.
  • the above sign transformation is to reverse the sign of all matrix coefficients in the matrix.
  • the first one of the two preset transformation matrices is a DCT2 'matrix
  • the second matrix is a DCT2'FS matrix or a DCT2'F matrix, which is applicable to all transformation sizes.
  • the first matrix of the two preset transformation matrices is a DCT2 'matrix
  • the second matrix is a DCT2'FS matrix or a DCT2'F matrix, which is suitable for transformation sizes of 4, 8, 16, and 32. Point situation.
  • the first matrix of the two preset transformation matrices is a DCT2 'matrix and the second matrix is a DCT2'FS matrix or a DCT2'F matrix
  • the DCT2' matrix, the DCT2'FS matrix, and the DCT2 ' There are fast algorithms for F matrix, so when the target transformation matrix pair (the target transformation matrix pair is formed by combining two preset transformation matrices) is used to inverse transform the inverse quantization coefficient of the current block, the inverse transformation process can be reduced Computational complexity in.
  • the horizontal transformation matrix in the target transformation matrix pair is a DCT2 'matrix
  • the target transformation The vertical transformation matrix in the matrix pair is a DCT2'FS matrix or a DCT2'F matrix
  • the vertical transformation matrix in the target transformation matrix pair is a DST4 matrix, where M is positive Integer.
  • the vertical transformation matrix in the target transformation matrix pair is a DCT2 'matrix
  • the target transformation The horizontal transformation matrix in the matrix pair is a DCT2'FS matrix or a DCT2'F matrix
  • the horizontal transformation matrix in the target transformation matrix pair is a DST4 matrix, where M is positive Integer.
  • the transformation size when the transformation size is greater than or equal to M points, it may be regarded as a large-size transformation scene, and when the transformation size is less than M points, it may be regarded as a small-size transformation scene.
  • the transformation matrix with a fast algorithm is used as the horizontal transformation matrix or the vertical transformation matrix in the target transformation matrix pair in the large-size transformation scene
  • the transformation matrix suitable for the small-size transformation scene is used as the target in the small-size transformation scene
  • the horizontal transformation matrix or the vertical transformation matrix in the transformation matrix pair can significantly reduce the complexity of inverse transformation in large-scale transformation scenes, and at the same time can ensure transformation performance in small-size scenes. It can reduce the complexity of inverse transformation and Ensure a balance between inverse transformation performance.
  • the horizontal transformation matrix in the target transformation matrix pair is a DCT2 ′ matrix
  • the target transformation The vertical transformation matrix in the matrix pair is a DST7 matrix
  • the vertical transformation matrix in the target transformation matrix pair is a DST4 matrix, where N is a positive integer.
  • the vertical transformation matrix in the target transformation matrix pair is a DCT2 ′ matrix
  • the target transformation The horizontal transformation matrix in the matrix pair is a DST7 matrix
  • the horizontal transformation matrix in the target transformation matrix pair is a DST4 matrix, where N is a positive integer.
  • N 16.
  • the transformation size when the transformation size is greater than or equal to N points, it may be regarded as a large-size transformation scene, and when the transformation size is less than M points, it may be regarded as a small-size transformation scene.
  • DCT2 'matrix and DST7 matrix are used as the target transformation matrix pair in large-scale transformation scenes
  • DCT2' matrix and DST4 matrix are used as the target transformation matrix pair
  • DCT2' matrix and DST4 matrix are used as the target transformation matrix pair
  • DCT2' matrix and DST4 matrix are used as the target transformation matrix pair
  • DCT2' matrix and DST4 matrix are used as the target transformation matrix pair
  • DCT2' matrix and DST4 matrix in small-size scenes (Inverse transform in size scene) as the target transform matrix pair
  • the above DST4 matrix may also be derived from the DCT2 matrix.
  • the L ⁇ L DST4 matrix can be derived (also called transformation) from the 2L ⁇ 2L DCT2 matrix.
  • a 4 ⁇ 4 DST4 matrix can be derived from an 8 ⁇ 8 DCT2 matrix
  • a 16 ⁇ 16 DST4 matrix can be derived from a 32 ⁇ 32 DCT2 matrix
  • a 32 ⁇ 32 DST4 matrix can be derived from a 64 ⁇ 64 DCT2 matrix Derived.
  • L ⁇ L DST4 matrix is derived from a 2L ⁇ 2L DCT2 matrix, which may specifically refer to extracting partial matrix coefficients in the DCT2 matrix as matrix coefficients of the DST4 matrix.
  • the above method further includes: parsing the code stream to obtain multi-core transformation flag bits; the corresponding relationship between the index value of the target transformation matrix pair and the index value of the target transformation matrix pair and the candidate transformation matrix pair , Determining a target transformation matrix pair from the candidate transformation matrix pairs, including: when the value of the multi-core transformation flag is the first value, according to the target transformation matrix pair index value and the target transformation Correspondence between the index value of the matrix pair and the candidate transformation matrix pair, determine the target transformation matrix pair from the candidate transformation matrix pair; when the value of the multi-core transformation flag bit is the second value, set DCT2 The matrix is determined as the horizontal transformation matrix and the vertical transformation matrix of the target transformation matrix pair.
  • the multi-core conversion can be performed only when the value of the multi-core conversion flag is the first value, and directly used when the value of the multi-core conversion flag is the second value (DCT2, DCT2) as the target transformation matrix to inversely transform the residual coefficients.
  • the multi-core conversion flag may specifically be MTS_flag.
  • MTS_flag 0, it may indicate that multi-core conversion is not performed (or, the meanings of 1 and 0 may be reversed).
  • a video encoding method includes: acquiring a residual block of an image block to be processed; acquiring candidate transform matrix pairs of the residual block according to preset mapping relationship information, wherein the candidate transform matrix pairs include A horizontal transformation matrix and a vertical transformation matrix, the horizontal transformation matrix and the vertical transformation matrix are both one of two preset transformation matrices, and the first of the two preset transformation matrices is The transformation matrix is a DCT2 'matrix, and the DCT2' matrix is a transposed matrix of the DCT2 matrix; the transformation matrix pair with the smallest rate distortion is selected from the candidate transformation matrix pairs as the target transformation matrix pair; and the residual block is performed according to the target transformation matrix pair Transform to obtain the transform coefficient of the image block to be processed; write the index value of the target transform matrix corresponding to the target transform matrix into the code stream.
  • the candidate transform matrix pairs include A horizontal transformation matrix and a vertical transformation matrix, the horizontal transformation matrix and the vertical transformation matrix are both one of two preset transformation matrices, and the first of the two preset
  • the above mapping relationship information may include a target transformation matrix pair index value and a transformation matrix pair corresponding to the target index value.
  • the candidate transformation matrix pair includes the DCT2 'matrix
  • the DCT2' matrix has a fast algorithm during the transformation process
  • a fast algorithm can be used, which can reduce the computational complexity of the transformation process.
  • the DCT2 'matrix is derived from the DCT2 matrix.
  • the matrix coefficients of the DCT2' matrix can be derived from the matrix coefficients of the DCT2 matrix without additional storage of the matrix coefficients of the DCT2 'matrix, which can reduce storage overhead.
  • the second one of the preset two transformation matrices is derived from a DCT2 matrix.
  • the second one of the preset two transformation matrices can be derived from the DCT2 matrix, it is not necessary to additionally store the matrix coefficients of the second transformation matrix, which can reduce storage overhead.
  • the second one of the preset two transformation matrices is a DCT2'FS matrix or a DCT2'F matrix.
  • F in the DCT2'FS matrix and DCT2'F matrix represent mirror images
  • S in the DCT2'FS matrix represents symbol transformation
  • the DCT2'F matrix is a matrix obtained by mirroring the DCT2 'matrix
  • the DCT2'FS matrix is a matrix obtained by mirroring the DCT2' matrix and then performing symbol conversion on the mirrored matrix.
  • the above-mentioned mirror image is a left-right mirror image.
  • Flipping a mirror image to the right and left of a matrix may refer to mirroring the matrix coefficients on the left side of the matrix to the right and mirroring the matrix coefficients on the right side of the matrix to the left.
  • the above-mentioned symbol transformation means that only the matrix coefficients of the even rows of the matrix are inverted, and the matrix coefficients of the odd rows of the matrix remain unchanged.
  • the above-mentioned symbol transformation means that only the matrix coefficients of odd rows of the matrix are inverted, and the matrix coefficients of even rows of the matrix remain unchanged.
  • the above sign transformation is to reverse the sign of all matrix coefficients in the matrix.
  • the first one of the two preset transformation matrices is a DCT2 'matrix
  • the second matrix is a DCT2'FS matrix or a DCT2'F matrix, which is applicable to all transformation sizes.
  • the first matrix of the two preset transformation matrices is a DCT2 'matrix
  • the second matrix is a DCT2'FS matrix or a DCT2'F matrix, which is suitable for transformation sizes of 4, 8, 16, and 32. Point situation.
  • the first matrix of the two preset transformation matrices is a DCT2 'matrix and the second matrix is a DCT2'FS matrix or a DCT2'F matrix
  • the DCT2' matrix, DCT2'FS matrix, and DCT2 ' There are fast algorithms for F matrix, so when the target transformation matrix pair (the target transformation matrix pair is formed by combining two preset transformation matrices) is used to transform the residual block, the calculation complexity in the inverse transformation process can be reduced degree.
  • the horizontal transform matrix in the target transform matrix pair is a DCT2 'matrix
  • the target The vertical transformation matrix in the transformation matrix pair is a DCT2'FS matrix or a DCT2'F matrix
  • the vertical transformation matrix in the target transformation matrix pair is a DST4 matrix, where, M It is a positive integer.
  • the vertical transformation matrix in the target transformation matrix pair is a DCT2 ′ matrix
  • the width of the residual block is greater than or equal to M points
  • the goal The horizontal transformation matrix in the transformation matrix pair is a DCT2'FS matrix or a DCT2'F matrix
  • the horizontal transformation matrix in the target transformation matrix pair is a DST4 matrix, where M It is a positive integer.
  • the transformation size when the transformation size is greater than or equal to M points, it may be regarded as a large-size transformation scene, and when the transformation size is less than M points, it may be regarded as a small-size transformation scene.
  • the transformation matrix with a fast algorithm is used as the horizontal transformation matrix or the vertical transformation matrix in the target transformation matrix pair in the large-size transformation scene
  • the transformation matrix suitable for the small-size transformation scene is used as the target in the small-size transformation scene
  • the horizontal transformation matrix or the vertical transformation matrix in the transformation matrix pair can significantly reduce the complexity of the transformation in a large-size transformation scene, and can also ensure the transformation performance in a small-size scene, and can reduce the transformation complexity and ensure the transformation. Balance performance.
  • the horizontal transform matrix in the target transform matrix pair is a DCT2 'matrix
  • the target The vertical transformation matrix in the transformation matrix pair is a DST7 matrix
  • the vertical transformation matrix in the target transformation matrix pair is a DST4 matrix, where N is a positive integer.
  • the vertical transformation matrix in the target transformation matrix pair is a DCT2 ′ matrix
  • the width of the residual block is greater than or equal to N points
  • the goal The horizontal transformation matrix in the transformation matrix pair is a DST7 matrix
  • the horizontal transformation matrix in the target transformation matrix pair is a DST4 matrix, where N is a positive integer.
  • N 16.
  • the transformation size when the transformation size is greater than or equal to N points, it may be regarded as a large-size transformation scene, and when the transformation size is less than M points, it may be regarded as a small-size transformation scene.
  • the DCT2 'matrix and DST7 matrix are used as the target transformation matrix pair in large-scale transformation scenarios
  • the DCT2' matrix and DST4 matrix are used in small-size scenarios (Transformation in the scene)
  • the target transformation matrix pair it can reduce the transformation complexity and improve the transformation performance.
  • the above DST4 matrix may also be derived from the DCT2 matrix.
  • the L ⁇ L DST4 matrix can be derived (also called transformation) from the 2L ⁇ 2L DCT2 matrix.
  • a 4 ⁇ 4 DST4 matrix can be derived from an 8 ⁇ 8 DCT2 matrix
  • a 16 ⁇ 16 DST4 matrix can be derived from a 32 ⁇ 32 DCT2 matrix
  • a 32 ⁇ 32 DST4 matrix can be derived from a 64 ⁇ 64 DCT2 matrix Derived.
  • L ⁇ L DST4 matrix is derived from a 2L ⁇ 2L DCT2 matrix, which may specifically refer to extracting partial matrix coefficients in the DCT2 matrix as matrix coefficients of the DST4 matrix.
  • a decoder in a third aspect, includes a module for performing the method in the first aspect or any implementation manner of the first aspect.
  • an encoder includes a module for performing the method in the second aspect or any implementation manner of the second aspect.
  • a decoder including: a memory and a processor, where the processor calls program codes stored in the memory to perform the method in the first aspect or any implementation manner of the first aspect Part or all of the steps.
  • the memory is a non-volatile memory.
  • the memory and the processor are coupled together.
  • an encoder including: a memory and a processor, where the processor calls program codes stored in the memory to perform the method in the second aspect or any implementation manner of the second aspect Part or all of the steps.
  • the memory is a non-volatile memory.
  • the memory and the processor are coupled together.
  • a computer-readable storage medium stores program code, wherein the program code includes a program for executing the first aspect or any one of the implementation manners of the first aspect Instructions for some or all steps of the method.
  • a computer-readable storage medium stores program code, wherein the program code includes a program for executing the second aspect or any implementation manner of the second aspect. Instructions for some or all steps of the method.
  • a computer program product which, when the computer program product runs on a computer, causes the computer to perform part or all of the steps of the method in the first aspect or any implementation manner of the first aspect Instructions.
  • a computer program product which, when the computer program product runs on a computer, causes the computer to perform part or all of the steps of the method in the second aspect or any implementation manner of the second aspect Instructions.
  • FIG. 1 is a block diagram of an example of a video encoding system for implementing embodiments of the present application
  • FIG. 2 is a block diagram of an example structure of a video encoder for implementing an embodiment of the present application
  • FIG. 3 is a block diagram of an example structure of a video decoder for implementing an embodiment of the present application
  • FIG. 4 shows a block diagram of an example structure including the encoder 20 of FIG. 2 and the decoder 30 of FIG. 3;
  • FIG. 5 shows a block diagram of another example of an encoding device or a decoding device
  • FIG. 6 is a schematic flowchart of a video decoding method according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a process of deriving the transformation matrix matrix of DCT2 'and the transformation matrix matrix of DCT2'FS from the transformation matrix matrix of DCT2;
  • FIG. 8 is a schematic flowchart of a video encoding method according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a fast algorithm circuit of a butterfly in a 16 ⁇ 16 DCT2 matrix in HEVC;
  • FIG. 10 is a schematic diagram of a 32 ⁇ 32 inverse transform implementation circuit according to an embodiment of the present application.
  • FIG. 11 is a schematic block diagram of a video decoder according to an embodiment of the present application.
  • the disclosure in conjunction with the described method may be equally applicable to the corresponding device or system for performing the method, and vice versa.
  • the corresponding device may include one or more units such as functional units to perform the one or more method steps described (eg, one unit performs one or more steps , Or multiple units, each of which performs one or more of multiple steps), even if such one or more units are not explicitly described or illustrated in the drawings.
  • the corresponding method may include one step to perform the functionality of one or more units (eg, one step executes one or more units Functionality, or multiple steps, each of which performs the functionality of one or more of the multiple units), even if such one or more steps are not explicitly described or illustrated in the drawings.
  • one step executes one or more units Functionality, or multiple steps, each of which performs the functionality of one or more of the multiple units
  • the features of the exemplary embodiments and / or aspects described herein may be combined with each other.
  • Video coding generally refers to processing a sequence of pictures that form a video or video sequence.
  • picture In the field of video coding, the terms “picture”, “frame” or “image” may be used as synonyms.
  • the video encoding used in this application means video encoding or video decoding.
  • Video encoding is performed on the source side, and usually includes processing (eg, by compressing) the original video picture to reduce the amount of data required to represent the video picture (thereby storing and / or transmitting more efficiently).
  • Video decoding is performed on the destination side and usually involves inverse processing relative to the encoder to reconstruct the video picture.
  • the video pictures (or collectively referred to as pictures, which will be explained below) involved in the embodiments should be understood to refer to "encoding” or “decoding” of video sequences.
  • the combination of the encoding part and the decoding part is also called codec (encoding and decoding).
  • the original video picture can be reconstructed, that is, the reconstructed video picture has the same quality as the original video picture (assuming no transmission loss or other data loss during storage or transmission).
  • further compression is performed by, for example, quantization to reduce the amount of data required to represent the video picture, but the decoder side cannot fully reconstruct the video picture, that is, the quality of the reconstructed video picture is better than the original video picture The quality is lower or worse.
  • Several video coding standards of H.261 belong to "lossy hybrid video codec” (ie, combining spatial and temporal prediction in the sample domain with 2D transform coding for applying quantization in the transform domain).
  • Each picture of the video sequence is usually divided into non-overlapping block sets, which are usually encoded at the block level.
  • the encoder side usually processes the encoded video at the block (video block) level.
  • the prediction block is generated by spatial (intra-picture) prediction and temporal (inter-picture) prediction.
  • the encoder duplicates the decoder processing loop so that the encoder and decoder generate the same prediction (eg, intra prediction and inter prediction) and / or reconstruction for processing, ie, encoding subsequent blocks.
  • the term "block” may be part of a picture or frame.
  • VVC Multipurpose Video Coding
  • VCEG VideoEG Coding Experts Group
  • ISO / IEC Motion Picture Experts Group Motion Pictures, Experts Group, MPEG
  • HEVC High-Efficiency Video Coding
  • JCT-VC Joint Collaboration Team Video on Coding
  • the CTU is split into multiple CUs by using a quadtree structure represented as a coding tree.
  • a decision is made at the CU level whether to use inter-picture (temporal) or intra-picture (spatial) prediction to encode picture regions.
  • Each CU can be further split into one, two, or four PUs according to the PU split type.
  • the same prediction process is applied within a PU, and related information is transmitted to the decoder on the basis of the PU.
  • the CU may be divided into transform units (TU) according to other quadtree structures similar to the coding tree used for the CU.
  • quad-tree and binary-tree are used to split the coding blocks.
  • the CU may have a square or rectangular shape.
  • the coding tree unit (coding unit) (CTU) is first divided by a quadtree structure.
  • the quad leaf nodes are further divided by a binary tree structure.
  • the binary leaf node is called a coding unit (CU), and the segmentation is used for prediction and transformation processing without any other segmentation.
  • CU coding unit
  • the segmentation is used for prediction and transformation processing without any other segmentation.
  • the CU, PU and TU have the same block size in the QTBT coding block structure.
  • FIG. 1 is a conceptual or schematic block diagram illustrating an exemplary encoding system 10, for example, a video encoding system 10 that can utilize the technology of the present application (this disclosure).
  • the encoder 20 e.g., video encoder 20
  • the decoder 30 e.g., video decoder 30
  • the encoding system 10 includes a source device 12 for providing encoded data 13, for example, encoded pictures 13, to a destination device 14 that decodes encoded data 13, for example.
  • the source device 12 includes an encoder 20, and optionally, may also include a picture source 16, such as a pre-processing unit 18 of a picture pre-processing unit 18, and a communication interface or communication unit 22.
  • a picture source 16 such as a pre-processing unit 18 of a picture pre-processing unit 18, and a communication interface or communication unit 22.
  • the picture source 16 may include or may be any kind of picture capturing device, for example, for capturing real-world pictures, and / or any kind of pictures or comments (for screen content encoding, some text on the screen is also considered to be pictures to be encoded Or a part of the image) generating equipment, for example, a computer graphics processor for generating computer animation pictures, or for acquiring and / or providing real-world pictures, computer animation pictures (for example, screen content, virtual reality (VR) ) Pictures) in any category of equipment, and / or any combination thereof (for example, augmented reality (AR) pictures).
  • a computer graphics processor for generating computer animation pictures, or for acquiring and / or providing real-world pictures, computer animation pictures (for example, screen content, virtual reality (VR) ) Pictures) in any category of equipment, and / or any combination thereof (for example, augmented reality (AR) pictures).
  • AR augmented reality
  • the (digital) picture is or can be regarded as a two-dimensional array or matrix of sampling points with luminance values.
  • the sampling points in the array may also be called pixels (short for picture elements) or pixels (pels).
  • the number of sampling points of the array or picture in the horizontal and vertical directions (or axis) defines the size and / or resolution of the picture.
  • three color components are usually used, that is, a picture can be represented or contain three sampling arrays.
  • the picture includes corresponding red, green and blue sampling arrays.
  • each pixel is usually expressed in a luma / chroma format or color space, for example, YCbCr, including the luminance component indicated by Y (sometimes also indicated by L) and the two chromaticities indicated by Cb and Cr Weight.
  • Luminance (abbreviated as luma) component Y represents brightness or gray-scale horizontal intensity (for example, the two are the same in gray-scale pictures), while two chroma (abbreviated as chroma) components Cb and Cr represent chroma or color information components .
  • the picture in YCbCr format includes a luminance sampling array of luminance sampling values (Y), and two chrominance sampling arrays of chrominance values (Cb and Cr).
  • RGB format pictures can be converted or transformed into YCbCr format and vice versa, this process is also called color transformation or conversion. If the picture is black and white, the picture may include only the brightness sampling array.
  • the picture source 16 may be, for example, a camera for capturing pictures, a memory such as a picture memory, including or storing previously captured or generated pictures, and / or any category of (internal Or external) interface.
  • the camera may be, for example, an integrated camera local or integrated in the source device, and the memory may be an integrated memory local or for example integrated in the source device.
  • the interface may be, for example, an external interface that receives pictures from an external video source.
  • the external video source is, for example, an external picture capture device, such as a camera, external memory, or external picture generation device.
  • the external picture generation device is, for example, an external computer graphics processor, computer Or server.
  • the interface may be any type of interface according to any proprietary or standardized interface protocol, such as a wired or wireless interface, an optical interface.
  • the interface for acquiring the picture data 17 may be the same interface as the communication interface 22 or a part of the communication interface 22.
  • the picture or picture data 17 may also be referred to as the original picture or the original picture data 17.
  • the pre-processing unit 18 is used to receive (original) picture data 17 and perform pre-processing on the picture data 17 to obtain pre-processed picture 19 or pre-processed picture data 19.
  • the preprocessing performed by the preprocessing unit 18 may include trimming, color format conversion (for example, conversion from RGB to YCbCr), color adjustment, or denoising. It can be understood that the pre-processing unit 18 may be an optional component.
  • An encoder 20 (eg, video encoder 20) is used to receive the pre-processed picture data 19 and provide the encoded picture data 21 (details will be described further below, for example, based on FIG. 2 or FIG. 4).
  • the communication interface 22 of the source device 12 may be used to receive the encoded picture data 21 and transmit it to other devices, for example, the destination device 14 or any other device, for storage or direct reconstruction, or for storing the corresponding
  • the encoded data 13 and / or the encoded picture data 21 is processed before transmission of the encoded data 13 to other devices, such as the destination device 14 or any other device for decoding or storage.
  • the destination device 14 includes a decoder 30 (for example, a video decoder 30), and optionally, may also include a communication interface or communication unit 28, a post-processing unit 32, and a display device 34.
  • a decoder 30 for example, a video decoder 30
  • a communication interface or communication unit 28 may also include a communication interface or communication unit 28, a post-processing unit 32, and a display device 34.
  • the communication interface 28 of the destination device 14 is used, for example, to receive the encoded picture data 21 or the encoded data 13 directly from the source device 12 or any other source, such as a storage device, and the storage device such as an encoded picture data storage device.
  • the communication interface 22 and the communication interface 28 can be used for direct communication through the direct communication link between the source device 12 and the destination device 14 or through any type of network to transmit or receive the encoded picture data 21 or the encoded data 13
  • the link is, for example, a direct wired or wireless connection, and any kind of network is, for example, a wired or wireless network or any combination thereof, or any kind of private and public networks, or any combination thereof.
  • the communication interface 22 may be used, for example, to encapsulate the encoded picture data 21 into a suitable format, such as a packet, for transmission on a communication link or communication network.
  • the communication interface 28 forming the corresponding part of the communication interface 22 may be used, for example, to depacketize the encoded data 13 to obtain the encoded picture data 21.
  • Both the communication interface 22 and the communication interface 28 may be configured as a one-way communication interface, as indicated by the arrow for the encoded picture data 13 from the source device 12 to the destination device 14 in FIG. 1, or as a two-way communication interface, and It can be used, for example, to send and receive messages to establish a connection, confirm and exchange any other information related to a communication link and / or data transmission such as encoded picture data transmission.
  • the decoder 30 is used to receive the encoded picture data 21 and provide the decoded picture data 31 or the decoded picture 31 (details will be described further below, for example, based on FIG. 3 or FIG. 5).
  • the post-processor 32 of the destination device 14 is used to post-process decoded picture data 31 (also referred to as reconstructed picture data), for example, decoded picture 131, to obtain post-processed picture data 33, for example, post-processing Picture 33.
  • the post-processing performed by the post-processing unit 32 may include, for example, color format conversion (for example, conversion from YCbCr to RGB), color adjustment, trimming, or resampling, or any other processing for, for example, preparing the decoded picture data 31 to The display device 34 displays.
  • the display device 34 of the destination device 14 is used to receive post-processed picture data 33 to display pictures to, for example, a user or a viewer.
  • the display device 34 may be or may include any type of display for presenting reconstructed pictures, for example, an integrated or external display or monitor.
  • the display may include a liquid crystal display (liquid crystal display, LCD), an organic light emitting diode (organic light emitting diode, OLED) display, a plasma display, a projector, a micro LED display, a liquid crystal on silicon (LCoS), Digital Light Processor (DLP) or other displays of any kind.
  • FIG. 1 depicts source device 12 and destination device 14 as separate devices
  • device embodiments may also include both source device 12 and destination device 14 or the functionality of both, ie source device 12 or corresponding Functionality of the destination device 14 or the corresponding functionality.
  • the source device 12 or corresponding functionality and the destination device 14 or corresponding functionality may be implemented using the same hardware and / or software, or using separate hardware and / or software, or any combination thereof .
  • Both the encoder 20 and the decoder 30 may be implemented as any of various suitable circuits, for example, one or more microprocessors, digital signal processors (digital signal processor, DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), discrete logic, hardware, or any combination thereof.
  • the device may store the instructions of the software in a suitable non-transitory computer-readable storage medium, and may use one or more processors to execute the instructions in hardware to perform the techniques of the present disclosure . Any one of the foregoing (including hardware, software, a combination of hardware and software, etc.) may be regarded as one or more processors.
  • Each of the video encoder 20 and the video decoder 30 may be included in one or more encoders or decoders, any of which may be integrated as a combined encoder / decoder in the corresponding device Part of the codec (codec).
  • the source device 12 may be referred to as a video encoding device or a video encoding device.
  • the destination device 14 may be referred to as a video decoding device or a video decoding device.
  • the source device 12 and the destination device 14 may be examples of video encoding devices or video encoding devices.
  • Source device 12 and destination device 14 may include any of a variety of devices, including any type of handheld or stationary devices, such as notebook or laptop computers, mobile phones, smart phones, tablets or tablet computers, cameras, desktops Computers, set-top boxes, televisions, display devices, digital media players, video game consoles, video streaming devices (such as content service servers or content distribution servers), broadcast receiver devices, broadcast transmitter devices, etc., and may not be used Or use any kind of operating system.
  • handheld or stationary devices such as notebook or laptop computers, mobile phones, smart phones, tablets or tablet computers, cameras, desktops Computers, set-top boxes, televisions, display devices, digital media players, video game consoles, video streaming devices (such as content service servers or content distribution servers), broadcast receiver devices, broadcast transmitter devices, etc., and may not be used Or use any kind of operating system.
  • source device 12 and destination device 14 may be equipped for wireless communication. Therefore, the source device 12 and the destination device 14 may be wireless communication devices.
  • the video encoding system 10 shown in FIG. 1 is only an example, and the technology of the present application may be applied to a video encoding setting (for example, video encoding or video decoding) that does not necessarily include any data communication between encoding and decoding devices. .
  • data can be retrieved from local storage, streamed on the network, and so on.
  • the video encoding device may encode the data and store the data to the memory, and / or the video decoding device may retrieve the data from the memory and decode the data.
  • encoding and decoding are performed by devices that do not communicate with each other but only encode data to and / or retrieve data from memory and decode the data.
  • video decoder 30 may be used to perform the reverse process.
  • the video decoder 30 may be used to receive and parse such syntax elements, and decode relevant video data accordingly.
  • video encoder 20 may entropy encode one or more defined syntax elements into an encoded video bitstream. In such instances, video decoder 30 may parse such grammatical elements and decode the relevant video data accordingly.
  • FIG. 2 shows a schematic / conceptual block diagram of an example of a video encoder 20 for implementing the technology of the present application (disclosure).
  • the video encoder 20 includes a residual calculation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transform processing unit 212, a reconstruction unit 214, a buffer 216, loop filtering A unit 220, a decoded picture buffer (DPB) 230, a prediction processing unit 260, and an entropy encoding unit 270.
  • the prediction processing unit 260 may include an inter prediction unit 244, an intra prediction unit 254, and a mode selection unit 262.
  • the inter prediction unit 244 may include a motion estimation unit and a motion compensation unit (not shown).
  • the video encoder 20 shown in FIG. 2 may also be referred to as a hybrid video encoder or a video encoder based on a hybrid video codec.
  • the residual calculation unit 204, the transform processing unit 206, the quantization unit 208, the prediction processing unit 260, and the entropy encoding unit 270 form the forward signal path of the encoder 20, while, for example, the inverse quantization unit 210, the inverse transform processing unit 212, and
  • the structural unit 214, the buffer 216, the loop filter 220, the decoded picture buffer (DPB) 230, and the prediction processing unit 260 form the backward signal path of the encoder, where the backward signal path of the encoder corresponds The signal path for the decoder (see decoder 30 in FIG. 3).
  • the encoder 20 receives a picture 201 or a block 203 of the picture 201 through, for example, an input 202, for example, forming a picture in a picture sequence of a video or a video sequence.
  • the picture block 203 may also be called a current picture block or a picture block to be coded
  • the picture 201 may be called a current picture or a picture to be coded (especially when the current picture is distinguished from other pictures in video coding, other pictures such as the same video sequence That is, the previously encoded and / or decoded pictures in the video sequence of the current picture are also included).
  • An embodiment of the encoder 20 may include a division unit (not shown in FIG. 2) for dividing the picture 201 into a plurality of blocks such as block 203, usually into a plurality of non-overlapping blocks.
  • the segmentation unit can be used to use the same block size and corresponding grid that defines the block size for all pictures in the video sequence, or to change the block size between pictures or subsets or picture groups, and divide each picture into The corresponding block.
  • the prediction processing unit 260 of the video encoder 20 may be used to perform any combination of the above-mentioned segmentation techniques.
  • block 203 is also or can be regarded as a two-dimensional array or matrix of sampling points with luminance values (sample values), although its size is smaller than picture 201.
  • the block 203 may include, for example, one sampling array (for example, the brightness array in the case of black and white picture 201) or three sampling arrays (for example, one brightness array and two chroma arrays in the case of color picture) or basis An array of any other number and / or category of color formats applied.
  • the number of sampling points in the horizontal and vertical direction (or axis) of the block 203 defines the size of the block 203.
  • the encoder 20 shown in FIG. 2 is used to encode the picture 201 block by block, for example, to perform encoding and prediction on each block 203.
  • the residual calculation unit 204 is used to calculate the residual block 205 based on the picture block 203 and the prediction block 265 (other details of the prediction block 265 are provided below), for example, by subtracting the prediction from the sample value of the picture block 203 by sample (pixel by pixel) The sample values of block 265 to obtain the residual block 205 in the sample domain.
  • the transform processing unit 206 is used to apply a transform such as discrete cosine transform (DCT) or discrete sine transform (DST) to the sample values of the residual block 205 to obtain transform coefficients 207 in the transform domain .
  • the transform coefficient 207 may also be referred to as a transform residual coefficient, and represents a residual block 205 in the transform domain.
  • the transform processing unit 206 may be used to apply integer approximations of DCT / DST, such as the transform specified by HEVC / H.265. Compared with the orthogonal DCT transform, this integer approximation is usually scaled by a factor. In order to maintain the norm of the residual block processed by the forward and inverse transform, an additional scaling factor is applied as part of the transform process.
  • the scaling factor is usually selected based on certain constraints, for example, the scaling factor is a power of two used for the shift operation, the bit depth of the transform coefficient, the accuracy, and the trade-off between implementation cost and so on.
  • a specific scaling factor can be specified for the inverse transform by the inverse transform processing unit 212 on the decoder 30 side (and corresponding inverse transform by the inverse transform processing unit 212 on the encoder 20 side), and accordingly, the encoder can be The 20 side specifies the corresponding scaling factor for the positive transform by the transform processing unit 206.
  • the quantization unit 208 is used to quantize the transform coefficient 207 by, for example, applying scalar quantization or vector quantization to obtain the quantized transform coefficient 209.
  • the quantized transform coefficient 209 may also be referred to as the quantized residual coefficient 209.
  • the quantization process can reduce the bit depth associated with some or all of the transform coefficients 207. For example, n-bit transform coefficients can be rounded down to m-bit transform coefficients during quantization, where n is greater than m.
  • the degree of quantization can be modified by adjusting the quantization parameter (QP). For example, for scalar quantization, different scales can be applied to achieve thinner or coarser quantization.
  • QP quantization parameter
  • a smaller quantization step size corresponds to a finer quantization
  • a larger quantization step size corresponds to a coarser quantization.
  • a suitable quantization step size can be indicated by a quantization parameter (QP).
  • the quantization parameter may be an index of a predefined set of suitable quantization steps.
  • smaller quantization parameters may correspond to fine quantization (smaller quantization step size)
  • larger quantization parameters may correspond to coarse quantization (larger quantization step size)
  • the quantization may include dividing by the quantization step size and the corresponding quantization or inverse quantization performed by, for example, inverse quantization 210, or may include multiplying the quantization step size.
  • Embodiments according to some standards such as HEVC may use quantization parameters to determine the quantization step size.
  • the quantization step size can be calculated based on the quantization parameter using fixed-point approximation that includes equations for division. Additional scaling factors can be introduced for quantization and inverse quantization to restore the norm of the residual block that may be modified due to the scale used in the fixed-point approximation of the equations for quantization step size and quantization parameter.
  • the scale of inverse transform and inverse quantization may be combined.
  • a custom quantization table can be used and signaled from the encoder to the decoder in a bitstream, for example. Quantization is a lossy operation, where the larger the quantization step, the greater the loss.
  • the inverse quantization unit 210 is used to apply the inverse quantization of the quantization unit 208 on the quantized coefficients to obtain the inverse quantization coefficient 211, for example, based on or using the same quantization step size as the quantization unit 208, apply the quantization scheme applied by the quantization unit 208 Inverse quantization scheme.
  • the inverse quantized coefficient 211 may also be referred to as the inverse quantized residual coefficient 211, which corresponds to the transform coefficient 207, although the loss due to quantization is usually not the same as the transform coefficient.
  • the inverse transform processing unit 212 is used to apply the inverse transform of the transform applied by the transform processing unit 206, for example, inverse discrete cosine transform (DCT) or inverse discrete sine transform (DST), in the sample domain
  • the inverse transform block 213 is obtained.
  • the inverse transform block 213 may also be referred to as an inverse transform dequantized block 213 or an inverse transform residual block 213.
  • the reconstruction unit 214 (eg, summer 214) is used to add the inverse transform block 213 (ie, the reconstructed residual block 213) to the prediction block 265 to obtain the reconstructed block 215 in the sample domain, for example, The sample values of the reconstructed residual block 213 and the sample values of the prediction block 265 are added.
  • a buffer unit 216 (or simply "buffer" 216), such as a line buffer 216, is used to buffer or store the reconstructed block 215 and corresponding sample values for, for example, intra prediction.
  • the encoder may be used to use the unfiltered reconstructed blocks and / or corresponding sample values stored in the buffer unit 216 for any type of estimation and / or prediction, such as intra prediction.
  • an embodiment of the encoder 20 may be configured such that the buffer unit 216 is used not only for storing the reconstructed block 215 for intra prediction 254, but also for the loop filter unit 220 (not shown in FIG. 2) Out), and / or, for example, causing the buffer unit 216 and the decoded picture buffer unit 230 to form a buffer.
  • Other embodiments may be used to use the filtered block 221 and / or blocks or samples from the decoded picture buffer 230 (neither shown in FIG. 2) as an input or basis for intra prediction 254.
  • the loop filter unit 220 (or simply "loop filter” 220) is used to filter the reconstructed block 215 to obtain the filtered block 221, thereby smoothly performing pixel conversion or improving video quality.
  • the loop filter unit 220 is intended to represent one or more loop filters, such as deblocking filters, sample-adaptive offset (SAO) filters, or other filters, such as bilateral filters, Adaptive loop filter (adaptive loop filter, ALF), or sharpening or smoothing filter, or collaborative filter.
  • the loop filter unit 220 is shown as an in-loop filter in FIG. 2, in other configurations, the loop filter unit 220 may be implemented as a post-loop filter.
  • the filtered block 221 may also be referred to as the filtered reconstructed block 221.
  • the decoded picture buffer 230 may store the reconstructed coding block after the loop filter unit 220 performs a filtering operation on the reconstructed coding block.
  • Embodiments of the encoder 20 may be used to output loop filter parameters (eg, sample adaptive offset information), for example, directly output or by the entropy encoding unit 270 or any other
  • the entropy coding unit outputs after entropy coding, for example, so that the decoder 30 can receive and apply the same loop filter parameters for decoding.
  • the decoded picture buffer (DPB) 230 may be a reference picture memory for storing reference picture data for the video encoder 20 to encode video data.
  • DPB 230 can be formed by any of a variety of memory devices, such as dynamic random access memory (dynamic random access (DRAM) (including synchronous DRAM (synchronous DRAM, SDRAM), magnetoresistive RAM (magnetoresistive RAM, MRAM), resistive RAM (resistive RAM, RRAM)) or other types of memory devices.
  • DRAM dynamic random access
  • the DPB 230 and the buffer 216 may be provided by the same memory device or separate memory devices.
  • a decoded picture buffer (DPB) 230 is used to store the filtered block 221.
  • the decoded picture buffer 230 may be further used to store other previous filtered blocks of the same current picture or different pictures such as previous reconstructed pictures, such as the previously reconstructed and filtered block 221, and may provide the complete previous The reconstructed ie decoded pictures (and corresponding reference blocks and samples) and / or partially reconstructed current pictures (and corresponding reference blocks and samples), for example for inter prediction.
  • a decoded picture buffer (DPB) 230 is used to store the reconstructed block 215.
  • the prediction processing unit 260 also known as the block prediction processing unit 260, is used to receive or acquire the block 203 (the current block 203 of the current picture 201) and the reconstructed picture data, such as the reference of the same (current) picture from the buffer 216 Samples and / or reference picture data 231 of one or more previously decoded pictures from the decoded picture buffer 230, and used to process such data for prediction, that is, to provide an inter prediction block 245 or an intra frame The prediction block 265 of the prediction block 255.
  • the mode selection unit 262 may be used to select a prediction mode (eg, intra or inter prediction mode) and / or the corresponding prediction block 245 or 255 used as the prediction block 265 to calculate the residual block 205 and reconstruct the reconstructed block 215.
  • a prediction mode eg, intra or inter prediction mode
  • / or the corresponding prediction block 245 or 255 used as the prediction block 265 to calculate the residual block 205 and reconstruct the reconstructed block 215.
  • An embodiment of the mode selection unit 262 may be used to select a prediction mode (eg, from those prediction modes supported by the prediction processing unit 260), which provides the best match or the minimum residual (the minimum residual means Better compression in transmission or storage), or provide minimum signaling overhead (minimum signaling overhead means better compression in transmission or storage), or consider or balance both at the same time.
  • the mode selection unit 262 may be used to determine a prediction mode based on rate distortion optimization (RDO), that is, to select a prediction mode that provides minimum bit rate distortion optimization, or to select a prediction mode in which the related rate distortion at least meets the prediction mode selection criteria .
  • RDO rate distortion optimization
  • the encoder 20 is used to determine or select the best or optimal prediction mode from the (predetermined) prediction mode set.
  • the set of prediction modes may include, for example, intra prediction modes and / or inter prediction modes.
  • the intra prediction mode set may include 35 different intra prediction modes, for example, non-directional modes such as DC (or mean) mode and planar mode, or directional modes as defined in H.265, or may include 67 Different intra prediction modes, for example, non-directional modes such as DC (or mean) mode and planar mode, or directional modes as defined in the developing H.266.
  • non-directional modes such as DC (or mean) mode and planar mode
  • directional modes as defined in the developing H.266.
  • the set of inter prediction modes depends on the available reference pictures (ie, for example, the aforementioned at least partially decoded pictures stored in the DBP 230) and other inter prediction parameters, such as whether the entire reference picture is used or only the reference is used A part of the picture, for example a search window area surrounding the area of the current block, to search for the best matching reference block, and / or for example depending on whether pixel interpolation such as half-pixel and / or quarter-pixel interpolation is applied.
  • the available reference pictures ie, for example, the aforementioned at least partially decoded pictures stored in the DBP 230
  • other inter prediction parameters such as whether the entire reference picture is used or only the reference is used
  • a part of the picture for example a search window area surrounding the area of the current block, to search for the best matching reference block, and / or for example depending on whether pixel interpolation such as half-pixel and / or quarter-pixel interpolation is applied.
  • skip mode and / or direct mode can also be applied.
  • the prediction processing unit 260 may be further used to split the block 203 into smaller block partitions or sub-blocks, for example, by iteratively using quad-tree (QT) splitting, binary-tree (BT) splitting, or trident Tree (triple-tree or alternative-tree, TT) partitioning, or any combination thereof, and for performing predictions for each of block partitions or sub-blocks, for example, where mode selection includes selecting the tree structure and selection of the partitioned block 203 The prediction mode applied to each of the block partitions or sub-blocks.
  • QT quad-tree
  • BT binary-tree
  • TT trident Tree
  • the inter prediction unit 244 may include a motion estimation (ME) unit (not shown in FIG. 2) and a motion compensation (MC) unit (not shown in FIG. 2).
  • the motion estimation unit is used to receive or acquire the picture block 203 (current picture block 203 of the current picture 201) and the decoded picture 231, or at least one or more previously reconstructed blocks, for example, one or more other / different previous warp
  • the reconstructed block of the picture 231 is decoded to perform motion estimation.
  • the video sequence may include the current picture and the previously decoded picture 31, or in other words, the current picture and the previously decoded picture 31 may be part of or form a sequence of pictures that form the video sequence.
  • the encoder 20 may be used to select a reference block from multiple reference blocks of the same or different pictures in multiple other pictures and provide a reference picture (or reference picture index) to a motion estimation unit (not shown in FIG. 2) ) And / or provide an offset (spatial offset) between the position of the reference block (X, Y coordinates) and the position of the current block (spatial offset) as an inter prediction parameter.
  • This offset is also called motion vector (MV).
  • the motion compensation unit is used to acquire, for example, receive inter prediction parameters, and perform inter prediction based on or using inter prediction parameters to obtain inter prediction blocks 245.
  • the motion compensation performed by the motion compensation unit may include extracting or generating a prediction block based on a motion / block vector determined by motion estimation (possibly performing interpolation of sub-pixel accuracy). Interpolation filtering can generate additional pixel samples from known pixel samples, potentially increasing the number of candidate prediction blocks that can be used to encode picture blocks.
  • the motion compensation unit 246 may locate the prediction block pointed to by the motion vector in a reference picture list. Motion compensation unit 246 may also generate syntax elements associated with blocks and video slices for use by video decoder 30 when decoding picture blocks of video slices.
  • the intra prediction unit 254 is used to acquire, for example, a picture block 203 (current picture block) that receives the same picture and one or more previously reconstructed blocks, such as reconstructed neighboring blocks, for intra estimation.
  • the encoder 20 may be used to select an intra prediction mode from a plurality of (predetermined) intra prediction modes.
  • Embodiments of the encoder 20 may be used to select an intra-prediction mode based on optimization criteria, for example, based on a minimum residual (eg, an intra-prediction mode that provides the prediction block 255 that is most similar to the current picture block 203) or minimum rate distortion.
  • a minimum residual eg, an intra-prediction mode that provides the prediction block 255 that is most similar to the current picture block 203
  • minimum rate distortion e.g, a minimum rate distortion.
  • the intra prediction unit 254 is further used to determine the intra prediction block 255 based on the intra prediction parameters of the intra prediction mode as selected. In any case, after selecting the intra-prediction mode for the block, the intra-prediction unit 254 is also used to provide the intra-prediction parameters to the entropy encoding unit 270, that is, to provide the selected intra-prediction mode for the block. Information. In one example, the intra prediction unit 254 may be used to perform any combination of intra prediction techniques described below.
  • the entropy coding unit 270 is used to encode an entropy coding algorithm or scheme (for example, variable length coding (VLC) scheme, context adaptive VLC (context adaptive VLC, CAVLC) scheme, arithmetic coding scheme, context adaptive binary arithmetic) Encoding (context adaptive) binary arithmetic coding (CABAC), syntax-based context-adaptive binary arithmetic coding (SBAC), probability interval entropy (probability interval interpartitioning entropy, PIPE) encoding or other entropy Encoding method or technique) applied to a single or all of the quantized residual coefficients 209, inter prediction parameters, intra prediction parameters, and / or loop filter parameters (or not applied) to obtain
  • VLC variable length coding
  • CABAC context adaptive binary arithmetic
  • SBAC syntax-based context-adaptive binary arithmetic coding
  • PIPE probability interval entropy encoding or other entropy Encoding method or technique
  • the encoded bitstream can be transmitted to the video decoder 30 or archived for later transmission or retrieval by the video decoder 30.
  • the entropy encoding unit 270 may also be used to entropy encode other syntax elements of the current video slice being encoded.
  • video encoder 20 may be used to encode video streams.
  • the non-transform based encoder 20 may directly quantize the residual signal without the transform processing unit 206 for certain blocks or frames.
  • the encoder 20 may have a quantization unit 208 and an inverse quantization unit 210 combined into a single unit.
  • FIG. 3 shows an exemplary video decoder 30 for implementing the technology of the present application.
  • the video decoder 30 is used to receive encoded picture data (eg, encoded bitstream) 21, for example, encoded by the encoder 20, to obtain a decoded picture 231.
  • encoded picture data eg, encoded bitstream
  • video decoder 30 receives video data from video encoder 20, such as an encoded video bitstream and associated syntax elements representing picture blocks of the encoded video slice.
  • the decoder 30 includes an entropy decoding unit 304, an inverse quantization unit 310, an inverse transform processing unit 312, a reconstruction unit 314 (such as a summer 314), a buffer 316, a loop filter 320, a The decoded picture buffer 330 and the prediction processing unit 360.
  • the prediction processing unit 360 may include an inter prediction unit 344, an intra prediction unit 354, and a mode selection unit 362.
  • video decoder 30 may perform a decoding pass that is generally reciprocal to the encoding pass described with reference to video encoder 20 of FIG. 2.
  • the entropy decoding unit 304 is used to perform entropy decoding on the encoded picture data 21 to obtain, for example, quantized coefficients 309 and / or decoded encoding parameters (not shown in FIG. 3), for example, inter prediction, intra prediction parameters , Any or all of the loop filter parameters and / or other syntax elements (decoded).
  • the entropy decoding unit 304 is further used to forward the inter prediction parameters, intra prediction parameters, and / or other syntax elements to the prediction processing unit 360.
  • Video decoder 30 may receive syntax elements at the video slice level and / or the video block level.
  • the inverse quantization unit 310 can be functionally the same as the inverse quantization unit 110
  • the inverse transform processing unit 312 can be functionally the same as the inverse transform processing unit 212
  • the reconstruction unit 314 can be functionally the same as the reconstruction unit 214
  • the buffer 316 can be functionally
  • the loop filter 320 may be functionally the same as the loop filter 220
  • the decoded picture buffer 330 may be functionally the same as the decoded picture buffer 230.
  • the prediction processing unit 360 may include an inter prediction unit 344 and an intra prediction unit 354, where the inter prediction unit 344 may be similar in function to the inter prediction unit 244, and the intra prediction unit 354 may be similar in function to the intra prediction unit 254 .
  • the prediction processing unit 360 is generally used to perform block prediction and / or obtain the prediction block 365 from the encoded data 21, and receive or obtain prediction-related parameters and / or information about the entropy decoding unit 304 (explicitly or implicitly). Information about the selected prediction mode.
  • the intra prediction unit 354 of the prediction processing unit 360 is used to signal-based the intra prediction mode and the previous decoded block from the current frame or picture. Data to generate a prediction block 365 for the picture block of the current video slice.
  • the inter prediction unit 344 eg, motion compensation unit
  • Other syntax elements generate a prediction block 365 for the video block of the current video slice.
  • a prediction block may be generated from a reference picture in a reference picture list.
  • the video decoder 30 may construct the reference frame lists: list 0 and list 1 using default construction techniques based on the reference pictures stored in the DPB 330.
  • the prediction processing unit 360 is used to determine the prediction information for the video block of the current video slice by parsing the motion vector and other syntax elements, and use the prediction information to generate the prediction block for the current video block being decoded. For example, the prediction processing unit 360 uses some received syntax elements to determine the prediction mode (eg, intra or inter prediction) of the video block used to encode the video slice, the inter prediction slice type (eg, B slice, P slice or GPB slice), construction information of one or more of the reference picture lists for slices, motion vectors for each inter-coded video block for slices, each warp for slices The inter prediction status and other information of the inter-coded video block to decode the video block of the current video slice.
  • the prediction mode eg, intra or inter prediction
  • the inter prediction slice type eg, B slice, P slice or GPB slice
  • construction information of one or more of the reference picture lists for slices motion vectors for each inter-coded video block for slices, each warp for slices
  • the inter prediction status and other information of the inter-coded video block
  • the inverse quantization unit 310 may be used to inverse quantize (ie, inverse quantize) the quantized transform coefficients provided in the bitstream and decoded by the entropy decoding unit 304.
  • the inverse quantization process may include using the quantization parameters calculated by the video encoder 20 for each video block in the video slice to determine the degree of quantization that should be applied and also determine the degree of inverse quantization that should be applied.
  • the inverse transform processing unit 312 is used to apply an inverse transform (eg, inverse DCT, inverse integer transform, or conceptually similar inverse transform process) to the transform coefficients, so as to generate a residual block in the pixel domain.
  • an inverse transform eg, inverse DCT, inverse integer transform, or conceptually similar inverse transform process
  • the reconstruction unit 314 (for example, the summer 314) is used to add the inverse transform block 313 (ie, the reconstructed residual block 313) to the prediction block 365 to obtain the reconstructed block 315 in the sample domain, for example, by adding The sample values of the reconstructed residual block 313 and the sample values of the prediction block 365 are added.
  • the loop filter unit 320 (during the encoding loop or after the encoding loop) is used to filter the reconstructed block 315 to obtain the filtered block 321 to smoothly perform pixel conversion or improve video quality.
  • the loop filter unit 320 may be used to perform any combination of filtering techniques described below.
  • the loop filter unit 320 is intended to represent one or more loop filters, such as deblocking filters, sample-adaptive offset (SAO) filters, or other filters, such as bilateral filters, Adaptive loop filter (adaptive loop filter, ALF), or sharpening or smoothing filter, or collaborative filter.
  • the loop filter unit 320 is shown as an in-loop filter in FIG. 3, in other configurations, the loop filter unit 320 may be implemented as a post-loop filter.
  • the decoded video block 321 in a given frame or picture is then stored in a decoded picture buffer 330 that stores reference pictures for subsequent motion compensation.
  • the decoder 30 is used, for example, to output the decoded picture 31 through the output 332 for presentation to the user or for the user to view.
  • video decoder 30 may be used to decode the compressed bitstream.
  • the decoder 30 may generate the output video stream without the loop filter unit 320.
  • the non-transform based decoder 30 may directly inversely quantize the residual signal without the inverse transform processing unit 312 for certain blocks or frames.
  • the video decoder 30 may have an inverse quantization unit 310 and an inverse transform processing unit 312 combined into a single unit.
  • the video encoding system 40 may include an imaging device 41, a video encoder 20, a video decoder 30 (and / or a video encoder implemented by the logic circuit 47 of the processing unit 46), an antenna 42, One or more processors 43, one or more memories 44, and / or display devices 45.
  • the imaging device 41, the antenna 42, the processing unit 46, the logic circuit 47, the video encoder 20, the video decoder 30, the processor 43, the memory 44, and / or the display device 45 can communicate with each other.
  • video encoding system 40 is shown with video encoder 20 and video decoder 30, in different examples, video encoding system 40 may include only video encoder 20 or only video decoder 30.
  • the video encoding system 40 may include an antenna 42.
  • the antenna 42 may be used to transmit or receive an encoded bit stream of video data.
  • the video encoding system 40 may include a display device 45.
  • the display device 45 may be used to present video data.
  • the logic circuit 47 may be implemented by the processing unit 46.
  • the processing unit 46 may include application-specific integrated circuit (ASIC) logic, a graphics processor, a general-purpose processor, and the like.
  • the video encoding system 40 may also include an optional processor 43, which may similarly include application-specific integrated circuit (ASIC) logic, a graphics processor, a general-purpose processor, and the like.
  • ASIC application-specific integrated circuit
  • the logic circuit 47 may be implemented by hardware, such as dedicated hardware for video encoding, etc., and the processor 43 may be implemented by general-purpose software, an operating system, or the like.
  • the memory 44 may be any type of memory, such as volatile memory (for example, static random access memory (Static Random Access Memory, SRAM), dynamic random access memory (Dynamic Random Access Memory, DRAM), etc.) or non-volatile Memory (for example, flash memory, etc.), etc.
  • the memory 44 may be implemented by cache memory.
  • the logic circuit 47 can access the memory 44 (eg, to implement an image buffer).
  • the logic circuit 47 and / or the processing unit 46 may include memory (eg, cache, etc.) for implementing image buffers and the like.
  • the video encoder 20 implemented by logic circuits may include an image buffer (eg, implemented by the processing unit 46 or the memory 44) and a graphics processing unit (eg, implemented by the processing unit 46).
  • the graphics processing unit may be communicatively coupled to the image buffer.
  • the graphics processing unit may include the video encoder 20 implemented by a logic circuit 47 to implement the various modules discussed with reference to FIG. 2 and / or any other encoder system or subsystem described herein.
  • Logic circuits can be used to perform the various operations discussed herein.
  • Video decoder 30 may be implemented by logic circuit 47 in a similar manner to implement the various modules discussed with reference to decoder 30 of FIG. 3 and / or any other decoder systems or subsystems described herein.
  • the video decoder 30 implemented by the logic circuit may include an image buffer (implemented by the processing unit 2820 or the memory 44) and a graphics processing unit (for example, implemented by the processing unit 46).
  • the graphics processing unit may be communicatively coupled to the image buffer.
  • the graphics processing unit may include a video decoder 30 implemented by a logic circuit 47 to implement various modules discussed with reference to FIG. 3 and / or any other decoder systems or subsystems described herein.
  • the antenna 42 of the video encoding system 40 may be used to receive the encoded bitstream of video data.
  • the encoded bitstream may include data related to encoded video frames, indicators, index values, mode selection data, etc. discussed herein, such as data related to encoded partitions (eg, transform coefficients or quantized transform coefficients , (As discussed) optional indicators, and / or data that defines the code segmentation).
  • the video encoding system 40 may also include a video decoder 30 coupled to the antenna 42 and used to decode the encoded bitstream.
  • the display device 45 is used to present video frames.
  • FIG. 5 is a simplified block diagram of an apparatus 500 that can be used as either or both of the source device 12 and the destination device 14 in FIG. 1 according to an exemplary embodiment.
  • the apparatus 500 may implement the technology of the present application.
  • the apparatus 500 may take the form of a computing system including multiple computing devices, or a single computing device such as a mobile phone, tablet computer, laptop computer, notebook computer, desktop computer, or the like.
  • the processor 502 in the device 500 may be a central processor.
  • the processor 502 may be any other type of device or multiple devices that can manipulate or process information currently or will be developed in the future.
  • a single processor such as processor 502 may be used to practice the disclosed embodiments, the use of more than one processor may achieve advantages in speed and efficiency.
  • the memory 504 in the apparatus 500 may be a read-only memory (Read Only Memory, ROM) device or a random access memory (random access memory, RAM) device. Any other suitable type of storage device may be used as the memory 504.
  • the memory 504 may include code and data 506 accessed by the processor 502 using the bus 512.
  • the memory 504 may further include an operating system 508 and application programs 510, the application programs 510 including at least one program that permits the processor 502 to perform the methods described herein.
  • the application program 510 may include applications 1 to N, and the applications 1 to N further include video encoding applications that perform the methods described herein.
  • the apparatus 500 may also include additional memory in the form of a secondary memory 514, which may be, for example, a memory card used with a mobile computing device. Because the video communication session may contain a large amount of information, the information may be stored in whole or in part in the secondary memory 514 and loaded into the memory 504 as needed for processing.
  • a secondary memory 514 may be, for example, a memory card used with a mobile computing device. Because the video communication session may contain a large amount of information, the information may be stored in whole or in part in the secondary memory 514 and loaded into the memory 504 as needed for processing.
  • Device 500 may also include one or more output devices, such as display 518.
  • the display 518 may be a touch-sensitive display that combines a display and a touch-sensitive element operable to sense touch input.
  • the display 518 may be coupled to the processor 502 through the bus 512.
  • other output devices that allow the user to program the device 500 or otherwise use the device 500 or provide other output devices as an alternative to the display 518 may be provided.
  • the display can be implemented in different ways, including through a liquid crystal display (liquid crystal) display (LCD), a cathode-ray tube (CRT) display, a plasma display or a light emitting diode (light emitting diode) diode (LED) display, such as organic LED (organic LED, OLED) display.
  • LCD liquid crystal display
  • CTR cathode-ray tube
  • plasma display or a light emitting diode (light emitting diode) diode (LED) display, such as organic LED (organic LED, OLED) display.
  • OLED organic LED
  • the apparatus 500 may also include or be in communication with an image sensing device 520, such as a camera or any other image sensing device 520 that can sense an image, such as a camera or an existing or future development It is an image of the user who runs the device 500.
  • the image sensing device 520 may be placed to directly face the user who runs the device 500.
  • the position and optical axis of the image sensing device 520 can be configured so that its field of view includes an area immediately adjacent to the display 518 and the display 518 is visible from the area.
  • the device 500 may also include or be in communication with a sound sensing device 522, such as a microphone or any other sound sensing device that can sense sound in the vicinity of the device 500, either existing or to be developed in the future.
  • the sound sensing device 522 may be placed to directly face the user who runs the apparatus 500, and may be used to receive sounds made by the user when the apparatus 500 is operated, such as voice or other utterances.
  • the processor 502 and the memory 504 of the device 500 are illustrated in FIG. 5 as being integrated in a single unit, other configurations may also be used.
  • the operation of the processor 502 may be distributed among multiple directly-coupled machines (each machine has one or more processors), or distributed in a local area or other network.
  • the memory 504 may be distributed among multiple machines, such as a network-based memory or a memory among multiple machines running the device 500. Although only a single bus is shown here, the bus 512 of the device 500 may be formed by multiple buses.
  • the slave memory 514 may be directly coupled to other components of the device 500 or may be accessed through a network, and may include a single integrated unit, such as one memory card, or multiple units, such as multiple memory cards. Therefore, the device 500 can be implemented in various configurations.
  • DCT2 matrix can also be abbreviated as DCT2
  • DCT2 'matrix can also be abbreviated as DCT2
  • DST4 matrix can also be abbreviated as DST4
  • DCT2'FS matrix can also be abbreviated as DCT2'FS
  • DCT2'F matrix can also be abbreviated as DCT2'F
  • DST7 matrix can also be abbreviated as DST7.
  • FIG. 6 is a schematic flowchart of a reverse video encoding method according to an embodiment of the present application. The method shown in FIG. 6 includes steps 1001 to 1005, and steps 1001 to 1005 will be described in detail below.
  • step 1001 after the code stream is obtained, the quantization coefficient of the current block and the target transform matrix pair index value can be obtained by performing operations such as entropy decoding on the code stream.
  • the prediction mode corresponding to the current block can also be obtained by performing operations such as entropy decoding on the code stream.
  • 1003 Determine a target transformation matrix pair from the candidate transformation matrix pair according to the target transformation matrix pair index value and the correspondence between the target transformation matrix pair index value and the candidate transformation matrix pair.
  • the candidate transformation matrix pair includes a horizontal transformation matrix and a vertical transformation matrix.
  • the horizontal transformation matrix and the vertical transformation matrix are both one of two preset transformation matrices.
  • the first transformation matrix is the DCT2 'matrix, and the DCT2' matrix is the transposed matrix of the DCT2 matrix.
  • the candidate transformation matrix pairs may include the following specific transformation matrix pairs:
  • the first transformation matrix and the second transformation matrix in parentheses may be a vertical transformation matrix and a horizontal transformation matrix, respectively.
  • the above transformation matrix B may be DCT2 '.
  • the target transformation matrix pair may be one of the above four transformation matrix pairs (specifically, which transformation matrix pair of the candidate transformation matrix pair may be based on the target transformation matrix pair index value and the target transformation matrix pair index value and the candidate transformation matrix pair To determine the correspondence between them).
  • the DCT8 matrix / DCT4 matrix in the prior art is replaced by the DCT2 'matrix (the DCT8 matrix / DCT4 matrix does not have a fast algorithm). It is possible to further simplify the transformation / inverse transformation of the DCT2 'matrix.
  • the DCT2'matrix is a transposition of the DCT2 matrix, the DCT2' matrix can multiplex the DCT2 matrix inverse transform implementation circuit (such as a multiplier), which can improve the utilization efficiency of the hardware circuit.
  • the 4x4 DCT2 matrix is as follows:
  • the 4x4 DCT2’ matrix is as follows:
  • the corresponding relationship (also called mapping relationship) between the index value of the target transformation matrix pair and the candidate transformation matrix pair can be shown in Table 1, where DCT2 'is the first transformation matrix among the two preset transformation matrices , Transformation matrix A is the second transformation matrix among the two preset transformation matrices.
  • the decoding end may determine the target transformation matrix pair according to the correspondence shown in Table 1. For example, if the decoding end obtains the target transform matrix pair index value by parsing the code stream, then the decoding end can determine that the target transform matrix pair consists of the transform matrix A and the DCT2 'matrix according to the correspondence shown in Table 1, where, Transformation matrix A is the vertical transformation matrix in the target transformation matrix pair, and DCT2 'is the horizontal transformation matrix in the target transformation matrix pair.
  • Table 1 is only a specific form of the correspondence between the target transformation matrix pair index value and the candidate transformation matrix pair (the candidate transformation matrix pair corresponding to each index value is also only an example).
  • the target The correspondence between the transformation matrix pair index value and the candidate transformation matrix pair is not limited to the specific form shown in Table 1.
  • the correspondence relationship between the target transformation matrix pair index value and the candidate transformation matrix pair can also be expressed in other forms than the table , This application does not limit this.
  • the value of the index value of the target transformation matrix in Table 1 is only a specific case. This application does not limit which transformation matrix corresponds to when the target transformation matrix specifically takes a certain value for the index value.
  • the table of the correspondence between the target transformation matrix pair index value and the candidate transformation matrix pair is only a specific case, and the representation form of the correspondence relationship between the target transformation matrix pair index value and the candidate transformation matrix pair is not limited to the table in this application. Representation).
  • the inverse transform can be performed according to formula (1) to obtain the residual block R.
  • A is the horizontal transformation matrix
  • B is the vertical transformation matrix
  • B represents the transposed matrix of matrix B. Since B is an orthogonal matrix, transposing B is equivalent to finding the inverse matrix of B.
  • the fast algorithm can be used when the DCT2 'is used for the inverse transformation, which can reduce the calculation complexity of the inverter process degree.
  • DCT2' since the DCT2 'matrix is a transpose of the DCT2 matrix, in the process of inverse transformation, DCT2' can reuse the inverse transformation realization circuit of DCT2, which can reduce the hardware implementation cost.
  • the DCT2 'matrix is derived from the DCT2 matrix.
  • the decoding end can store the matrix coefficients of the DCT2 matrix or the DCT2 matrix in advance. When inverse transformation is required, the decoding end can derive the matrix coefficients of the DCT2 'matrix from the matrix coefficients in the DCT2 matrix.
  • the matrix coefficients of the DCT2' matrix can be derived from the matrix coefficients of the DCT2 without additional storage of the matrix coefficients of the DCT2 'matrix, which can reduce storage overhead.
  • the 4x4 DCT2 matrix is as follows:
  • the second one of the preset two transformation matrices is a DCT2'FS matrix or a DCT2'F matrix.
  • F in the DCT2'FS matrix and DCT2'F matrix represent mirror images
  • S in the DCT2'FS matrix represents symbol transformation
  • the DCT2'F matrix is a matrix obtained by mirroring the DCT2 'matrix
  • the DCT2'FS matrix is a matrix obtained by mirroring the DCT2' matrix and then performing symbol conversion on the mirrored matrix.
  • the above-mentioned mirror image may be a left-right mirror image.
  • Flipping a mirror image to the right and left of a matrix may refer to mirroring the matrix coefficients on the left side of the matrix to the right and mirroring the matrix coefficients on the right side of the matrix to the left.
  • the above-mentioned symbol transformation means that only the matrix coefficients of the even rows of the matrix are inverted, and the matrix coefficients of the odd rows of the matrix remain unchanged.
  • the above-mentioned symbol transformation means that only the matrix coefficients of odd rows of the matrix are inverted, and the matrix coefficients of even rows of the matrix remain unchanged.
  • the above sign transformation is to reverse the sign of all matrix coefficients in the matrix.
  • the first one of the two preset transformation matrices is a DCT2 'matrix
  • the second matrix is a DCT2'FS matrix or a DCT2'F matrix, which is applicable to all transformation sizes (for example, the transformation size here can be Including 4 o'clock, 8 o'clock, 16 o'clock and 32 o'clock, etc.).
  • the corresponding relationship between the index value of the target transformation matrix pair and the candidate transformation matrix pair can be as shown in Table 2 As shown.
  • Transformation matrix Fast algorithm Number of multiplications required for transformation 32-point DCT2’FS matrix ODD16 + ODD8 + ODD4 + ODD2 16x16 + 8x8 + 4x4 + 2x2 16-point DCT2’FS matrix ODD8 + ODD4 + ODD2 8x8 + 4x4 + 2x2 8-point DCT2’FS matrix ODD4 + ODD2 4x4 + 2x2 4-point DCT2’FS matrix ODD2 2x2 32-point DCT2 'matrix ODD16 + ODD8 + ODD4 + ODD2 16x16 + 8x8 + 4x4 + 2x2 16-point DCT2 'matrix ODD8 + ODD4 + ODD2 8x8 + 4x4 + 2x2 8-point DCT2 'matrix ODD4 + ODD2 4x4 + 2x2 4 point DCT2 'matrix ODD4 + ODD2 4x4 + 2x2 4 point DCT2 'matrix ODD
  • the horizontal transform matrix in the target transform matrix pair is a DCT2 'matrix
  • the vertical transform matrix in the target transform matrix pair is a DCT2'FS matrix or DCT2'F matrix
  • the vertical transformation matrix in the target transformation matrix pair is a DST4 matrix, where M is a positive integer.
  • the vertical transform matrix in the target transform matrix pair is a DCT2 'matrix.
  • the horizontal transform matrix in the target transform matrix pair is a DCT2'FS matrix or DCT2'F matrix; when the height of the current block is less than M points, the horizontal transformation matrix in the target transformation matrix pair is a DST4 matrix, where M is a positive integer.
  • the above M may be 32.
  • the transformation matrix with a fast algorithm is used as the horizontal transformation matrix or the vertical transformation matrix in the target transformation matrix pair in the large-size transformation scene
  • the transformation matrix suitable for the small-size transformation scene is used as the target in the small-size transformation scene
  • the horizontal transformation matrix or the vertical transformation matrix in the transformation matrix pair can significantly reduce the complexity of inverse transformation in large-scale transformation scenes, and at the same time can ensure transformation performance in small-size scenes. It can reduce the complexity of inverse transformation and Ensure a balance between inverse transformation performance.
  • the target transform matrix pair may be composed of a DCT2 'matrix and a DCT2'FS matrix (or DCT2'F matrix).
  • the target transform matrix pair index value and candidate The correspondence between transformation matrix pairs can be shown in Table 4.
  • the candidate transformation matrix pair may be composed of a DCT2 'matrix and a DST4 matrix.
  • the correspondence between the target transformation matrix pair index value and the candidate transformation matrix pair may be as follows Table 5 shows.
  • the second one of the preset two transformation matrices is derived from the DCT2 matrix.
  • the second one of the preset two transformation matrices can be derived from the DCT2 matrix, it is not necessary to additionally store the matrix coefficients of the second transformation matrix, which can reduce storage overhead.
  • DCT2'FS matrix, DCT2'F matrix, and DST4 matrix can be derived from the DCT2 matrix, it is not necessary to additionally store the matrix coefficients of these matrices, which can reduce storage overhead.
  • a DCT2'FS matrix for a DCT2'FS matrix, a DCT2'F matrix, and a DST4 matrix, whether it is a 32-point matrix or a matrix with a smaller size, it can be derived from a 64-point DCT2 transformation matrix.
  • a 32-point DCT2'FS matrix you can first obtain a 32-point DCT2 'transformation matrix according to the 32-point DCT2 matrix, and then mirror and sign transform the 32-point DCT2' matrix to obtain DCT2'FS (
  • the 32-point DCT2'F matrix can be obtained only by mirroring the DCT2 'matrix).
  • a DCT4 matrix can be extracted from a 32 (or 16, 8, 8) point DCT2 matrix, and then the DST4 matrix can be obtained through operations such as mirroring and symbol transformation.
  • the two preset transformation matrices may be DCT2 'and DCT2'FS matrix (or DCT2'F matrix); when the transformation size is less than 32, the two preset The transformation matrix may be a DCT2 'matrix and a DST4 matrix.
  • the 4x4 DCT2 matrix is as follows:
  • the 4x4 DCT2 ’matrix can be obtained first.
  • the obtained 4x4 DCT2’ matrix is as follows:
  • the matrix coefficients of the 4x4 DCT2’ matrix can be flipped left and right to obtain the 4x4 DCT2’F.
  • the 4x4 DCT2’F matrix is as follows:
  • the second one of the preset two transformation matrices is DCT2'F
  • the second one of the two preset transformation matrices is obtained through the above-mentioned derivation process.
  • the above 4x4 DCT2'F matrix can be symbolically transformed to obtain a 4x4 DCT2'FS matrix.
  • the 4x4 DCT2'FS matrix is as follows :
  • this application adopts the DCT2 'matrix and DCT2'FS matrix as the target transformation matrix pair in the large-scale scene, and uses the DCT2' matrix and DST4 matrix as the target transformation matrix pair in the small-scale scene to reduce the computational complexity
  • the effect of the target transformation matrix pair is composed of DCT2 'matrix and DST4 matrix (at 4-16 points), and the target transformation matrix pair is composed of DCT2' matrix and DCT2'FS matrix (at 32 points) as an example.
  • the calculation complexity is analyzed, and the analysis results are shown in Table 6.
  • Transformation matrix Fast algorithm Number of multiplications required for transformation 32-point DCT2’FS matrix ODD16 + ODD8 + ODD4 + ODD2 16x16 + 8x8 + 4x4 + 2x2 4-16 points DST4 matrix No fast algorithm, use matrix multiplication 16x16x16 + 8x8x8 + 4x4x4 32-point DCT2 'matrix ODD16 + ODD8 + ODD4 + ODD2 16x16 + 8x8 + 4x4 + 2x2 16-point DCT2 'matrix ODD8 + ODD4 + ODD2 8x8 + 4x4 + 2x2 8-point DCT2 'matrix ODD4 + ODD2 4x4 + 2x2 4 point DCT2 'matrix ODD2 2x2
  • the matrix multiplication size does not exceed 16x16, which greatly reduces the number of multiplications, and thus largely Reduced computational complexity.
  • the DCT2 'matrix may be a 32x32 matrix
  • the DCT2'F matrix may be a 32x32 matrix
  • the 32 ⁇ 32 DCT2 ’matrix is as follows:
  • the 32 ⁇ 32 DCT2’F matrix is as follows:
  • the coefficients of the first row of the DCT2 'matrix are arranged from large to small (except for the first coefficient), which is close to or similar to the ranking rule of the coefficients of the first row of the DCT8 matrix / DCT4 matrix.
  • the coefficients of the first row of the DCT2'F matrix are arranged from small to large (except for the last coefficient), which is close to or similar to the ranking rule of the coefficients of the first row of the DST7 matrix / DST4 matrix. Therefore, in the embodiments of the present application, by using a transformation matrix similar to the transformation matrix used in the existing scheme, it is possible to ensure that the performance loss is small during the transformation / inverse transformation process.
  • the transformation matrix in the target transformation matrix pair can Derived.
  • the target transform matrix pair is composed of a DCT2 'matrix and a DCT2'FS matrix (or DCT2'F matrix).
  • the target transform matrix The performance of the DCT2 'matrix and the DST4 matrix is tested. Compared with the DCT8 matrix and the DST7 matrix in the existing solution, the test performance of this application is shown in Table 7 and Table 8.
  • Table 7 is the test result obtained under the condition of the intra prediction mode
  • Table 8 is the test result obtained under the condition of the random access mode (either intra prediction or inter prediction can be used during prediction).
  • Y represents the luminance component of the video image
  • U / V represents the chrominance component of the video image
  • the value below Y / U / V represents the percentage of increase in coded bits under the same video image quality
  • the negative value represents the decrease in coded bits.
  • EncT and DecT represent the encoding and decoding time, respectively.
  • the present application can simplify the calculation process, reduce codec time, and improve codec efficiency.
  • the DST7 matrix or DST4 matrix may also be set as the transformation matrix in the target transformation matrix pair.
  • the horizontal transform matrix in the target transform matrix pair is a DCT2 'matrix, and when the height of the current block is greater than or equal to N points, the vertical transform matrix in the target transform matrix pair is a DST7 matrix; in the current When the height of the block is less than N points, the vertical transformation matrix in the target transformation matrix pair is a DST4 matrix, where N is a positive integer.
  • the vertical transformation matrix in the target transformation matrix pair is a DCT2 'matrix.
  • the horizontal transformation matrix in the target transformation matrix pair is a DST7 matrix; in the current When the width of the block is less than N points, the horizontal transformation matrix in the target transformation matrix pair is a DST4 matrix, where N is a positive integer.
  • N 16.
  • the transformation size when the transformation size is greater than or equal to N points, it may be regarded as a large-size transformation scene, and when the transformation size is less than M points, it may be regarded as a small-size transformation scene.
  • DCT2 'matrix and DST7 matrix are used as the target transformation matrix pair in large-scale transformation scenes
  • DCT2' matrix and DST4 matrix are used as the target transformation matrix pair
  • DCT2' matrix and DST4 matrix are used as the target transformation matrix pair
  • DCT2' matrix and DST4 matrix are used as the target transformation matrix pair
  • DCT2' matrix and DST4 matrix are used as the target transformation matrix pair
  • DCT2' matrix and DST4 matrix in small-size scenes (Inverse transform in size scene) as the target transform matrix pair
  • the target transform matrix pair may be composed of a DCT2 'matrix and a DST7 matrix.
  • the correspondence between the target transform matrix pair index value and the candidate transform matrix pair may be as shown in the table 9 shown.
  • the target transform matrix pair can be composed of a DCT2 'matrix and a DST4 matrix.
  • the correspondence between the target transform matrix pair index value and the candidate transform matrix pair can be as shown in Table 10. Show.
  • the 4 ⁇ 4 DST matrix and 4 ⁇ 4 DST7 transformation matrix can be specifically as follows:
  • the target transformation matrix pair when the variable size is greater than or equal to 16, the target transformation matrix pair may be composed of a DCT2 'matrix and a DST7 matrix, and when the variable size is less than 16, the target transformation matrix pair may be a DCT2' matrix Compared with the performance of the transformation / inverse transformation when the DST4 matrix is composed, compared with the DCT8 matrix and the DST7 matrix used in the existing scheme, the test performance of the scheme of this application is shown in Table 11 and Table 12.
  • Table 11 is the test results obtained under the intra-prediction mode test conditions
  • Table 12 is the test results obtained under the random access mode test conditions (either intra prediction or inter prediction can be used for prediction).
  • Y represents the luminance component of the video image
  • U / V represents the chrominance component of the video image
  • the value below Y / U / V represents the percentage of increase in coded bits under the same video image quality
  • the negative value represents the decrease in coded bits.
  • EncT and DecT represent the encoding and decoding time, respectively.
  • the present application can simplify the calculation process, reduce the codec time, and improve the codec performance.
  • the method shown in FIG. 6 further includes: parsing the code stream to obtain multi-core transformation flag bits; the index value according to the target transformation matrix pair and the target transformation matrix pair index value and Correspondence between the candidate transformation matrix pairs, and determining the target transformation matrix pair from the candidate transformation matrix pairs includes: when the value of the multi-core transformation flag is the first value, according to the target transformation The index value of the matrix pair and the corresponding relationship between the index value of the target transformation matrix pair and the candidate transformation matrix pair, the target transformation matrix pair is determined from the candidate transformation matrix pair; the value of the multi-core transformation flag bit is the first In the case of a value, the DCT2 matrix is determined as the target transformation matrix pair.
  • determining the DCT2 matrix as the target transformation matrix pair may refer to using the DCT2 matrix as the horizontal transformation matrix and the vertical transformation matrix in the target transformation matrix pair.
  • the multi-core conversion can be performed only when the value of the multi-core conversion flag is the first value, and directly used when the value of the multi-core conversion flag is the second value (DCT2, DCT2) as the target transformation matrix to inversely transform the residual coefficients.
  • the multi-core conversion flag may specifically be MTS_flag. When MTS_flag is the first value, it indicates that multi-core conversion is performed, and when MTS_flag is the second value, it indicates that multi-core conversion is not performed.
  • the first value and the second value may be 1 and 0 respectively, or the second value and the first value may also be 0 and 1 respectively.
  • the video decoding method of the embodiment of the present application is described in detail above with reference to FIG. 6, and the video encoding method of the embodiment of the present application is described below with reference to FIG. 8. It should be understood that the video encoding method shown in FIG. 8 is shown in FIG. 6 The corresponding video encoding method is corresponding (the final code stream shown in the video encoding method shown in FIG. 8 can be processed using the video decoding method shown in FIG. 6). In order to avoid unnecessary repetition, the following application is combined with FIG. 8 When the video encoding method of the embodiment is introduced, repeated description is appropriately omitted.
  • FIG. 8 is a schematic flowchart of a video encoding method according to an embodiment of the present application. 8 is a schematic flowchart of a video encoding method according to an embodiment of the present application. The method shown in FIG. 8 may be executed by the encoding end device. The method shown in FIG. 8 includes steps 2001 to 2005. The following describes steps 2001 to 2005 separately.
  • the above-mentioned residual block can be obtained by making a difference between the image block to be processed and the prediction block (as shown in FIG. 1 to obtain the residual block by making a difference between the image block to be processed and the prediction block).
  • the inter prediction mode or the intra prediction mode can be used.
  • the candidate transformation matrix pair includes a horizontal transformation matrix and a vertical transformation matrix.
  • the horizontal transformation matrix and the vertical transformation matrix are each one of two preset transformation matrices.
  • the first transformation matrix in the transformation matrix is a DCT2 'matrix, and the DCT2' matrix is a transposed matrix of the DCT2 matrix.
  • the above mapping relationship information may include a target transformation matrix pair index value and a transformation matrix pair corresponding to the target index value, and the above mapping relationship information may be stored in advance at the encoding end and the decoding end.
  • mapping relationship between the index value of the target transformation matrix pair and the candidate transformation matrix pair can be shown in Table 13, where DCT2 'is the first transformation among the two preset transformation matrices Matrix, transformation matrix A is the second transformation matrix among the two preset transformation matrices.
  • the candidate transformation matrix pair is composed of transformation matrix A and DCT 2 '.
  • the encoding end may try the four transformation matrix pairs in Table 13 during the transformation process, and calculate the rate-distortion cost corresponding to each transformation matrix pair, and then select the transformation matrix pair with the lowest rate-distortion cost as the target transformation matrix pair.
  • the transformation ie, matrix multiplication
  • A is the transformation matrix matrix in the horizontal direction
  • B is the transformation matrix matrix in the vertical direction
  • A represents the transposed matrix of matrix A. Since A is an orthogonal matrix, transposing A is equivalent to finding the inverse matrix of A.
  • the rate-distortion cost corresponding to (DCT2 'matrix, transformation matrix A) is the lowest, then the (DCT2' matrix, transformation matrix A ) As the target transformation matrix pair.
  • the residual block can be transformed according to the transformation matrix pair, and the target transformation matrix pair index value (the index value is specifically 2) corresponding to (DCT2 'matrix, transformation matrix A) can be written into the code stream.
  • the target transformation matrix pair can be determined according to the correspondence between the target transformation matrix pair index value 2 and the pre-stored target transformation matrix pair index value and candidate transformation matrix pair.
  • the candidate transformation matrix pair includes the DCT2 'matrix
  • the DCT2' matrix has a fast algorithm during the transformation process
  • a fast algorithm can be used, which can reduce the computational complexity of the transformation process.
  • the DCT2 'matrix is derived from the DCT2 matrix.
  • the matrix coefficients of the DCT2' matrix can be derived from the matrix coefficients of the DCT2 matrix without additional storage of the matrix coefficients of the DCT2 'matrix, which can reduce storage overhead.
  • the second one of the preset two transformation matrices is a DCT2'FS matrix or a DCT2'F matrix.
  • F in the DCT2'FS matrix and DCT2'F matrix represent mirror images
  • S in the DCT2'FS matrix represents symbol transformation
  • the DCT2'F matrix is a matrix obtained by mirroring the DCT2 'matrix
  • the DCT2'FS matrix is a matrix obtained by mirroring the DCT2' matrix and then performing symbol conversion on the mirrored matrix.
  • the above-mentioned mirror image is a left-right mirror image.
  • Flipping a mirror image to the right and left of a matrix may refer to mirroring the matrix coefficients on the left side of the matrix to the right and mirroring the matrix coefficients on the right side of the matrix to the left.
  • the above-mentioned symbol transformation means that only the matrix coefficients of the even rows of the matrix are inverted, and the matrix coefficients of the odd rows of the matrix remain unchanged.
  • the above-mentioned symbol transformation means that only the matrix coefficients of odd rows of the matrix are inverted, and the matrix coefficients of even rows of the matrix remain unchanged.
  • the above sign transformation is to reverse the sign of all matrix coefficients in the matrix.
  • the first one of the two preset transformation matrices is a DCT2 'matrix
  • the second matrix is a DCT2'FS matrix or a DCT2'F matrix, which is applicable to all transformation sizes.
  • the first matrix of the two preset transformation matrices is a DCT2 'matrix
  • the second matrix is a DCT2'FS matrix or a DCT2'F matrix, which is suitable for transformation sizes of 4, 8, 16, and 32. Point situation.
  • the first matrix of the two preset transformation matrices is a DCT2 'matrix and the second matrix is a DCT2'FS matrix or a DCT2'F matrix
  • the DCT2' matrix, the DCT2'FS matrix, and the DCT2 ' There are fast algorithms for the F matrix, so when the target transformation matrix pair (the target transformation matrix pair is formed by combining two preset transformation matrices) is used to transform the residual block, the calculation in the inverse transformation process can be reduced the complexity.
  • the horizontal transform matrix in the target transform matrix pair is a DCT2 'matrix
  • the vertical transform in the target transform matrix pair The matrix is a DCT2'FS matrix or a DCT2'F matrix; when the height of the residual block is less than M points, the vertical transformation matrix in the target transformation matrix pair is a DST4 matrix, where M is a positive integer.
  • the vertical transform matrix in the target transform matrix pair is a DCT2 'matrix
  • the horizontal transform in the target transform matrix pair The matrix is a DCT2'FS matrix or a DCT2'F matrix; when the width of the residual block is less than M points, the horizontal transformation matrix in the target transformation matrix pair is a DST4 matrix, where M is a positive integer.
  • the transformation size when the transformation size is greater than or equal to M points, it may be regarded as a large-size transformation scene, and when the transformation size is less than M points, it may be regarded as a small-size transformation scene.
  • the transformation matrix with a fast algorithm is used as the horizontal transformation matrix or the vertical transformation matrix in the target transformation matrix pair in the large-size transformation scene
  • the transformation matrix suitable for the small-size transformation scene is used as the target in the small-size transformation scene
  • the horizontal transformation matrix or the vertical transformation matrix in the transformation matrix pair can significantly reduce the complexity of the transformation in a large-size transformation scene, and can also ensure the transformation performance in a small-size scene, and can reduce the transformation complexity and ensure the transformation. Balance performance.
  • the second one of the preset two transformation matrices is derived from the DCT2 matrix.
  • the second one of the preset two transformation matrices can be derived from the DCT2 matrix, it is not necessary to additionally store the matrix coefficients of the second transformation matrix, which can reduce storage overhead.
  • the horizontal transform matrix in the target transform matrix pair is a DCT2 'matrix, and when the height of the residual block is greater than or equal to N points, the vertical transform in the target transform matrix pair
  • the matrix is a DST7 matrix; when the height of the residual block is less than N points, the vertical transformation matrix in the target transformation matrix pair is a DST4 matrix, where N is a positive integer.
  • the vertical transform matrix in the target transform matrix pair is a DCT2 'matrix
  • the horizontal transform in the target transform matrix pair The matrix is a DST7 matrix
  • the horizontal transformation matrix in the target transformation matrix pair is a DST4 matrix, where N is a positive integer.
  • N 16.
  • the transformation size when the transformation size is greater than or equal to N points, it may be regarded as a large-size transformation scene, and when the transformation size is less than M points, it may be regarded as a small-size transformation scene.
  • the DCT2 'matrix and DST7 matrix are used as the target transformation matrix pair in large-scale transformation scenarios
  • the DCT2' matrix and DST4 matrix are used in small-size scenarios (Transformation in the scene)
  • the target transformation matrix pair it can reduce the transformation complexity and improve the transformation performance.
  • the implementation circuit of the transformation matrix in the embodiment of the present application may multiplex the transformation / inverse transformation implementation circuit corresponding to the 2Nx2N DCT2 matrix, the circuit multiplexing will be described in detail as follows.
  • Fig. 9 depicts the implementation of the butterfly fast algorithm circuit of 16 ⁇ 16 DCT2 matrix in HEVC.
  • the butterfly fast algorithm circuit of 16 ⁇ 16 DCT2 matrix includes 4 ⁇ 4 DCT2 matrix and 8 ⁇ 8 DCT2 matrix.
  • Matrix, 4 ⁇ 4 DCT4 matrix and 8 ⁇ 8 DCT4 matrix implementation circuit that is to say, when implementing the transformation of 4 ⁇ 4 DCT2 matrix, 8 ⁇ 8 DCT2 matrix, 4 ⁇ 4 DCT4 matrix and 8 ⁇ 8 DCT4 matrix Directly multiplex the circuit implementation of 16 ⁇ 16 DCT2 matrix; but only 4 ⁇ 4 DCT2 matrix and 8 ⁇ 8 DCT2 matrix can reuse butterfly fast algorithm circuit, while the implementation of 4 ⁇ 4 DCT4 matrix and 8 ⁇ 8 DCT4 matrix can The realization circuit of multiplexing 16 ⁇ 16 DCT2 matrix, but does not use the butterfly fast algorithm.
  • the partial transformation of the inverse transform circuit (the corresponding Chinese translation is Partial butterfly) fast implementation method.
  • the realization of DCT2 matrix inverse transformation can be decomposed into three modules of EVEN, ODD and ADDSUB, where EVEN means column transformation using a matrix composed of odd row coefficients of DCT2 matrix, ODD means column formation using a matrix composed of DCT2 matrix even row coefficients Transform, ADDSUB means add and subtract module.
  • FIG. 10 describes a 32 ⁇ 32 inverse transform implementation circuit, in which the EVEN4 module, ODD4 module, and ADDSUB4 module form a 4 ⁇ 4 matrix inverse transform implementation circuit 701; the 4 ⁇ 4 matrix inverse transform implementation circuit 701, ODD8
  • the module and ADDSUB8 module form the inverse transform realization circuit 702 of 8 ⁇ 8 matrix; the inverse transform realization circuit 702 of 8 ⁇ 8 matrix, the ODD16 module and ADDSUB16 module form the inverse transform realization circuit 703 of 16 ⁇ 16 matrix; 16 ⁇ 16 matrix
  • the inverse transform circuit of 703 is implemented, the ODD16 module and the ADDSUB16 module form a 32 ⁇ 32 matrix inverse transform circuit 704.
  • the video encoding method and the video encoding method of the embodiment of the present application are described in detail above with reference to FIGS. 1 to 10, and the video decoder of the embodiment of the present application is described below with reference to FIG. 11.
  • the video decoder shown in FIG. 11 can perform
  • the above-mentioned relevant limitations on the video decoder method of the embodiment of the present application also apply to the video decoder shown in FIG. 11, in order to avoid unnecessary repetition, the following When the video decoder device of the embodiment is introduced, duplication of description is appropriately omitted.
  • FIG. 11 is a schematic block diagram of a video decoder according to an embodiment of the present application.
  • the video decoder 300 shown in FIG. 11 includes:
  • the entropy decoding unit 310 is used to parse the code stream to obtain the index value of the target transformation matrix pair for the inverse transformation processing of the current block and the quantization coefficient of the current block;
  • the inverse quantization unit 320 is configured to perform inverse quantization processing on the quantization coefficient of the current block to obtain the inverse quantization coefficient of the current block;
  • the inverse transform processing unit 330 is configured to determine a target transform matrix pair from the candidate transform matrix pair according to the target transform matrix pair index value and the correspondence between the target transform matrix pair index value and the candidate transform matrix pair ,
  • the candidate transformation matrix pair includes a horizontal transformation matrix and a vertical transformation matrix
  • the horizontal transformation matrix and the vertical transformation matrix are both one of two preset transformation matrices
  • the preset The first of the two transformation matrices is the DCT2 'matrix, where the DCT2' matrix is the transposed matrix of the DCT2 matrix;
  • the inverse transform processing unit 330 is further configured to perform inverse transform processing on the inverse quantization coefficient of the current block according to the target transform matrix, to obtain a reconstructed residual block of the current block;
  • the reconstruction unit 340 is configured to obtain the reconstructed block of the current block according to the reconstructed residual block of the current block.
  • the fast algorithm can be used when the DCT2 'is used for the inverse transformation, which can reduce the calculation complexity of the inverter process degree.
  • DCT2' since the DCT2 'matrix is a transpose of the DCT2 matrix, in the process of inverse transformation, DCT2' can reuse the inverse transformation realization circuit of DCT2, which can reduce the hardware implementation cost.
  • the DCT2 'matrix is derived from the DCT2 matrix.
  • the second one of the preset two transformation matrices is a DCT2'FS matrix or a DCT2'F matrix.
  • the horizontal transform matrix in the target transform matrix pair is a DCT2 'matrix, and when the height of the current block is greater than or equal to M points, the vertical transform matrix in the target transform matrix pair It is a DCT2'FS matrix or a DCT2'F matrix; when the height of the current block is less than M points, the vertical transformation matrix in the target transformation matrix pair is a DST4 matrix, where M is a positive integer.
  • the vertical transformation matrix in the target transformation matrix pair is a DCT2 'matrix, and when the width of the current block is greater than or equal to M points, the horizontal transformation matrix in the target transformation matrix pair It is a DCT2'FS matrix or a DCT2'F matrix; when the height of the current block is less than M points, the horizontal transformation matrix in the target transformation matrix pair is a DST4 matrix, where M is a positive integer.
  • the second one of the preset two transformation matrices is derived from the DCT2 matrix.
  • the horizontal transform matrix in the target transform matrix pair is a DCT2 'matrix, and when the height of the current block is greater than or equal to N points, the vertical transform matrix in the target transform matrix pair Is a DST7 matrix; when the height of the current block is less than N points, the vertical transformation matrix in the target transformation matrix pair is a DST4 matrix, where N is a positive integer.
  • the vertical transformation matrix in the target transformation matrix pair is a DCT2 'matrix, and when the width of the current block is greater than or equal to N points, the horizontal transformation matrix in the target transformation matrix pair Is a DST7 matrix; when the width of the current block is less than N points, the horizontal transformation matrix in the target transformation matrix pair is a DST4 matrix, where N is a positive integer.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the units is only a division of logical functions.
  • there may be other divisions for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application essentially or part of the contribution to the existing technology or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to enable a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (random access memory, RAM), magnetic disk or optical disk and other media that can store program codes .

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Abstract

本申请公开了视频编解码技术领域中的视频解码方法和视频解码器。该方法包括：解析码流，以获取当前块进行逆变换处理的目标变换矩阵对索引值以及当前块的量化系数；对当前块的量化系数进行逆量化处理，以获取当前块的反量化系数；根据目标变换矩阵对索引值以及目标变换矩阵对索引值与候选变换矩阵对之间的对应关系，从候选变换矩阵对中确定目标变换矩阵对；根据目标变换矩阵对当前块的反量化系数进行逆变换处理，以得到当前块的重建残差块；根据当前块的重建残差块获得当前块的重构块。本申请能够降低逆变换时的计算复杂度。

Description

视频解码方法和视频解码器
本申请要求于2018年11月23日提交中国专利局、申请号为201811409192.6、申请名称为“视频解码方法和视频解码器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及视频编解码技术领域，并且更具体地，涉及一种视频解码方法和解码器。
背景技术
数字视频能力可并入到多种多样的装置中，包含数字电视、数字直播系统、无线广播系统、个人数字助理(personal digital assistant，PDA)、膝上型或桌上型计算机、平板计算机、电子图书阅读器、数码相机、数字记录装置、数字媒体播放器、视频游戏装置、视频游戏控制台、蜂窝式或卫星无线电电话(所谓的“智能电话”)、视频电话会议装置、视频流式传输装置及其类似者。数字视频装置实施视频压缩技术，例如，在由MPEG-2、MPEG-4、ITU-T H.263、ITU-T H.264/MPEG-4第10部分高级视频编码(AVC)定义的标准、视频编码标准H.265/高效视频编码(high efficiency video coding，HEVC)标准以及此类标准的扩展中所描述的视频压缩技术。视频装置可通过实施此类视频压缩技术来更有效率地发射、接收、编码、解码和/或存储数字视频信息。
视频压缩技术执行空间(图像内)预测和/或时间(图像间)预测以减少或去除视频序列中固有的冗余。对于基于块的视频编码，视频条带(即，视频帧或视频帧的一部分)可分割成若干图像块，所述图像块也可被称作树块、编码单元(coding unit，CU)和/或编码节点。使用关于同一图像中的相邻块中的参考样本的空间预测来编码图像的待帧内编码(I)条带中的图像块。图像的待帧间编码(P或B)条带中的图像块可使用相对于同一图像中的相邻块中的参考样本的空间预测或相对于其它参考图像中的参考样本的时间预测。图像可被称作帧，且参考图像可被称作参考帧。
在对图像块进行编码的过程中，需要对图像块进行预测，得到残差系数，然后再对残差系数进行变换、量化以及熵编码得到编码码流。其中，在变换的过程中，可能会尝试采用不同的变换矩阵对对残差系数进行变换，然后根据编码代价从中选择合适的变换矩阵对对残差系数进行变换。
传统方案在变换过程中除了采用DCT2矩阵进行变换之外，还可能会采用DCT矩阵8和DCT7矩阵进行变换。但是，由于采用DCT8矩阵和DCT7矩阵进行变换时的计算复杂度较高。
发明内容
本申请提供一种视频解码方法、视频编码方法及视频解码器和视频编码器，以简化逆 变换/变换时的计算复杂度。
第一方面，提供了一种逆视频编码方法，该方法包括：解析码流，以获取当前块进行逆变换处理的目标变换矩阵对索引值以及所述当前块的量化系数；对所述当前块的量化系数进行逆量化处理，以获取所述当前块的反量化系数；根据所述目标变换矩阵对索引值以及所述目标变换矩阵对索引值与候选变换矩阵对之间的对应关系，从所述候选变换矩阵对中确定目标变换矩阵对，其中，所述候选变换矩阵对包括水平方向变换矩阵和垂直方向变换矩阵，所述水平方向变换矩阵和所述垂直方向变换矩阵均为预设的两个变换矩阵中的一个，所述预设的两个变换矩阵中的第一个变换矩阵为DCT2’矩阵，其中，DCT2’矩阵为DCT2矩阵的转置矩阵；根据所述当前块的反量化系数进行逆变换处理，以得到所述当前块的重建残差块；根据所述当前块的重建残差块获得所述当前块的重构块。
应理解，在本申请中，逆量化也可以称为反量化，逆变换也可以称为反变换。
本申请中，由于候选变换矩阵对中包含DCT2’矩阵，而DCT2’矩阵逆变换过程中存在快速算法，因此，当采用DCT2’进行逆变换时能够采用快速算法，能够降低逆变过程的计算复杂度。
此外，由于DCT2’矩阵是DCT2矩阵的转置，因此，在逆变换的过程中，DCT2’能够复用DCT2的逆变换实现电路，能够降低硬件实现成本。
结合第一方面，在第一方面的某些实现方式中，DCT2’矩阵是根据DCT2矩阵推导得到的。
本申请中，由于DCT2’矩阵是DCT2矩阵的转置矩阵，因此，DCT2’矩阵的矩阵系数能够根据DCT2矩阵的矩阵系数推导出来，而不必额外存储DCT2’矩阵的矩阵系数，能够减少存储开销。
结合第一方面，在第一方面的某些实现方式中，所述预设的两个变换矩阵中的第二个变换矩阵是根据DCT2矩阵推导得到的。
本申请中，由于预设的两个变换矩阵中的第二个变换矩阵可以根据DCT2矩阵推导得到，因此，而不必额外存储该第二个变换矩阵的矩阵系数，能够减少存储开销。
结合第一方面，在第一方面的某些实现方式中，预设的两个变换矩阵中的第二个变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵。
其中，DCT2’FS矩阵和DCT2’F矩阵中的F表示镜像，DCT2’FS矩阵中的S表示符号变换。DCT2’F矩阵是对DCT2’矩阵进行镜像之后得到的矩阵，DCT2’FS矩阵是先对DCT2’矩阵进行镜像，然后再对镜像得到的矩阵进行符号变换得到的矩阵。
具体地，当上述第二个变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵时，DCT2’FS矩阵或者DCT2’F矩阵可以由相应大小的DCT矩阵推导得到。例如，16×16的DCT2’FS矩阵或者16×16的DCT2’F矩阵均可以由16×16的DCT2’F矩阵推导得到。
可选地，上述镜像是左右翻转镜像。
对一个矩阵左右翻转镜像可以是指将矩阵左侧的矩阵系数镜像到右侧，将矩阵右侧的矩阵系数镜像到左侧。
可选地，上述符号变换是指仅对矩阵的偶数行的矩阵系数进行符号取反，而矩阵的奇数行的矩阵系数保持不变。
可选地，上述符号变换是指仅对矩阵的奇数行的矩阵系数进行符号取反，而矩阵的偶 数行的矩阵系数保持不变。
可选地，上述符号变换是对矩阵中所有的矩阵系数的符号取反。
可选地，预设的两个变换矩阵中的第一个矩阵为DCT2’矩阵，第二个矩阵为DCT2’FS矩阵或者DCT2’F矩阵适用于所有的变换尺寸。
具体地，预设的两个变换矩阵中的第一个矩阵为DCT2’矩阵，第二个矩阵为DCT2’FS矩阵或者DCT2’F矩阵适用于变换尺寸为4点、8点、16点和32点的情况。
本申请中，由于DCT2’FS和DCT2’F矩阵在逆变换过程中存在快速算法，能够简化逆变换时的计算复杂度。
具体地，当预设的两个变换矩阵中的第一个矩阵为DCT2’矩阵，第二个矩阵为DCT2’FS矩阵或者DCT2’F矩阵时，由于DCT2’矩阵、DCT2’FS矩阵和DCT2’F矩阵均存在快速算法，因此，当采用目标变换矩阵对(目标变换矩阵对由预设的两个变换矩阵组合而成)对当前块的反量化系数进行逆变换处理时，能够降低逆变换过程中的计算复杂度。
结合第一方面，在第一方面的某些实现方式中，所述目标变换矩阵对中的水平变换矩阵为DCT2’矩阵，当所述当前块的高大于或者等于M点时，所述目标变换矩阵对中的垂直变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵；当所述当前块的高小于M点时，所述目标变换矩阵对中的垂直变换矩阵为DST4矩阵，其中，M为正整数。
结合第一方面，在第一方面的某些实现方式中，所述目标变换矩阵对中的垂直变换矩阵为DCT2’矩阵，当所述当前块的宽大于或者等于M点时，所述目标变换矩阵对中的水平变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵；当所述当前块的高小于M点时，所述目标变换矩阵对中的水平变换矩阵为DST4矩阵，其中，M为正整数。
可选地，上述M＝32。
应理解，当变换尺寸大于或者等于M点时可以认为是大尺寸变换场景，当变换尺寸小于M点时可以认为是小尺寸变换场景。
本申请中，在大尺寸变换场景下采用具有快速算法的变换矩阵作为目标变换矩阵对中的水平变换矩阵或者垂直变换矩阵，而在小尺寸变换场景下采用适合小尺寸变换场景的变换矩阵作为目标变换矩阵对中的水平变换矩阵或者垂直变换矩阵，能够在大尺寸变换场景下，显著的降低逆变换的复杂度，同时还能在小尺寸场景下保证变换性能，能够在降低逆变换复杂度和保证逆变换性能之间取得平衡。
结合第一方面，在第一方面的某些实现方式中，所述目标变换矩阵对中的水平变换矩阵为DCT2’矩阵，当所述当前块的高大于或者等于N点时，所述目标变换矩阵对中的垂直变换矩阵为DST7矩阵；当所述当前块的高小于N点时，所述目标变换矩阵对中的垂直变换矩阵为DST4矩阵，其中，N为正整数。
结合第一方面，在第一方面的某些实现方式中，所述目标变换矩阵对中的垂直变换矩阵为DCT2’矩阵，当所述当前块的宽大于或者等于N点时，所述目标变换矩阵对中的水平变换矩阵为DST7矩阵；当所述当前块的宽小于N点时，所述目标变换矩阵对中的水平变换矩阵为DST4矩阵，其中，N为正整数。
可选地，N＝16。
应理解，当变换尺寸大于或者等于N点时可以认为是大尺寸变换场景，当变换尺寸小于M点时可以认为是小尺寸变换场景。
本申请中，在大尺寸变换场景下采用DCT2’矩阵和DST7矩阵(适用于大尺寸场景下的逆变换)作为目标变换矩阵对，在小尺寸场景下采用DCT2’矩阵和DST4矩阵(适用于小尺寸场景下的逆变换)作为目标变换矩阵对，能够在降低逆变换复杂度的同时，提高逆变换的性能。
上述DST4矩阵也可以是根据DCT2矩阵推导得到的。
具体地，L×L的DST4矩阵可以由2L×2L的DCT2矩阵推导(也可以称为变换)得到。例如，4×4的DST4矩阵可以由8×8的DCT2矩阵推导得到，16×16的DST4矩阵可以由32×32的DCT2矩阵推导得到，32×32的DST4矩阵可以由64×64的DCT2矩阵推导得到。
应理解，上述L×L的DST4矩阵由2L×2L的DCT2矩阵推导得到，具体可以是指抽取DCT2矩阵中的部分矩阵系数作为DST4矩阵的矩阵系数。
可选地，上述方法还包括：解析码流，以获取多核变换标志位；所述根据所述目标变换矩阵对索引值以及所述目标变换矩阵对索引值与候选变换矩阵对之间的对应关系，从所述候选变换矩阵对中确定目标变换矩阵对，包括：在所述多核变换标志位的取值为第一取值的情况下，根据所述目标变换矩阵对索引值以及所述目标变换矩阵对索引值与候选变换矩阵对之间的对应关系，从所述候选变换矩阵对中确定目标变换矩阵对；在所述多核变换标志位的取值为第二取值的情况下，将DCT2矩阵确定为目标变换矩阵对中的水平方向变换矩阵和垂直方向变换矩阵。
也就是说，在本申请中，可以在多核变换标志位的取值为第一取值的情况下才进行多核变换，而在多核变换标志位的取值为第二取值的情况下直接采用(DCT2，DCT2)作为目标变换矩阵对对残差系数进行逆变换。
上述多核变换标志位具体可以是MTS_flag，当MTS_flag＝1时可以表示进行多核变换，当MTS_flag＝0时可以表示不进行多核变换(或者，也可以将1和0表示的含义对调)。
第二方面，提供了一种视频编码方法，该方法包括：获取待处理图像块的残差块；根据预设的映射关系信息获取残差块的候选变换矩阵对，其中，候选变换矩阵对包括水平方向变换矩阵和垂直方向变换矩阵，所述水平方向变换矩阵和所述垂直方向变换矩阵均为预设的两个变换矩阵中的一个，所述预设的两个变换矩阵中的第一个变换矩阵为DCT2’矩阵，DCT2’矩阵为DCT2矩阵的转置矩阵；从候选变换矩阵对中选择出率失真最小的变换矩阵对作为目标变换矩阵对；根据目标变换矩阵对，对残差块进行变换，得到待处理图像块的变换系数；将目标变换矩阵对应的目标变换矩阵对索引值写入码流。
上述映射关系信息可以包括目标变换矩阵对索引值以及目标索引值对应的变换矩阵对。
本申请中，由于候选变换矩阵对中包含DCT2’矩阵，而DCT2’矩阵在变换过程中存在快速算法，当采用DCT2’矩阵进行变换时能够采用快速算法，能够降低变换过程的计算复杂度。
结合第二方面，在第二方面的某些实现方式中，DCT2’矩阵是根据DCT2矩阵推导得到的。
本申请中，由于DCT2’矩阵是DCT2矩阵的转置矩阵，因此，DCT2’矩阵的矩阵系数能够根据DCT2矩阵的矩阵系数推导出来，而不必额外存储DCT2’矩阵的矩阵系数，能够减少存储开销。
结合第二方面，在第二方面的某些实现方式中，所述预设的两个变换矩阵中的第二个变换矩阵是根据DCT2矩阵推导得到的。
本申请中，由于预设的两个变换矩阵中的第二个变换矩阵可以根据DCT2矩阵推导得到，因此，而不必额外存储该第二个变换矩阵的矩阵系数，能够减少存储开销。
结合第二方面，在第二方面的某些实现方式中，预设的两个变换矩阵中的第二个变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵。
其中，DCT2’FS矩阵和DCT2’F矩阵中的F表示镜像，DCT2’FS矩阵中的S表示符号变换。DCT2’F矩阵是对DCT2’矩阵进行镜像之后得到的矩阵，DCT2’FS矩阵是先对DCT2’矩阵进行镜像，然后再对镜像得到的矩阵进行符号变换得到的矩阵。
可选地，上述镜像是左右翻转镜像。
对一个矩阵左右翻转镜像可以是指将矩阵左侧的矩阵系数镜像到右侧，将矩阵右侧的矩阵系数镜像到左侧。
可选地，上述符号变换是指仅对矩阵的偶数行的矩阵系数进行符号取反，而矩阵的奇数行的矩阵系数保持不变。
可选地，上述符号变换是指仅对矩阵的奇数行的矩阵系数进行符号取反，而矩阵的偶数行的矩阵系数保持不变。
可选地，上述符号变换是对矩阵中所有的矩阵系数的符号取反。
可选地，预设的两个变换矩阵中的第一个矩阵为DCT2’矩阵，第二个矩阵为DCT2’FS矩阵或者DCT2’F矩阵适用于所有的变换尺寸。
具体地，预设的两个变换矩阵中的第一个矩阵为DCT2’矩阵，第二个矩阵为DCT2’FS矩阵或者DCT2’F矩阵适用于变换尺寸为4点、8点、16点和32点的情况。
本申请中，由于DCT2’FS和DCT2’F矩阵在变换过程中存在快速算法，能够简化变换时的计算复杂度。
具体地，当预设的两个变换矩阵中的第一个矩阵为DCT2’矩阵，第二个矩阵为DCT2’FS矩阵或者DCT2’F矩阵时，由于DCT2’矩阵、DCT2’FS矩阵和DCT2’F矩阵均存在快速算法，因此，当采用目标变换矩阵对(目标变换矩阵对由预设的两个变换矩阵组合而成)对残差块进行变换处理时，能够降低逆变换过程中的计算复杂度。
结合第二方面，在第二方面的某些实现方式中，所述目标变换矩阵对中的水平变换矩阵为DCT2’矩阵，当所述残差块的高大于或者等于M点时，所述目标变换矩阵对中的垂直变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵；当所述残差块的高小于M点时，所述目标变换矩阵对中的垂直变换矩阵为DST4矩阵，其中，M为正整数。
结合第二方面，在第二方面的某些实现方式中，所述目标变换矩阵对中的垂直变换矩阵为DCT2’矩阵，当所述残差块的宽大于或者等于M点时，所述目标变换矩阵对中的水平变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵；当所述残差块的宽小于M点时，所述目标变换矩阵对中的水平变换矩阵为DST4矩阵，其中，M为正整数。
可选地，上述M＝32。
应理解，当变换尺寸大于或者等于M点时可以认为是大尺寸变换场景，当变换尺寸小于M点时可以认为是小尺寸变换场景。
本申请中，在大尺寸变换场景下采用具有快速算法的变换矩阵作为目标变换矩阵对中 的水平变换矩阵或者垂直变换矩阵，而在小尺寸变换场景下采用适合小尺寸变换场景的变换矩阵作为目标变换矩阵对中的水平变换矩阵或者垂直变换矩阵，能够在大尺寸变换场景下，显著的降低变换的复杂度，同时还能在小尺寸场景下保证变换性能，能够在降低变换复杂度和保证变换性能之间取得平衡。
结合第二方面，在第二方面的某些实现方式中，所述目标变换矩阵对中的水平变换矩阵为DCT2’矩阵，当所述残差块的高大于或者等于N点时，所述目标变换矩阵对中的垂直变换矩阵为DST7矩阵；当所述残差块的高小于N点时，所述目标变换矩阵对中的垂直变换矩阵为DST4矩阵，其中，N为正整数。
结合第二方面，在第二方面的某些实现方式中，所述目标变换矩阵对中的垂直变换矩阵为DCT2’矩阵，当所述残差块的宽大于或者等于N点时，所述目标变换矩阵对中的水平变换矩阵为DST7矩阵；当所述残差块的宽小于N点时，所述目标变换矩阵对中的水平变换矩阵为DST4矩阵，其中，N为正整数。
可选地，N＝16。
应理解，当变换尺寸大于或者等于N点时可以认为是大尺寸变换场景，当变换尺寸小于M点时可以认为是小尺寸变换场景。
本申请中，在大尺寸变换场景下采用DCT2’矩阵和DST7矩阵(适用于大尺寸场景下的变换)作为目标变换矩阵对，在小尺寸场景下采用DCT2’矩阵和DST4矩阵(适用于小尺寸场景下的变换)作为目标变换矩阵对，能够在降低变换复杂度的同时，提高变换的性能。
上述DST4矩阵也可以是根据DCT2矩阵推导得到的。
具体地，L×L的DST4矩阵可以由2L×2L的DCT2矩阵推导(也可以称为变换)得到。例如，4×4的DST4矩阵可以由8×8的DCT2矩阵推导得到，16×16的DST4矩阵可以由32×32的DCT2矩阵推导得到，32×32的DST4矩阵可以由64×64的DCT2矩阵推导得到。
应理解，上述L×L的DST4矩阵由2L×2L的DCT2矩阵推导得到，具体可以是指抽取DCT2矩阵中的部分矩阵系数作为DST4矩阵的矩阵系数。
第三方面，提供一种解码器，该解码器包括用于执行上述第一方面或者第一方面中的任意一种实现方式中的方法的模块。
第四方面，提供一种编码器，该编码器包括用于执行上述第二方面或者第二方面中的任意一种实现方式中的方法的模块。
第五方面，提供一种解码器，包括：存储器和处理器，所述处理器调用存储在所述存储器中的程序代码以执行第一方面或者第一方面中的任意一种实现方式中的方法的部分或全部步骤。
可选地，所述存储器为非易失性存储器。
可选地，所述存储器与处理器耦合在一起。
第六方面，提供一种编码器，包括：存储器和处理器，所述处理器调用存储在所述存储器中的程序代码以执行第二方面或者第二方面中的任意一种实现方式中的方法的部分或全部步骤。
可选地，存储器为非易失性存储器。
可选地，所述存储器与处理器耦合在一起。
第七方面，提供一种计算机可读存储介质，所述计算机可读存储介质存储了程序代码，其中，所述程序代码包括用于执行第一方面或者第一方面中任意一种实现方式中的方法的部分或全部步骤的指令。
第八方面，提供一种计算机可读存储介质，所述计算机可读存储介质存储了程序代码，其中，所述程序代码包括用于执行第二方面或者第二方面中任意一种实现方式中的方法的部分或全部步骤的指令。
第九方面，提供一种计算机程序产品，当所述计算机程序产品在计算机上运行时，使得所述计算机执行第一方面或者第一方面中的任意一种实现方式中的方法的部分或全部步骤的指令。
第十方面，提供一种计算机程序产品，当所述计算机程序产品在计算机上运行时，使得所述计算机执行第二方面或者第二方面中的任意一种实现方式中的方法的部分或全部步骤的指令。
附图说明
图1是用于实现本申请实施例的视频编码系统实例的框图；
图2是用于实现本申请实施例的视频编码器实例结构的框图；
图3是于实现本申请实施例的视频解码器实例结构的框图；
图4示出了包含图2的编码器20和图3的解码器30的实例结构的框图；
图5示出了另一种编码装置或解码装置实例的框图；
图6是本申请实施例的视频解码方法的示意性流程图；
图7是根据DCT2的变换矩阵矩阵推导DCT2’的变换矩阵矩阵和DCT2’FS的变换矩阵矩阵的过程的示意图；
图8是本申请实施例的视频编码方法的示意性流程图；
图9是HEVC中16×16 DCT2矩阵的蝶形快速算法电路实现示意图；
图10是本申请实施例的32×32的反变换实现电路示意图；
图11是本申请实施例的视频解码器的示意性框图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
在以下描述中，参考形成本公开一部分并以说明之方式示出本申请实施例的具体方面或可使用本申请实施例的具体方面的附图。应理解，本申请实施例可在其它方面中使用，并可包括附图中未描绘的结构或逻辑变化。因此，以下详细描述不应以限制性的意义来理解，且本申请的范围由所附权利要求书界定。
例如，应理解，结合所描述方法的揭示内容可以同样适用于用于执行所述方法的对应设备或系统，且反之亦然。例如，如果描述一个或多个具体方法步骤，则对应的设备可以包含如功能单元等一个或多个单元，来执行所描述的一个或多个方法步骤(例如，一个单元执行一个或多个步骤，或多个单元，其中每个都执行多个步骤中的一个或多个)，即使附图中未明确描述或说明这种一个或多个单元。另一方面，例如，如果基于如功能单元等一个或多个单元描述具体装置，则对应的方法可以包含一个步骤来执行一个或多个单元的 功能性(例如，一个步骤执行一个或多个单元的功能性，或多个步骤，其中每个执行多个单元中一个或多个单元的功能性)，即使附图中未明确描述或说明这种一个或多个步骤。进一步，应理解的是，除非另外明确提出，本文中所描述的各示例性实施例和/或方面的特征可以相互组合。
视频编码通常是指处理形成视频或视频序列的图片序列。在视频编码领域，术语“图片(picture)”、“帧(frame)”或“图像(image)”可以用作同义词。本申请(或本公开)中使用的视频编码表示视频编码或视频解码。视频编码在源侧执行，通常包括处理(例如，通过压缩)原始视频图片以减少表示该视频图片所需的数据量(从而更高效地存储和/或传输)。视频解码在目的地侧执行，通常包括相对于编码器作逆处理，以重构视频图片。实施例涉及的视频图片(或总称为图片，下文将进行解释)“编码”应理解为涉及视频序列的“编码”或“解码”。编码部分和解码部分的组合也称为编解码(编码和解码)。
无损视频编码情况下，可以重构原始视频图片，即经重构视频图片具有与原始视频图片相同的质量(假设存储或传输期间没有传输损耗或其它数据丢失)。在有损视频编码情况下，通过例如量化执行进一步压缩，来减少表示视频图片所需的数据量，而解码器侧无法完全重构视频图片，即经重构视频图片的质量相比原始视频图片的质量较低或较差。
H.261的几个视频编码标准属于“有损混合型视频编解码”(即，将样本域中的空间和时间预测与变换域中用于应用量化的2D变换编码结合)。视频序列的每个图片通常分割成不重叠的块集合，通常在块层级上进行编码。换句话说，编码器侧通常在块(视频块)层级处理亦即编码视频，例如，通过空间(图片内)预测和时间(图片间)预测来产生预测块，从当前块(当前处理或待处理的块)减去预测块以获得残差块，在变换域变换残差块并量化残差块，以减少待传输(压缩)的数据量，而解码器侧将相对于编码器的逆处理部分应用于经编码或经压缩块，以重构用于表示的当前块。另外，编码器复制解码器处理循环，使得编码器和解码器生成相同的预测(例如帧内预测和帧间预测)和/或重构，用于处理亦即编码后续块。
如本文中所用，术语“块”可以为图片或帧的一部分。为便于描述，参考多用途视频编码(VVC：Versatile Video Coding)或由ITU-T视频编码专家组(Video Coding Experts Group，VCEG)和ISO/IEC运动图像专家组(Motion Picture Experts Group，MPEG)的视频编码联合工作组(Joint Collaboration Team on Video Coding，JCT-VC)开发的高效视频编码(High-Efficiency Video Coding，HEVC)描述本申请实施例。本领域普通技术人员理解本申请实施例不限于HEVC或VVC。可以指CU、PU和TU。在HEVC中，通过使用表示为编码树的四叉树结构将CTU拆分为多个CU。在CU层级处作出是否使用图片间(时间)或图片内(空间)预测对图片区域进行编码的决策。每个CU可以根据PU拆分类型进一步拆分为一个、两个或四个PU。一个PU内应用相同的预测过程，并在PU基础上将相关信息传输到解码器。在通过基于PU拆分类型应用预测过程获取残差块之后，可以根据类似于用于CU的编码树的其它四叉树结构将CU分割成变换单元(transform unit，TU)。在视频压缩技术最新的发展中，使用四叉树和二叉树(Quad-tree and binary tree，QTBT)分割帧来分割编码块。在QTBT块结构中，CU可以为正方形或矩形形状。在VVC中，编码树单元(coding tree unit，CTU)首先由四叉树结构分割。四叉树叶节点进一步由二进制树结构分割。二进制树叶节点称为编码单元(coding unit，CU)，所述分段用于预测 和变换处理，无需其它任何分割。这表示CU、PU和TU在QTBT编码块结构中的块大小相同。同时，还提出与QTBT块结构一起使用多重分割，例如三叉树分割。
为了对视频编解码的过程有一个初步的了解和认识，下面结合图1至4描述编码器20、解码器30和编码解码系统10、40的实施例(在基于图10更详细描述本申请实施例之前)。
图1为绘示示例性编码系统10的概念性或示意性框图，例如，可以利用本申请(本公开)技术的视频编码系统10。视频编码系统10的编码器20(例如，视频编码器20)和解码器30(例如，视频解码器30)表示可用于根据本申请中描述的各种实例执行用于视频编码或视频解码方法的技术的设备实例。如图1中所示，编码系统10包括源设备12，用于向例如解码经编码数据13的目的地设备14提供经编码数据13，例如，经编码图片13。
源设备12包括编码器20，另外亦即可选地，可以包括图片源16，例如图片预处理单元18的预处理单元18，以及通信接口或通信单元22。
图片源16可以包括或可以为任何类别的图片捕获设备，用于例如捕获现实世界图片，和/或任何类别的图片或评论(对于屏幕内容编码，屏幕上的一些文字也认为是待编码的图片或图像的一部分)生成设备，例如，用于生成计算机动画图片的计算机图形处理器，或用于获取和/或提供现实世界图片、计算机动画图片(例如，屏幕内容、虚拟现实(virtual reality，VR)图片)的任何类别设备，和/或其任何组合(例如，实景(augmented reality，AR)图片)。
(数字)图片为或者可以视为具有亮度值的采样点的二维阵列或矩阵。阵列中的采样点也可以称为像素(pixel)(像素(picture element)的简称)或像素(pel)。阵列或图片在水平和垂直方向(或轴线)上的采样点数目定义图片的尺寸和/或分辨率。为了表示颜色，通常采用三个颜色分量，即图片可以表示为或包含三个采样阵列。RBG格式或颜色空间中，图片包括对应的红色、绿色及蓝色采样阵列。但是，在视频编码中，每个像素通常以亮度/色度格式或颜色空间表示，例如，YCbCr，包括Y指示的亮度分量(有时也可以用L指示)以及Cb和Cr指示的两个色度分量。亮度(简写为luma)分量Y表示亮度或灰度水平强度(例如，在灰度等级图片中两者相同)，而两个色度(简写为chroma)分量Cb和Cr表示色度或颜色信息分量。相应地，YCbCr格式的图片包括亮度采样值(Y)的亮度采样阵列，和色度值(Cb和Cr)的两个色度采样阵列。RGB格式的图片可以转换或变换为YCbCr格式，反之亦然，该过程也称为色彩变换或转换。如果图片是黑白的，该图片可以只包括亮度采样阵列。
图片源16(例如，视频源16)可以为，例如用于捕获图片的相机，例如图片存储器的存储器，包括或存储先前捕获或产生的图片，和/或获取或接收图片的任何类别的(内部或外部)接口。相机可以为，例如，本地的或集成在源设备中的集成相机，存储器可为本地的或例如集成在源设备中的集成存储器。接口可以为，例如，从外部视频源接收图片的外部接口，外部视频源例如为外部图片捕获设备，比如相机、外部存储器或外部图片生成设备，外部图片生成设备例如为外部计算机图形处理器、计算机或服务器。接口可以为根据任何专有或标准化接口协议的任何类别的接口，例如有线或无线接口、光接口。获取图片数据17的接口可以是与通信接口22相同的接口或是通信接口22的一部分。
区别于预处理单元18和预处理单元18执行的处理，图片或图片数据17(例如，视频数据16)也可以称为原始图片或原始图片数据17。
预处理单元18用于接收(原始)图片数据17并对图片数据17执行预处理，以获得经预处理的图片19或经预处理的图片数据19。例如，预处理单元18执行的预处理可以包括整修、色彩格式转换(例如，从RGB转换为YCbCr)、调色或去噪。可以理解，预处理单元18可以是可选组件。
编码器20(例如，视频编码器20)用于接收经预处理的图片数据19并提供经编码图片数据21(下文将进一步描述细节，例如，基于图2或图4)。
源设备12的通信接口22可以用于接收经编码图片数据21并传输至其它设备，例如，目的地设备14或任何其它设备，以用于存储或直接重构，或用于在对应地存储经编码数据13和/或传输经编码数据13至其它设备之前处理经编码图片数据21，其它设备例如为目的地设备14或任何其它用于解码或存储的设备。
目的地设备14包括解码器30(例如，视频解码器30)，另外亦即可选地，可以包括通信接口或通信单元28、后处理单元32和显示设备34。
目的地设备14的通信接口28用于例如，直接从源设备12或任何其它源接收经编码图片数据21或经编码数据13，任何其它源例如为存储设备，存储设备例如为经编码图片数据存储设备。
通信接口22和通信接口28可以用于藉由源设备12和目的地设备14之间的直接通信链路或藉由任何类别的网络传输或接收经编码图片数据21或经编码数据13，直接通信链路例如为直接有线或无线连接，任何类别的网络例如为有线或无线网络或其任何组合，或任何类别的私网和公网，或其任何组合。
通信接口22可以例如用于将经编码图片数据21封装成合适的格式，例如包，以在通信链路或通信网络上传输。
形成通信接口22的对应部分的通信接口28可以例如用于解封装经编码数据13，以获得经编码图片数据21。
通信接口22和通信接口28都可以配置为单向通信接口，如图1中用于经编码图片数据13的从源设备12指向目的地设备14的箭头所指示，或配置为双向通信接口，以及可以用于例如发送和接收消息来建立连接、确认和交换任何其它与通信链路和/或例如经编码图片数据传输的数据传输有关的信息。
解码器30用于接收经编码图片数据21并提供经解码图片数据31或经解码图片31(下文将进一步描述细节，例如，基于图3或图5)。
目的地设备14的后处理器32用于后处理经解码图片数据31(也称为经重构图片数据)，例如，经解码图片131，以获得经后处理图片数据33，例如，经后处理图片33。后处理单元32执行的后处理可以包括，例如，色彩格式转换(例如，从YCbCr转换为RGB)、调色、整修或重采样，或任何其它处理，用于例如准备经解码图片数据31以由显示设备34显示。
目的地设备14的显示设备34用于接收经后处理图片数据33以向例如用户或观看者显示图片。显示设备34可以为或可以包括任何类别的用于呈现经重构图片的显示器，例如，集成的或外部的显示器或监视器。例如，显示器可以包括液晶显示器(liquid crystal  display，LCD)、有机发光二极管(organic light emitting diode，OLED)显示器、等离子显示器、投影仪、微LED显示器、硅基液晶(liquid crystal on silicon，LCoS)、数字光处理器(digital light processor，DLP)或任何类别的其它显示器。
虽然图1将源设备12和目的地设备14绘示为单独的设备，但设备实施例也可以同时包括源设备12和目的地设备14或同时包括两者的功能性，即源设备12或对应的功能性以及目的地设备14或对应的功能性。在此类实施例中，可以使用相同硬件和/或软件，或使用单独的硬件和/或软件，或其任何组合来实施源设备12或对应的功能性以及目的地设备14或对应的功能性。
本领域技术人员基于描述明显可知，不同单元的功能性或图1所示的源设备12和/或目的地设备14的功能性的存在和(准确)划分可能根据实际设备和应用有所不同。
编码器20(例如，视频编码器20)和解码器30(例如，视频解码器30)都可以实施为各种合适电路中的任一个，例如，一个或多个微处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application-specific integrated circuit，ASIC)、现场可编程门阵列(field-programmable gate array，FPGA)、离散逻辑、硬件或其任何组合。如果部分地以软件实施所述技术，则设备可将软件的指令存储于合适的非暂时性计算机可读存储介质中，且可使用一或多个处理器以硬件执行指令从而执行本公开的技术。前述内容(包含硬件、软件、硬件与软件的组合等)中的任一者可视为一或多个处理器。视频编码器20和视频解码器30中的每一个可以包含在一或多个编码器或解码器中，所述编码器或解码器中的任一个可以集成为对应设备中的组合编码器/解码器(编解码器)的一部分。
源设备12可称为视频编码设备或视频编码装置。目的地设备14可称为视频解码设备或视频解码装置。源设备12以及目的地设备14可以是视频编码设备或视频编码装置的实例。
源设备12和目的地设备14可以包括各种设备中的任一个，包含任何类别的手持或静止设备，例如，笔记本或膝上型计算机、移动电话、智能电话、平板或平板计算机、摄像机、台式计算机、机顶盒、电视、显示设备、数字媒体播放器、视频游戏控制台、视频流式传输设备(例如内容服务服务器或内容分发服务器)、广播接收器设备、广播发射器设备等，并可以不使用或使用任何类别的操作系统。
在一些情况下，源设备12和目的地设备14可以经装备以用于无线通信。因此，源设备12和目的地设备14可以为无线通信设备。
在一些情况下，图1中所示视频编码系统10仅为示例，本申请的技术可以适用于不必包含编码和解码设备之间的任何数据通信的视频编码设置(例如，视频编码或视频解码)。在其它实例中，数据可从本地存储器检索、在网络上流式传输等。视频编码设备可以对数据进行编码并且将数据存储到存储器，和/或视频解码设备可以从存储器检索数据并且对数据进行解码。在一些实例中，由并不彼此通信而是仅编码数据到存储器和/或从存储器检索数据且解码数据的设备执行编码和解码。
应理解，对于以上参考视频编码器20所描述的实例中的每一个，视频解码器30可以用于执行相反过程。关于信令语法元素，视频解码器30可以用于接收并解析这种语法元素，相应地解码相关视频数据。在一些例子中，视频编码器20可以将一个或多个定义……的语法元素熵编码成经编码视频比特流。在此类实例中，视频解码器30可以解析这种语 法元素，并相应地解码相关视频数据。
编码器&编码方法
图2示出用于实现本申请(公开)技术的视频编码器20的实例的示意性/概念性框图。在图2的实例中，视频编码器20包括残差计算单元204、变换处理单元206、量化单元208、逆量化单元210、逆变换处理单元212、重构单元214、缓冲器216、环路滤波器单元220、经解码图片缓冲器(decoded picture buffer，DPB)230、预测处理单元260和熵编码单元270。预测处理单元260可以包含帧间预测单元244、帧内预测单元254和模式选择单元262。帧间预测单元244可以包含运动估计单元和运动补偿单元(未图示)。图2所示的视频编码器20也可以称为混合型视频编码器或根据混合型视频编解码器的视频编码器。
例如，残差计算单元204、变换处理单元206、量化单元208、预测处理单元260和熵编码单元270形成编码器20的前向信号路径，而例如逆量化单元210、逆变换处理单元212、重构单元214、缓冲器216、环路滤波器220、经解码图片缓冲器(decoded picture buffer，DPB)230、预测处理单元260形成编码器的后向信号路径，其中编码器的后向信号路径对应于解码器的信号路径(参见图3中的解码器30)。
编码器20通过例如输入202，接收图片201或图片201的块203，例如，形成视频或视频序列的图片序列中的图片。图片块203也可以称为当前图片块或待编码图片块，图片201可以称为当前图片或待编码图片(尤其是在视频编码中将当前图片与其它图片区分开时，其它图片例如同一视频序列亦即也包括当前图片的视频序列中的先前经编码和/或经解码图片)。
分割
编码器20的实施例可以包括分割单元(图2中未绘示)，用于将图片201分割成多个例如块203的块，通常分割成多个不重叠的块。分割单元可以用于对视频序列中所有图片使用相同的块大小以及定义块大小的对应栅格，或用于在图片或子集或图片群组之间更改块大小，并将每个图片分割成对应的块。
在一个实例中，视频编码器20的预测处理单元260可以用于执行上述分割技术的任何组合。
如图片201，块203也是或可以视为具有亮度值(采样值)的采样点的二维阵列或矩阵，虽然其尺寸比图片201小。换句话说，块203可以包括，例如，一个采样阵列(例如黑白图片201情况下的亮度阵列)或三个采样阵列(例如，彩色图片情况下的一个亮度阵列和两个色度阵列)或依据所应用的色彩格式的任何其它数目和/或类别的阵列。块203的水平和垂直方向(或轴线)上采样点的数目定义块203的尺寸。
如图2所示的编码器20用于逐块编码图片201，例如，对每个块203执行编码和预测。
残差计算
残差计算单元204用于基于图片块203和预测块265(下文提供预测块265的其它细节)计算残差块205，例如，通过逐样本(逐像素)将图片块203的样本值减去预测块265的样本值，以在样本域中获取残差块205。
变换
变换处理单元206用于在残差块205的样本值上应用例如离散余弦变换(discrete cosine transform，DCT)或离散正弦变换(discrete sine transform，DST)的变换，以在变换域中获取变换系数207。变换系数207也可以称为变换残差系数，并在变换域中表示残差块205。
变换处理单元206可以用于应用DCT/DST的整数近似值，例如为HEVC/H.265指定的变换。与正交DCT变换相比，这种整数近似值通常由某一因子按比例缩放。为了维持经正变换和逆变换处理的残差块的范数，应用额外比例缩放因子作为变换过程的一部分。比例缩放因子通常是基于某些约束条件选择的，例如，比例缩放因子是用于移位运算的2的幂、变换系数的位深度、准确性和实施成本之间的权衡等。例如，在解码器30侧通过例如逆变换处理单元212为逆变换(以及在编码器20侧通过例如逆变换处理单元212为对应逆变换)指定具体比例缩放因子，以及相应地，可以在编码器20侧通过变换处理单元206为正变换指定对应比例缩放因子。
量化
量化单元208用于例如通过应用标量量化或向量量化来量化变换系数207，以获得经量化变换系数209。经量化变换系数209也可以称为经量化残差系数209。量化过程可以减少与部分或全部变换系数207有关的位深度。例如，可在量化期间将n位变换系数向下舍入到m位变换系数，其中n大于m。可通过调整量化参数(quantization parameter，QP)修改量化程度。例如，对于标量量化，可以应用不同的标度来实现较细或较粗的量化。较小量化步长对应较细量化，而较大量化步长对应较粗量化。可以通过量化参数(quantization parameter，QP)指示合适的量化步长。例如，量化参数可以为合适的量化步长的预定义集合的索引。例如，较小的量化参数可以对应精细量化(较小量化步长)，较大量化参数可以对应粗糙量化(较大量化步长)，反之亦然。量化可以包含除以量化步长以及例如通过逆量化210执行的对应的量化或逆量化，或者可以包含乘以量化步长。根据例如HEVC的一些标准的实施例可以使用量化参数来确定量化步长。一般而言，可以基于量化参数使用包含除法的等式的定点近似来计算量化步长。可以引入额外比例缩放因子来进行量化和反量化，以恢复可能由于在用于量化步长和量化参数的等式的定点近似中使用的标度而修改的残差块的范数。在一个实例实施方式中，可以合并逆变换和反量化的标度。或者，可以使用自定义量化表并在例如比特流中将其从编码器通过信号发送到解码器。量化是有损操作，其中量化步长越大，损耗越大。
逆量化单元210用于在经量化系数上应用量化单元208的逆量化，以获得经反量化系数211，例如，基于或使用与量化单元208相同的量化步长，应用量化单元208应用的量化方案的逆量化方案。经反量化系数211也可以称为经反量化残差系数211，对应于变换系数207，虽然由于量化造成的损耗通常与变换系数不相同。
逆变换处理单元212用于应用变换处理单元206应用的变换的逆变换，例如，逆离散余弦变换(discrete cosine transform，DCT)或逆离散正弦变换(discrete sine transform，DST)，以在样本域中获取逆变换块213。逆变换块213也可以称为逆变换经反量化块213或逆变换残差块213。
重构单元214(例如，求和器214)用于将逆变换块213(即经重构残差块213)添加至预测块265，以在样本域中获取经重构块215，例如，将经重构残差块213的样本值与 预测块265的样本值相加。
可选地，例如线缓冲器216的缓冲器单元216(或简称“缓冲器”216)用于缓冲或存储经重构块215和对应的样本值，用于例如帧内预测。在其它的实施例中，编码器可以用于使用存储在缓冲器单元216中的未经滤波的经重构块和/或对应的样本值来进行任何类别的估计和/或预测，例如帧内预测。
例如，编码器20的实施例可以经配置以使得缓冲器单元216不只用于存储用于帧内预测254的经重构块215，也用于环路滤波器单元220(在图2中未示出)，和/或，例如使得缓冲器单元216和经解码图片缓冲器单元230形成一个缓冲器。其它实施例可以用于将经滤波块221和/或来自经解码图片缓冲器230的块或样本(图2中均未示出)用作帧内预测254的输入或基础。
环路滤波器单元220(或简称“环路滤波器”220)用于对经重构块215进行滤波以获得经滤波块221，从而顺利进行像素转变或提高视频质量。环路滤波器单元220旨在表示一个或多个环路滤波器，例如去块滤波器、样本自适应偏移(sample-adaptive offset，SAO)滤波器或其它滤波器，例如双边滤波器、自适应环路滤波器(adaptive loop filter，ALF)，或锐化或平滑滤波器，或协同滤波器。尽管环路滤波器单元220在图2中示出为环内滤波器，但在其它配置中，环路滤波器单元220可实施为环后滤波器。经滤波块221也可以称为经滤波的经重构块221。经解码图片缓冲器230可以在环路滤波器单元220对经重构编码块执行滤波操作之后存储经重构编码块。
编码器20(对应地，环路滤波器单元220)的实施例可以用于输出环路滤波器参数(例如，样本自适应偏移信息)，例如，直接输出或由熵编码单元270或任何其它熵编码单元熵编码后输出，例如使得解码器30可以接收并应用相同的环路滤波器参数用于解码。
经解码图片缓冲器(decoded picture buffer，DPB)230可以为存储参考图片数据供视频编码器20编码视频数据之用的参考图片存储器。DPB 230可由多种存储器设备中的任一个形成，例如动态随机存储器(dynamic random access memory，DRAM)(包含同步DRAM(synchronous DRAM，SDRAM)、磁阻式RAM(magnetoresistive RAM，MRAM)、电阻式RAM(resistive RAM，RRAM))或其它类型的存储器设备。可以由同一存储器设备或单独的存储器设备提供DPB 230和缓冲器216。在某一实例中，经解码图片缓冲器(decoded picture buffer，DPB)230用于存储经滤波块221。经解码图片缓冲器230可以进一步用于存储同一当前图片或例如先前经重构图片的不同图片的其它先前的经滤波块，例如先前经重构和经滤波块221，以及可以提供完整的先前经重构亦即经解码图片(和对应参考块和样本)和/或部分经重构当前图片(和对应参考块和样本)，例如用于帧间预测。在某一实例中，如果经重构块215无需环内滤波而得以重构，则经解码图片缓冲器(decoded picture buffer，DPB)230用于存储经重构块215。
预测处理单元260，也称为块预测处理单元260，用于接收或获取块203(当前图片201的当前块203)和经重构图片数据，例如来自缓冲器216的同一(当前)图片的参考样本和/或来自经解码图片缓冲器230的一个或多个先前经解码图片的参考图片数据231，以及用于处理这类数据进行预测，即提供可以为经帧间预测块245或经帧内预测块255的预测块265。
模式选择单元262可以用于选择预测模式(例如帧内或帧间预测模式)和/或对应的 用作预测块265的预测块245或255，以计算残差块205和重构经重构块215。
模式选择单元262的实施例可以用于选择预测模式(例如，从预测处理单元260所支持的那些预测模式中选择)，所述预测模式提供最佳匹配或者说最小残差(最小残差意味着传输或存储中更好的压缩)，或提供最小信令开销(最小信令开销意味着传输或存储中更好的压缩)，或同时考虑或平衡以上两者。模式选择单元262可以用于基于码率失真优化(rate distortion optimization，RDO)确定预测模式，即选择提供最小码率失真优化的预测模式，或选择相关码率失真至少满足预测模式选择标准的预测模式。
下文将详细解释编码器20的实例(例如，通过预测处理单元260)执行的预测处理和(例如，通过模式选择单元262)执行的模式选择。
如上文所述，编码器20用于从(预先确定的)预测模式集合中确定或选择最好或最优的预测模式。预测模式集合可以包括例如帧内预测模式和/或帧间预测模式。
帧内预测模式集合可以包括35种不同的帧内预测模式，例如，如DC(或均值)模式和平面模式的非方向性模式，或如H.265中定义的方向性模式，或者可以包括67种不同的帧内预测模式，例如，如DC(或均值)模式和平面模式的非方向性模式，或如正在发展中的H.266中定义的方向性模式。
(可能的)帧间预测模式集合取决于可用参考图片(即，例如前述存储在DBP 230中的至少部分经解码图片)和其它帧间预测参数，例如取决于是否使用整个参考图片或只使用参考图片的一部分，例如围绕当前块的区域的搜索窗区域，来搜索最佳匹配参考块，和/或例如取决于是否应用如半像素和/或四分之一像素内插的像素内插。
除了以上预测模式，也可以应用跳过模式和/或直接模式。
预测处理单元260可以进一步用于将块203分割成较小的块分区或子块，例如，通过迭代使用四叉树(quad-tree，QT)分割、二叉树(binary-tree，BT)分割或三叉树(triple-tree or ternary-tree，TT)分割，或其任何组合，以及用于例如为块分区或子块中的每一个执行预测，其中模式选择包括选择分割的块203的树结构和选择应用于块分区或子块中的每一个的预测模式。
帧间预测单元244可以包含运动估计(motion estimation，ME)单元(图2中未示出)和运动补偿(motion compensation，MC)单元(图2中未示出)。运动估计单元用于接收或获取图片块203(当前图片201的当前图片块203)和经解码图片231，或至少一个或多个先前经重构块，例如，一个或多个其它/不同先前经解码图片231的经重构块，来进行运动估计。例如，视频序列可以包括当前图片和先前经解码图片31，或换句话说，当前图片和先前经解码图片31可以是形成视频序列的图片序列的一部分，或者形成该图片序列。
例如，编码器20可以用于从多个其它图片中的同一或不同图片的多个参考块中选择参考块，并向运动估计单元(图2中未示出)提供参考图片(或参考图片索引)和/或提供参考块的位置(X、Y坐标)与当前块的位置之间的偏移(空间偏移)作为帧间预测参数。该偏移也称为运动向量(motion vector，MV)。
运动补偿单元用于获取，例如接收帧间预测参数，并基于或使用帧间预测参数执行帧间预测来获取帧间预测块245。由运动补偿单元(图2中未示出)执行的运动补偿可以包含基于通过运动估计(可能执行对子像素精确度的内插)确定的运动/块向量取出或生成 预测块。内插滤波可从已知像素样本产生额外像素样本，从而潜在地增加可用于编码图片块的候选预测块的数目。一旦接收到用于当前图片块的PU的运动向量，运动补偿单元246可以在一个参考图片列表中定位运动向量指向的预测块。运动补偿单元246还可以生成与块和视频条带相关联的语法元素，以供视频解码器30在解码视频条带的图片块时使用。
帧内预测单元254用于获取，例如接收同一图片的图片块203(当前图片块)和一个或多个先前经重构块，例如经重构相邻块，以进行帧内估计。例如，编码器20可以用于从多个(预定)帧内预测模式中选择帧内预测模式。
编码器20的实施例可以用于基于优化标准选择帧内预测模式，例如基于最小残差(例如，提供最类似于当前图片块203的预测块255的帧内预测模式)或最小码率失真。
帧内预测单元254进一步用于基于如所选择的帧内预测模式的帧内预测参数确定帧内预测块255。在任何情况下，在选择用于块的帧内预测模式之后，帧内预测单元254还用于向熵编码单元270提供帧内预测参数，即提供指示所选择的用于块的帧内预测模式的信息。在一个实例中，帧内预测单元254可以用于执行下文描述的帧内预测技术的任意组合。
熵编码单元270用于将熵编码算法或方案(例如，可变长度编码(variable length coding，VLC)方案、上下文自适应VLC(context adaptive VLC，CAVLC)方案、算术编码方案、上下文自适应二进制算术编码(context adaptive binary arithmetic coding，CABAC)、基于语法的上下文自适应二进制算术编码(syntax-based context-adaptive binary arithmetic coding，SBAC)、概率区间分割熵(probability interval partitioning entropy，PIPE)编码或其它熵编码方法或技术)应用于经量化残差系数209、帧间预测参数、帧内预测参数和/或环路滤波器参数中的单个或所有上(或不应用)，以获得可以通过输出272以例如经编码比特流21的形式输出的经编码图片数据21。可以将经编码比特流传输到视频解码器30，或将其存档稍后由视频解码器30传输或检索。熵编码单元270还可用于熵编码正被编码的当前视频条带的其它语法元素。
视频编码器20的其它结构变型可用于编码视频流。例如，基于非变换的编码器20可以在没有针对某些块或帧的变换处理单元206的情况下直接量化残差信号。在另一实施方式中，编码器20可具有组合成单个单元的量化单元208和逆量化单元210。
图3示出示例性视频解码器30，用于实现本申请的技术。视频解码器30用于接收例如由编码器20编码的经编码图片数据(例如，经编码比特流)21，以获得经解码图片231。在解码过程期间，视频解码器30从视频编码器20接收视频数据，例如表示经编码视频条带的图片块的经编码视频比特流及相关联的语法元素。
在图3的实例中，解码器30包括熵解码单元304、逆量化单元310、逆变换处理单元312、重构单元314(例如求和器314)、缓冲器316、环路滤波器320、经解码图片缓冲器330以及预测处理单元360。预测处理单元360可以包含帧间预测单元344、帧内预测单元354和模式选择单元362。在一些实例中，视频解码器30可执行大体上与参照图2的视频编码器20描述的编码遍次互逆的解码遍次。
熵解码单元304用于对经编码图片数据21执行熵解码，以获得例如经量化系数309和/或经解码的编码参数(图3中未示出)，例如，帧间预测、帧内预测参数、环路滤波器参数和/或其它语法元素中(经解码)的任意一个或全部。熵解码单元304进一步用于 将帧间预测参数、帧内预测参数和/或其它语法元素转发至预测处理单元360。视频解码器30可接收视频条带层级和/或视频块层级的语法元素。
逆量化单元310功能上可与逆量化单元110相同，逆变换处理单元312功能上可与逆变换处理单元212相同，重构单元314功能上可与重构单元214相同，缓冲器316功能上可与缓冲器216相同，环路滤波器320功能上可与环路滤波器220相同，经解码图片缓冲器330功能上可与经解码图片缓冲器230相同。
预测处理单元360可以包括帧间预测单元344和帧内预测单元354，其中帧间预测单元344功能上可以类似于帧间预测单元244，帧内预测单元354功能上可以类似于帧内预测单元254。预测处理单元360通常用于执行块预测和/或从经编码数据21获取预测块365，以及从例如熵解码单元304(显式地或隐式地)接收或获取预测相关参数和/或关于所选择的预测模式的信息。
当视频条带经编码为经帧内编码(I)条带时，预测处理单元360的帧内预测单元354用于基于信号表示的帧内预测模式及来自当前帧或图片的先前经解码块的数据来产生用于当前视频条带的图片块的预测块365。当视频帧经编码为经帧间编码(即B或P)条带时，预测处理单元360的帧间预测单元344(例如，运动补偿单元)用于基于运动向量及从熵解码单元304接收的其它语法元素生成用于当前视频条带的视频块的预测块365。对于帧间预测，可从一个参考图片列表内的一个参考图片中产生预测块。视频解码器30可基于存储于DPB 330中的参考图片，使用默认建构技术来建构参考帧列表：列表0和列表1。
预测处理单元360用于通过解析运动向量和其它语法元素，确定用于当前视频条带的视频块的预测信息，并使用预测信息产生用于正经解码的当前视频块的预测块。例如，预测处理单元360使用接收到的一些语法元素确定用于编码视频条带的视频块的预测模式(例如，帧内或帧间预测)、帧间预测条带类型(例如，B条带、P条带或GPB条带)、用于条带的参考图片列表中的一个或多个的建构信息、用于条带的每个经帧间编码视频块的运动向量、条带的每个经帧间编码视频块的帧间预测状态以及其它信息，以解码当前视频条带的视频块。
逆量化单元310可用于逆量化(即，反量化)在比特流中提供且由熵解码单元304解码的经量化变换系数。逆量化过程可包含使用由视频编码器20针对视频条带中的每一视频块所计算的量化参数来确定应该应用的量化程度并同样确定应该应用的逆量化程度。
逆变换处理单元312用于将逆变换(例如，逆DCT、逆整数变换或概念上类似的逆变换过程)应用于变换系数，以便在像素域中产生残差块。
重构单元314(例如，求和器314)用于将逆变换块313(即经重构残差块313)添加到预测块365，以在样本域中获取经重构块315，例如通过将经重构残差块313的样本值与预测块365的样本值相加。
环路滤波器单元320(在编码循环期间或在编码循环之后)用于对经重构块315进行滤波以获得经滤波块321，从而顺利进行像素转变或提高视频质量。在一个实例中，环路滤波器单元320可以用于执行下文描述的滤波技术的任意组合。环路滤波器单元320旨在表示一个或多个环路滤波器，例如去块滤波器、样本自适应偏移(sample-adaptive offset，SAO)滤波器或其它滤波器，例如双边滤波器、自适应环路滤波器(adaptive loop filter， ALF)，或锐化或平滑滤波器，或协同滤波器。尽管环路滤波器单元320在图3中示出为环内滤波器，但在其它配置中，环路滤波器单元320可实施为环后滤波器。
随后将给定帧或图片中的经解码视频块321存储在存储用于后续运动补偿的参考图片的经解码图片缓冲器330中。
解码器30用于例如，藉由输出332输出经解码图片31，以向用户呈现或供用户查看。
视频解码器30的其它变型可用于对压缩的比特流进行解码。例如，解码器30可以在没有环路滤波器单元320的情况下生成输出视频流。例如，基于非变换的解码器30可以在没有针对某些块或帧的逆变换处理单元312的情况下直接逆量化残差信号。在另一实施方式中，视频解码器30可以具有组合成单个单元的逆量化单元310和逆变换处理单元312。
图4是根据一示例性实施例的包含图2的编码器20和/或图3的解码器30的视频编码系统40的实例的说明图。系统40可以实现本申请的各种技术的组合。在所说明的实施方式中，视频编码系统40可以包含成像设备41、视频编码器20、视频解码器30(和/或藉由处理单元46的逻辑电路47实施的视频编码器)、天线42、一个或多个处理器43、一个或多个存储器44和/或显示设备45。
如图所示，成像设备41、天线42、处理单元46、逻辑电路47、视频编码器20、视频解码器30、处理器43、存储器44和/或显示设备45能够互相通信。如所论述，虽然用视频编码器20和视频解码器30绘示视频编码系统40，但在不同实例中，视频编码系统40可以只包含视频编码器20或只包含视频解码器30。
在一些实例中，如图所示，视频编码系统40可以包含天线42。例如，天线42可以用于传输或接收视频数据的经编码比特流。另外，在一些实例中，视频编码系统40可以包含显示设备45。显示设备45可以用于呈现视频数据。在一些实例中，如图所示，逻辑电路47可以通过处理单元46实施。处理单元46可以包含专用集成电路(application-specific integrated circuit，ASIC)逻辑、图形处理器、通用处理器等。视频编码系统40也可以包含可选处理器43，该可选处理器43类似地可以包含专用集成电路(application-specific integrated circuit，ASIC)逻辑、图形处理器、通用处理器等。在一些实例中，逻辑电路47可以通过硬件实施，如视频编码专用硬件等，处理器43可以通过通用软件、操作系统等实施。另外，存储器44可以是任何类型的存储器，例如易失性存储器(例如，静态随机存取存储器(Static Random Access Memory，SRAM)、动态随机存储器(Dynamic Random Access Memory，DRAM)等)或非易失性存储器(例如，闪存等)等。在非限制性实例中，存储器44可以由超速缓存内存实施。在一些实例中，逻辑电路47可以访问存储器44(例如用于实施图像缓冲器)。在其它实例中，逻辑电路47和/或处理单元46可以包含存储器(例如，缓存等)用于实施图像缓冲器等。
在一些实例中，通过逻辑电路实施的视频编码器20可以包含(例如，通过处理单元46或存储器44实施的)图像缓冲器和(例如，通过处理单元46实施的)图形处理单元。图形处理单元可以通信耦合至图像缓冲器。图形处理单元可以包含通过逻辑电路47实施的视频编码器20，以实施参照图2和/或本文中所描述的任何其它编码器系统或子系统所论述的各种模块。逻辑电路可以用于执行本文所论述的各种操作。
视频解码器30可以以类似方式通过逻辑电路47实施，以实施参照图3的解码器30和/或本文中所描述的任何其它解码器系统或子系统所论述的各种模块。在一些实例中， 逻辑电路实施的视频解码器30可以包含(通过处理单元2820或存储器44实施的)图像缓冲器和(例如，通过处理单元46实施的)图形处理单元。图形处理单元可以通信耦合至图像缓冲器。图形处理单元可以包含通过逻辑电路47实施的视频解码器30，以实施参照图3和/或本文中所描述的任何其它解码器系统或子系统所论述的各种模块。
在一些实例中，视频编码系统40的天线42可以用于接收视频数据的经编码比特流。如所论述，经编码比特流可以包含本文所论述的与编码视频帧相关的数据、指示符、索引值、模式选择数据等，例如与编码分割相关的数据(例如，变换系数或经量化变换系数，(如所论述的)可选指示符，和/或定义编码分割的数据)。视频编码系统40还可包含耦合至天线42并用于解码经编码比特流的视频解码器30。显示设备45用于呈现视频帧。
图5是根据一示例性实施例的可用作图1中的源设备12和目的地设备14中的任一个或两个的装置500的简化框图。装置500可以实现本申请的技术，装置500可以采用包含多个计算设备的计算系统的形式，或采用例如移动电话、平板计算机、膝上型计算机、笔记本电脑、台式计算机等单个计算设备的形式。
装置500中的处理器502可以为中央处理器。或者，处理器502可以为现有的或今后将研发出的能够操控或处理信息的任何其它类型的设备或多个设备。如图所示，虽然可以使用例如处理器502的单个处理器实践所揭示的实施方式，但是使用一个以上处理器可以实现速度和效率方面的优势。
在一实施方式中，装置500中的存储器504可以为只读存储器(Read Only Memory，ROM)设备或随机存取存储器(random access memory，RAM)设备。任何其他合适类型的存储设备都可以用作存储器504。存储器504可以包括代码和由处理器502使用总线512访问的数据506。存储器504可进一步包括操作系统508和应用程序510，应用程序510包含至少一个准许处理器502执行本文所描述的方法的程序。例如，应用程序510可以包括应用1到N，应用1到N进一步包括执行本文所描述的方法的视频编码应用。装置500还可包含采用从存储器514形式的附加存储器，该从存储器514例如可以为与移动计算设备一起使用的存储卡。因为视频通信会话可能含有大量信息，这些信息可以整体或部分存储在从存储器514中，并按需要加载到存储器504用于处理。
装置500还可包含一或多个输出设备，例如显示器518。在一个实例中，显示器518可以为将显示器和可操作以感测触摸输入的触敏元件组合的触敏显示器。显示器518可以通过总线512耦合于处理器502。除了显示器518还可以提供其它准许用户对装置500编程或以其它方式使用装置500的输出设备，或提供其它输出设备作为显示器518的替代方案。当输出设备是显示器或包含显示器时，显示器可以以不同方式实现，包含通过液晶显示器(liquid crystal display，LCD)、阴极射线管(cathode-ray tube，CRT)显示器、等离子显示器或发光二极管(light emitting diode，LED)显示器，如有机LED(organic LED，OLED)显示器。
装置500还可包含图像感测设备520或与其连通，图像感测设备520例如为相机或为现有的或今后将研发出的可以感测图像的任何其它图像感测设备520，所述图像例如为运行装置500的用户的图像。图像感测设备520可以放置为直接面向运行装置500的用户。在一实例中，可以配置图像感测设备520的位置和光轴以使其视野包含紧邻显示器518的区域且从该区域可见显示器518。
装置500还可包含声音感测设备522或与其连通，声音感测设备522例如为麦克风或为现有的或今后将研发出的可以感测装置500附近的声音的任何其它声音感测设备。声音感测设备522可以放置为直接面向运行装置500的用户，并可以用于接收用户在运行装置500时发出的声音，例如语音或其它发声。
虽然图5中将装置500的处理器502和存储器504绘示为集成在单个单元中，但是还可以使用其它配置。处理器502的运行可以分布在多个可直接耦合的机器中(每个机器具有一个或多个处理器)，或分布在本地区域或其它网络中。存储器504可以分布在多个机器中，例如基于网络的存储器或多个运行装置500的机器中的存储器。虽然此处只绘示单个总线，但装置500的总线512可以由多个总线形成。进一步地，从存储器514可以直接耦合至装置500的其它组件或可以通过网络访问，并且可包括单个集成单元，例如一个存储卡，或多个单元，例如多个存储卡。因此，可以以多种配置实施装置500。
在本申请中，DCT2矩阵也可以简写成DCT2，DCT2’矩阵也可以简写成DCT2，DST4矩阵也可以简写成DST4，DCT2’FS矩阵也可以简写成DCT2’FS，DCT2’F矩阵也可以简写成DCT2’F，DST7矩阵也可以简写成DST7。
下面先结合图6对本申请实施例的视频编码方法进行详细的介绍。
图6是本申请实施例的逆视频编码方法的示意性流程图。图6所示的方法包括步骤1001至步骤1005，下面分别对步骤1001至步骤1005进行详细的介绍。
1001、解析码流，以获取当前块进行逆变换处理的目标变换矩阵对索引值以及当前块的量化系数。
在步骤1001中，在获取到码流之后，可以通过对码流进行熵解码等操作来获取当前块的量化系数和目标变换矩阵对索引值。
可选地，通过对码流进行熵解码等操作还可以获取当前块对应的预测模式。
1002、对当前块的量化系数进行逆量化处理，以获取当前块的反量化系数。
1003、根据所述目标变换矩阵对索引值以及所述目标变换矩阵对索引值与候选变换矩阵对之间的对应关系，从所述候选变换矩阵对中确定目标变换矩阵对。
其中，上述候选变换矩阵对包括水平方向变换矩阵和垂直方向变换矩阵，该水平方向变换矩阵和垂直方向变换矩阵均为预设的两个变换矩阵中的一个，该预设的两个变换矩阵中的第一个变换矩阵为DCT2’矩阵，DCT2’矩阵为DCT2矩阵的转置矩阵。
上述候选变换矩阵对可以包括以下具体的变换矩阵对：
(1)、(变换矩阵A，变换矩阵A)；
(2)、(变换矩阵A，变换矩阵B)；
(3)、(变换矩阵B，变换矩阵A)；
(4)、(变换矩阵B，变换矩阵B)。
其中，括号中的第一个变换矩阵和第二个变换矩阵可以分别是垂直方向变换矩阵和水平方向变换矩阵。
上述变换矩阵B可以是DCT2’。
上述目标变换矩阵对可以是上述四个变换矩阵对中的一个(具体是候选变换矩阵对中的哪个变换矩阵对可以根据目标变换矩阵对索引值以及目标变换矩阵对索引值与候选变换矩阵对之间的对应关系来确定)。
对于DCT2’矩阵来说，由于DCT2’矩阵的变换/逆变换存在快速算法，因此，利用DCT2’矩阵来替换现有技术中的DCT8矩阵/DCT4矩阵(DCT8矩阵/DCT4矩阵不存在快速算法)。能够进一步简化DCT2’矩阵的变换/逆变换的实现。同时，由于DCT2’矩阵是DCT2矩阵的转置，DCT2’矩阵可以复用DCT2矩阵的变换逆变换实现电路(如乘法器)，能够提高硬件电路的利用效率。
例如，4x4 DCT2矩阵具体如下：
Figure PCTCN2019119213-appb-000001
对该矩阵进行转置就可得到4x4 DCT2’矩阵，4x4 DCT2’矩阵具体如下：
Figure PCTCN2019119213-appb-000002
目标变换矩阵对索引值与候选变换矩阵对之间的对应关系(也可以称为映射关系)可以如表1所示，其中，DCT2’是预设的两个变换矩阵中的第一个变换矩阵，变换矩阵A是预设的两个变换矩阵中的第二个变换矩阵。
表1
Figure PCTCN2019119213-appb-000003
如表1所示，解码端在获取到目标变换矩阵对索引之后，可以根据表1所示的对应关系确定目标变换矩阵对。例如，解码端通过解析码流获取目标变换矩阵对索引值为1，那么，解码端根据表1中所示的对应关系就可以确定目标变换矩阵对由变换矩阵A和DCT2’矩阵组成，其中，变换矩阵A为目标变换矩阵对中的垂直方向变换矩阵，DCT2’为目标变换矩阵对中的水平方向变换矩阵。
应理解，表1只是目标变换矩阵对索引值与候选变换矩阵对的对应关系的一种具体的形式(每个索引值对应的候选变换矩阵对也只是一种举例)，在本申请中，目标变换矩阵对索引值与候选变换矩阵对的对应关系并不限于表1中所示的具体形式，目标变换矩阵对索引值与候选变换矩阵对的对应关系还可以用表格之外的其它形式来表示，本申请对此不做限制。
另外，表1中的目标变换矩阵对索引值的取值也只是一种具体的情况，本申请对目标变换矩阵对索引值具体取某个数值时对应哪个变换矩阵对不做限制(下文中表示目标变换矩阵对索引值与候选变换矩阵对的对应关系的表格也只是一种具体的情况，目标变换矩阵 对索引值与候选变换矩阵对的对应关系的表现形式并不限于本申请中的表格所表示的形式)。
1004、根据目标变换矩阵对对当前块的反量化系数进行逆变换处理，以得到当前块的重建残差块；
1005、根据当前块的重建残差块获得当前块的重构块
具体地，假设目标变换矩阵对为(A，B)，解码获取到的变换系数块为F，那么，可以根据公式(1)进行逆变换，得到残差块R。其中，A为水平方向变换矩阵，B为垂直方向变换矩阵，
R＝B’*F*A       (1)
其中B’表示矩阵B的转置矩阵，由于B为正交矩阵，对B进行转置相当于求B的逆矩阵。
本申请中，由于候选变换矩阵对中包含DCT2’矩阵，而DCT2’矩阵逆变换过程中存在快速算法，因此，当采用DCT2’进行逆变换时能够采用快速算法，能够降低逆变过程的计算复杂度。
进一步的，由于DCT2’矩阵是DCT2矩阵的转置，因此，在逆变换的过程中，DCT2’能够复用DCT2的逆变换实现电路，能够降低硬件实现成本。
可选地，DCT2’矩阵是根据DCT2矩阵推导得到的。
解码端可以预先存储DCT2矩阵或者DCT2矩阵的矩阵系数，当需要运用进行逆变换时，解码端可以根据DCT2矩阵中的矩阵系数推导DCT2’矩阵的矩阵系数。
本申请中，由于DCT2’矩阵是DCT2矩阵的转置，因此，DCT2’矩阵的矩阵系数能够根据DCT2的矩阵系数推导出来，而不必额外存储DCT2’矩阵的矩阵系数，能够减少存储开销。
下面结合具体的例子对如何根据DCT2矩阵推导DCT2’矩阵进行说明。
例如，4x4 DCT2矩阵具体如下：
Figure PCTCN2019119213-appb-000004
那么，通过对4x4 DCT2矩阵进行转置，可以得到4x4 DCT2’矩阵，得到的4x4 DCT2’矩阵具体如下：
Figure PCTCN2019119213-appb-000005
可选地，作为一个实施例，预设的两个变换矩阵中的第二个变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵。
其中，DCT2’FS矩阵和DCT2’F矩阵中的F表示镜像，DCT2’FS矩阵中的S表示符号变换。DCT2’F矩阵是对DCT2’矩阵进行镜像之后得到的矩阵，DCT2’FS矩阵是先对DCT2’矩阵进行镜像，然后再对镜像得到的矩阵进行符号变换得到的矩阵。
上述镜像可以是左右翻转镜像。
对一个矩阵左右翻转镜像可以是指将矩阵左侧的矩阵系数镜像到右侧，将矩阵右侧的矩阵系数镜像到左侧。
可选地，上述符号变换是指仅对矩阵的偶数行的矩阵系数进行符号取反，而矩阵的奇数行的矩阵系数保持不变。
可选地，上述符号变换是指仅对矩阵的奇数行的矩阵系数进行符号取反，而矩阵的偶数行的矩阵系数保持不变。
可选地，上述符号变换是对矩阵中所有的矩阵系数的符号取反。
本申请中，由于DCT2’FS和DCT2’F矩阵在逆变换过程中存在快速算法，能够简化逆变换时的计算复杂度。
可选的，预设的两个变换矩阵中的第一个矩阵为DCT2’矩阵，第二个矩阵为DCT2’FS矩阵或者DCT2’F矩阵适用于所有的变换尺寸(例如，这里的变换尺寸可以包括4点、8点、16点和32点等等)。
当预设的两个变换矩阵中的第一个矩阵为DCT2’矩阵，第二个矩阵为DCT2’FS矩阵时，目标变换矩阵对索引值与候选变换矩阵对之间的对应关系可以如表2所示。
表2
Figure PCTCN2019119213-appb-000006
为了更清楚的说明本申请采用在任何变换尺寸下都采用DCT2'矩阵和DCT2’FS矩阵作为目标变换矩阵对时的效果，下面以目标变换矩阵对中采用4-32点的DCT2'矩阵和4-32点的DCT2’FS矩阵为例，对逆变换时的计算复杂度进行分析，分析结果如表3所示。
表3
变换矩阵 快速算法(ODD矩阵尺寸) 变换所需乘法次数
32点DCT2’FS矩阵 ODD16+ODD8+ODD4+ODD2 16x16+8x8+4x4+2x2
16点DCT2’FS矩阵 ODD8+ODD4+ODD2 8x8+4x4+2x2
8点DCT2’FS矩阵 ODD4+ODD2 4x4+2x2
4点DCT2’FS矩阵 ODD2 2x2
32点DCT2'矩阵 ODD16+ODD8+ODD4+ODD2 16x16+8x8+4x4+2x2
16点DCT2'矩阵 ODD8+ODD4+ODD2 8x8+4x4+2x2
8点DCT2'矩阵 ODD4+ODD2 4x4+2x2
4点DCT2'矩阵 ODD2 2x2
由表3可知，对于4点、8点、16点以及32点的DCT2'矩阵和DCT2’FS矩阵来说，矩阵乘法尺寸(ODD矩阵尺寸)不超过16x16，大大降低了乘法次数，从而在很大程度上降低了计算复杂度。
另外，通过对变换/逆变换的过程进行分析发现，变换过程的计算复杂度主要来自于大尺寸变换，因此，可以在进行大尺寸变换场景下采用一些具有快速算法的变换矩阵进行变换，而在进行小尺寸变换场景下，仍然可以采用一些传统方案中应用的变换矩阵。
可选地，作为一个实施例，目标变换矩阵对中的水平变换矩阵为DCT2’矩阵，在当前块的高大于或者等于M点时，目标变换矩阵对中的垂直变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵；在当前块的高小于M点时，目标变换矩阵对中的垂直变换矩阵为DST4矩阵，其中，M为正整数。
可选地，作为一个实施例，目标变换矩阵对中的垂直变换矩阵为DCT2’矩阵，在当前块的宽大于或者等于M点时，目标变换矩阵对中的水平变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵；在当前块的高小于M点时，目标变换矩阵对中的水平变换矩阵为DST4矩阵，其中，M为正整数。
上述M可以为32。
本申请中，在大尺寸变换场景下采用具有快速算法的变换矩阵作为目标变换矩阵对中的水平变换矩阵或者垂直变换矩阵，而在小尺寸变换场景下采用适合小尺寸变换场景的变换矩阵作为目标变换矩阵对中的水平变换矩阵或者垂直变换矩阵，能够在大尺寸变换场景下，显著的降低逆变换的复杂度，同时还能在小尺寸场景下保证变换性能，能够在降低逆变换复杂度和保证逆变换性能之间取得平衡。
当上述M为32时，如果变换尺寸大于等于32，那么，目标变换矩阵对可以由DCT2’矩阵和DCT2’FS矩阵(或者DCT2’F矩阵)组成，此时，目标变换矩阵对索引值与候选变换矩阵对之间的对应关系可以如表4所示。
表4
Figure PCTCN2019119213-appb-000007
当上述M为32时，如果变换尺寸小于32，那么，候选变换矩阵对可以由DCT2’矩阵和DST4矩阵组成，此时，目标变换矩阵对索引值与候选变换矩阵对之间的对应关系可以如表5所示。
表5
Figure PCTCN2019119213-appb-000008
可选地，作为一个实施例，预设的两个变换矩阵中的第二个变换矩阵是根据DCT2矩阵推导得到的。
本申请中，由于预设的两个变换矩阵中的第二个变换矩阵可以根据DCT2矩阵推导得到，因此，而不必额外存储该第二个变换矩阵的矩阵系数，能够减少存储开销。
本申请中，由于DCT2’FS矩阵、DCT2’F矩阵以及DST4矩阵可以根据DCT2矩阵推导得到，因此，而不必额外存储这些矩阵的矩阵系数，能够减少存储开销。
在本申请中，对于DCT2’FS矩阵、DCT2’F矩阵以及DST4矩阵来说，无论是32点矩阵还是尺寸更小矩阵，都可以根据64点的DCT2变换矩阵推导得到。
例如，对于32点的DCT2’FS矩阵来说,可以先根据32点的DCT2矩阵先得到32点的DCT2’变换矩阵，然后再对32点的DCT2’矩阵进行镜像和符号变换得到DCT2’FS(32点的DCT2’F矩阵只需要对DCT2’矩阵进行镜像就可以得到)。
例如，对于16点(或8点、4点)的DST4矩阵，可以从32(或16,、8)点DCT2矩阵中抽取出来DCT4矩阵，然后经过镜像和符号变换等操作得到DST4矩阵。
综上分析可知，当变换尺寸大于或者等于32时，预设的两个变换矩阵可以是DCT2’和DCT2’FS矩阵(或者DCT2’F矩阵)；当变换尺寸小于32时，预设的两个变换矩阵可以是和DCT2’矩阵和DST4矩阵。
下面结合具体的例子对如何根据DCT2矩阵推导预设的两个变换矩阵中的第二个变换矩阵进行说明。
下面以4x4矩阵为例，对根据DCT2矩阵推导得到DCT2’FS矩阵和DCT2’F矩阵的过程进行详细说明。
例如，4x4 DCT2矩阵具体如下：
Figure PCTCN2019119213-appb-000009
那么，通过对4x4 DCT2矩阵中的进行转置，可以先得到4x4 DCT2’矩阵，得到的4x4DCT2’矩阵具体如下：
Figure PCTCN2019119213-appb-000010
在得到4x4 DCT2’矩阵之后，可以通过对4x4 DCT2’矩阵的矩阵系数进行左右翻转镜像得到4x4 DCT2’F，4x4 DCT2’F矩阵具体如下：
Figure PCTCN2019119213-appb-000011
当预设的两个变换矩阵中的第二个变换矩阵为DCT2’F时，通过上述推导过程就得到了预设的两个变换矩阵中的第二个变换矩阵。
而当预设的两个变换矩阵中的第二个变换矩阵为DCT2’FS时，可以通过对上述4x4 DCT2’F矩阵进行符号变换，以得到4x4 DCT2’FS矩阵，4x4 DCT2’FS矩阵具体如下：
Figure PCTCN2019119213-appb-000012
为了更清楚的说明本申请在大尺寸场景下采用DCT2'矩阵和DCT2’FS矩阵作为目标变换矩阵对，小尺寸场景下采用DCT2'矩阵和DST4矩阵作为目标变换矩阵对进行变换时降低计算复杂度的效果，下面以目标变换矩阵对由DCT2'矩阵和DST4矩阵组成(4-16点时)，以及目标变换矩阵对由DCT2'矩阵和DCT2’FS矩阵组成(32点时)为例对变换的计算复杂度进行分析，分析结果如表6所示。
表6
变换矩阵 快速算法(ODD矩阵尺寸) 变换所需乘法次数
32点DCT2’FS矩阵 ODD16+ODD8+ODD4+ODD2 16x16+8x8+4x4+2x2
4-16点DST4矩阵 无快速算法,采用矩阵乘法 16x16x16+8x8x8+4x4x4
32点DCT2'矩阵 ODD16+ODD8+ODD4+ODD2 16x16+8x8+4x4+2x2
16点DCT2'矩阵 ODD8+ODD4+ODD2 8x8+4x4+2x2
8点DCT2'矩阵 ODD4+ODD2 4x4+2x2
4点DCT2'矩阵 ODD2 2x2
由表6可知，对于4-16点DST4矩阵和DCT2'矩阵以及32点DCT2’FS矩阵来说，矩阵乘法尺寸(ODD矩阵尺寸)不超过16x16，大大降低了乘法次数，从而在很大程度上降低了计算复杂度。
在本申请中，当变换尺寸为32点时，DCT2’矩阵可以是32×32矩阵，DCT2’F矩阵可以是32×32矩阵。
32×32 DCT2’矩阵具体如下：
Figure PCTCN2019119213-appb-000013
Figure PCTCN2019119213-appb-000014
Figure PCTCN2019119213-appb-000015
Figure PCTCN2019119213-appb-000016
32×32 DCT2’F矩阵具体如下：
Figure PCTCN2019119213-appb-000017
Figure PCTCN2019119213-appb-000018
Figure PCTCN2019119213-appb-000019
从上述示例可看出，DCT2’矩阵的首行系数从大到小排列(除了第一个系数外)，这与DCT8矩阵/DCT4矩阵的首行系数排序规律接近或相似。而DCT2’F矩阵的首行系数从小到大排列(除了最后一个系数外)，这与DST7矩阵/DST4矩阵的首行系数排序规律接近或相似。因此，在本申请实施例中，通过采用与现有方案中采用的变换矩阵近似的变换矩阵，能够在变换/逆变换过程中保证性能损失较小。
在本申请中，当目标变换矩阵对由DCT2’矩阵和DCT2’FS矩阵(或者DCT2’F矩阵或者DST4矩阵)组成时，对于任何变换尺寸，目标变换矩阵对中的变换矩阵均可以从DCT2矩阵推导得到。
下面变换尺寸为4×4为例对从8x8 DCT2矩阵中导出4x4 DCT2’矩阵和4x4 DCT2’FS矩阵的过程进行详细的说明。
如图7所示，从8x8 DCT2矩阵中抽取部分系数(按照4×4的大小抽取8x8 DCT2矩阵左半部分的奇数行的矩阵系数)，组成4x4矩阵(即DCT2 4x4变换矩阵)，然后进行转置，获得4x4 DCT2’矩阵。
如图7所示，从8x8 DCT2矩阵中抽取部分系数(按照4×4的大小抽取8x8 DCT2矩阵的偶数行的矩阵系数)，组成4x4矩阵，然后对该4x4矩阵进行转置和符号变换(对系 数按行或列取反)，即可获得4x4 DCT2’FS矩阵。
为了对本申请的效果进行分析，本申请对变换尺寸大于或者等于32时，目标变换矩阵对由DCT2’矩阵和DCT2’FS矩阵(或者DCT2’F矩阵)组成，变换尺寸小于32时，目标变换矩阵对由DCT2’矩阵和DST4矩阵组成时的性能进行测试，与现有方案中采用DCT8矩阵和DST7矩阵的方式相比，本申请的测试性能如表7和表8所示。
表7
测试视频序列 Y U V EncT DecT
序列A1 0.79％ 1.14％ 1.18％ 95％ 91％
序列A2 0.34％ 0.33％ 0.31％ 95％ 92％
序列B 0.19％ 0.29％ 0.30％ 95％ 93％
序列C -0.23％ -0.09％ 0.08％ 97％ 95％
序列E 0.16％ 0.25％ 0.17％ 96％ 96％
全部序列 0.22％ 0.35％ 0.38％ 96％ 93％
序列D -0.31％ -0.07％ -0.42％ 97％ 97％
表8
测试视频序列 Y U V EncT DecT
序列A1 0.43％ 0.69％ 0.70％ 99％ 98％
序列A2 0.20％ 0.23％ 0.12％ 99％ 99％
序列B 0.18％ 0.17％ 0.38％ 99％ 98％
序列C -0.06％ 0.05％ 0.07％ 99％ 98％
全部序列 0.17％ 0.25％ 0.31％ 99％ 98％
序列D -0.11％ -0.26％ 0.09％ 99％ 98％
其中，上述表7是在帧内预测模式条件下得到的测试结果，表8是在随机接入模式(预测时既可以采用帧内预测也可以采用帧间预测)条件下得到的测试结果。Y表示视频图像的亮度分量，U/V表示视频图像的色度分量，Y/U/V下面的数值表示在相同视频图像质量下编码比特增加的百分比，数值为负表示编码比特减少。EncT和DecT分别表示编码和解码时间。
由表7可知，本申请与现有方案相比编码比特增加0.22％(主要看亮度分量Y)，而编码时间减少了4％，解码时间减少了7％。由表8可知，本申请与现有方案相比编码比特增加0.17％(主要看亮度分量Y)，而编码时间减少了1％，解码时间减少了2％。
由表7和表8可知，与现有方案相比，本申请能够简化计算过程，减少编解码时间，提高编解码效率。
由上述表7和表8可知，对于序列A，编码比特增加的较多，因此，为了改善性能，还可以将DST7矩阵或者DST4矩阵设置为目标变换矩阵对中的变换矩阵。
可选地，作为一个实施例，目标变换矩阵对中的水平变换矩阵为DCT2’矩阵，在当前块的高大于或者等于N点时，目标变换矩阵对中的垂直变换矩阵为DST7矩阵；在当前块的高小于N点时，目标变换矩阵对中的垂直变换矩阵为DST4矩阵，其中，N为正整数。
可选地，作为一个实施例，目标变换矩阵对中的垂直变换矩阵为DCT2’矩阵，在当前 块的宽大于或者等于N点时，目标变换矩阵对中的水平变换矩阵为DST7矩阵；在当前块的宽小于N点时，目标变换矩阵对中的水平变换矩阵为DST4矩阵，其中，N为正整数。
可选地，N＝16。
应理解，当变换尺寸大于或者等于N点时可以认为是大尺寸变换场景，当变换尺寸小于M点时可以认为是小尺寸变换场景。
本申请中，在大尺寸变换场景下采用DCT2’矩阵和DST7矩阵(适用于大尺寸场景下的逆变换)作为目标变换矩阵对，在小尺寸场景下采用DCT2’矩阵和DST4矩阵(适用于小尺寸场景下的逆变换)作为目标变换矩阵对，能够在降低逆变换复杂度的同时，提高逆变换的性能。
由于DST7矩阵的首行系数的变化斜率要比DST4平缓，因而，将DST7应用到大尺寸变换场景下，而同时将DST4矩阵应用到下尺寸的场景下，能够获取较好的编解码性能。
在当前块的变换尺寸大于或者等于16点时，目标变换矩阵对可以由DCT2’矩阵和为DST7矩阵组成，此时，目标变换矩阵对索引值与候选变换矩阵对之间的对应关系可以如表9所示。
表9
Figure PCTCN2019119213-appb-000020
在当前块的变换尺寸小于16点时，目标变换矩阵对可以由DCT2’矩阵和为DST4矩阵组成，此时，目标变换矩阵对索引值与候选变换矩阵对之间的对应关系可以如表10所示。
表10
Figure PCTCN2019119213-appb-000021
其中，4×4的DST矩阵和4×4的DST7变换矩阵可以具体如下所示：
4×4的DST变换矩阵：
Figure PCTCN2019119213-appb-000022
4×4的DST7变换矩阵：
Figure PCTCN2019119213-appb-000023
为了对本申请的效果进行分析，本申请对变尺寸大于或者等于16时，目标变换矩阵对可以由DCT2’矩阵和为DST7矩阵组成，对变尺寸小于16时，目标变换矩阵对可以由DCT2’矩阵和为DST4矩阵组成时进行变换/逆变换时的性能进行了测试，与现有方案中采用DCT8矩阵和DST7矩阵相比，本申请方案的测试性能如表11和表12所示。
表11
测试视频序列 Y U V EncT DecT
序列A1 0.10％ 0.44％ -0.06％ 99％ 99％
序列A2 -0.15％ -0.56％ -0.15％ 98％ 99％
序列B -0.33％ 0.11％ -0.53％ 98％ 102％
序列C -0.36％ -0.13％ 0.08％ 101％ 102％
序列E -0.27％ -0.25％ -0.24％ 100％ 98％
全部序列 -0.22％ -0.06％ -0.20％ 99％ 100％
序列D -0.28％ -1.44％ 0.03％ 101％ 100％
表12
测试视频序列 Y U V EncT DecT
序列A1 0.00％ -0.18％ 0.33％ 100％ 101％
序列A2 -0.11％ -0.09％ -0.12％ 100％ 98％
序列B -0.21％ -0.30％ -0.26％ 99％ 99％
序列C -0.17％ 0.39％ 0.12％ 100％ 95％
全部序列 -0.13％ -0.05％ -0.01％ 100％ 98％
序列D -0.11％ -0.10％ 1.19％ 100％ 102％
其中，上述表11是在帧内预测模式测试条件下得到的测试结果，表12是随机接入模式测试条件(预测时既可以采用帧内预测也可以采用帧间预测)下得到的测试结果。Y表示视频图像的亮度分量，U/V表示视频图像的色度分量，Y/U/V下面的数值表示在相同视频图像质量下编码比特增加的百分比，数值为负表示编码比特减少。EncT和DecT分别表示编码和解码时间。
由表11可知，本申请与现有方案相比编码比特减少了0.22％(主要看亮度分量Y)，相当于性能提升了0.22％，编码时间减少了1％。由表12可知，本申请与现有方案相比编码比特减少了0.13％(主要看亮度分量Y)，相当于性能提升了0.13％，解码时间减少了2％。
由表11和表12可知，与现有方案相比，本申请能够在简化计算过程，减少编解码时间的同时提升编解码性能。
可选地，作为一个实施例，图6所示的方法还包括：解析码流，以获取多核变换标志位；所述根据所述目标变换矩阵对索引值以及所述目标变换矩阵对索引值与候选变换矩阵 对之间的对应关系，从所述候选变换矩阵对中确定目标变换矩阵对，包括：在所述多核变换标志位的取值为第一取值的情况下，根据所述目标变换矩阵对索引值以及所述目标变换矩阵对索引值与候选变换矩阵对之间的对应关系，从所述候选变换矩阵对中确定目标变换矩阵对；在所述多核变换标志位的取值为第一取值的情况下，将DCT2矩阵确定为目标变换矩阵对。
其中，将DCT2矩阵确定为目标变换矩阵对可以是指将DCT2矩阵作为目标变换矩阵对中的水平方向的变换矩阵与垂直方向的变换矩阵。
也就是说，在本申请中，可以在多核变换标志位的取值为第一取值的情况下才进行多核变换，而在多核变换标志位的取值为第二取值的情况下直接采用(DCT2，DCT2)作为目标变换矩阵对残差系数进行逆变换。
上述多核变换标志位具体可以是MTS_flag，当MTS_flag为第一取值时表示进行多核变换，当MTS_flag为第二取值时表示不进行多核变换。
上述第一取值和第二取值可以分别为1和0，或者，上述第二取值和第一取值也可以分别为0和1。
上文结合图6对本申请实施例的视频解码方法进行了详细的描述，下面结合图8对本申请实施例的视频编码方法进行描述，应理解，图8所示的视频编码方法与图6所示的视频编码方法是相对应的(图8所示的视频编码方法最终得到的码流可以采用图6所示的视频解码方法进行处理)，为了避免不必要的重复，下面在结合图8对本申请实施例的视频编码方法进行介绍时适当省略重复的描述。
图8是本申请实施例的视频编码方法的示意性流程图。图8是本申请实施例的视频编码方法的示意性流程图。图8所示的方法可以由编码端设备执行，图8所示的方法包括步骤2001至步骤2005，下面分别对步骤2001至步骤2005进行介绍。
2001、获取待处理图像块的残差块。
上述残差块可以通过待处理图像块与预测块做差得到(如图1所示待处理图像块与预测块做差可得到残差块)，在得到该待处理图像块的预测块的过程中可以采用帧间预测模式或者帧内预测模式。
2002、根据预设的映射关系信息获取残差块的候选变换矩阵对。
其中，候选变换矩阵对包括水平方向变换矩阵和垂直方向变换矩阵，所述水平方向变换矩阵和所述垂直方向变换矩阵均为预设的两个变换矩阵中的一个，所述预设的两个变换矩阵中的第一个变换矩阵为DCT2’矩阵，DCT2’矩阵为DCT2矩阵的转置矩阵。
上述映射关系信息可以包括目标变换矩阵对索引值以及目标索引值对应的变换矩阵对，上述映射关系信息可以预先存储在编码端和解码端。
上述目标变换矩阵对索引值与候选变换矩阵对之间的对应关系(也可以称为映射关系)可以如表13所示，其中，DCT2’是预设的两个变换矩阵中的第一个变换矩阵，变换矩阵A是预设的两个变换矩阵中的第二个变换矩阵。
表13
Figure PCTCN2019119213-appb-000024
Figure PCTCN2019119213-appb-000025
如表13所示，根据表13中所示的映射关系信息，可以得知候选变换矩阵对是由变换矩阵A与DCT2’组成。
2003、从候选变换矩阵对中选择出率失真最小的变换矩阵对作为目标变换矩阵对。
例如，编码端在变换过程中可以尝试表13中4种变换矩阵对，并计算出每种变换矩阵对对应的率失真代价，然后从中选择率失真代价最小的变换矩阵对作为目标变换矩阵对。
2004、根据目标变换矩阵对，对残差块进行变换，得到待处理图像块的变换系数。
具体地，假设目标变换矩阵对为(A，B)，残差块为R，那么，可以根据公式(2)进行变换(即矩阵相乘)，得到残差块变换系数F。其中，A为水平方向的变换矩阵矩阵，B为垂直方向的变换矩阵矩阵，
F＝B*R*A’      (2)
其中A’表示矩阵A的转置矩阵，由于A为正交矩阵，对A进行转置相当于求A的逆矩阵。
2005、将目标变换矩阵对对应的目标变换矩阵对索引值写入码流。
例如，通过计算表13所示的各种候选变换矩阵对对应的率失真代价，发现(DCT2’矩阵，变换矩阵A)对应的率失真代价最低，那么，可以将(DCT2’矩阵，变换矩阵A)作为目标变换矩阵对。接下来，就可以根据该变换矩阵对对残差块进行变换，并将(DCT2’矩阵，变换矩阵A)对应的目标变换矩阵对索引值(索引值具体为2)写入到码流中。这样当解码端解析到码流后，根据目标变换矩阵对索引值2和预先存储的目标变换矩阵对索引值与候选变换矩阵对之间的对应关系可以确定出目标变换矩阵对。
本申请中，由于候选变换矩阵对中包含DCT2’矩阵，而DCT2’矩阵在变换过程中存在快速算法，当采用DCT2’矩阵进行变换时能够采用快速算法，能够降低变换过程的计算复杂度。
可选地，作为一个实施例，DCT2’矩阵是根据DCT2矩阵推导得到的。
本申请中，由于DCT2’矩阵是DCT2矩阵的转置矩阵，因此，DCT2’矩阵的矩阵系数能够根据DCT2矩阵的矩阵系数推导出来，而不必额外存储DCT2’矩阵的矩阵系数，能够减少存储开销。
可选地，作为一个实施例，预设的两个变换矩阵中的第二个变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵。
其中，DCT2’FS矩阵和DCT2’F矩阵中的F表示镜像，DCT2’FS矩阵中的S表示符号变换。DCT2’F矩阵是对DCT2’矩阵进行镜像之后得到的矩阵，DCT2’FS矩阵是先对DCT2’矩阵进行镜像，然后再对镜像得到的矩阵进行符号变换得到的矩阵。
可选地，上述镜像是左右翻转镜像。
对一个矩阵左右翻转镜像可以是指将矩阵左侧的矩阵系数镜像到右侧，将矩阵右侧的矩阵系数镜像到左侧。
可选地，上述符号变换是指仅对矩阵的偶数行的矩阵系数进行符号取反，而矩阵的奇数行的矩阵系数保持不变。
可选地，上述符号变换是指仅对矩阵的奇数行的矩阵系数进行符号取反，而矩阵的偶数行的矩阵系数保持不变。
可选地，上述符号变换是对矩阵中所有的矩阵系数的符号取反。
可选地，预设的两个变换矩阵中的第一个矩阵为DCT2’矩阵，第二个矩阵为DCT2’FS矩阵或者DCT2’F矩阵适用于所有的变换尺寸。
具体地，预设的两个变换矩阵中的第一个矩阵为DCT2’矩阵，第二个矩阵为DCT2’FS矩阵或者DCT2’F矩阵适用于变换尺寸为4点、8点、16点和32点的情况。
本申请中，由于DCT2’FS和DCT2’F矩阵在变换过程中存在快速算法，能够简化变换时的计算复杂度。
具体地，当预设的两个变换矩阵中的第一个矩阵为DCT2’矩阵，第二个矩阵为DCT2’FS矩阵或者DCT2’F矩阵时，由于DCT2’矩阵、DCT2’FS矩阵和DCT2’F矩阵均存在快速算法，因此，当采用目标变换矩阵对(目标变换矩阵对由预设的两个变换矩阵组合而成)对对残差块进行变换处理时，能够降低逆变换过程中的计算复杂度。
可选地，作为一个实施例，所述目标变换矩阵对中的水平变换矩阵为DCT2’矩阵，当所述残差块的高大于或者等于M点时，所述目标变换矩阵对中的垂直变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵；当所述残差块的高小于M点时，所述目标变换矩阵对中的垂直变换矩阵为DST4矩阵，其中，M为正整数。
可选地，作为一个实施例，所述目标变换矩阵对中的垂直变换矩阵为DCT2’矩阵，当所述残差块的宽大于或者等于M点时，所述目标变换矩阵对中的水平变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵；当所述残差块的宽小于M点时，所述目标变换矩阵对中的水平变换矩阵为DST4矩阵，其中，M为正整数。
可选地，上述M＝32。
应理解，当变换尺寸大于或者等于M点时可以认为是大尺寸变换场景，当变换尺寸小于M点时可以认为是小尺寸变换场景。
本申请中，在大尺寸变换场景下采用具有快速算法的变换矩阵作为目标变换矩阵对中的水平变换矩阵或者垂直变换矩阵，而在小尺寸变换场景下采用适合小尺寸变换场景的变换矩阵作为目标变换矩阵对中的水平变换矩阵或者垂直变换矩阵，能够在大尺寸变换场景下，显著的降低变换的复杂度，同时还能在小尺寸场景下保证变换性能，能够在降低变换复杂度和保证变换性能之间取得平衡。
可选地，作为一个实施例，所述预设的两个变换矩阵中的第二个变换矩阵是根据DCT2矩阵推导得到的。
本申请中，由于预设的两个变换矩阵中的第二个变换矩阵可以根据DCT2矩阵推导得到，因此，而不必额外存储该第二个变换矩阵的矩阵系数，能够减少存储开销。
可选地，作为一个实施例，所述目标变换矩阵对中的水平变换矩阵为DCT2’矩阵，当所述残差块的高大于或者等于N点时，所述目标变换矩阵对中的垂直变换矩阵为DST7矩阵；当所述残差块的高小于N点时，所述目标变换矩阵对中的垂直变换矩阵为DST4矩阵，其中，N为正整数。
可选地，作为一个实施例，所述目标变换矩阵对中的垂直变换矩阵为DCT2’矩阵，当所述残差块的宽大于或者等于N点时，所述目标变换矩阵对中的水平变换矩阵为DST7矩阵；当所述残差块的宽小于N点时，所述目标变换矩阵对中的水平变换矩阵为DST4矩阵，其中，N为正整数。
可选地，N＝16。
应理解，当变换尺寸大于或者等于N点时可以认为是大尺寸变换场景，当变换尺寸小于M点时可以认为是小尺寸变换场景。
本申请中，在大尺寸变换场景下采用DCT2’矩阵和DST7矩阵(适用于大尺寸场景下的变换)作为目标变换矩阵对，在小尺寸场景下采用DCT2’矩阵和DST4矩阵(适用于小尺寸场景下的变换)作为目标变换矩阵对，能够在降低变换复杂度的同时，提高变换的性能。
为了更详细的了解本申请中的变换矩阵，下面对常用的变换矩阵对应的变换核(根据变换核可以推导出相应的变换矩阵)的基本构造进行介绍，常见的变换矩阵对应的变换核的基函数如表14所示。
表14
Figure PCTCN2019119213-appb-000026
为了明确本申请实施例中的变换矩阵的实现电路可以复用2Nx2N DCT2矩阵对应的变换/反变换实现电路，如下对电路复用进行具体的描述。
图9描述了HEVC中16×16 DCT2矩阵的蝶形快速算法电路实现，从图9可以看出，16×16 DCT2矩阵的蝶形快速算法电路中包括了4×4 DCT2矩阵，8×8 DCT2矩阵，4×4 DCT4矩阵以及8×8 DCT4矩阵的实现电路，也就是说，在实现4×4 DCT2矩阵，8×8 DCT2矩阵，4×4 DCT4矩阵以及8×8 DCT4矩阵的变换时可以直接复用16×16 DCT2矩阵的电路实现；但是只有4×4 DCT2矩阵和8×8 DCT2矩阵可以复用蝶形快速算法电路，而4×4 DCT4矩阵以及8×8  DCT4矩阵的实现虽然能够复用16×16 DCT2矩阵的实现电路，但是并没有使用蝶形快速算法。
另外，文献Core Transform Design in the High Efficiency Video Coding(HEVC)Standard(对应的中文翻译为高效视频编码(HEVC)标准中的核心变换设计)所揭示的反变换电路的partial butterfly(对应的中文翻译为部分蝶形)快速实现方法。DCT2矩阵反变换的实现，可以分解成EVEN、ODD和ADDSUB三个模块，其中EVEN表示利用由DCT2矩阵奇数行系数组成的矩阵进行列变换，ODD表示利用由DCT2矩阵偶数行系数组成的矩阵进行列变换，ADDSUB表示加减模块。
例如，图10描述了32×32的反变换实现电路，其中，EVEN4模块，ODD4模块以及ADDSUB4模块组成了4×4矩阵的反变换实现电路701；4×4矩阵的反变换实现电路701，ODD8模块以及ADDSUB8模块组成了8×8矩阵的反变换实现电路702；8×8矩阵的反变换实现电路702，ODD16模块以及ADDSUB16模块组成了16×16矩阵的反变换实现电路703；16×16矩阵的反变换电路实现703，ODD16模块以及ADDSUB16模块组成了32×32矩阵的反变换实现电路704。
上文结合图1至图10对本申请实施例的视频编码方法和视频编码方法进行了详细介绍，下面结合图11对本申请实施例的视频解码器进行介绍，图11所示的视频解码器能够执行本申请实施例的视频解码方法中的各个步骤，上文中对本申请实施例的视频解码器方法的相关限定同样也适用于图11所示的视频解码器，为了避免不必要的重复，下面对本申请实施例的视频解码器装置进行介绍时适当省略重复的描述。
图11是本申请实施例的视频解码器的示意性框图。图11所示的视频解码器300包括：
熵解码单元310，用于解析码流，以获取当前块进行逆变换处理的目标变换矩阵对索引值以及所述当前块的量化系数；
逆量化单元320，用于对所述当前块的量化系数进行逆量化处理，以获取所述当前块的反量化系数；
逆变换处理单元330，用于根据所述目标变换矩阵对索引值以及所述目标变换矩阵对索引值与候选变换矩阵对之间的对应关系，从所述候选变换矩阵对中确定目标变换矩阵对，其中，所述候选变换矩阵对包括水平方向变换矩阵和垂直方向变换矩阵，所述水平方向变换矩阵和所述垂直方向变换矩阵均为预设的两个变换矩阵中的一个，所述预设的两个变换矩阵中的第一个变换矩阵为DCT2’矩阵，其中，DCT2’矩阵为DCT2矩阵的转置矩阵；
所述逆变换处理单元330还用于根据所述目标变换矩阵对所述当前块的反量化系数进行逆变换处理，以得到所述当前块的重建残差块；
重构单元340，用于根据所述当前块的重建残差块获得所述当前块的重构块。
本申请中，由于候选变换矩阵对中包含DCT2’矩阵，而DCT2’矩阵逆变换过程中存在快速算法，因此，当采用DCT2’进行逆变换时能够采用快速算法，能够降低逆变过程的计算复杂度。
此外，由于DCT2’矩阵是DCT2矩阵的转置，因此，在逆变换的过程中，DCT2’能够复用DCT2的逆变换实现电路，能够降低硬件实现成本。
可选地，作为一个实施例，DCT2’矩阵是根据DCT2矩阵推导得到的。
可选地，作为一个实施例，所述预设的两个变换矩阵中的第二个变换矩阵为DCT2’FS 矩阵或者DCT2’F矩阵。
可选地，作为一个实施例，所述目标变换矩阵对中的水平变换矩阵为DCT2’矩阵，当所述当前块的高大于或者等于M点时，所述目标变换矩阵对中的垂直变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵；当所述当前块的高小于M点时，所述目标变换矩阵对中的垂直变换矩阵为DST4矩阵，其中，M为正整数。
可选地，作为一个实施例，所述目标变换矩阵对中的垂直变换矩阵为DCT2’矩阵，当所述当前块的宽大于或者等于M点时，所述目标变换矩阵对中的水平变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵；当所述当前块的高小于M点时，所述目标变换矩阵对中的水平变换矩阵为DST4矩阵，其中，M为正整数。
可选地，作为一个实施例，所述预设的两个变换矩阵中的第二个变换矩阵是根据DCT2矩阵推导得到的。
可选地，作为一个实施例，所述目标变换矩阵对中的水平变换矩阵为DCT2’矩阵，当所述当前块的高大于或者等于N点时，所述目标变换矩阵对中的垂直变换矩阵为DST7矩阵；当所述当前块的高小于N点时，所述目标变换矩阵对中的垂直变换矩阵为DST4矩阵，其中，N为正整数。
可选地，作为一个实施例，所述目标变换矩阵对中的垂直变换矩阵为DCT2’矩阵，当所述当前块的宽大于或者等于N点时，所述目标变换矩阵对中的水平变换矩阵为DST7矩阵；当所述当前块的宽小于N点时，所述目标变换矩阵对中的水平变换矩阵为DST4矩阵，其中，N为正整数。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现 有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种视频解码方法，其特征在于，包括：
    解析码流，以获取当前块进行逆变换处理的目标变换矩阵对索引值以及所述当前块的量化系数；
    对所述当前块的量化系数进行逆量化处理，以获取所述当前块的反量化系数；
    根据所述目标变换矩阵对索引值以及所述目标变换矩阵对索引值与候选变换矩阵对之间的对应关系，从所述候选变换矩阵对中确定目标变换矩阵对，其中，所述候选变换矩阵对包括水平方向变换矩阵和垂直方向变换矩阵，所述水平方向变换矩阵和所述垂直方向变换矩阵均为预设的两个变换矩阵中的一个，所述预设的两个变换矩阵中的第一个变换矩阵为DCT2’矩阵，其中，DCT2’矩阵为DCT2矩阵的转置矩阵；
    根据所述目标变换矩阵对对所述当前块的反量化系数进行逆变换处理，以得到所述当前块的重建残差块；
    根据所述当前块的重建残差块获得所述当前块的重构块。
  2. 如权利要求1所述的方法，其特征在于，所述预设的两个变换矩阵中的第二个变换矩阵是根据DCT2矩阵推导得到的。
  3. 如权利要求1或2所述的方法，其特征在于，所述预设的两个变换矩阵中的第二个变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵。
  4. 如权利要求1-3中任一项所述的方法，其特征在于，所述目标变换矩阵对中的水平变换矩阵为DCT2’矩阵，当所述当前块的高大于或者等于M点时，所述目标变换矩阵对中的垂直变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵；当所述当前块的高小于M点时，所述目标变换矩阵对中的垂直变换矩阵为DST4矩阵，其中，M为正整数。
  5. 如权利要求1-3中任一项所述的方法，其特征在于，所述目标变换矩阵对中的垂直变换矩阵为DCT2’矩阵，当所述当前块的宽大于或者等于M点时，所述目标变换矩阵对中的水平变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵；当所述当前块的高小于M点时，所述目标变换矩阵对中的水平变换矩阵为DST4矩阵，其中，M为正整数。
  6. 如权利要求1所述的方法，其特征在于，所述目标变换矩阵对中的水平变换矩阵为DCT2’矩阵，当所述当前块的高大于或者等于N点时，所述目标变换矩阵对中的垂直变换矩阵为DST7矩阵；当所述当前块的高小于N点时，所述目标变换矩阵对中的垂直变换矩阵为DST4矩阵，其中，N为正整数。
  7. 如权利要求1所述的方法，其特征在于，所述目标变换矩阵对中的垂直变换矩阵为DCT2’矩阵，当所述当前块的宽大于或者等于N点时，所述目标变换矩阵对中的水平变换矩阵为DST7矩阵；当所述当前块的宽小于N点时，所述目标变换矩阵对中的水平变换矩阵为DST4矩阵，其中，N为正整数。
  8. 一种视频解码器，其特征在于，包括：
    熵解码单元，用于解析码流，以获取当前块进行逆变换处理的目标变换矩阵对索引值以及所述当前块的量化系数；
    逆量化单元，用于对所述当前块的量化系数进行逆量化处理，以获取所述当前块的反 量化系数；
    逆变换处理单元，用于根据所述目标变换矩阵对索引值以及所述目标变换矩阵对索引值与候选变换矩阵对之间的对应关系，从所述候选变换矩阵对中确定目标变换矩阵对，其中，所述候选变换矩阵对包括水平方向变换矩阵和垂直方向变换矩阵，所述水平方向变换矩阵和所述垂直方向变换矩阵均为预设的两个变换矩阵中的一个，所述预设的两个变换矩阵中的第一个变换矩阵为DCT2’矩阵，其中，DCT2’矩阵为DCT2矩阵的转置矩阵；
    所述逆变换处理单元还用于根据所述目标变换矩阵对对所述当前块的反量化系数进行逆变换处理，以得到所述当前块的重建残差块；
    重构单元，用于根据所述当前块的重建残差块获得所述当前块的重构块。
  9. 如权利要求8所述的方法，其特征在于，所述预设的两个变换矩阵中的第二个变换矩阵是根据DCT2矩阵推导得到的。
  10. 如权利要求8或9所述的视频解码器，其特征在于，所述预设的两个变换矩阵中的第二个变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵。
  11. 如权利要求8-10中任一项所述的视频解码器，其特征在于，所述目标变换矩阵对中的水平变换矩阵为DCT2’矩阵，当所述当前块的高大于或者等于M点时，所述目标变换矩阵对中的垂直变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵；当所述当前块的高小于M点时，所述目标变换矩阵对中的垂直变换矩阵为DST4矩阵，其中，M为正整数。
  12. 如权利要求8-10中任一项所述的视频解码器，其特征在于，所述目标变换矩阵对中的垂直变换矩阵为DCT2’矩阵，当所述当前块的宽大于或者等于M点时，所述目标变换矩阵对中的水平变换矩阵为DCT2’FS矩阵或者DCT2’F矩阵；当所述当前块的高小于M点时，所述目标变换矩阵对中的水平变换矩阵为DST4矩阵，其中，M为正整数。
  13. 如权利要求8所述的视频解码器，其特征在于，所述目标变换矩阵对中的水平变换矩阵为DCT2’矩阵，当所述当前块的高大于或者等于N点时，所述目标变换矩阵对中的垂直变换矩阵为DST7矩阵；当所述当前块的高小于N点时，所述目标变换矩阵对中的垂直变换矩阵为DST4矩阵，其中，N为正整数。
  14. 如权利要求8所述的视频解码器，其特征在于，所述目标变换矩阵对中的垂直变换矩阵为DCT2’矩阵，当所述当前块的宽大于或者等于N点时，所述目标变换矩阵对中的水平变换矩阵为DST7矩阵；当所述当前块的宽小于N点时，所述目标变换矩阵对中的水平变换矩阵为DST4矩阵，其中，N为正整数。
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