WO2020057537A1 - 视频解码方法及视频解码器，视频编码方法及视频编码器 - Google Patents

视频解码方法及视频解码器，视频编码方法及视频编码器 Download PDF

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WO2020057537A1
WO2020057537A1 PCT/CN2019/106383 CN2019106383W WO2020057537A1 WO 2020057537 A1 WO2020057537 A1 WO 2020057537A1 CN 2019106383 W CN2019106383 W CN 2019106383W WO 2020057537 A1 WO2020057537 A1 WO 2020057537A1
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matrix
transformation
transformation matrix
dct2
pair
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PCT/CN2019/106383
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English (en)
French (fr)
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林永兵
郑建铧
朱策
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华为技术有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/119—Adaptive subdivision aspects, e.g. subdivision of a picture into rectangular or non-rectangular coding blocks

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  • the embodiments of the present application generally relate to the field of video encoding, and more specifically, to a video decoding method and a video decoder, a video encoding method, and a video encoder.
  • Video encoding (video encoding and decoding) is widely used in digital video applications, such as broadcast digital TV, video transmission on the Internet and mobile networks, real-time conversation applications such as video chat and video conferencing, DVD and Blu-ray discs, video content acquisition and editing systems And security applications for camcorders.
  • Video Coding AVC
  • ITU-T H.265 High Efficiency Video Coding
  • 3D three-dimensional
  • HEVC High Efficiency Video Coding
  • the embodiments of the present application provide a video decoding method and a video decoder, a video encoding method, and a video encoder, which can simplify the implementation of transform / inverse transform.
  • the present invention provides a video decoding method, including:
  • Parse the received code stream to obtain indication information of a transformation matrix pair that performs inverse transformation processing on the current block and a quantization coefficient of the current block, where the transformation matrix pair includes a horizontal transformation matrix and a vertical transformation matrix;
  • the horizontal transformation matrix and the vertical transformation matrix included in the candidate transformation matrix pair are both preset two One of the transformation matrices; one of the two transformation matrices is a deformation of the DST4 matrix or the DST4 matrix, and the other of the two transformation matrices is a deformation of the DCT2 'matrix or the DCT2' matrix, where the DCT2 'matrix is DCT2 matrix transpose matrix;
  • a reconstructed block of the current block is obtained according to a reconstructed residual block of the current block.
  • the horizontal transformation matrix and the vertical transformation matrix included in any one of the candidate transformation pairs are either the same or different.
  • the number of the candidate transformation matrix pairs may be two, three, or four.
  • the deformation of the DCT2 'matrix or the DCT2' matrix has a butterfly fast algorithm in the transformation / inverse transformation
  • the implementation of the transformation / inverse transformation can be simplified.
  • the deformation of the DCT2 'matrix or the DCT2' matrix and the deformation of the DST4 matrix or the DST4 matrix can be directly multiplexed with the transformation / inverse transformation implementation circuit corresponding to the DCT2 matrix, so the transformation / inverse transformation module can simplify the transformation when implemented by the circuit / Inverse conversion module to implement circuit design.
  • the deformation of the DST4 matrix is obtained by performing sign transformation on coefficients of at least a part of rows or at least a part of columns in the DST4 matrix;
  • the deformation of the DCT2 'matrix is obtained by performing a sign transformation on coefficients of at least a part of rows or at least a part of columns in the DCT2' matrix.
  • the number of candidate transformation matrix pairs is four; when one of the two transformation matrices is a DST4 matrix and the other is a DCT2 'matrix, the four candidates
  • the vertical transformation matrix included in the first transformation matrix pair in the transformation matrix pair is a DST4 matrix
  • the horizontal transformation matrix included in the first transformation matrix pair is a DST4 matrix
  • a vertical transformation matrix included in a second transformation matrix pair of the four candidate transformation matrix pairs is a DST4 matrix, and a horizontal transformation matrix included in the second transformation matrix pair is a DCT2 'matrix;
  • a vertical transformation matrix included in a third transformation matrix pair of the four candidate transformation matrix pairs is a DCT2 'matrix, and a horizontal transformation matrix included in the third transformation matrix pair is a DST4 matrix;
  • a vertical transformation matrix included in a fourth transformation matrix pair of the four candidate transformation matrix pairs is a DCT2 'matrix
  • a horizontal transformation matrix included in the fourth transformation matrix pair is a DCT2' matrix
  • the number of candidate transformation matrix pairs is four; when one of the two transformation matrices is a deformation of the DST4 matrix and the other is a deformation of the DCT2 ′ matrix, all The vertical transformation matrix included in the first transformation matrix pair of the four candidate transformation matrix pairs is a deformation of the DST4 matrix, and the horizontal transformation matrix included in the first transformation matrix pair is a deformation of the DST4 matrix;
  • the vertical transformation matrix included in the second transformation matrix pair of the four candidate transformation matrix pairs is a deformation of the DST4 matrix
  • the horizontal transformation matrix included in the second transformation matrix pair is a deformation of the DCT2 'matrix
  • a vertical transformation matrix included in the third transformation matrix pair of the four candidate transformation matrix pairs is a deformation of the DCT2 'matrix, and a horizontal transformation matrix included in the third transformation matrix pair is a deformation of the DST4 matrix;
  • a vertical transformation matrix included in the fourth transformation matrix pair of the four candidate transformation matrix pairs is a modification of the DCT2 'matrix
  • a horizontal transformation matrix included in the fourth transformation matrix pair is a transformation of the DCT2' matrix
  • the indication information includes an identifier of a vertical transformation matrix in a transformation matrix pair used to instruct the current block to perform inverse transformation processing, and used to instruct the current block to perform Identification of the horizontal transformation matrix in the transformation matrix pair of the inverse transformation process.
  • the method before performing the inverse transform processing on the inverse quantization coefficient of the current block by the transform matrix that performs inverse transform processing according to the current block, the method further includes: It is assumed that the algorithm derives the transformation matrix included in the transformation matrix pair in which the current block is subjected to inverse transformation processing from the DCT2 matrix.
  • the pair of transform matrices that perform inverse transform processing on the current block includes a DST4 matrix; the size of the DCT2 matrix is 64; and the derived from the DCT2 matrix according to a preset algorithm
  • the transformation matrix included in the transformation matrix for inverse transformation processing of the current block includes: deriving the DST4 matrix from the DCT2 matrix according to the following formula:
  • transMatrix represents the DCT2 matrix
  • nTbs represents the size of the DST4 matrix
  • the offset 64-nTbs indicates the column offset
  • (-1) j means perform sign conversion.
  • the pair of transform matrices for inverse transform processing of the current block includes a DCT2 ′ matrix; the size of the DCT2 matrix is 64; and the derived from the DCT2 matrix according to a preset algorithm
  • the transformation matrix included in the transformation matrix for inverse transformation processing of the current block includes: deriving the DCT2 ′ matrix from the DCT2 matrix according to the following formula:
  • transMatrix represents the DCT2 matrix
  • nTbs represents the size of the DCT2 '
  • 0 ⁇ i ⁇ nTbS-1 0 ⁇ j ⁇ nTbS-1.
  • the present invention provides an encoding method, including:
  • the transformation matrix pair used to transform the current residual block, the transformation matrix pair including a horizontal transformation matrix and a vertical transformation matrix; the transformation matrix pair is one of the candidate transformation matrix pairs, so The horizontal transformation matrix and vertical transformation matrix included in the candidate transformation matrix pair are each one of two preset transformation matrices; one of the two transformation matrices is a DST4 matrix or a modification of the DST4 matrix, and the two The other of the transformation matrices is a deformation of the DCT2 'matrix or the DCT2' matrix, wherein the DCT2 'matrix is a transposed matrix of the DCT2 matrix;
  • the quantized coefficient is subjected to entropy coding processing and written into a code stream.
  • the horizontal transformation matrix and the vertical transformation matrix included in any one of the candidate transformation pairs are either the same or different.
  • the number of the candidate transformation matrix pairs may be two, three, or four.
  • the deformation of the DCT2 'matrix or the DCT2' matrix has a butterfly fast algorithm in the transformation / inverse transformation
  • the implementation of the transformation / inverse transformation can be simplified.
  • the deformation of the DCT2 'matrix or the DCT2' matrix and the deformation of the DST4 matrix or the DST4 matrix can be directly multiplexed with the transformation / inverse transformation implementation circuit corresponding to the DCT2 matrix, so the transformation / inverse transformation module can simplify the transformation when implemented by the circuit / Inverse conversion module to implement circuit design.
  • the deformation of the DST4 matrix is obtained by performing sign transformation on coefficients of at least a part of rows or at least a part of columns in the DST4 matrix;
  • the deformation of the DCT2 'matrix is obtained by performing a sign transformation on coefficients of at least a part of rows or at least a part of columns in the DCT2' matrix.
  • the number of candidate transformation matrix pairs is four; when one of the two transformation matrices is a DST4 matrix and the other is a DCT2 'matrix, the four candidates
  • the vertical transformation matrix included in the first transformation matrix pair in the transformation matrix pair is a DST4 matrix
  • the horizontal transformation matrix included in the first transformation matrix pair is a DST4 matrix
  • a vertical transformation matrix included in a second transformation matrix pair of the four candidate transformation matrix pairs is a DST4 matrix, and a horizontal transformation matrix included in the second transformation matrix pair is a DCT2 'matrix;
  • a vertical transformation matrix included in a third transformation matrix pair of the four candidate transformation matrix pairs is a DCT2 'matrix, and a horizontal transformation matrix included in the third transformation matrix pair is a DST4 matrix;
  • a vertical transformation matrix included in a fourth transformation matrix pair of the four candidate transformation matrix pairs is a DCT2 'matrix
  • a horizontal transformation matrix included in the fourth transformation matrix pair is a DCT2' matrix
  • the number of candidate transformation matrix pairs is four; when one of the two transformation matrices is a deformation of the DST4 matrix and the other is a deformation of the DCT2 ′ matrix, all The vertical transformation matrix included in the first transformation matrix pair of the four candidate transformation matrix pairs is a deformation of the DST4 matrix, and the horizontal transformation matrix included in the first transformation matrix pair is a deformation of the DST4 matrix;
  • the vertical transformation matrix included in the second transformation matrix pair of the four candidate transformation matrix pairs is a deformation of the DST4 matrix
  • the horizontal transformation matrix included in the second transformation matrix pair is a deformation of the DCT2 'matrix
  • a vertical transformation matrix included in the third transformation matrix pair of the four candidate transformation matrix pairs is a deformation of the DCT2 'matrix, and a horizontal transformation matrix included in the third transformation matrix pair is a deformation of the DST4 matrix;
  • a vertical transformation matrix included in the fourth transformation matrix pair of the four candidate transformation matrix pairs is a modification of the DCT2 'matrix
  • a horizontal transformation matrix included in the fourth transformation matrix pair is a transformation of the DCT2' matrix
  • the method further includes: deriving a transformation matrix included in the transformation matrix pair from a DCT2 matrix according to a preset algorithm.
  • the transformation matrix included in the transformation matrix pair includes a DST4 matrix; the size of the DCT2 matrix is 64; and the transformation matrix is derived from the DCT2 matrix according to a preset algorithm
  • the included transformation matrix includes: deriving the DST4 matrix from the DCT2 matrix according to the following formula:
  • transMatrix represents the DCT2 matrix
  • nTbs represents the size of the DST4 matrix
  • the offset 64-nTbs indicates the column offset
  • (-1) j means perform sign conversion.
  • the transformation matrix included in the transformation matrix pair includes a DCT2 ′ matrix; the size of the DCT2 matrix is 64; and the transformation is derived from the DCT2 matrix according to a preset algorithm.
  • the transformation matrix included in the matrix pair includes: deriving the DCT2 ′ matrix from the DCT2 matrix according to the following formula:
  • transMatrix represents the DCT2 matrix
  • nTbs represents the size of the DCT2 '
  • 0 ⁇ i ⁇ nTbS-1 0 ⁇ j ⁇ nTbS-1.
  • the present invention provides a video decoder, including:
  • An entropy decoding unit configured to parse the received code stream to obtain indication information of a transformation matrix pair that performs inverse transformation processing on the current block and a quantization coefficient of the current block, where the transformation matrix pair includes a horizontal transformation matrix and a vertical transformation matrix;
  • An inverse quantization unit configured to perform inverse quantization processing on the quantization coefficients of the current block to obtain inverse quantization coefficients of the current block
  • An inverse transformation processing unit configured to determine, from the four candidate transformation matrix pairs, a transformation matrix pair that performs inverse transformation processing on the current block according to the instruction information; a horizontal transformation matrix and a vertical direction included in the candidate transformation matrix pair
  • the transformation matrices are one of two preset transformation matrices; one of the two transformation matrices is a DST4 matrix or a modification of the DST4 matrix, and the other of the two transformation matrices is a DCT2 'matrix or a DCT2' matrix.
  • a variant of the DCT2 ′ matrix is the transposed matrix of the DCT2 matrix; inverse transform processing is performed on the inverse quantization coefficients of the current block according to a transform matrix that performs inverse transform processing on the current block to obtain the current block's Reconstruction residual block;
  • a reconstruction unit configured to obtain a reconstruction block of the current block based on a reconstruction residual block of the current block.
  • the horizontal transformation matrix and the vertical transformation matrix included in any one of the candidate transformation pairs are either the same or different.
  • the number of the candidate transformation matrix pairs may be two, three, or four.
  • the deformation of the DST4 matrix is obtained by performing a sign transformation on coefficients of at least a part of rows or at least a part of columns in the DST4 matrix;
  • the deformation of the DCT2 'matrix is obtained by performing a sign transformation on coefficients of at least a part of rows or at least a part of columns in the DCT2' matrix.
  • the number of candidate transformation matrix pairs is four; when one of the two transformation matrices is a DST4 matrix and the other is a DCT2 'matrix, the four candidates
  • the vertical transformation matrix included in the first transformation matrix pair in the transformation matrix pair is a DST4 matrix
  • the horizontal transformation matrix included in the first transformation matrix pair is a DST4 matrix
  • a vertical transformation matrix included in a second transformation matrix pair of the four candidate transformation matrix pairs is a DST4 matrix, and a horizontal transformation matrix included in the second transformation matrix pair is a DCT2 'matrix;
  • a vertical transformation matrix included in a third transformation matrix pair of the four candidate transformation matrix pairs is a DCT2 'matrix, and a horizontal transformation matrix included in the third transformation matrix pair is a DST4 matrix;
  • a vertical transformation matrix included in a fourth transformation matrix pair of the four candidate transformation matrix pairs is a DCT2 'matrix
  • a horizontal transformation matrix included in the fourth transformation matrix pair is a DCT2' matrix
  • the number of candidate transformation matrix pairs is four; when one of the two transformation matrices is a deformation of the DST4 matrix and the other is a deformation of the DCT2 ′ matrix, all the The vertical transformation matrix included in the first transformation matrix pair of the four candidate transformation matrix pairs is a deformation of the DST4 matrix, and the horizontal transformation matrix included in the first transformation matrix pair is a deformation of the DST4 matrix;
  • the vertical transformation matrix included in the second transformation matrix pair of the four candidate transformation matrix pairs is a deformation of the DST4 matrix
  • the horizontal transformation matrix included in the second transformation matrix pair is a deformation of the DCT2 'matrix
  • a vertical transformation matrix included in the third transformation matrix pair of the four candidate transformation matrix pairs is a deformation of the DCT2 'matrix, and a horizontal transformation matrix included in the third transformation matrix pair is a deformation of the DST4 matrix;
  • a vertical transformation matrix included in the fourth transformation matrix pair of the four candidate transformation matrix pairs is a modification of the DCT2 'matrix
  • a horizontal transformation matrix included in the fourth transformation matrix pair is a transformation of the DCT2' matrix
  • the indication information includes an identifier of a vertical transformation matrix in a transformation matrix pair used to instruct the current block to perform inverse transformation processing, and used to instruct the current block to perform Identification of the horizontal transformation matrix in the transformation matrix pair of the inverse transformation process.
  • the inverse transformation processing unit is further configured to derive a transformation matrix included in a transformation matrix pair for performing inverse transformation processing on the current block from a DCT2 matrix according to a preset algorithm.
  • the pair of transformation matrices that perform inverse transformation processing on the current block includes a DST4 matrix; the size of the DCT2 matrix is 64; and the inverse transformation processing unit is specifically configured to: Derive the DST4 matrix from the DCT2 matrix:
  • transMatrix represents the DCT2 matrix
  • nTbs represents the size of the DST4 matrix
  • the offset 64-nTbs indicates the column offset
  • (-1) j means perform sign conversion.
  • the pair of transform matrices for inverse transform processing of the current block includes a DCT2 ′ matrix; the size of the DCT2 matrix is 64; and the inverse transform processing unit is specifically configured to:
  • the formula derives the DCT2 'matrix from the DCT2 matrix:
  • transMatrix represents the DCT2 matrix
  • nTbs represents the size of the DCT2 '
  • 0 ⁇ i ⁇ nTbS-1 0 ⁇ j ⁇ nTbS-1.
  • the present invention provides a video encoder, including:
  • a transformation processing unit configured to determine indication information of a transformation matrix pair used to transform the current residual block, the transformation matrix pair including a horizontal transformation matrix and a vertical transformation matrix; the transformation matrix pair is a candidate transformation matrix
  • One of the pairs, the horizontal transformation matrix and the vertical transformation matrix included in the candidate transformation matrix pair are both one of two preset transformation matrices; one of the two transformation matrices is a DST4 matrix or a DST4 matrix , The other of the two transformation matrices is a transformation of a DCT2 ′ matrix or a DCT2 ′ matrix, wherein the DCT2 ′ matrix is a transposed matrix of the DCT2 matrix;
  • a quantization unit which performs quantization processing on a transformation coefficient obtained by performing transformation processing on the current residual block through the transformation matrix to obtain a quantized coefficient of the current residual block;
  • An entropy coding unit configured to perform entropy coding processing on the quantization coefficient of the current residual block and the indication information
  • the output is used to write the indication information of the transform matrix pair after the entropy coding process and the quantization coefficient of the current residual block after the entropy coding process into a code stream.
  • the horizontal transformation matrix and the vertical transformation matrix included in any one of the candidate transformation pairs are either the same or different.
  • the number of the candidate transformation matrix pairs may be two, three, or four.
  • the deformation of the DST4 matrix is obtained by performing sign transformation on coefficients of at least a part of rows or at least a part of columns in the DST4 matrix;
  • the deformation of the DCT2 'matrix is obtained by performing a sign transformation on coefficients of at least a part of rows or at least a part of columns in the DCT2' matrix.
  • the number of candidate transformation matrix pairs is four; when one of the two transformation matrices is a DST4 matrix and the other is a DCT2 'matrix, the four candidates
  • the vertical transformation matrix included in the first transformation matrix pair in the transformation matrix pair is a DST4 matrix
  • the horizontal transformation matrix included in the first transformation matrix pair is a DST4 matrix
  • a vertical transformation matrix included in a second transformation matrix pair of the four candidate transformation matrix pairs is a DST4 matrix, and a horizontal transformation matrix included in the second transformation matrix pair is a DCT2 'matrix;
  • a vertical transformation matrix included in a third transformation matrix pair of the four candidate transformation matrix pairs is a DCT2 'matrix, and a horizontal transformation matrix included in the third transformation matrix pair is a DST4 matrix;
  • a vertical transformation matrix included in a fourth transformation matrix pair of the four candidate transformation matrix pairs is a DCT2 'matrix
  • a horizontal transformation matrix included in the fourth transformation matrix pair is a DCT2' matrix
  • the number of candidate transformation matrix pairs is four; when one of the two transformation matrices is a deformation of the DST4 matrix and the other is a deformation of the DCT2 ′ matrix, all The vertical transformation matrix included in the first transformation matrix pair of the four candidate transformation matrix pairs is a deformation of the DST4 matrix, and the horizontal transformation matrix included in the first transformation matrix pair is a deformation of the DST4 matrix;
  • the vertical transformation matrix included in the second transformation matrix pair of the four candidate transformation matrix pairs is a deformation of the DST4 matrix
  • the horizontal transformation matrix included in the second transformation matrix pair is a deformation of the DCT2 'matrix
  • a third transformation matrix pair among the four candidate transformation matrix pairs is a deformation of the DCT2 ′ matrix, and a horizontal transformation matrix included in the third transformation matrix pair is a deformation of the DST4 matrix;
  • a vertical transformation matrix included in the fourth transformation matrix pair of the four candidate transformation matrix pairs is a modification of the DCT2 'matrix
  • a horizontal transformation matrix included in the fourth transformation matrix pair is a transformation of the DCT2' matrix
  • the transformation processing unit is further configured to derive a transformation matrix included in the transformation matrix pair from a DCT2 matrix according to a preset algorithm.
  • the transformation matrix pair includes a DST4 matrix; the size of the DCT2 matrix is 64; and the transformation processing unit is specifically configured to: derive the derived from the DCT2 matrix according to the following formula
  • the DST4 matrix :
  • transMatrix represents the DCT2 matrix
  • nTbs represents the size of the DST4 matrix
  • the offset 64-nTbs indicates the column offset
  • (-1) j means perform sign conversion.
  • the transformation matrix pair includes a DCT2 ′ matrix; the size of the DCT2 matrix is 64; and the inverse transformation processing unit is specifically configured to derive from the DCT2 matrix according to the following formula Out the DCT2 'matrix:
  • transMatrix represents the DCT2 matrix
  • nTbs represents the size of the DCT2 '
  • 0 ⁇ i ⁇ nTbS-1 0 ⁇ j ⁇ nTbS-1.
  • the present invention relates to a device for decoding a video stream, including a processor and a memory.
  • the memory stores instructions that cause the processor to execute the method according to the first aspect or any possible embodiment of the first aspect.
  • the present invention relates to a video encoding device, including a processor and a memory.
  • the memory stores instructions that cause the processor to execute a method according to the second aspect or any possible embodiment of the second aspect.
  • a computer-readable storage medium which stores instructions thereon, which, when executed, cause one or more processors to decode video data.
  • the instructions cause the one or more processors to execute a method according to the first aspect or any possible embodiment of the first aspect.
  • a computer-readable storage medium on which instructions are stored, which, when executed, cause one or more processors to encode video data.
  • the instructions cause the one or more processors to perform a method according to the second aspect or any possible embodiment of the second aspect.
  • a video decoder which includes an execution circuit for performing the method as in the first aspect or any possible embodiment of the first aspect.
  • a video encoder which includes an execution circuit for performing the method as in the second aspect or any possible embodiment of the second aspect.
  • the invention relates to a computer program comprising a program code which, when run on a computer, performs a method according to the first aspect or any possible embodiment of the first aspect.
  • the invention relates to a computer program comprising a program code which, when run on a computer, performs a method according to the second aspect or any possible embodiment of the second aspect.
  • FIG. 1 is a block diagram of an example of a video encoding system for implementing an embodiment of the present invention
  • FIG. 2 is a block diagram showing an example structure of a video encoder for implementing an embodiment of the present invention
  • FIG. 3 is a block diagram showing an example structure of a video decoder for implementing an embodiment of the present invention
  • FIG. 4 is a diagram showing the encoder 20 of FIG. 2 and the decoder 30 of FIG. 3.
  • FIG. 5 is a block diagram illustrating another example of an encoding device or a decoding device
  • FIG. 6 is a schematic diagram of a butterfly fast algorithm circuit implementation of a 16 ⁇ 16 DCT2 matrix in HEVC
  • FIG. 7 is a schematic diagram showing a 32 ⁇ 32 inverse transform implementation circuit according to an embodiment
  • FIG. 8 is a schematic diagram illustrating an implementation circuit according to an embodiment
  • FIG. 9 is a schematic diagram illustrating an inverse transform architecture of an 8x8 DCT2 matrix according to an embodiment
  • FIG. 10 is a flowchart illustrating a video decoding method according to an embodiment
  • FIG. 11 is a flowchart illustrating a video encoding method according to an embodiment.
  • the disclosure in connection with the described method may be equally applicable to a corresponding device or system for performing the method, and vice versa.
  • the corresponding device may include one or more units such as functional units to perform the described one or more method steps (e.g., one unit performs one or more steps Or multiple units, each of which performs one or more of the multiple steps), even if such one or more units are not explicitly described or illustrated in the drawings.
  • the corresponding method may include a step to perform the functionality of one or more units (e.g., a step performs one or more units Functionality, or multiple steps, where each performs the functionality of one or more of the multiple units), even if such one or more steps are not explicitly described or illustrated in the drawings.
  • a step performs one or more units Functionality, or multiple steps, where each performs the functionality of one or more of the multiple units
  • the features of the various exemplary embodiments and / or aspects described herein may be combined with each other, unless explicitly stated otherwise.
  • Video coding generally refers to processing a sequence of pictures that form a video or a video sequence.
  • picture In the field of video coding, the terms “picture”, “frame” or “image” can be used as synonyms.
  • Video encoding used in this application means video encoding or video decoding.
  • Video encoding is performed on the source side and typically involves processing (e.g., by compressing) the original video picture to reduce the amount of data required to represent the video picture (thus storing and / or transmitting more efficiently).
  • Video decoding is performed on the destination side and usually involves inverse processing relative to the encoder to reconstruct the video picture.
  • the video pictures (or collectively referred to as pictures, which will be explained below) referred to in the embodiments should be understood as “encoding” or “decoding” related to a video sequence.
  • the combination of the encoding part and the decoding part is also called codec (encoding and decoding).
  • the original video picture can be reconstructed, that is, the reconstructed video picture has the same quality as the original video picture (assuming there is no transmission loss or other data loss during storage or transmission).
  • further compression is performed by, for example, quantization to reduce the amount of data required to represent the video picture, and the decoder side cannot completely reconstruct the video picture, that is, the quality of the reconstructed video picture is compared to the original video picture The quality is lower or worse.
  • Each picture of a video sequence is usually partitioned into a set of non-overlapping blocks, usually encoded at the block level.
  • the encoder side usually processes at the block (video block) level, that is, encodes the video.
  • the prediction block is generated by spatial (intra-picture) prediction and temporal (inter-picture) prediction.
  • Processed block subtract the prediction block to obtain the residual block, transform the residual block in the transform domain and quantize the residual block to reduce the amount of data to be transmitted (compressed), and the decoder side will perform inverse processing relative to the encoder Partially applied to an encoded or compressed block to reconstruct the current block for representation.
  • the encoder duplicates the decoder processing loop so that the encoder and decoder generate the same predictions (such as intra prediction and inter prediction) and / or reconstruction for processing, that is, encoding subsequent blocks.
  • the term "block” may be part of a picture or frame.
  • VVC Multi-purpose Video Coding
  • VCEG Video Coding Experts Group
  • MPEG ISO / IEC Motion Picture Experts Group
  • HEVC High-Efficiency Video Coding
  • JCT-VC Joint Collaboration, Video Coding
  • Each CU can be further split into one, two or four PUs according to the PU split type. The same prediction process is applied within a PU, and related information is transmitted to the decoder on the basis of the PU.
  • a CU may be partitioned into a transform unit (TU) according to other quad-tree structures similar to a coding tree for a CU.
  • TU transform unit
  • quad-tree and binary-tree (QTBT) split frames are used to split coded blocks.
  • the CU may be a square or rectangular shape.
  • a coding tree unit (CTU) is first divided by a quad tree structure.
  • the quad leaf nodes are further partitioned by a binary tree structure.
  • Binary leaf nodes are called coding units (CUs), and the segments are used for prediction and transformation processing without any other segmentation.
  • CUs coding units
  • the segments are used for prediction and transformation processing without any other segmentation.
  • CUs coding units
  • the segments are used for prediction and transformation processing without any other segmentation.
  • the CU, PU, and TU have the same block size in the QTBT coded block structure.
  • Embodiments of the encoder 20, the decoder 30, and the encoding and decoding systems 10, 40 are described below based on FIGS. 1 to 4 (before the embodiments of the present invention are described in more detail based on FIG. 10).
  • FIG. 1 is a conceptual or schematic block diagram illustrating an exemplary encoding system 10.
  • a video encoding system 10 that can use the technology of the present application (the present disclosure).
  • the encoder 20 (e.g., video encoder 20) and decoder 30 (e.g., video decoder 30) of the video encoding system 10 represent methods that can be used to perform methods for video encoding or video decoding according to various examples described in this application. Equipment examples of technology.
  • the encoding system 10 includes a source device 12 for providing the encoded data 13, such as the encoded picture 13, to a destination device 14 that decodes the encoded data 13, for example.
  • the source device 12 includes an encoder 20, and in addition, optionally, may include a picture source 16, such as a pre-processing unit 18 of a picture pre-processing unit 18, and a communication interface or communication unit 22.
  • a picture source 16 such as a pre-processing unit 18 of a picture pre-processing unit 18, and a communication interface or communication unit 22.
  • the picture source 16 may include or may be any kind of picture capture device for, for example, capturing real-world pictures, and / or any kind of pictures or comments (for screen content encoding, some text on the screen is also considered to be a picture to be encoded Or a part of an image) generating device, for example, a computer graphics processor for generating computer animated pictures, or for obtaining and / or providing real world pictures, computer animated pictures (for example, screen content, virtual reality (VR) ) Pictures) of any type of device, and / or any combination thereof (eg, augmented reality (AR) pictures).
  • a computer graphics processor for generating computer animated pictures, or for obtaining and / or providing real world pictures, computer animated pictures (for example, screen content, virtual reality (VR) ) Pictures) of any type of device, and / or any combination thereof (eg, augmented reality (AR) pictures).
  • AR augmented reality
  • a (digital) picture is or can be regarded as a two-dimensional array or matrix of sampling points with luminance values.
  • the sampling points in the array may also be called pixels (short for picture element) or pixels.
  • the number of sampling points of the array or picture in the horizontal and vertical directions (or axes) defines the size and / or resolution of the picture.
  • three color components are usually used, that is, a picture can be represented as or contain three sampling arrays.
  • pictures include corresponding red, green, and blue sampling arrays.
  • each pixel is usually represented in a luma / chroma format or color space, for example, YCbCr, including the luma component indicated by Y (sometimes also indicated by L) and the two chroma indicated by Cb and Cr Weight.
  • Luma (abbreviated as luma) component Y represents luminance or gray level intensity (for example, both are the same in a grayscale picture), while two chroma (abbreviated as chroma) components Cb and Cr represent chroma or color information components .
  • a picture in the YCbCr format includes a luminance sampling array of luminance sampling values (Y), and two chrominance sampling arrays of chrominance values (Cb and Cr).
  • Y luminance sampling values
  • Cb and Cr chrominance sampling arrays of chrominance values
  • Pictures in RGB format can be converted or converted to YCbCr format, and vice versa. This process is also called color conversion or conversion. If the picture is black and white, the picture can include only an array of luminance samples.
  • the picture source 16 may be, for example, a camera for capturing pictures, such as a memory of a picture memory, including or storing a previously captured or generated picture, and / or any category (internal) of obtaining or receiving a picture Or external) interface.
  • the camera may be, for example, an integrated camera that is local or integrated in the source device, and the memory may be local or, for example, an integrated memory that is integrated in the source device.
  • the interface may be, for example, an external interface for receiving pictures from an external video source.
  • the external video source is, for example, an external picture capture device, such as a camera, an external memory, or an external picture generation device.
  • the external picture generation device is, for example, an external computer graphics processor, a computer.
  • the interface may be any type of interface according to any proprietary or standardized interface protocol, such as a wired or wireless interface, an optical interface.
  • the interface for acquiring the picture data 17 may be the same interface as the communication interface 22 or a part of the communication interface 22.
  • a picture or picture data 17 (e.g., video data 16) may also be referred to as an original picture or original picture data 17.
  • the pre-processing unit 18 is configured to receive (original) picture data 17 and perform pre-processing on the picture data 17 to obtain a pre-processed picture 19 or pre-processed picture data 19.
  • the pre-processing performed by the pre-processing unit 18 may include trimming, color format conversion (for example, conversion from RGB to YCbCr), color correction, or denoising. It is understood that the pre-processing unit 18 may be an optional component.
  • An encoder 20 (eg, video encoder 20) is used to receive the pre-processed picture data 19 and provide the encoded picture data 21 (details will be further described below, for example, based on FIG. 2 or FIG. 4).
  • the communication interface 22 of the source device 12 can be used to receive the encoded picture data 21 and transmit it to other devices, such as the destination device 14 or any other device, for storage or direct reconstruction, or for correspondingly storing the
  • the encoded data 13 and / or the encoded picture data 21 are processed before transmitting the encoded data 13 to other devices, such as the destination device 14 or any other device for decoding or storage.
  • the destination device 14 includes a decoder 30 (for example, a video decoder 30), and in addition, optionally, it may include a communication interface or communication unit 28, a post-processing unit 32, and a display device 34.
  • a decoder 30 for example, a video decoder 30
  • the communication interface 28 of the destination device 14 is used, for example, to receive the encoded picture data 21 or the encoded data 13 directly from the source device 12 or any other source.
  • Any other source is, for example, a storage device, and the storage device is, for example, encoded picture data storage. device.
  • the communication interface 22 and the communication interface 28 can be used for direct communication through a direct communication link between the source device 12 and the destination device 14 or transmission or reception of encoded picture data 21 or encoded data 13 through any type of network
  • the link is, for example, a direct wired or wireless connection, and any type of network is, for example, a wired or wireless network or any combination thereof, or any type of private and public network, or any combination thereof.
  • the communication interface 22 may be used, for example, to encapsulate the encoded picture data 21 into a suitable format, such as a packet, for transmission over a communication link or communication network.
  • the communication interface 28 forming a corresponding portion of the communication interface 22 may be used, for example, to decapsulate the encoded data 13 to obtain the encoded picture data 21.
  • Both the communication interface 22 and the communication interface 28 may be configured as unidirectional communication interfaces, as indicated by the arrows for the encoded picture data 13 from the source device 12 to the destination device 14 in FIG. 1, or configured as bidirectional communication interfaces, and It can be used, for example, to send and receive messages to establish a connection, acknowledge, and exchange any other information related to a communication link and / or data transmission such as encoded picture data transmission.
  • the decoder 30 is configured to receive the encoded picture data 21 and provide the decoded picture data 31 or the decoded picture 31 (details will be further described below, for example, based on FIG. 3 or FIG. 5).
  • the post-processor 32 of the destination device 14 is used to post-process decoded picture data 31 (also referred to as reconstructed picture data), for example, decoded picture 131 to obtain post-processed picture data 33, for example, post-processed Picture 33.
  • the post-processing performed by the post-processing unit 32 may include, for example, color format conversion (e.g., conversion from YCbCr to RGB), color correction, retouching, or resampling, or any other processing, such as preparing the decoded picture data 31 to
  • the display device 34 displays it.
  • the display device 34 of the destination device 14 is used to receive post-processed picture data 33 to display pictures to, for example, a user or a viewer.
  • the display device 34 may be or may include any kind of display for presenting a reconstructed picture, such as an integrated or external display or monitor.
  • the display may include a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a plasma display, a projector, a micro LED display, a liquid crystal on silicon (LCoS), Digital light processor (DLP) or any other display of any kind.
  • FIG. 1 illustrates the source device 12 and the destination device 14 as separate devices
  • the device embodiment may also include the source device 12 and the destination device 14 or both, ie, the source device 12 or corresponding And the functionality of the destination device 14 or equivalent.
  • the same hardware and / or software, or separate hardware and / or software, or any combination thereof may be used to implement the source device 12 or corresponding functionality and the destination device 14 or corresponding functionality .
  • Both the encoder 20 e.g., video encoder 20
  • decoder 30 e.g., video decoder 30
  • DSP digital signal processors
  • ASIC application-specific integrated circuit
  • FPGA field-programmable gate array
  • the device may store the software's instructions in a suitable non-transitory computer-readable storage medium, and may use one or more processors to execute the instructions in hardware to perform the techniques of the present disclosure.
  • processors any one of the foregoing (including hardware, software, a combination of hardware and software, etc.) can be considered as one or more processors.
  • Each of the video encoder 20 and the video decoder 30 may be included in one or more encoders or decoders, and any of the encoders or decoders may be integrated as a combined encoder / decoder in a corresponding device (Codec).
  • the source device 12 may be referred to as a video encoding device or a video encoding device.
  • the destination device 14 may be referred to as a video decoding device or a video decoding device.
  • the source device 12 and the destination device 14 may be examples of a video encoding device or a video encoding apparatus.
  • Source device 12 and destination device 14 may include any of a variety of devices, including any type of handheld or stationary device, such as a notebook or laptop computer, mobile phone, smartphone, tablet or tablet computer, video camera, desktop Computer, set-top box, TV, display device, digital media player, video game console, video streaming device (such as content service server or content distribution server), broadcast receiver device, broadcast transmitter device, etc., and may not be used Or use any kind of operating system.
  • a notebook or laptop computer mobile phone, smartphone, tablet or tablet computer, video camera, desktop Computer, set-top box, TV, display device, digital media player, video game console, video streaming device (such as content service server or content distribution server), broadcast receiver device, broadcast transmitter device, etc., and may not be used Or use any kind of operating system.
  • source device 12 and destination device 14 may be equipped for wireless communication. Therefore, the source device 12 and the destination device 14 may be wireless communication devices.
  • the video encoding system 10 shown in FIG. 1 is merely an example, and the techniques of the present application may be applicable to a video encoding setting (eg, video encoding or video decoding) that does not necessarily include any data communication between encoding and decoding devices. .
  • data may be retrieved from local storage, streamed over a network, and the like.
  • the video encoding device may encode the data and store the data to a memory, and / or the video decoding device may retrieve the data from the memory and decode the data.
  • encoding and decoding are performed by devices that do not communicate with each other but only encode data to and / or retrieve data from memory and decode data.
  • video decoder 30 may be used to perform the reverse process.
  • video decoder 30 may be used to receive and parse such syntax elements, and decode related video data accordingly.
  • video encoder 20 may entropy encode one or more syntax elements that define ... into an encoded video bitstream.
  • video decoder 30 may parse such syntax elements and decode related video data accordingly.
  • FIG. 2 shows a schematic / conceptual block diagram of an example of a video encoder 20 for implementing the technology of the present (disclosed) application.
  • the video encoder 20 includes a residual calculation unit 204, a transformation processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transformation processing unit 212, a reconstruction unit 214, a buffer 216, and a loop filter.
  • the prediction processing unit 260 may include an inter prediction unit 244, an intra prediction unit 254, and a mode selection unit 262.
  • the inter prediction unit 244 may include a motion estimation unit and a motion compensation unit (not shown).
  • the video encoder 20 shown in FIG. 2 may also be referred to as a hybrid video encoder or a video encoder according to a hybrid video codec.
  • the residual calculation unit 204, the transformation processing unit 206, the quantization unit 208, the prediction processing unit 260, and the entropy encoding unit 270 form the forward signal path of the encoder 20, while the inverse quantization unit 210, the inverse transformation processing unit 212,
  • the constructing unit 214, the buffer 216, the loop filter 220, the decoded picture buffer (DPB) 230, and the prediction processing unit 260 form a backward signal path of the encoder, wherein the backward signal path of the encoder corresponds to To the decoder's signal path (see decoder 30 in Figure 3).
  • the encoder 20 receives a picture 201 or a block 203 of the picture 201 through, for example, an input 202, for example, a picture in a picture sequence forming a video or a video sequence.
  • Picture block 203 can also be called the current picture block or the picture block to be encoded
  • picture 201 can be called the current picture or the picture to be encoded (especially when the current picture is distinguished from other pictures in video encoding, other pictures, such as the same video sequence (Ie previously encoded and / or decoded pictures in the video sequence of the current picture).
  • An embodiment of the encoder 20 may include a segmentation unit (not shown in FIG. 2) for segmenting the picture 201 into multiple blocks, such as the block 203, and generally into multiple non-overlapping blocks.
  • the segmentation unit can be used to use the same block size and corresponding raster to define the block size for all pictures in the video sequence, or to change the block size between pictures or subsets or groups of pictures, and split each picture into Corresponding block.
  • the prediction processing unit 260 of the video encoder 20 may be used to perform any combination of the aforementioned segmentation techniques.
  • block 203 is also or can be regarded as a two-dimensional array or matrix of sampling points with brightness values (sampling values), although its size is smaller than picture 201.
  • the block 203 may include, for example, one sampling array (e.g., a luminance array in the case of a black and white picture 201) or three sampling arrays (e.g., one luminance array and two chroma arrays in the case of a color picture) or a basis An array of any other number and / or category of color formats applied.
  • the number of sampling points in the horizontal and vertical directions (or axes) of the block 203 defines the size of the block 203.
  • the encoder 20 shown in FIG. 2 is used to encode a picture 201 block by block, for example, performing encoding and prediction on each block 203.
  • the residual calculation unit 204 is configured to calculate the residual block 205 based on the picture block 203 and the prediction block 265 (the other details of the prediction block 265 are provided below). Sample values of block 265 to obtain residual block 205 in the sample domain.
  • the transform processing unit 206 is configured to apply a transform such as discrete cosine transform (DCT) or discrete sine transform (DST) on the sample values of the residual block 205 to obtain transform coefficients 207 in the transform domain.
  • a transform such as discrete cosine transform (DCT) or discrete sine transform (DST)
  • DCT discrete cosine transform
  • DST discrete sine transform
  • the transform coefficient 207 may also be referred to as a transform residual coefficient, and represents a residual block 205 in a transform domain.
  • the transform processing unit 206 may be used to apply an integer approximation of DCT / DST, such as the transform specified for HEVC / H.265. Compared to an orthogonal DCT transform, this integer approximation is usually scaled by a factor. To maintain the norm of the residual blocks processed by the forward and inverse transforms, an additional scaling factor is applied as part of the transform process.
  • the scaling factor is usually selected based on certain constraints, for example, the scaling factor is a power of two used for shift operations, the bit depth of the transform coefficients, the trade-off between accuracy, and implementation cost.
  • a specific scaling factor is specified on the decoder 30 side by, for example, the inverse transform processing unit 212 (and on the encoder 20 side by, for example, the inverse transform processing unit 212 as the corresponding inverse transform), and accordingly, the The 20 side specifies a corresponding scaling factor for the positive transformation through the transformation processing unit 206.
  • the quantization unit 208 is used to quantize the transform coefficient 207, for example, by applying scalar quantization or vector quantization to obtain a quantized transform coefficient 209.
  • the quantized transform coefficient 209 may also be referred to as a quantized residual coefficient 209.
  • the quantization process can reduce the bit depth associated with some or all of the transform coefficients 207. For example, n-bit transform coefficients may be rounded down to m-bit transform coefficients during quantization, where n is greater than m.
  • the degree of quantization can be modified by adjusting the quantization parameter (QP). For scalar quantization, for example, different scales can be applied to achieve finer or coarser quantization.
  • a smaller quantization step size corresponds to a finer quantization, while a larger quantization step size corresponds to a coarser quantization.
  • An appropriate quantization step size can be indicated by a quantization parameter (QP).
  • the quantization parameter may be an index of a predefined set of suitable quantization steps.
  • smaller quantization parameters may correspond to fine quantization (smaller quantization step size)
  • larger quantization parameters may correspond to coarse quantization (larger quantization step size)
  • Quantization may include division by a quantization step size and corresponding quantization or inverse quantization performed, for example, by inverse quantization 210, or may include multiplication by a quantization step size.
  • Embodiments according to some standards such as HEVC may use quantization parameters to determine the quantization step size.
  • the quantization step size can be calculated using a fixed-point approximation using an equation containing division based on the quantization parameter. Additional scaling factors may be introduced for quantization and inverse quantization to restore the norm of the residual block that may be modified due to the scale used in the fixed-point approximation of the equation for the quantization step size and quantization parameter.
  • inverse transform and inverse quantization scales can be combined.
  • a custom quantization table can be used and signaled from the encoder to the decoder in, for example, a bitstream. Quantization is a lossy operation, where the larger the quantization step, the greater the loss.
  • the inverse quantization unit 210 is configured to apply the inverse quantization of the quantization unit 208 on the quantized coefficients to obtain the inverse quantized coefficients 211. For example, based on or using the same quantization step as the quantization unit 208, the quantization scheme applied by the quantization unit 208 is applied. Inverse quantization scheme.
  • the dequantized coefficient 211 may also be referred to as a dequantized residual coefficient 211, which corresponds to the transform coefficient 207, although the loss due to quantization is usually different from the transform coefficient.
  • the inverse transform processing unit 212 is used to apply an inverse transform of the transform applied by the transform processing unit 206, for example, an inverse discrete cosine transform (DCT) or an inverse discrete sine transform (DST), in the sample domain.
  • DCT inverse discrete cosine transform
  • DST inverse discrete sine transform
  • the inverse transform block 213 may also be referred to as an inverse transform inverse quantized block 213 or an inverse transform residual block 213.
  • the reconstruction unit 214 (for example, the summer 214) is used to add the inverse transform block 213 (that is, the reconstructed residual block 213) to the prediction block 265 to obtain the reconstructed block 215 in the sample domain.
  • the sample values of the reconstructed residual block 213 are added to the sample values of the prediction block 265.
  • a buffer unit 216 (or simply "buffer" 216), such as a line buffer 216, is used to buffer or store the reconstructed block 215 and corresponding sample values, for example, for intra prediction.
  • the encoder may be used to use any unfiltered reconstructed block and / or corresponding sample values stored in the buffer unit 216 for any category of estimation and / or prediction, such as intra-frame prediction.
  • an embodiment of the encoder 20 may be configured such that the buffer unit 216 is used not only for storing the reconstructed block 215 for intra prediction 254, but also for the loop filter unit 220 (not shown in FIG. 2). Out), and / or, for example, to make the buffer unit 216 and the decoded picture buffer unit 230 form a buffer.
  • Other embodiments may be used to use the filtered block 221 and / or blocks or samples from the decoded picture buffer 230 (neither shown in FIG. 2) as the input or basis for the intra prediction 254.
  • the loop filter unit 220 (or simply "loop filter” 220) is configured to filter the reconstructed block 215 to obtain a filtered block 221, so as to smoothly perform pixel conversion or improve video quality.
  • the loop filter unit 220 is intended to represent one or more loop filters, such as a deblocking filter, a sample-adaptive offset (SAO) filter, or other filters, such as a bilateral filter, Adaptive loop filters (adaptive loop filters, ALF), or sharpening or smoothing filters, or cooperative filters.
  • the loop filter unit 220 is shown as an in-loop filter in FIG. 2, in other configurations, the loop filter unit 220 may be implemented as a post-loop filter.
  • the filtered block 221 may also be referred to as a filtered reconstructed block 221.
  • the decoded picture buffer 230 may store the reconstructed encoded block after the loop filter unit 220 performs a filtering operation on the reconstructed encoded block.
  • An embodiment of the encoder 20 may be used to output loop filter parameters (e.g., sample adaptive offset information), for example, directly output or by the entropy coding unit 270 or any other
  • the entropy coding unit outputs after entropy coding, for example, so that the decoder 30 can receive and apply the same loop filter parameters for decoding.
  • the decoded picture buffer (DPB) 230 may be a reference picture memory that stores reference picture data for the video encoder 20 to encode video data.
  • DPB 230 can be formed by any of a variety of memory devices, such as dynamic random access (DRAM) (including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), and resistive RAM (resistive RAM, RRAM)) or other types of memory devices.
  • DRAM dynamic random access
  • SDRAM synchronous DRAM
  • MRAM magnetoresistive RAM
  • RRAM resistive RAM
  • the DPB 230 and the buffer 216 may be provided by the same memory device or separate memory devices.
  • a decoded picture buffer (DPB) 230 is used to store the filtered block 221.
  • the decoded picture buffer 230 may be further used to store other previous filtered blocks of the same current picture or different pictures such as previously reconstructed pictures, such as the previously reconstructed and filtered block 221, and may provide a complete previous Reconstruction is the decoded picture (and corresponding reference blocks and samples) and / or part of the reconstructed current picture (and corresponding reference blocks and samples), for example for inter prediction.
  • a decoded picture buffer (DPB) 230 is used to store the reconstructed block 215.
  • Prediction processing unit 260 also referred to as block prediction processing unit 260, is used to receive or obtain block 203 (current block 203 of current picture 201) and reconstructed picture data, such as a reference to the same (current) picture from buffer 216 Samples and / or reference picture data 231 from one or more previously decoded pictures from the decoded picture buffer 230, and used to process such data for prediction, i.e., may be provided as inter-predicted blocks 245 or intra- Prediction block 265 of prediction block 255.
  • the mode selection unit 262 may be used to select a prediction mode (such as an intra or inter prediction mode) and / or a corresponding prediction block 245 or 255 used as the prediction block 265 to calculate the residual block 205 and reconstruct the reconstructed block 215.
  • a prediction mode such as an intra or inter prediction mode
  • a corresponding prediction block 245 or 255 used as the prediction block 265 to calculate the residual block 205 and reconstruct the reconstructed block 215.
  • An embodiment of the mode selection unit 262 may be used to select a prediction mode (e.g., selected from those prediction modes supported by the prediction processing unit 260) that provides the best match or minimum residual (minimum residual means Better compression in transmission or storage), or provide minimal signaling overhead (minimum signaling overhead means better compression in transmission or storage), or consider or balance both.
  • the mode selection unit 262 may be used to determine a prediction mode based on rate distortion optimization (RDO), that is, to select a prediction mode that provides the minimum code rate distortion optimization, or to select a prediction mode whose related code rate distortion meets at least the prediction mode selection criteria. .
  • RDO rate distortion optimization
  • the encoder 20 is used to determine or select the best or optimal prediction mode from a set of (predetermined) prediction modes.
  • the prediction mode set may include, for example, an intra prediction mode and / or an inter prediction mode.
  • the set of intra prediction modes may include 35 different intra prediction modes, for example, non-directional modes such as DC (or average) mode and planar mode, or directional modes as defined in H.265, or may include 67 Different intra prediction modes, such as non-directional modes such as DC (or mean) mode and planar mode, or directional modes as defined in the developing H.266.
  • the set of (possible) inter-prediction modes depends on the available reference pictures (i.e., at least part of the decoded pictures previously stored in DBP 230) and other inter-prediction parameters, such as whether to use the entire reference picture or only the reference A part of the picture, such as a search window area surrounding the area of the current block, searches for the best matching reference block, and / or depends on, for example, whether pixel interpolation such as half-pixel and / or quarter-pixel interpolation is applied.
  • a skip mode and / or a direct mode can also be applied.
  • the prediction processing unit 260 may be further configured to divide the block 203 into smaller block partitions or sub-blocks, for example, using a quad-tree (QT) partition, a binary-tree (BT) partition, or a triple fork by iteration. Tree-triple-ternary-tree (TT) segmentation, or any combination thereof, and for performing predictions, for example, for each of block partitions or sub-blocks, where mode selection includes the tree structure and selection of the partitioned block 203 A prediction mode applied to each of a block partition or a sub-block.
  • QT quad-tree
  • BT binary-tree
  • TT Tree-triple-ternary-tree
  • the inter prediction unit 244 may include a motion estimation (ME) unit (not shown in FIG. 2) and a motion compensation (MC) unit (not shown in FIG. 2).
  • the motion estimation unit is configured to receive or obtain picture block 203 (current picture block 203 of current picture 201) and decoded picture 231, or at least one or more previously reconstructed blocks, for example, one or more other / different previous
  • the reconstructed block of picture 231 is decoded for motion estimation.
  • the video sequence may include the current picture and the previously decoded picture 31, or in other words, the current picture and the previously decoded picture 31 may be part of the picture sequence forming the video sequence or form the picture sequence.
  • the encoder 20 may be used to select a reference block from multiple reference blocks of the same or different pictures in multiple other pictures, and provide a reference picture (or reference picture index) to a motion estimation unit (not shown in FIG. 2). ) And / or provide an offset (spatial offset) between the position (X, Y coordinates) of the reference block and the position of the current block as an inter prediction parameter.
  • This offset is also called a motion vector (MV).
  • the motion compensation unit is used for obtaining, for example, receiving inter prediction parameters, and performing inter prediction based on or using the inter prediction parameters to obtain the inter prediction block 245.
  • Motion compensation performed by a motion compensation unit may include taking out or generating a prediction block based on a motion / block vector determined through motion estimation (possibly performing interpolation on sub-pixel accuracy). Interpolation filtering can generate additional pixel samples from known pixel samples, potentially increasing the number of candidate prediction blocks that can be used to encode picture blocks.
  • the motion compensation unit 246 may locate the prediction block pointed to by the motion vector in a reference picture list.
  • Motion compensation unit 246 may also generate syntax elements associated with blocks and video slices for use by video decoder 30 when decoding picture blocks of video slices.
  • the intra prediction unit 254 is configured to obtain, for example, a picture block 203 (current picture block) and one or more previously reconstructed blocks, such as reconstructed neighboring blocks, that receive the same picture for intra estimation.
  • the encoder 20 may be used to select an intra prediction mode from a plurality of (predetermined) intra prediction modes.
  • Embodiments of the encoder 20 may be used to select an intra-prediction mode based on an optimization criterion, such as based on a minimum residual (eg, an intra-prediction mode that provides a prediction block 255 most similar to the current picture block 203) or a minimum code rate distortion.
  • an optimization criterion such as based on a minimum residual (eg, an intra-prediction mode that provides a prediction block 255 most similar to the current picture block 203) or a minimum code rate distortion.
  • the intra prediction unit 254 is further configured to determine the intra prediction block 255 based on the intra prediction parameters of the intra prediction mode as selected. In any case, after selecting the intra prediction mode for the block, the intra prediction unit 254 is further configured to provide the intra prediction parameters to the entropy encoding unit 270, that is, to provide an indication of the selected intra prediction mode for the block. Information. In one example, the intra prediction unit 254 may be used to perform any combination of intra prediction techniques described below.
  • the entropy coding unit 270 is configured to apply an entropy coding algorithm or scheme (for example, a variable length coding (VLC) scheme, a context adaptive VLC (context adaptive VLC, CAVLC) scheme, an arithmetic coding scheme, and a context adaptive binary arithmetic Coding (context, adaptive binary coding, CABAC), syntax-based context-adaptive binary arithmetic coding (SBAC), probability interval partitioning entropy (PIPE) coding, or other entropy (Coding method or technique) is applied to one or all of the quantized residual coefficients 209, inter prediction parameters, intra prediction parameters, and / or loop filter parameters (or not applied) to obtain
  • the encoded picture data 21 is output in the form of, for example, an encoded bit stream 21.
  • the encoded bitstream may be transmitted to video decoder 30 or archived for later transmission or retrieval by video decoder 30.
  • the entropy encoding unit 270 may also be used to entropy encode other syntax elements of the current video slice that is being encoded.
  • video encoder 20 may be used to encode a video stream.
  • the non-transform-based encoder 20 may directly quantize the residual signal without a transform processing unit 206 for certain blocks or frames.
  • the encoder 20 may have a quantization unit 208 and an inverse quantization unit 210 combined into a single unit.
  • FIG. 3 illustrates an exemplary video decoder 30 for implementing the techniques of the present application.
  • the video decoder 30 is configured to receive, for example, encoded picture data (eg, an encoded bit stream) 21 encoded by the encoder 20 to obtain a decoded picture 231.
  • video decoder 30 receives video data from video encoder 20, such as an encoded video bitstream and associated syntax elements representing picture blocks of encoded video slices.
  • the decoder 30 includes an entropy decoding unit 304, an inverse quantization unit 310, an inverse transform processing unit 312, a reconstruction unit 314 (such as a summer 314), a buffer 316, a loop filter 320, The decoded picture buffer 330 and the prediction processing unit 360.
  • the prediction processing unit 360 may include an inter prediction unit 344, an intra prediction unit 354, and a mode selection unit 362.
  • video decoder 30 may perform a decoding pass that is substantially inverse to the encoding pass described with reference to video encoder 20 of FIG. 2.
  • the entropy decoding unit 304 is configured to perform entropy decoding on the encoded picture data 21 to obtain, for example, quantized coefficients 309 and / or decoded encoding parameters (not shown in FIG. 3), for example, inter prediction, intra prediction parameters , (Filtered) any or all of the loop filter parameters and / or other syntax elements.
  • the entropy decoding unit 304 is further configured to forward the inter prediction parameters, the intra prediction parameters, and / or other syntax elements to the prediction processing unit 360.
  • Video decoder 30 may receive syntax elements at the video slice level and / or the video block level.
  • the inverse quantization unit 310 may be functionally the same as the inverse quantization unit 110
  • the inverse transformation processing unit 312 may be functionally the same as the inverse transformation processing unit 212
  • the reconstruction unit 314 may be functionally the same as the reconstruction unit 214
  • the buffer 316 may be functionally
  • the loop filter 320 may be functionally the same as the loop filter 220
  • the decoded picture buffer 330 may be functionally the same as the decoded picture buffer 230.
  • the prediction processing unit 360 may include an inter prediction unit 344 and an intra prediction unit 354.
  • the inter prediction unit 344 may be functionally similar to the inter prediction unit 244 and the intra prediction unit 354 may be functionally similar to the intra prediction unit 254.
  • the prediction processing unit 360 is generally used to perform block prediction and / or obtain a prediction block 365 from the encoded data 21, and to receive or obtain prediction-related parameters from, for example, an entropy decoding unit 304 (explicitly or implicitly) and / or Information about the selected prediction mode.
  • the intra-prediction unit 354 of the prediction processing unit 360 is used for the intra-prediction mode based on the signal representation and the previously decoded block from the current frame or picture Data to generate a prediction block 365 for a picture block of the current video slice.
  • the inter-prediction unit 344 e.g., a motion compensation unit
  • the other syntax elements generate a prediction block 365 for a video block of the current video slice.
  • a prediction block may be generated from a reference picture in a reference picture list.
  • the video decoder 30 may construct a reference frame list using a default construction technique based on the reference pictures stored in the DPB 330: List 0 and List 1.
  • the prediction processing unit 360 is configured to determine prediction information for a video block of a current video slice by analyzing a motion vector and other syntax elements, and use the prediction information to generate a prediction block for a current video block that is being decoded. For example, the prediction processing unit 360 uses some of the received syntax elements to determine a prediction mode (e.g., intra or inter prediction) of a video block used to encode a video slice, an inter prediction slice type (e.g., B slice, P slice or GPB slice), construction information for one or more of the reference picture lists for the slice, motion vectors for each inter-coded video block for the slice, each warp for the slice The inter-prediction status and other information of the inter-coded video block to decode the video block of the current video slice.
  • a prediction mode e.g., intra or inter prediction
  • an inter prediction slice type e.g., B slice, P slice or GPB slice
  • construction information for one or more of the reference picture lists for the slice motion vectors for each inter-coded video block
  • the inverse quantization unit 310 may be used for inverse quantization (ie, inverse quantization) of the quantized transform coefficients provided in the bitstream and decoded by the entropy decoding unit 304.
  • the inverse quantization process may include using the quantization parameters calculated by video encoder 20 for each video block in the video slice to determine the degree of quantization that should be applied and also to determine the degree of inverse quantization that should be applied.
  • the inverse transform processing unit 312 is configured to apply an inverse transform (for example, an inverse DCT, an inverse integer transform, or a conceptually similar inverse transform process) to the transform coefficients to generate a residual block in the pixel domain.
  • an inverse transform for example, an inverse DCT, an inverse integer transform, or a conceptually similar inverse transform process
  • Reconstruction unit 314 (e.g., summer 314) is used to add inverse transform block 313 (i.e., reconstructed residual block 313) to prediction block 365 to obtain reconstructed block 315 in the sample domain, such as by The sample values of the reconstructed residual block 313 are added to the sample values of the prediction block 365.
  • the loop filter unit 320 (during or after the encoding cycle) is used to filter the reconstructed block 315 to obtain the filtered block 321 so as to smoothly perform pixel conversion or improve video quality.
  • the loop filter unit 320 may be used to perform any combination of filtering techniques described below.
  • the loop filter unit 320 is intended to represent one or more loop filters, such as a deblocking filter, a sample-adaptive offset (SAO) filter, or other filters such as a bilateral filter, Adaptive loop filters (adaptive loop filters, ALF), or sharpening or smoothing filters, or cooperative filters.
  • the loop filter unit 320 is shown as an in-loop filter in FIG. 3, in other configurations, the loop filter unit 320 may be implemented as a post-loop filter.
  • the decoded video block 321 in a given frame or picture is then stored in a decoded picture buffer 330 that stores reference pictures for subsequent motion compensation.
  • the decoder 30 is used, for example, to output a decoded picture 31 through an output 332 for presentation to or review by a user.
  • video decoder 30 may be used to decode the compressed bitstream.
  • the decoder 30 may generate an output video stream without the loop filter unit 320.
  • the non-transform-based decoder 30 may directly inversely quantize the residual signal without the inverse transform processing unit 312 for certain blocks or frames.
  • the video decoder 30 may have an inverse quantization unit 310 and an inverse transform processing unit 312 combined into a single unit.
  • FIG. 4 is an explanatory diagram of an example of a video encoding system 40 including the encoder 20 of FIG. 2 and / or the decoder 30 of FIG. 3 according to an exemplary embodiment.
  • the system 40 may implement a combination of various techniques of the present application.
  • the video encoding system 40 may include an imaging device 41, a video encoder 20, a video decoder 30 (and / or a video encoder implemented by the logic circuit 47 of the processing unit 46), an antenna 42, One or more processors 43, one or more memories 44, and / or a display device 45.
  • the imaging device 41, antenna 42, processing unit 46, logic circuit 47, video encoder 20, video decoder 30, processor 43, memory 44, and / or display device 45 can communicate with each other.
  • video encoding system 40 is shown with video encoder 20 and video decoder 30, in different examples, video encoding system 40 may include only video encoder 20 or only video decoder 30.
  • the video encoding system 40 may include an antenna 42.
  • the antenna 42 may be used to transmit or receive an encoded bit stream of video data.
  • the video encoding system 40 may include a display device 45.
  • the display device 45 may be used to present video data.
  • the logic circuit 47 may be implemented by the processing unit 46.
  • the processing unit 46 may include application-specific integrated circuit (ASIC) logic, a graphics processor, a general-purpose processor, and the like.
  • the video encoding system 40 may also include an optional processor 43, which may similarly include application-specific integrated circuit (ASIC) logic, a graphics processor, a general-purpose processor, and the like.
  • ASIC application-specific integrated circuit
  • the logic circuit 47 may be implemented by hardware, such as dedicated hardware for video encoding, and the processor 43 may be implemented by general software, operating system, and the like.
  • the memory 44 may be any type of memory, such as volatile memory (e.g., Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), etc.) or non-volatile memory Memory (for example, flash memory, etc.).
  • the memory 44 may be implemented by a cache memory.
  • the logic circuit 47 may access the memory 44 (eg, for implementing an image buffer).
  • the logic circuit 47 and / or the processing unit 46 may include a memory (eg, a cache, etc.) for implementing an image buffer or the like.
  • video encoder 20 implemented by logic circuits may include an image buffer (eg, implemented by processing unit 46 or memory 44) and a graphics processing unit (eg, implemented by processing unit 46).
  • the graphics processing unit may be communicatively coupled to the image buffer.
  • the graphics processing unit may include a video encoder 20 implemented by a logic circuit 47 to implement the various modules discussed with reference to FIG. 2 and / or any other encoder system or subsystem described herein.
  • Logic circuits can be used to perform various operations discussed herein.
  • Video decoder 30 may be implemented in a similar manner by logic circuit 47 to implement the various modules discussed with reference to decoder 30 of FIG. 3 and / or any other decoder system or subsystem described herein.
  • video decoder 30 implemented by a logic circuit may include an image buffer (implemented by processing unit 2820 or memory 44) and a graphics processing unit (eg, implemented by processing unit 46).
  • the graphics processing unit may be communicatively coupled to the image buffer.
  • the graphics processing unit may include a video decoder 30 implemented by a logic circuit 47 to implement various modules discussed with reference to FIG. 3 and / or any other decoder system or subsystem described herein.
  • the antenna 42 of the video encoding system 40 may be used to receive an encoded bit stream of video data.
  • the encoded bitstream may contain data, indicators, index values, mode selection data, etc. related to encoded video frames discussed herein, such as data related to coded segmentation (e.g., transform coefficients or quantized transform coefficients) , (As discussed) optional indicators, and / or data defining code partitions).
  • the video encoding system 40 may also include a video decoder 30 coupled to the antenna 42 and used to decode the encoded bitstream.
  • the display device 45 is used to present video frames.
  • FIG. 5 is a simplified block diagram of an apparatus 500 that can be used as either or both of the source device 12 and the destination device 14 in FIG. 1 according to an exemplary embodiment.
  • the device 500 may implement the technology of the present application.
  • the device 500 may be in the form of a computing system including multiple computing devices, or in the form of a single computing device such as a mobile phone, tablet computer, laptop computer, notebook computer, desktop computer, and the like.
  • the processor 502 in the apparatus 500 may be a central processing unit.
  • the processor 502 may be any other type of device or multiple devices capable of manipulating or processing information, existing or to be developed in the future.
  • speed and efficiency advantages can be achieved using more than one processor.
  • the memory 504 in the device 500 may be a read-only memory (ROM) device or a random access memory (RAM) device. Any other suitable type of storage device can be used as the memory 504.
  • the memory 504 may include code and data 506 accessed by the processor 502 using the bus 512.
  • the memory 504 may further include an operating system 508 and an application program 510, which contains at least one program that permits the processor 502 to perform the methods described herein.
  • the application program 510 may include applications 1 to N, and applications 1 to N further include a video encoding application that performs the methods described herein.
  • the device 500 may also include additional memory in the form of a slave memory 514, which may be, for example, a memory card for use with a mobile computing device. Because a video communication session may contain a large amount of information, this information may be stored in whole or in part in the slave memory 514 and loaded into the memory 504 for processing as needed.
  • the apparatus 500 may also include one or more output devices, such as a display 518.
  • the display 518 may be a touch-sensitive display combining a display and a touch-sensitive element operable to sense a touch input.
  • the display 518 may be coupled to the processor 502 through a bus 512.
  • other output devices may be provided that allow the user to program or otherwise use the device 500, or provide other output devices as an alternative to the display 518.
  • the display can be implemented in different ways, including through a liquid crystal display (LCD), a cathode-ray tube (CRT) display, a plasma display, or a light emitting diode diode (LED) displays, such as organic LED (OLED) displays.
  • LCD liquid crystal display
  • CTR cathode-ray tube
  • plasma display a plasma display
  • LED light emitting diode diode
  • OLED organic LED
  • the apparatus 500 may further include or be in communication with an image sensing device 520, such as a camera or any other image sensing device 520 that can or will be developed in the future to sense an image, such as An image of a user running the device 500.
  • the image sensing device 520 may be placed directly facing a user of the running apparatus 500.
  • the position and optical axis of the image sensing device 520 may be configured such that its field of view includes an area immediately adjacent to the display 518 and the display 518 is visible from the area.
  • the device 500 may also include or be in communication with a sound sensing device 522, such as a microphone or any other sound sensing device that can or will be developed in the future to sense the sound near the device 500.
  • the sound sensing device 522 may be placed directly facing the user of the operating device 500 and may be used to receive a sound, such as a voice or other sound, emitted by the user when the device 500 is running.
  • the processor 502 and the memory 504 of the apparatus 500 are shown in FIG. 5 as being integrated in a single unit, other configurations may be used.
  • the operation of the processor 502 may be distributed among multiple directly-coupled machines (each machine has one or more processors), or distributed in a local area or other network.
  • the memory 504 may be distributed among multiple machines, such as a network-based memory or a memory among multiple machines running the apparatus 500.
  • the bus 512 of the device 500 may be formed by multiple buses.
  • the slave memory 514 may be directly coupled to other components of the device 500 or may be accessed through a network, and may include a single integrated unit, such as one memory card, or multiple units, such as multiple memory cards. Therefore, the apparatus 500 can be implemented in various configurations.
  • multi-core transformation selection (MTS: multiple transformation selection) can make full use of the characteristics of different transformation matrices to better adapt to these residual characteristics. So as to achieve the purpose of improving encoding compression performance.
  • the corresponding transformation matrix can be obtained according to the basis function corresponding to the transformation kernel, such as a DCT2 matrix, a DST7 matrix, a DCT8 matrix, and so on.
  • the transform size includes: 4x4, 8x8, 16x16, 32x32.
  • the horizontal / vertical transformation matrix can be combined into 4 kinds of transformation matrix pairs, respectively corresponding to different index numbers. These indexes are written into the code stream and tell the decoder which set of transformation matrix pairs to use.
  • the prediction residual block R is transformed (that is, matrix multiplication) by using the transformation matrices AH and B to obtain a transformation coefficient block F.
  • the coefficient block F is then entropy coded into the code stream.
  • the index of the transform matrix pair obtained by decoding determines the transform matrix pair to be used, and the transform matrix is used to perform inverse transform of the decoded coefficient block in the vertical and horizontal directions to obtain the prediction residual block.
  • the transform matrix is used to perform inverse transform of the decoded coefficient block in the vertical and horizontal directions to obtain the prediction residual block.
  • Reconstructed residual block Specifically, an A matrix and a B matrix are used to perform inverse transformation (that is, matrix multiplication) on the transform coefficient block F obtained by decoding to obtain a residual block R.
  • a ' represents the transposed matrix of the A matrix
  • B' represents the transposed matrix of the B matrix. Since both the A matrix and the B matrix are orthogonal matrices, transposition is equivalent to an inversion matrix.
  • matrix multiplication is generally implemented by a butterfly fast algorithm when implementing a circuit, so that the symmetry of the matrix coefficients can be used to reduce the number of multiplications required.
  • the DST7 and DCT8 transforms do not have a fast butterfly algorithm (partial butterfly) similar to the DCT2 transform; therefore, only matrix multiplication can be used, and the computational complexity (such as the number of multiplications) is high.
  • the draft VVC standard also uses a DCT2 matrix as a transformation matrix, and the size includes 4x4 to 128x128.
  • C DST4 matrix
  • D DCT4 matrix, that is, the DST4 matrix and the DCT4 matrix are used to replace the DST7 matrix and the DCT8 matrix in the prior art 2.
  • DST4 and DCT4 have similar characteristics of the transformation kernel basis functions. The specific transformation basis functions are shown in Table 4.
  • transformation kernels are determined to be DST4 and DCT4
  • corresponding transformation matrices that is, DST4 matrices and DCT4 matrices can be obtained according to the basis functions corresponding to the transformation kernels.
  • the coefficients of the 8X8 DCT2 matrix include the 4X4 DCT2 matrix (such as the coefficients in bold italics in Table 5 are the same as those in Table 6) and the 4X4 DCT4 matrix (such as the coefficients underlined in Table 5 and Table 7 has the same coefficients). It can be seen from Tables 7 and 8 that the DST4 matrix can be obtained by performing mirroring (FLIP) and sign transformation on the DCT4 matrix.
  • FLIP mirroring
  • Table 9 describes the data of the MTS algorithm under AI test conditions
  • Table 10 describes the data of the MTS algorithm under RA test conditions
  • the values in the table represent the percentage increase in coding bits at the same video image quality.
  • Class X (A1, A2, B, C, or E) represents the test video sequence
  • Y, U / V represent the luminance and chrominance components of the video image
  • EncT and DecT represent the encoding and decoding time, respectively.
  • the test condition AI indicates All Intra
  • the test condition RA indicates random access.
  • Figure 6 describes the implementation of the butterfly fast algorithm circuit of the 16 ⁇ 16 DCT2 matrix in HEVC.
  • the butterfly fast algorithm circuit of the 16 ⁇ 16 DCT2 matrix includes the 4 ⁇ 4 DCT2 matrix and 8 ⁇ 8 DCT2.
  • Matrix, 4 ⁇ 4 DCT4 matrix, and 8 ⁇ 8 DCT4 matrix implementation circuit that is, it is possible to realize the transformation of 4 ⁇ 4 DCT2 matrix, 8 ⁇ 8 DCT2 matrix, 4 ⁇ 4 DCT4 matrix, and 8 ⁇ 8 DCT4 matrix.
  • an MTS implementation scheme provided by an embodiment of the present invention is shown in Table 11.
  • C DST4 matrix
  • E DCT2 'matrix
  • DCT2' matrix is the transposed matrix of DCT2 matrix
  • the symbol "'" indicates transposed.
  • the transposed matrix of the DCT2 matrix is consistent with the DCT3 matrix.
  • An implementation example of the 4 ⁇ 4 DST4 matrix is shown in Table 8.
  • An implementation example of the 4 ⁇ 4 DCT2 'matrix is shown in Table 12.
  • Table 9 replaces the DCT4 matrix in Table 3 with the DCT2 'matrix.
  • the implementation of the transform / inverse transform can be further simplified.
  • the transform / inverse transform implementation circuit corresponding to the DCT2 matrix can still be reused.
  • the DST4 matrix can be multiplexed with 2Nx2N DCT2 matrix transformation / inverse transformation implementation circuit after FLIP, symbol transformation, and other operations.
  • the coefficients of the transformation matrix used can be easily derived from the 2Nx2N DCT2 matrix without the need for additional storage space; and the implementation circuit of the transformation matrix used can reuse the transformation / inverse transformation implementation circuit corresponding to the 2Nx2N DCT2 matrix , Can simplify the design of the implementation circuit of the codec.
  • the implementation circuit of the transformation matrix in the embodiment of the present invention may multiplex the transformation / inverse transformation implementation circuit corresponding to the 2Nx2N DCT2 matrix
  • the circuit multiplexing is specifically described below.
  • the method of fast implementation of partial butterfly of the inverse transform circuit disclosed in the document Core Transform Design, High Efficiency, Video Coding (HEVC) Standard The realization of DCT2 matrix inverse transformation can be decomposed into three modules of EVEN, ODD and ADDSUB.
  • EVEN means using a matrix composed of DCT2 matrix odd row coefficients for column transformation
  • ODD means using a matrix composed of DCT2 matrix even row coefficients for columns. Transformation, ADDSUB represents the addition and subtraction module.
  • FIG. 7 illustrates a 32 ⁇ 32 inverse transform implementation circuit.
  • the Even4 module, Odd4 module, and Addsub4 module form a 4 ⁇ 4 matrix inverse transform implementation circuit 701; a 4 ⁇ 4 matrix inverse transform implementation circuit 701, Odd8 Module and Addsub8 module constitute 8 ⁇ 8 matrix inverse transform implementation circuit 702; 8 ⁇ 8 matrix inverse transform implementation circuit 702, Odd16 module and Addsub16 module constitute 16 ⁇ 16 matrix inverse transform implementation circuit 703; 16 ⁇ 16 matrix
  • the inverse transform circuit 703 is implemented by the Odd16 module and the Addsub16 module to form a 32 ⁇ 32 matrix inverse transform circuit 704.
  • FIG. 8 illustrates an implementation circuit. As shown in FIG. 8, the matrix multiplication circuits of the Even4 module and the Odd4 module can be shared by the transform circuit and the inverse transform circuit.
  • Figure 9 depicts the inverse transform architecture of an 8x8 DCT2 matrix, where d n represents the coefficients of the n-th row and column 0 in a 32x32 DCT2 matrix.
  • Figure 9 specifically describes the internal structure of the matrix multiplication operation implemented by the EVEN module and the ODD module .
  • the EVEN8 and ODD8 matrices can be obtained from the 2Nx2N DCT2 matrix.
  • the 4x4 EVEN8 transformation matrix can be obtained as follows:
  • the EVEN8 matrix is actually a DCT2 'matrix.
  • the 4x4 ODD8 transformation matrix can be obtained as follows:
  • the matrix of Table 18 is transposed or symbol-transformed to obtain a 4x4 transformation matrix ODD8 as shown in Table 19.
  • the ODD8 matrix is actually a DST4 matrix deformation.
  • the DST4 matrix can be subjected to sign transformation.
  • the ODD8 matrix can be obtained by inverting the negative sign of the odd column coefficients of the DST4 matrix.
  • Table 12 and Table 16 are the same, that is, the 4 ⁇ 4 DCT2 'transformation matrix can be directly derived from the 8x8 DCT2 matrix, so the implementation circuit of the 4 ⁇ 4 DCT2' transformation matrix also contains In the 2Nx2N DCT2 transform / inverse transform implementation circuit, the implementation of the 4 ⁇ 4 DCT2 'transform matrix can be directly multiplexed with the 2Nx2N DCT2 implementation circuit.
  • an MTS implementation scheme provided by an embodiment of the present invention is shown in Table 20.
  • the above transformation may be a matrix transformation (for example, an inversion operation) of the matrix by row or column.
  • the deformation requirements for the C matrix and the E matrix will be different.
  • the DST4 matrix must be multiplexed with the 2Nx2N DCT2 matrix implementation circuit through FLIP and symbol transformation processing (which becomes a DCT4 matrix); while in the MTS scheme described in Table 11, it is mentioned that The implementation circuit of the 2Nx2N DCT2 matrix actually contains the 0DD8 matrix, and the DST4 matrix can be turned into an ODD8 matrix only by sign transformation to achieve multiplexing.
  • a variety of C matrix and E matrix variants can better adapt to different 2Nx2N DCT2 matrix implementation circuits, thereby simplifying circuit reuse.
  • some deformations of the C and E matrices can be directly derived from the 2Nx2N DCT2 matrix, which can simplify the process of deriving the coefficients of the C and E matrices.
  • a modification of the C matrix can be the inversion of the odd rows of the C matrix, and the result is shown in Table 21:
  • Table 21 and Table 19 are the same and can be derived directly from the coefficients of the 8x8 DCT2 matrix without any additional operations, so the derivation process of C's deformation matrix can be further simplified.
  • the circuits of different 2Nx2N DCT2 matrices can be adapted to simplify circuit reuse, while ensuring that the coding compression performance has a small impact.
  • the matrix coefficients of the transformation matrix used can be directly derived from the 2Nx2N DCT2 matrix without additional storage space; and the implementation circuit of the used transformation matrix can directly reuse the transformation / inverse transformation corresponding to the 2Nx2N DCT2 matrix
  • the implementation circuit can simplify the design of the implementation circuit of the codec.
  • the above transformation may be a matrix transformation (for example, an inversion operation) of the matrix by row or column.
  • the above transformation may be a matrix transformation (for example, an inversion operation) of the matrix by row or column.
  • C DST4 matrix
  • E DCT2 'matrix
  • C DST4 matrix
  • E DCT2 'matrix
  • C DST4 matrix
  • E DCT2 'matrix
  • C DST4 matrix
  • E DCT2 'matrix
  • C DST4 matrix
  • E DCT2 'matrix
  • C DST4 matrix
  • E DCT2 'matrix
  • C DST4 matrix
  • E DCT2 'matrix
  • C DST4 matrix
  • E DCT2 'matrix
  • At least one of the above-mentioned DST4 matrix, DCT2 'matrix, deformation of DST4 matrix, or deformation of DCT2' matrix can be obtained from an 8 ⁇ 8 DCT2 matrix. Since the encoder or decoder stores an 8 ⁇ 8 DCT2 matrix, at least one of the above-mentioned DST4 matrix, DCT2 ′ matrix, deformation of the DST4 matrix, or deformation of the DCT2 ′ matrix can be reduced from the 8 ⁇ 8 DCT2 matrix. The number of transformation matrices that the encoder or decoder needs to store, thus reducing the storage space of the encoder or decoder by the transformation matrix.
  • At least one of the above-mentioned DST4 matrix, DCT2 'matrix, deformation of DST4 matrix, or deformation of DCT2' matrix may also be directly obtained from a 64 ⁇ 64 DCT2 matrix. Since the encoder or decoder stores a 64 ⁇ 64 DCT2 matrix, at least one of the above-mentioned DST4 matrix, DCT2 ′ matrix, deformation of the DST4 matrix, or deformation of the DCT2 ′ matrix can be reduced from the 64 ⁇ 64 DCT2 matrix. The number of transformation matrices that the encoder or decoder needs to store, thus reducing the storage space of the encoder or decoder by the transformation matrix.
  • the above-mentioned 64 ⁇ 64 DCT2 matrix can be shown in Table 34 and Table 35 (because the 64 ⁇ 64 DCT2 matrix is relatively large, it is represented by two tables, where Table 34 describes the matrix Columns 0 to 15 (denoted as transMatrixCol0to15), and Table 35 describes columns 16 to 31 of the matrix (denoted as transMatrixCol16to31).
  • the 64x64 DCT2 matrix transMatrix can be obtained through Table 34 and Table 35.
  • transMatrix [m] [n] (n & 1? -1: 1) * transMatrixCol16to31 [47-m] [n]
  • transMatrix [m] [n] (n & 1? -1: 1) * transMatrixCol0to15 [63-m] [n]
  • trType is used to indicate the transformation kernel, for example, to indicate whether the transformation kernel is a deformation of the DST4 matrix / DST4 matrix or a deformation of the DCT2 'matrix / DCT2' matrix.
  • trType can also take other values to indicate the DST4 matrix and the DCT2 'matrix.
  • the embodiment of the present invention does not limit the correspondence between trType and the transformation matrix, as long as the value of trType can correspond to the transformation matrix one-to-one, it will not affect the implementation of the embodiment of the present invention.
  • the DST4 matrix can be derived from the 64 ⁇ 64 DCT2 matrix by the following formula (1):
  • transMatrix represents the DCT2 matrix (64 ⁇ 64 DCT2 matrix)
  • nTbs represents the size of the transformation matrix, 0 ⁇ i ⁇ nTbS-1, 0 ⁇ j ⁇ nTbS-1
  • the offset 64-nTbs represents the column's offset , Offset to the last nTbs column of the 64x64 matrix
  • (-1) j means perform sign conversion.
  • i represents column coordinates of coefficients in the transformation matrix
  • j represents row coordinates of coefficients in the transformation matrix
  • the 8 ⁇ 8 DST4 matrix is derived according to formula (1):
  • the size of the DST4 matrix is 16 or 32, it can also be derived by using formula (1), which is not described again.
  • the DCT2' matrix can be derived from the 64 ⁇ 64 DCT2 matrix by the following formula (2):
  • transMatrix represents the DCT2 matrix (64 ⁇ 64 DCT2 matrix)
  • nTbs represents the size of the transformation matrix, 0 ⁇ i ⁇ nTbS-1, 0 ⁇ j ⁇ nTbS-1.
  • the size of the DCT2 'matrix is 16 or 32, it can also be derived by using formula (2), which will not be described again.
  • the encoder or decoder may further derive a DCT2 matrix of a small size from a stored DCT2 matrix of a large size.
  • a DCT2 matrix with a size smaller than 64 can be derived according to the following formula (3).
  • transMatrix represents the DCT2 matrix (64 ⁇ 64 DCT2 matrix)
  • nTbs represents the size of the transformation matrix, 0 ⁇ i ⁇ nTbS-1, 0 ⁇ j ⁇ nTbS-1.
  • FIG. 10 describes a flow of a video decoding method according to an embodiment of the present invention.
  • the method may be performed by the video decoder shown in FIG. 3, for example.
  • the method includes:
  • the transformation matrix pair includes a horizontal transformation matrix and a vertical transformation matrix.
  • 1002 Perform inverse quantization processing on a quantization coefficient of the current block to obtain an inverse quantization coefficient of the current block.
  • the horizontal transformation matrix and the vertical transformation matrix included in the candidate transformation matrix pair are preset.
  • One of two transformation matrices; one of the two transformation matrices is a deformation of a DST4 matrix or a DST4 matrix, and the other of the two transformation matrices is a deformation of a DCT2 'matrix or a DCT2' matrix.
  • the number of candidate transformation matrix pairs may be two, three, or four.
  • the horizontal transformation matrix and the vertical transformation matrix included in any one of the candidate transformation matrix pairs are either the same or different.
  • the deformation of the DST4 matrix is obtained by performing a sign transformation on the coefficients of at least a part of the rows or at least a part of the columns in the DST4 matrix.
  • the sign transformation may be a sign inversion.
  • the deformation of the DCT2 'matrix is obtained by performing a sign transformation on the coefficients of at least a part of the rows or at least a part of the columns in the DCT2' matrix.
  • the sign transformation may be a sign inversion.
  • the candidate transformation matrix pair may be a candidate transformation matrix pair described in any one of Table 11, Table 20, Table 24, Table 25, or Table 26-Table 33.
  • the number of the candidate transformation matrix pairs is four; the indication information of the transformation matrix pairs subjected to inverse transformation processing of the current block is the indexes in Table 11, Table 20, Table 24, or Table 25 .
  • Table 11 Taking Table 11 as an example, if the index is 0, it means that the vertical transformation matrix in the transformation matrix pair in which the current block is subjected to inverse transformation processing is DST4 matrix, and the numerical transformation matrix is DST4 matrix; if the index is 1, it means that the current block is processed.
  • the vertical transformation matrix in the transformation matrix pair of the inverse transformation process is DST4 matrix
  • the numerical transformation matrix is the DCT2 'matrix
  • the index is 2, it indicates that the vertical transformation matrix in the transformation matrix pair of the inverse transformation process of the current block is DCT2.
  • the numerical transformation matrix is the DST4 matrix
  • the index is 3
  • it means that the vertical transformation matrix in the transformation matrix pair in which the current block is inversely transformed is the DCT2' matrix
  • the numerical transformation matrix is the DCT2 'matrix.
  • the indication information of a transformation matrix pair that performs inverse transformation processing on the current block includes an identifier of a vertical transformation matrix in the transformation matrix pair that instructs the current block to perform inverse transformation processing, and indicates that The identifier of the horizontal transformation matrix in the transformation matrix pair where the current block is subjected to inverse transformation processing. For example, one bit is used as the identifier of the transformation matrix in the vertical direction, and another bit is used as the identifier of the transformation matrix in the horizontal direction.
  • bit value of the vertical transformation matrix is 0, it means that the vertical transformation matrix is a DST4 matrix, otherwise it means that the vertical transformation matrix is a DCT2 'matrix; if the bit of the horizontal transformation matrix is A value of 0 indicates that the horizontal transformation matrix is a DST4 matrix, and vice versa indicates that the horizontal transformation matrix is a DCT2 'matrix.
  • the bit value of the vertical transformation matrix is 0, it means that the vertical transformation matrix is a deformation of the DST4 matrix, otherwise it means that the vertical transformation matrix is a deformation of the DCT2 'matrix; if the horizontal transformation matrix is a deformation If the value of the bit is 0, it means that the horizontal transformation matrix is a deformation of the DST4 matrix, and vice versa it means that the horizontal transformation matrix is a deformation of the DCT2 'matrix.
  • the bit value of the vertical transformation matrix is 0, it means that the vertical transformation matrix is a deformation of the DST4 matrix, otherwise it means that the vertical transformation matrix is a DCT2 'matrix; if the bits of the horizontal transformation matrix are The value of the bit is 0, which means that the horizontal transformation matrix is a deformation of the DST4 matrix; otherwise, it means that the horizontal transformation matrix is a DCT2 'matrix.
  • bit value of the vertical transformation matrix is 0, it means that the vertical transformation matrix is a DST4 matrix, otherwise it means that the vertical transformation matrix is a deformation of the DCT2 'matrix; if the bit of the horizontal transformation matrix is a deformation The value of the bit is 0, which means that the horizontal transformation matrix is a DST4 matrix; otherwise, it means that the horizontal transformation matrix is a deformation of the DCT2 'matrix.
  • 1004 Perform inverse transform processing on the inverse quantization coefficients of the current block according to a transform matrix that performs inverse transform processing on the current block to obtain a reconstructed residual block of the current block.
  • the deformation of the DCT2 'matrix or the DCT2' matrix has a butterfly fast algorithm in the transformation / inverse transformation
  • the implementation of the transformation / inverse transformation can be simplified.
  • the deformation of the DCT2 'matrix or the DCT2' matrix and the deformation of the DST4 matrix or the DST4 matrix can be directly multiplexed with the transformation / inverse transformation implementation circuit corresponding to the DCT2 matrix, so the transformation / inverse transformation module can simplify the transformation when implemented by the circuit / Inverse conversion module to implement circuit design.
  • the method may further include: deriving a transformation matrix included in the transformation matrix pair for performing inverse transformation processing on the current block from the DCT2 matrix according to a preset algorithm.
  • the inferred transform of the current block for inverse transform processing is derived from the DCT2 matrix according to a preset algorithm.
  • the transformation matrix included in the matrix pair may include: deriving the DST4 matrix according to the foregoing formula (1).
  • the inferred transform of the current block for inverse transform processing is derived from the DCT2 matrix according to a preset algorithm.
  • the transformation matrix included in the transformation matrix pair may include: deriving the DCT2 ′ matrix according to the foregoing formula (2).
  • the decoder only needs to store the DCT2 matrix to derive the matrices included in the transformation matrix pair, so the number of transformation matrices that the decoder needs to store can be reduced, thereby reducing the storage space of the decoder by the transformation matrix.
  • FIG. 11 describes a flow of a video encoding method according to an embodiment of the present invention.
  • the method may be performed by, for example, the video encoder shown in FIG. 2.
  • the method includes:
  • the transformation matrix pair includes a horizontal transformation matrix and a vertical transformation matrix.
  • the transformation matrix pair is one of the candidate transformation matrix pairs.
  • the horizontal transformation matrix and the vertical transformation matrix included in the candidate transformation matrix pair are both one of two preset transformation matrices; one of the two transformation matrices is a deformation of the DST4 matrix or the DST4 matrix, so The other of the two transformation matrices is a deformation of the DCT2 'matrix or the DCT2' matrix.
  • the horizontal transformation matrix and the vertical transformation matrix included in any one of the candidate transformation matrix pairs are either the same or different.
  • the number of candidate transformation matrix pairs may be two, three, or four.
  • the deformation of the DST4 matrix is obtained by performing a sign transformation on the coefficients of at least a part of the rows or at least a part of the columns in the DST4 matrix.
  • the negative sign transformation may be a sign inversion .
  • the deformation of the DCT2 'matrix is obtained by performing a sign transformation on the coefficients of at least a part of the rows or at least a part of the columns in the DCT2' matrix.
  • the sign transformation may be a sign inversion.
  • the candidate transformation matrix pair may be a candidate transformation matrix pair described in any one of Table 11, Table 20, Table 24, Table 25, or Table 26-Table 33.
  • the encoder may use the four candidate transformation matrices to perform horizontal transformation and vertical transformation on the residual block, thereby selecting the transformation matrix pair with the lowest rate-distortion cost as the current residual block.
  • the transformation matrix pair for the transformation process is further determined from any one of Table 11, Table 20, or Table 24-33 to indicate the indication information of the transformation matrix pair for the current residual block to be transformed.
  • the deformation of the DCT2 'matrix or the DCT2' matrix has a butterfly fast algorithm in the transformation / inverse transformation
  • the implementation of the transformation / inverse transformation can be simplified.
  • the deformation of the DCT2 'matrix or the DCT2' matrix and the deformation of the DST4 matrix or the DST4 matrix can be directly multiplexed with the transformation / inverse transformation implementation circuit corresponding to the DCT2 matrix, so the transformation / inverse transformation module can simplify the transformation when implemented by the circuit / Inverse conversion module to implement circuit design.
  • the encoding method further includes: deriving a transformation matrix included in the transformation matrix pair from a DCT2 matrix according to a preset algorithm.
  • the deriving the transformation matrix included in the transformation matrix pair from the DCT2 matrix according to a preset algorithm includes:
  • the DST4 matrix is derived according to the above formula (1).
  • the derivation of the transformation matrix included in the transformation matrix pair from the DCT2 matrix according to a preset algorithm includes: : Derive the DCT2 'matrix according to the above formula (1).
  • the encoder only needs to store the DCT2 matrix to derive the matrix included in the transformation matrix pair, so the number of transformation matrices that the encoder needs to store can be reduced, thereby reducing the storage space of the encoder by the transformation matrix.
  • the structure of the video decoder 30 provided by one embodiment of the present invention is shown in FIG. 3 and includes:
  • the entropy decoding unit 304 is configured to parse the received code stream to obtain indication information of a transformation matrix pair that performs inverse transformation processing on the current block and a quantization coefficient 309 of the current block.
  • the transformation matrix pair includes a horizontal transformation matrix and a vertical Direction transformation matrix.
  • the inverse quantization unit 310 is configured to perform inverse quantization processing on the quantization coefficient 309 of the current block to obtain the inverse quantization coefficient 311 of the current block.
  • An inverse transformation processing unit 312 configured to determine, from the candidate transformation matrix pair, a transformation matrix pair that performs inverse transformation processing on the current block according to the instruction information; the candidate transformation matrix pair includes a horizontal transformation matrix and a vertical transformation
  • the matrices are one of two preset transformation matrices; one of the two transformation matrices is a DST4 matrix or a modification of the DST4 matrix, and the other of the two transformation matrices is a DCT2 'matrix or a DCT2' matrix.
  • Deformation performing inverse transform processing on the inverse quantization coefficients of the current block according to a transform matrix that performs inverse transform processing on the current block to obtain a reconstructed residual block 313 of the current block.
  • a reconstruction unit 314 is configured to obtain a reconstruction block 315 of the current block based on a reconstruction residual block of the current block.
  • the inverse transform processing unit 312 may be further configured to: from a DCT2 matrix, derive a transform matrix included in the transform matrix of the current block for inverse transform processing according to a preset algorithm.
  • the inverse transformation processing unit 312 may be specifically configured to derive the according to the above formula (1) DST4 matrix.
  • the inverse transformation processing unit 312 may be specifically configured to derive the calculated matrix according to the above formula (2).
  • the DCT2 'matrix is described.
  • the structure of the video encoder 20 provided by one embodiment of the present invention is shown in FIG. 2 and includes:
  • a transformation processing unit 206 configured to determine indication information of a transformation matrix pair used to transform the current residual block 205, the transformation matrix pair including a horizontal transformation matrix and a vertical transformation matrix; the transformation matrix pair is a candidate One of a transformation matrix pair, the horizontal transformation matrix and the vertical transformation matrix included in the candidate transformation matrix pair are both one of two preset transformation matrices; one of the two transformation matrices is a DST4 matrix or A deformation of the DST4 matrix, the other of the two transformation matrices being a deformation of the DCT2 'matrix or the DCT2' matrix.
  • a quantization unit 207 performs quantization processing on the transformation coefficient 207 obtained by performing transformation processing on the current residual block through the transformation matrix to obtain a quantized coefficient of the current residual block.
  • the transformation coefficient 207 can be specifically obtained by the transformation processing unit 206.
  • An entropy coding unit 270 configured to perform entropy coding processing on the quantization coefficient of the current residual block and the indication information
  • An output 272 is used to write the indication information of the transform matrix pair after the entropy coding process and the quantization coefficient of the current residual block after the entropy coding process into a code stream.
  • the transformation processing unit 206 may be further configured to derive a transformation matrix included in the transformation matrix pair from a DCT2 matrix according to a preset algorithm.
  • the transformation processing unit 206 may be specifically configured to derive the DST4 matrix according to the above formula (1).
  • the transform processing unit 206 may be specifically configured to derive the DCT2' matrix according to the above formula (2).
  • An embodiment of the present invention further provides a video decoder, which includes an execution circuit for performing any one of the video decoding methods described above.
  • An embodiment of the present invention further provides a video decoder, including: at least one processor; and a non-volatile computer-readable storage medium coupled to the at least one processor, the non-volatile computer-readable storage The medium stores a computer program executable by the at least one processor, and when the computer program is executed by the at least one processor, the video decoder is used to execute any one of the video decoding methods described above.
  • An embodiment of the present invention further provides a video encoder, which includes an execution circuit for executing any one of the video encoding methods described above.
  • An embodiment of the present invention further provides a video encoder, including: at least one processor; and a non-volatile computer-readable storage medium coupled to the at least one processor, the non-volatile computer-readable storage The medium stores a computer program executable by the at least one processor, and when the computer program is executed by the at least one processor, the video decoder is used to perform any one of the video encoding methods described above.
  • An embodiment of the present invention further provides a computer-readable storage medium for storing a computer program executable by a processor, and when the computer program is executed by the at least one processor, performing any one of the foregoing methods. .
  • An embodiment of the present invention further provides a computer program, and when the computer program is executed, any one of the foregoing methods is performed.
  • a computer-readable medium may include a computer-readable storage medium, which corresponds to a tangible medium such as a data storage medium or a communication medium including any medium that facilitates transfer of a computer program from one place to another, according to a communication protocol, for example.
  • computer-readable media generally may correspond to (1) tangible computer-readable storage media that is non-transitory, or (2) a communication medium such as a signal or carrier wave.
  • a data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, codes, and / or data structures used to implement the techniques described in this disclosure.
  • the computer program product may include a computer-readable medium.
  • such computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage or other magnetic storage devices, flash memory, or may be used to store instructions or data structures Any other media that requires program code and is accessible by the computer.
  • any connection is properly termed a computer-readable medium.
  • a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology such as infrared, radio, and microwave is used to transmit instructions from a website, server, or other remote source
  • Coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of the medium.
  • the computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transitory media, but are instead directed to non-transitory tangible storage media.
  • magnetic disks and compact discs include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), flexible discs and Blu-ray discs, where the discs are usually magnetic The data is reproduced, while the optical disk uses a laser to reproduce the data optically. Combinations of the above should also be included within the scope of computer-readable media.
  • processors such as one or more digital signal processors (DSPs), general purpose microprocessors, application specific integrated circuits , ASIC), field programmable logic array (field programmable logic arrays, FPGA) or other equivalent integrated or discrete logic circuits.
  • DSPs digital signal processors
  • ASIC application specific integrated circuits
  • FPGA field programmable logic arrays
  • processors may refer to any of the above-described structures or any other structure suitable for implementing the techniques described herein.
  • the functionality described herein may be provided within dedicated hardware and / or software modules for encoding and decoding, or incorporated in a composite codec. Also, the techniques could be fully implemented in one or more circuits or logic elements.
  • the techniques of this disclosure may be implemented in a variety of devices or devices that include a wireless handset, an integrated circuit (IC), or a collection of ICs (eg, a chipset).
  • IC integrated circuit
  • the present disclosure describes various components, modules, or units to emphasize functional aspects of the device for performing the disclosed techniques, but does not necessarily need to be implemented by different hardware units.
  • the various units may be combined in a codec hardware unit in combination with suitable software and / or firmware, or provided by a collection of interoperable hardware units, which include as described above One or more processors.

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Abstract

本发明公开了一种视频解码方法和视频解码器。所述方法包括：解析接收的码流，以获得当前块进行逆变换处理的变换矩阵对的指示信息以及所述当前块的量化系数；对所述当前块的量化系数进行逆量化处理以获得所述当前块的反量化系数；根据所述指示信息从四个候选变换矩阵对中确定所述当前块进行逆变换处理的变换矩阵对；所述四个候选变换矩阵对所包括的水平方向变换矩阵和垂直方向变换矩阵均为预设的两个变换矩阵中的一个；所述两个变换矩阵中一个为DST4矩阵或DST4矩阵的变形，所述两个变换矩阵中的另一个为DCT2'矩阵或DCT2'矩阵的变形；根据所述当前块进行逆变换处理的变换矩阵对获得所述当前块的重构块。使用本专利，可以简化变换/反变换的实现。

Description

视频解码方法及视频解码器，视频编码方法及视频编码器
本申请要求于2018年9月21日提交中国国家知识产权局、申请号为201811107865.2、发明名称为“视频解码方法及视频解码器，视频编码方法及视频编码器”，以及于2018年9月29日提交中国国家知识产权局、申请号为201811150819.0、发明名称为“视频解码方法及视频解码器，视频编码方法及视频编码器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例大体上涉及视频编码领域，更确切地说，涉及视频解码方法及视频解码器，视频编码方法及视频编码器。
背景技术
视频编码(视频编码和解码)广泛用于数字视频应用，例如广播数字电视、互联网和移动网络上的视频传播、视频聊天和视频会议等实时会话应用、DVD和蓝光光盘、视频内容采集和编辑系统以及可携式摄像机的安全应用。
随着1990年H.261标准中基于块的混合型视频编码方式的发展，新的视频编码技术和工具得到发展并为新的视频编码标准形成基础。其它视频编码标准包括MPEG-1视频、MPEG-2视频、ITU-T H.262/MPEG-2、ITU-T H.263、ITU-T H.264/MPEG-4第10部分高级视频编码(Advanced Video Coding，AVC)、ITU-T H.265/高效视频编码(High Efficiency Video Coding，HEVC)…以及此类标准的扩展，例如可扩展性和/或3D(three-dimensional)扩展。随着视频创建和使用变得越来越广泛，视频流量成为通信网络和数据存储的最大负担。因此大多数视频编码标准的目标之一是相较之前的标准，在不牺牲图片质量的前提下减少比特率。即使最新的高效视频编码(High Efficiency video coding，HEVC)可以在不牺牲图片质量的前提下比AVC大约多压缩视频一倍，仍然亟需新技术相对HEVC进一步压缩视频。
发明内容
本申请实施例提供视频解码方法及视频解码器，视频编码方法及视频编码器，可以可以简化变换/反变换的实现。
前述和其它目标通过独立权利要求的主题实现。其它实现方式通过从属权利要求、说明书以及附图是显而易见的。
第一方面，本发明提供了一种视频解码方法，包括：
解析接收的码流，以获得当前块进行逆变换处理的变换矩阵对的指示信息以及所述当前块的量化系数，所述变换矩阵对包括水平方向变换矩阵和垂直方向变换矩阵；
对所述当前块的量化系数进行逆量化处理以获得所述当前块的反量化系数；
根据所述指示信息从候选变换矩阵对中确定所述当前块进行逆变换处理的变换矩阵对；所述候选变换矩阵对所包括的水平方向变换矩阵和垂直方向变换矩阵均为预设的两个变换矩阵中的一个；所述两个变换矩阵中一个为DST4矩阵或DST4矩阵的变形，所述两个变换矩阵中的另一个为DCT2’矩阵或DCT2’矩阵的变形，其中，DCT2’矩阵为DCT2矩 阵的转置矩阵；
根据所述当前块进行逆变换处理的变换矩阵对对所述当前块的反量化系数进行逆变换处理，以得到所述当前块的重建残差块；
根据所述当前块的重建残差块获得所述当前块的重构块。
其中，任意一个所述候选变换对所包括的水平方向变换矩阵和垂直方向变换矩阵要么相同要么不同。
其中，所述候选变换矩阵对的数量可以为2个，3个或4个。
可见，由于DCT2’矩阵或DCT2’矩阵的变形在变换/反变换时存在蝶形快速算法，因此可以简化变换/反变换的实现。同时，DCT2’矩阵或DCT2’矩阵的变形以及DST4矩阵或DST4矩阵的变形均可以直接复用DCT2矩阵对应的变换/反变换实现电路，因此在变换/反变换模块在通过电路实现时可以简化变换/反变换模块的实现电路的设计。
结合第一方面，在可能的实施方式中，所述DST4矩阵的变形是通过对所述DST4矩阵中的至少一部分行或至少一部分列的系数进行符号变换获得；或
所述DCT2’矩阵的变形是通过对所述DCT2’矩阵中的至少一部分行或至少一部分列的系数进行符号变换获得。
结合第一方面，在可能的实施方式中，所述候选变换矩阵对的数量为四个；在所述两个变换矩阵中一个为DST4矩阵，另一个为DCT2’矩阵时，所述四个候选变换矩阵对中的第一个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵，所述第一个变换矩阵对包括的水平方向变换矩阵为DST4矩阵；
所述四个候选变换矩阵对中的第二个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵，所述第二个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵；
所述四个候选变换矩阵对中的第三个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵，所述第三个变换矩阵对包括的水平方向变换矩阵为DST4矩阵；
所述四个候选变换矩阵对中的第四个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵，所述第四个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵。
结合第一方面，在可能的实施方式中，所述候选变换矩阵对的数量为四个；在所述两个变换矩阵中一个为DST4矩阵的变形，另一个为DCT2’矩阵的变形时，所述四个候选变换矩阵对中的第一个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵的变形，所述第一个变换矩阵对包括的水平方向变换矩阵为DST4矩阵的变形；
所述四个候选变换矩阵对中的第二个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵的变形，所述第二个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵的变形；
所述四个候选变换矩阵对中的第三个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵的变形，所述第三个变换矩阵对包括的水平方向变换矩阵为DST4矩阵的变形；
所述四个候选变换矩阵对中的第四个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵的变形，所述第四个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵的变形。
结合第一方面，在可能的实施方式中，所述指示信息包括用于指示所述当前块进行逆变换处理的变换矩阵对中的垂直方向变换矩阵的标识，以及用于指示所述当前块进行逆变换处理的变换矩阵对中的水平方向变换矩阵的标识。
结合第一方面，在可能的实施方式中，所述根据所述当前块进行逆变换处理的变换矩阵对对所述当前块的反量化系数进行逆变换处理前，所述方法还包括：根据预设算法从DCT2矩阵推导出所述当前块进行逆变换处理的变换矩阵对所包括的变换矩阵。
结合第一方面，在可能的实施方式中，所述当前块进行逆变换处理的变换矩阵对包括DST4矩阵；所述DCT2矩阵的大小为64；所述根据预设算法从DCT2矩阵推导出所述当前块进行逆变换处理的变换矩阵对所包括的变换矩阵包括：根据如下公式从所述DCT2矩阵推导出所述DST4矩阵：
Figure PCTCN2019106383-appb-000001
其中，transMatrix表示所述DCT2矩阵，nTbs表示所述DST4矩阵的大小，0≤i≤nTbS–1，0≤j≤nTbS–1；偏移量64-nTbs表示列的偏移；偏移量
Figure PCTCN2019106383-appb-000002
表示行的偏移；(-1) j表示进行符号变换。
结合第一方面，在可能的实施方式中，所述当前块进行逆变换处理的变换矩阵对包括DCT2’矩阵；所述DCT2矩阵的大小为64；所述根据预设算法从DCT2矩阵推导出所述当前块进行逆变换处理的变换矩阵对所包括的变换矩阵包括：根据如下公式从所述DCT2矩阵推导出所述DCT2’矩阵：
transMatrix[j][i×2 6-Log2(nTbs)]；
其中，transMatrix表示所述DCT2矩阵，nTbs表示所述DCT2’的大小，0≤i≤nTbS–1，0≤j≤nTbS–1。
第二方面，本发明提供了一种编码方法，包括：
确定用于对当前残差块进行变换处理的变换矩阵对的指示信息，所述变换矩阵对包括水平方向变换矩阵和垂直方向变换矩阵；所述变换矩阵对是候选变换矩阵对中的一个，所述候选变换矩阵对所包括的水平方向变换矩阵和垂直方向变换矩阵均为预设的两个变换矩阵中的一个；所述两个变换矩阵中一个为DST4矩阵或DST4矩阵的变形，所述两个变换矩阵中的另一个为DCT2’矩阵或DCT2’矩阵的变形，其中，DCT2’矩阵为DCT2矩阵的转置矩阵；
对通过所述变换矩阵对对所述当前残差块进行变换处理获得的变换系数进行量化处理，以获得所述当前残差块的量化系数；
将所述变换矩阵对的指示信息写入码流；和
将所述量化系数进行熵编码处理后写入码流。
其中，任意一个所述候选变换对所包括的水平方向变换矩阵和垂直方向变换矩阵要么相同要么不同。
其中，所述候选变换矩阵对的数量可以为2个，3个或4个。
可见，由于DCT2’矩阵或DCT2’矩阵的变形在变换/反变换时存在蝶形快速算法，因此可以简化变换/反变换的实现。同时，DCT2’矩阵或DCT2’矩阵的变形以及DST4矩阵或DST4矩阵的变形均可以直接复用DCT2矩阵对应的变换/反变换实现电路，因此在变换/反变换模块在通过电路实现时可以简化变换/反变换模块的实现电路的设计。
结合第二方面，在可能的实施方式中，所述DST4矩阵的变形是通过对所述DST4矩阵中的至少一部分行或至少一部分列的系数进行符号变换获得；或
所述DCT2’矩阵的变形是通过对所述DCT2’矩阵中的至少一部分行或至少一部分列的系数进行符号变换获得。
结合第二方面，在可能的实施方式中，所述候选变换矩阵对的数量为四个；在所述两个变换矩阵中一个为DST4矩阵，另一个为DCT2’矩阵时，所述四个候选变换矩阵对中的第一个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵，所述第一个变换矩阵对包括的水平方向变换矩阵为DST4矩阵；
所述四个候选变换矩阵对中的第二个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵，所述第二个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵；
所述四个候选变换矩阵对中的第三个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵，所述第三个变换矩阵对包括的水平方向变换矩阵为DST4矩阵；
所述四个候选变换矩阵对中的第四个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵，所述第四个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵。
结合第二方面，在可能的实施方式中，所述候选变换矩阵对的数量为四个；在所述两个变换矩阵中一个为DST4矩阵的变形，另一个为DCT2’矩阵的变形时，所述四个候选变换矩阵对中的第一个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵的变形，所述第一个变换矩阵对包括的水平方向变换矩阵为DST4矩阵的变形；
所述四个候选变换矩阵对中的第二个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵的变形，所述第二个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵的变形；
所述四个候选变换矩阵对中的第三个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵的变形，所述第三个变换矩阵对包括的水平方向变换矩阵为DST4矩阵的变形；
所述四个候选变换矩阵对中的第四个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵的变形，所述第四个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵的变形。
结合第二方面，在可能的实施方式中，所述方法还包括：根据预设算法从DCT2矩阵推导出所述变换矩阵对所包括的变换矩阵。
结合第二方面，在可能的实施方式中，所述变换矩阵对所包括的变换矩阵包括DST4矩阵；所述DCT2矩阵的大小为64；所述根据预设算法从DCT2矩阵推导出所述变换矩阵对所包括的变换矩阵包括：根据如下公式从所述DCT2矩阵推导出所述DST4矩阵：
Figure PCTCN2019106383-appb-000003
其中，transMatrix表示所述DCT2矩阵，nTbs表示所述DST4矩阵的大小，0≤i≤nTbS–1，0≤j≤nTbS–1；偏移量64-nTbs表示列的偏移；偏移量
Figure PCTCN2019106383-appb-000004
表示行的偏移；(-1) j表示进行符号变换。
结合第一方面，在可能的实施方式中，所述变换矩阵对所包括的变换矩阵包括DCT2’矩阵；所述DCT2矩阵的大小为64；所述根据预设算法从DCT2矩阵推导出所述变换矩阵对所包括的变换矩阵包括：根据如下公式从所述DCT2矩阵推导出所述DCT2’矩阵：
transMatrix[j][i×2 6-Log2(nTbs)]；
其中，transMatrix表示所述DCT2矩阵，nTbs表示所述DCT2’的大小，0≤i≤nTbS–1，0≤j≤nTbS–1。
第三方面，本发明提供了一种视频解码器，包括：
熵解码单元，用于解析接收的码流，以获得当前块进行逆变换处理的变换矩阵对的指示信息以及所述当前块的量化系数，所述变换矩阵对包括水平方向变换矩阵和垂直方向变换矩阵；
逆量化单元，用于对所述当前块的量化系数进行逆量化处理以获得所述当前块的反量化系数；
逆变换处理单元，用于根据所述指示信息从四个候选变换矩阵对中确定所述当前块进行逆变换处理的变换矩阵对；所述候选变换矩阵对所包括的水平方向变换矩阵和垂直方向变换矩阵均为预设的两个变换矩阵中的一个；所述两个变换矩阵中一个为DST4矩阵或DST4矩阵的变形，所述两个变换矩阵中的另一个为DCT2’矩阵或DCT2’矩阵的变形，其中，DCT2’矩阵为DCT2矩阵的转置矩阵；根据所述当前块进行逆变换处理的变换矩阵对对所述当前块的反量化系数进行逆变换处理，以得到所述当前块的重建残差块；
重构单元，用于基于所述当前块的重建残差块获得所述当前块的重构块。
其中，任意一个所述候选变换对所包括的水平方向变换矩阵和垂直方向变换矩阵要么相同要么不同。
其中，所述候选变换矩阵对的数量可以为2个，3个或4个。
结合第三方面，在可能的实施方式中，所述DST4矩阵的变形是通过对所述DST4矩阵中的至少一部分行或至少一部分列的系数进行符号变换获得；或
所述DCT2’矩阵的变形是通过对所述DCT2’矩阵中的至少一部分行或至少一部分列的系数进行符号变换获得。
结合第三方面，在可能的实施方式中，所述候选变换矩阵对的数量为四个；在所述两个变换矩阵中一个为DST4矩阵，另一个为DCT2’矩阵时，所述四个候选变换矩阵对中的第一个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵，所述第一个变换矩阵对包括的水平方向变换矩阵为DST4矩阵；
所述四个候选变换矩阵对中的第二个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵，所述第二个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵；
所述四个候选变换矩阵对中的第三个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵，所述第三个变换矩阵对包括的水平方向变换矩阵为DST4矩阵；
所述四个候选变换矩阵对中的第四个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵，所述第四个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵。
结合第三方面，在可能的实施方式中，所述候选变换矩阵对的数量为四个；在所述两个变换矩阵中一个为DST4矩阵的变形，另一个为DCT2’矩阵的变形时，所述四个候选变换矩阵对中的第一个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵的变形，所述第一个变换矩阵对包括的水平方向变换矩阵为DST4矩阵的变形；
所述四个候选变换矩阵对中的第二个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵的变形，所述第二个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵的变形；
所述四个候选变换矩阵对中的第三个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵的变形，所述第三个变换矩阵对包括的水平方向变换矩阵为DST4矩阵的变形；
所述四个候选变换矩阵对中的第四个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵的变形，所述第四个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵的变形。
结合第三方面，在可能的实施方式中，所述指示信息包括用于指示所述当前块进行逆变换处理的变换矩阵对中的垂直方向变换矩阵的标识，以及用于指示所述当前块进行逆变换处理的变换矩阵对中的水平方向变换矩阵的标识。
结合第三方面，在可能的实施方式中，所述逆变换处理单元还用于：根据预设算法从DCT2矩阵推导出所述当前块进行逆变换处理的变换矩阵对所包括的变换矩阵。
结合第三方面，在可能的实施方式中，所述当前块进行逆变换处理的变换矩阵对包括DST4矩阵；所述DCT2矩阵的大小为64；所述逆变换处理单元具体用于：根据如下公式从所述DCT2矩阵推导出所述DST4矩阵：
；
其中，transMatrix表示所述DCT2矩阵，nTbs表示所述DST4矩阵的大小，0≤i≤nTbS–1，0≤j≤nTbS–1；偏移量64-nTbs表示列的偏移；偏移量
Figure PCTCN2019106383-appb-000005
表示行的偏移；(-1) j表示进行符号变换。
结合第三方面，在可能的实施方式中，所述当前块进行逆变换处理的变换矩阵对包括DCT2’矩阵；所述DCT2矩阵的大小为64；所述逆变换处理单元具体用于：根据如下公式从所述DCT2矩阵推导出所述DCT2’矩阵：
transMatrix[j][i×2 6-Log2(nTbs)]；
其中，transMatrix表示所述DCT2矩阵，nTbs表示所述DCT2’的大小，0≤i≤nTbS–1，0≤j≤nTbS–1。
第四方面，本发明提供了一种视频编码器，包括：
变换处理单元，用于确定用于对当前残差块进行变换处理的变换矩阵对的指示信息，所述变换矩阵对包括水平方向变换矩阵和垂直方向变换矩阵；所述变换矩阵对是候选变换矩阵对中的一个，所述候选变换矩阵对所包括的水平方向变换矩阵和垂直方向变换矩阵均为预设的两个变换矩阵中的一个；所述两个变换矩阵中一个为DST4矩阵或DST4矩阵的变形，所述两个变换矩阵中的另一个为DCT2’矩阵或DCT2’矩阵的变形，其中，DCT2’矩阵为DCT2矩阵的转置矩阵；
量化单元，对通过所述变换矩阵对对所述当前残差块进行变换处理获得的变换系数进行量化处理，以获得所述当前残差块的量化系数；
熵编码单元，用于对所述当前残差块的量化系数和所述指示信息进行熵编码处理；
输出，用于将熵编码处理后的所述变换矩阵对的指示信息和熵编码处理后的所述当前残差块的量化系数写入码流。
其中，任意一个所述候选变换对所包括的水平方向变换矩阵和垂直方向变换矩阵要么相同要么不同。
其中，所述候选变换矩阵对的数量可以为2个，3个或4个。
结合第四方面，在可能的实施方式中，所述DST4矩阵的变形是通过对所述DST4矩阵中的至少一部分行或至少一部分列的系数进行符号变换获得；或
所述DCT2’矩阵的变形是通过对所述DCT2’矩阵中的至少一部分行或至少一部分列的系数进行符号变换获得。
结合第四方面，在可能的实施方式中，所述候选变换矩阵对的数量为四个；在所述两个变换矩阵中一个为DST4矩阵，另一个为DCT2’矩阵时，所述四个候选变换矩阵对中的第一个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵，所述第一个变换矩阵对包括的水平方向变换矩阵为DST4矩阵；
所述四个候选变换矩阵对中的第二个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵，所述第二个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵；
所述四个候选变换矩阵对中的第三个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵，所述第三个变换矩阵对包括的水平方向变换矩阵为DST4矩阵；
所述四个候选变换矩阵对中的第四个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵，所述第四个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵。
结合第四方面，在可能的实施方式中，所述候选变换矩阵对的数量为四个；在所述两个变换矩阵中一个为DST4矩阵的变形，另一个为DCT2’矩阵的变形时，所述四个候选变换矩阵对中的第一个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵的变形，所述第一个变换矩阵对包括的水平方向变换矩阵为DST4矩阵的变形；
所述四个候选变换矩阵对中的第二个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵的变形，所述第二个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵的变形；
所述四个候选变换矩阵对中的第三个变换矩阵对包括的垂直方向变换矩阵为DCT2’ 矩阵的变形，所述第三个变换矩阵对包括的水平方向变换矩阵为DST4矩阵的变形；
所述四个候选变换矩阵对中的第四个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵的变形，所述第四个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵的变形。
结合第四方面，在可能的实施方式中，所述变换处理单元还用于：根据预设算法从DCT2矩阵推导出所述变换矩阵对所包括的变换矩阵。
结合第四方面，在可能的实施方式中，所述变换矩阵对包括DST4矩阵；所述DCT2矩阵的大小为64；所述变换处理单元具体用于：根据如下公式从所述DCT2矩阵推导出所述DST4矩阵：
Figure PCTCN2019106383-appb-000006
其中，transMatrix表示所述DCT2矩阵，nTbs表示所述DST4矩阵的大小，0≤i≤nTbS–1，0≤j≤nTbS–1；偏移量64-nTbs表示列的偏移；偏移量
Figure PCTCN2019106383-appb-000007
表示行的偏移；(-1) j表示进行符号变换。
结合第四方面，在可能的实施方式中，所述变换矩阵对包括DCT2’矩阵；所述DCT2矩阵的大小为64；所述逆变换处理单元具体用于：根据如下公式从所述DCT2矩阵推导出所述DCT2’矩阵：
transMatrix[j][i×2 6-Log2(nTbs)]×x[j]；
其中，transMatrix表示所述DCT2矩阵，nTbs表示所述DCT2’的大小，0≤i≤nTbS–1，0≤j≤nTbS–1。
第五方面，本发明涉及解码视频流的装置，包含处理器和存储器。所述存储器存储指令，所述指令使得所述处理器执行根据第一方面或第一方面任何可能实施例的方法。
第六方面，本发明涉及视频编码的装置，包含处理器和存储器。所述存储器存储指令，所述指令使得所述处理器执行根据第二方面或第二方面任何可能实施例的方法。
第七方面，提出计算机可读存储介质，其上储存有指令，所述指令执行时，使得一个或多个处理器解码视频数据。所述指令使得所述一个或多个处理器执行根据第一方面或第一方面任何可能实施例的方法。
第八方面，提出计算机可读存储介质，其上储存有指令，所述指令执行时，使得一个或多个处理器编码视频数据。所述指令使得所述一个或多个处理器执行根据第二方面或第二方面任何可能实施例的方法。
第九方面，提出一种视频解码器，包括用于执行如第一方面或第一方面任何可能实施例的方法的执行电路。
第十方面，提出一种视频编码器，包括用于执行如第二方面或第二方面任何可能实施例的方法的执行电路。
第十一方面，本发明涉及包括程序代码的计算机程序，所述程序代码在计算机上运行时执行根据根据第一方面或第一方面任何可能实施例的方法。
第十二方面，本发明涉及包括程序代码的计算机程序，所述程序代码在计算机上运行时执行根据根据第二方面或第二方面任何可能实施例的方法。
在附图及以下说明中阐述一个或多个实施例的细节。其它特征、目的和优点通过说明书、附图以及权利要求是显而易见的。
附图说明
为了更清楚地说明本申请实施例或背景技术中的技术方案，下面将对本申请实施例或背景技术中所需要使用的附图进行说明。
图1是用于实现本发明实施例的视频编码系统实例的框图；
图2是示出用于实现本发明实施例的视频编码器实例结构的框图；
图3是示出用于实现本发明实施例的视频解码器实例结构的框图；
图4是绘示包含图2的编码器20和图3的解码器30
图5是绘示另一种编码装置或解码装置实例的框图；
图6是绘示HEVC中16×16 DCT2矩阵的蝶形快速算法电路实现示意图；
图7是绘示根据一实施例的32×32的反变换实现电路示意图；
图8是绘示根据一实施例的实现电路示意图；
图9是绘示根据一实施例的8x8 DCT2矩阵的反变换架构示意图；
图10是绘示根据一实施例的视频解码方法的流程图；
图11是绘示根据一实施例的视频编码方法的流程图。
以下如果没有关于相同参考符号的具体注释，相同的参考符号是指相同或至少功能上等效的特征。
具体实施方式
以下描述中，参考形成本公开一部分并以说明之方式示出本发明实施例的具体方面或可使用本发明实施例的具体方面的附图。应理解，本发明实施例可在其它方面中使用，并可包括附图中未描绘的结构或逻辑变化。因此，以下详细描述不应以限制性的意义来理解，且本发明的范围由所附权利要求书界定。
例如，应理解，结合所描述方法的揭示内容可以同样适用于用于执行所述方法的对应设备或系统，且反之亦然。例如，如果描述一个或多个具体方法步骤，则对应的设备可以包含如功能单元等一个或多个单元，来执行所描述的一个或多个方法步骤(例如，一个单元执行一个或多个步骤，或多个单元，其中每个都执行多个步骤中的一个或多个)，即使附图中未明确描述或说明这种一个或多个单元。另一方面，例如，如果基于如功能单元等一个或多个单元描述具体装置，则对应的方法可以包含一个步骤来执行一个或多个单元的功能性(例如，一个步骤执行一个或多个单元的功能性，或多个步骤，其中每个执行多个单元中一个或多个单元的功能性)，即使附图中未明确描述或说明这种一个或多个步骤。进一步，应理解的是，除非另外明确提出，本文中所描述的各示例性实施例和/或方面的特征可以相互组合。
视频编码通常是指处理形成视频或视频序列的图片序列。在视频编码领域，术语“图片(picture)”、“帧(frame)”或“图像(image)”可以用作同义词。本申请(或本公开)中使用的视频编码表示视频编码或视频解码。视频编码在源侧执行，通常包括处理(例如，通过压缩)原始视频图片以减少表示该视频图片所需的数据量(从而更高效地存储和/或传输)。视频解码在目的地侧执行，通常包括相对于编码器作逆处理，以重构视频图片。实施例涉及的视频图片(或总称为图片，下文将进行解释)“编码”应理解为涉及视频序列的“编码”或“解码”。编码部分和解码部分的组合也称为编解码(编码和解码)。
无损视频编码情况下，可以重构原始视频图片，即经重构视频图片具有与原始视频图片相同的质量(假设存储或传输期间没有传输损耗或其它数据丢失)。在有损视频编码情况下，通过例如量化执行进一步压缩，来减少表示视频图片所需的数据量，而解码器侧无法完全重构视频图片，即经重构视频图片的质量相比原始视频图片的质量较低或较差。
H.261的几个视频编码标准属于“有损混合型视频编解码”(即，将样本域中的空间和时间预测与变换域中用于应用量化的2D变换编码结合)。视频序列的每个图片通常分割成不重叠的块集合，通常在块层级上进行编码。换句话说，编码器侧通常在块(视频块)层级处理亦即编码视频，例如，通过空间(图片内)预测和时间(图片间)预测来产生预测块，从当前块(当前处理或待处理的块)减去预测块以获得残差块，在变换域变换残差块并量化残差块，以减少待传输(压缩)的数据量，而解码器侧将相对于编码器的逆处理部分应用于经编码或经压缩块，以重构用于表示的当前块。另外，编码器复制解码器处理循环，使得编码器和解码器生成相同的预测(例如帧内预测和帧间预测)和/或重构，用于处理亦即编码后续块。
如本文中所用，术语“块”可以为图片或帧的一部分。为便于描述，参考多用途视频编码(VVC：Versatile Video Coding)或由ITU-T视频编码专家组(Video Coding Experts Group，VCEG)和ISO/IEC运动图像专家组(Motion Picture Experts Group，MPEG)的视频编码联合工作组(Joint Collaboration Team on Video Coding，JCT-VC)开发的高效视频编码(High-Efficiency Video Coding，HEVC)描述本发明实施例。本领域普通技术人员理解本发明实施例不限于HEVC或VVC。可以指CU、PU和TU。在HEVC中，通过使用表示为编码树的四叉树结构将CTU拆分为多个CU。在CU层级处作出是否使用图片间(时间)或图片内(空间)预测对图片区域进行编码的决策。每个CU可以根据PU拆分类型进一步拆分为一个、两个或四个PU。一个PU内应用相同的预测过程，并在PU基础上将相关信息传输到解码器。在通过基于PU拆分类型应用预测过程获取残差块之后，可以根据类似于用于CU的编码树的其它四叉树结构将CU分割成变换单元(transform unit，TU)。在视频压缩技术最新的发展中，使用四叉树和二叉树(Quad-tree and binary tree，QTBT)分割帧来分割编码块。在QTBT块结构中，CU可以为正方形或矩形形状。在VVC中，编码树单元(coding tree unit，CTU)首先由四叉树结构分割。四叉树叶节点进一步由二进制树结构分割。二进制树叶节点称为编码单元(coding unit，CU)，所述分段用于预测和变换处理，无需其它任何分割。这表示CU、PU和TU在QTBT编码块结构中的块大小相同。同时，还提出与QTBT块结构一起使用多重分割，例如三叉树分割。
以下基于图1至4描述编码器20、解码器30和编码解码系统10、40的实施例(在基于图10更详细描述本发明实施例之前)。
图1为绘示示例性编码系统10的概念性或示意性框图，例如，可以利用本申请(本公开)技术的视频编码系统10。视频编码系统10的编码器20(例如，视频编码器20)和解码器30(例如，视频解码器30)表示可用于根据本申请中描述的各种实例执行用于视频编码或视频解码方法的技术的设备实例。如图1中所示，编码系统10包括源设备12，用于向例如解码经编码数据13的目的地设备14提供经编码数据13，例如，经编码图片13。
源设备12包括编码器20，另外亦即可选地，可以包括图片源16，例如图片预处理单元18的预处理单元18，以及通信接口或通信单元22。
图片源16可以包括或可以为任何类别的图片捕获设备，用于例如捕获现实世界图片，和/或任何类别的图片或评论(对于屏幕内容编码，屏幕上的一些文字也认为是待编码的图片或图像的一部分)生成设备，例如，用于生成计算机动画图片的计算机图形处理器，或用于获取和/或提供现实世界图片、计算机动画图片(例如，屏幕内容、虚拟现实(virtual reality，VR)图片)的任何类别设备，和/或其任何组合(例如，实景(augmented reality，AR)图片)。
(数字)图片为或者可以视为具有亮度值的采样点的二维阵列或矩阵。阵列中的采样点也可以称为像素(pixel)(像素(picture element)的简称)或像素(pel)。阵列或图片在水平和垂直方向(或轴线)上的采样点数目定义图片的尺寸和/或分辨率。为了表示颜色，通常采用三个颜色分量，即图片可以表示为或包含三个采样阵列。RBG格式或颜色空间中，图片包括对应的红色、绿色及蓝色采样阵列。但是，在视频编码中，每个像素通常以亮度/色度格式或颜色空间表示，例如，YCbCr，包括Y指示的亮度分量(有时也可以用L指示)以及Cb和Cr指示的两个色度分量。亮度(简写为luma)分量Y表示亮度或灰度水平强度(例如，在灰度等级图片中两者相同)，而两个色度(简写为chroma)分量Cb和Cr表示色度或颜色信息分量。相应地，YCbCr格式的图片包括亮度采样值(Y)的亮度采样阵列，和色度值(Cb和Cr)的两个色度采样阵列。RGB格式的图片可以转换或变换为YCbCr格式，反之亦然，该过程也称为色彩变换或转换。如果图片是黑白的，该图片可以只包括亮度采样阵列。
图片源16(例如，视频源16)可以为，例如用于捕获图片的相机，例如图片存储器的存储器，包括或存储先前捕获或产生的图片，和/或获取或接收图片的任何类别的(内部或外部)接口。相机可以为，例如，本地的或集成在源设备中的集成相机，存储器可为本地的或例如集成在源设备中的集成存储器。接口可以为，例如，从外部视频源接收图片的外部接口，外部视频源例如为外部图片捕获设备，比如相机、外部存储器或外部图片生成设备，外部图片生成设备例如为外部计算机图形处理器、计算机或服务器。接口可以为根据任何专有或标准化接口协议的任何类别的接口，例如有线或无线接口、光接口。获取图片数据17的接口可以是与通信接口22相同的接口或是通信接口22的一部分。
区别于预处理单元18和预处理单元18执行的处理，图片或图片数据17(例如，视频 数据16)也可以称为原始图片或原始图片数据17。
预处理单元18用于接收(原始)图片数据17并对图片数据17执行预处理，以获得经预处理的图片19或经预处理的图片数据19。例如，预处理单元18执行的预处理可以包括整修、色彩格式转换(例如，从RGB转换为YCbCr)、调色或去噪。可以理解，预处理单元18可以是可选组件。
编码器20(例如，视频编码器20)用于接收经预处理的图片数据19并提供经编码图片数据21(下文将进一步描述细节，例如，基于图2或图4)。
源设备12的通信接口22可以用于接收经编码图片数据21并传输至其它设备，例如，目的地设备14或任何其它设备，以用于存储或直接重构，或用于在对应地存储经编码数据13和/或传输经编码数据13至其它设备之前处理经编码图片数据21，其它设备例如为目的地设备14或任何其它用于解码或存储的设备。
目的地设备14包括解码器30(例如，视频解码器30)，另外亦即可选地，可以包括通信接口或通信单元28、后处理单元32和显示设备34。
目的地设备14的通信接口28用于例如，直接从源设备12或任何其它源接收经编码图片数据21或经编码数据13，任何其它源例如为存储设备，存储设备例如为经编码图片数据存储设备。
通信接口22和通信接口28可以用于藉由源设备12和目的地设备14之间的直接通信链路或藉由任何类别的网络传输或接收经编码图片数据21或经编码数据13，直接通信链路例如为直接有线或无线连接，任何类别的网络例如为有线或无线网络或其任何组合，或任何类别的私网和公网，或其任何组合。
通信接口22可以例如用于将经编码图片数据21封装成合适的格式，例如包，以在通信链路或通信网络上传输。
形成通信接口22的对应部分的通信接口28可以例如用于解封装经编码数据13，以获得经编码图片数据21。
通信接口22和通信接口28都可以配置为单向通信接口，如图1中用于经编码图片数据13的从源设备12指向目的地设备14的箭头所指示，或配置为双向通信接口，以及可以用于例如发送和接收消息来建立连接、确认和交换任何其它与通信链路和/或例如经编码图片数据传输的数据传输有关的信息。
解码器30用于接收经编码图片数据21并提供经解码图片数据31或经解码图片31(下文将进一步描述细节，例如，基于图3或图5)。
目的地设备14的后处理器32用于后处理经解码图片数据31(也称为经重构图片数据)，例如，经解码图片131，以获得经后处理图片数据33，例如，经后处理图片33。后处理单元32执行的后处理可以包括，例如，色彩格式转换(例如，从YCbCr转换为RGB)、调色、整修或重采样，或任何其它处理，用于例如准备经解码图片数据31以由显示设备34显示。
目的地设备14的显示设备34用于接收经后处理图片数据33以向例如用户或观看者显 示图片。显示设备34可以为或可以包括任何类别的用于呈现经重构图片的显示器，例如，集成的或外部的显示器或监视器。例如，显示器可以包括液晶显示器(liquid crystal display，LCD)、有机发光二极管(organic light emitting diode，OLED)显示器、等离子显示器、投影仪、微LED显示器、硅基液晶(liquid crystal on silicon，LCoS)、数字光处理器(digital light processor，DLP)或任何类别的其它显示器。
虽然图1将源设备12和目的地设备14绘示为单独的设备，但设备实施例也可以同时包括源设备12和目的地设备14或同时包括两者的功能性，即源设备12或对应的功能性以及目的地设备14或对应的功能性。在此类实施例中，可以使用相同硬件和/或软件，或使用单独的硬件和/或软件，或其任何组合来实施源设备12或对应的功能性以及目的地设备14或对应的功能性。
本领域技术人员基于描述明显可知，不同单元的功能性或图1所示的源设备12和/或目的地设备14的功能性的存在和(准确)划分可能根据实际设备和应用有所不同。
编码器20(例如，视频编码器20)和解码器30(例如，视频解码器30)都可以实施为各种合适电路中的任一个，例如，一个或多个微处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application-specific integrated circuit，ASIC)、现场可编程门阵列(field-programmable gate array，FPGA)、离散逻辑、硬件或其任何组合。如果部分地以软件实施所述技术，则设备可将软件的指令存储于合适的非暂时性计算机可读存储介质中，且可使用一或多个处理器以硬件执行指令从而执行本公开的技术。前述内容(包含硬件、软件、硬件与软件的组合等)中的任一者可视为一或多个处理器。视频编码器20和视频解码器30中的每一个可以包含在一或多个编码器或解码器中，所述编码器或解码器中的任一个可以集成为对应设备中的组合编码器/解码器(编解码器)的一部分。
源设备12可称为视频编码设备或视频编码装置。目的地设备14可称为视频解码设备或视频解码装置。源设备12以及目的地设备14可以是视频编码设备或视频编码装置的实例。
源设备12和目的地设备14可以包括各种设备中的任一个，包含任何类别的手持或静止设备，例如，笔记本或膝上型计算机、移动电话、智能电话、平板或平板计算机、摄像机、台式计算机、机顶盒、电视、显示设备、数字媒体播放器、视频游戏控制台、视频流式传输设备(例如内容服务服务器或内容分发服务器)、广播接收器设备、广播发射器设备等，并可以不使用或使用任何类别的操作系统。
在一些情况下，源设备12和目的地设备14可以经装备以用于无线通信。因此，源设备12和目的地设备14可以为无线通信设备。
在一些情况下，图1中所示视频编码系统10仅为示例，本申请的技术可以适用于不必包含编码和解码设备之间的任何数据通信的视频编码设置(例如，视频编码或视频解码)。在其它实例中，数据可从本地存储器检索、在网络上流式传输等。视频编码设备可以对数据进行编码并且将数据存储到存储器，和/或视频解码设备可以从存储器检索数据并且对数据进行解码。在一些实例中，由并不彼此通信而是仅编码数据到存储器和/或从存储器检索 数据且解码数据的设备执行编码和解码。
应理解，对于以上参考视频编码器20所描述的实例中的每一个，视频解码器30可以用于执行相反过程。关于信令语法元素，视频解码器30可以用于接收并解析这种语法元素，相应地解码相关视频数据。在一些例子中，视频编码器20可以将一个或多个定义……的语法元素熵编码成经编码视频比特流。在此类实例中，视频解码器30可以解析这种语法元素，并相应地解码相关视频数据。
编码器&编码方法
图2示出用于实现本申请(公开)技术的视频编码器20的实例的示意性/概念性框图。在图2的实例中，视频编码器20包括残差计算单元204、变换处理单元206、量化单元208、逆量化单元210、逆变换处理单元212、重构单元214、缓冲器216、环路滤波器单元220、经解码图片缓冲器(decoded picture buffer，DPB)230、预测处理单元260和熵编码单元270。预测处理单元260可以包含帧间预测单元244、帧内预测单元254和模式选择单元262。帧间预测单元244可以包含运动估计单元和运动补偿单元(未图示)。图2所示的视频编码器20也可以称为混合型视频编码器或根据混合型视频编解码器的视频编码器。
例如，残差计算单元204、变换处理单元206、量化单元208、预测处理单元260和熵编码单元270形成编码器20的前向信号路径，而例如逆量化单元210、逆变换处理单元212、重构单元214、缓冲器216、环路滤波器220、经解码图片缓冲器(decoded picture buffer，DPB)230、预测处理单元260形成编码器的后向信号路径，其中编码器的后向信号路径对应于解码器的信号路径(参见图3中的解码器30)。
编码器20通过例如输入202，接收图片201或图片201的块203，例如，形成视频或视频序列的图片序列中的图片。图片块203也可以称为当前图片块或待编码图片块，图片201可以称为当前图片或待编码图片(尤其是在视频编码中将当前图片与其它图片区分开时，其它图片例如同一视频序列亦即也包括当前图片的视频序列中的先前经编码和/或经解码图片)。
分割
编码器20的实施例可以包括分割单元(图2中未绘示)，用于将图片201分割成多个例如块203的块，通常分割成多个不重叠的块。分割单元可以用于对视频序列中所有图片使用相同的块大小以及定义块大小的对应栅格，或用于在图片或子集或图片群组之间更改块大小，并将每个图片分割成对应的块。
在一个实例中，视频编码器20的预测处理单元260可以用于执行上述分割技术的任何组合。
如图片201，块203也是或可以视为具有亮度值(采样值)的采样点的二维阵列或矩阵，虽然其尺寸比图片201小。换句话说，块203可以包括，例如，一个采样阵列(例如黑白图片201情况下的亮度阵列)或三个采样阵列(例如，彩色图片情况下的一个亮度阵列和两个色度阵列)或依据所应用的色彩格式的任何其它数目和/或类别的阵列。块203的水平和垂直方向(或轴线)上采样点的数目定义块203的尺寸。
如图2所示的编码器20用于逐块编码图片201，例如，对每个块203执行编码和预测。
残差计算
残差计算单元204用于基于图片块203和预测块265(下文提供预测块265的其它细节)计算残差块205，例如，通过逐样本(逐像素)将图片块203的样本值减去预测块265的样本值，以在样本域中获取残差块205。
变换
变换处理单元206用于在残差块205的样本值上应用例如离散余弦变换(discrete cosine transform，DCT)或离散正弦变换(discrete sine transform，DST)的变换，以在变换域中获取变换系数207。变换系数207也可以称为变换残差系数，并在变换域中表示残差块205。
变换处理单元206可以用于应用DCT/DST的整数近似值，例如为HEVC/H.265指定的变换。与正交DCT变换相比，这种整数近似值通常由某一因子按比例缩放。为了维持经正变换和逆变换处理的残差块的范数，应用额外比例缩放因子作为变换过程的一部分。比例缩放因子通常是基于某些约束条件选择的，例如，比例缩放因子是用于移位运算的2的幂、变换系数的位深度、准确性和实施成本之间的权衡等。例如，在解码器30侧通过例如逆变换处理单元212为逆变换(以及在编码器20侧通过例如逆变换处理单元212为对应逆变换)指定具体比例缩放因子，以及相应地，可以在编码器20侧通过变换处理单元206为正变换指定对应比例缩放因子。
量化
量化单元208用于例如通过应用标量量化或向量量化来量化变换系数207，以获得经量化变换系数209。经量化变换系数209也可以称为经量化残差系数209。量化过程可以减少与部分或全部变换系数207有关的位深度。例如，可在量化期间将n位变换系数向下舍入到m位变换系数，其中n大于m。可通过调整量化参数(quantization parameter，QP)修改量化程度。例如，对于标量量化，可以应用不同的标度来实现较细或较粗的量化。较小量化步长对应较细量化，而较大量化步长对应较粗量化。可以通过量化参数(quantization parameter，QP)指示合适的量化步长。例如，量化参数可以为合适的量化步长的预定义集合的索引。例如，较小的量化参数可以对应精细量化(较小量化步长)，较大量化参数可以对应粗糙量化(较大量化步长)，反之亦然。量化可以包含除以量化步长以及例如通过逆量化210执行的对应的量化或逆量化，或者可以包含乘以量化步长。根据例如HEVC的一些标准的实施例可以使用量化参数来确定量化步长。一般而言，可以基于量化参数使用包含除法的等式的定点近似来计算量化步长。可以引入额外比例缩放因子来进行量化和反量化，以恢复可能由于在用于量化步长和量化参数的等式的定点近似中使用的标度而修改的残差块的范数。在一个实例实施方式中，可以合并逆变换和反量化的标度。或者，可以使用自定义量化表并在例如比特流中将其从编码器通过信号发送到解码器。量化是有损操作，其中量化步长越大，损耗越大。
逆量化单元210用于在经量化系数上应用量化单元208的逆量化，以获得经反量化系数211，例如，基于或使用与量化单元208相同的量化步长，应用量化单元208应用的量化 方案的逆量化方案。经反量化系数211也可以称为经反量化残差系数211，对应于变换系数207，虽然由于量化造成的损耗通常与变换系数不相同。
逆变换处理单元212用于应用变换处理单元206应用的变换的逆变换，例如，逆离散余弦变换(discrete cosine transform，DCT)或逆离散正弦变换(discrete sine transform，DST)，以在样本域中获取逆变换块213。逆变换块213也可以称为逆变换经反量化块213或逆变换残差块213。
重构单元214(例如，求和器214)用于将逆变换块213(即经重构残差块213)添加至预测块265，以在样本域中获取经重构块215，例如，将经重构残差块213的样本值与预测块265的样本值相加。
可选地，例如线缓冲器216的缓冲器单元216(或简称“缓冲器”216)用于缓冲或存储经重构块215和对应的样本值，用于例如帧内预测。在其它的实施例中，编码器可以用于使用存储在缓冲器单元216中的未经滤波的经重构块和/或对应的样本值来进行任何类别的估计和/或预测，例如帧内预测。
例如，编码器20的实施例可以经配置以使得缓冲器单元216不只用于存储用于帧内预测254的经重构块215，也用于环路滤波器单元220(在图2中未示出)，和/或，例如使得缓冲器单元216和经解码图片缓冲器单元230形成一个缓冲器。其它实施例可以用于将经滤波块221和/或来自经解码图片缓冲器230的块或样本(图2中均未示出)用作帧内预测254的输入或基础。
环路滤波器单元220(或简称“环路滤波器”220)用于对经重构块215进行滤波以获得经滤波块221，从而顺利进行像素转变或提高视频质量。环路滤波器单元220旨在表示一个或多个环路滤波器，例如去块滤波器、样本自适应偏移(sample-adaptive offset，SAO)滤波器或其它滤波器，例如双边滤波器、自适应环路滤波器(adaptive loop filter，ALF)，或锐化或平滑滤波器，或协同滤波器。尽管环路滤波器单元220在图2中示出为环内滤波器，但在其它配置中，环路滤波器单元220可实施为环后滤波器。经滤波块221也可以称为经滤波的经重构块221。经解码图片缓冲器230可以在环路滤波器单元220对经重构编码块执行滤波操作之后存储经重构编码块。
编码器20(对应地，环路滤波器单元220)的实施例可以用于输出环路滤波器参数(例如，样本自适应偏移信息)，例如，直接输出或由熵编码单元270或任何其它熵编码单元熵编码后输出，例如使得解码器30可以接收并应用相同的环路滤波器参数用于解码。
经解码图片缓冲器(decoded picture buffer，DPB)230可以为存储参考图片数据供视频编码器20编码视频数据之用的参考图片存储器。DPB 230可由多种存储器设备中的任一个形成，例如动态随机存储器(dynamic random access memory，DRAM)(包含同步DRAM(synchronous DRAM，SDRAM)、磁阻式RAM(magnetoresistive RAM，MRAM)、电阻式RAM(resistive RAM，RRAM))或其它类型的存储器设备。可以由同一存储器设备或单独的存储器设备提供DPB 230和缓冲器216。在某一实例中，经解码图片缓冲器(decoded picture buffer，DPB)230用于存储经滤波块221。经解码图片缓冲器230可以进一步用于 存储同一当前图片或例如先前经重构图片的不同图片的其它先前的经滤波块，例如先前经重构和经滤波块221，以及可以提供完整的先前经重构亦即经解码图片(和对应参考块和样本)和/或部分经重构当前图片(和对应参考块和样本)，例如用于帧间预测。在某一实例中，如果经重构块215无需环内滤波而得以重构，则经解码图片缓冲器(decoded picture buffer，DPB)230用于存储经重构块215。
预测处理单元260，也称为块预测处理单元260，用于接收或获取块203(当前图片201的当前块203)和经重构图片数据，例如来自缓冲器216的同一(当前)图片的参考样本和/或来自经解码图片缓冲器230的一个或多个先前经解码图片的参考图片数据231，以及用于处理这类数据进行预测，即提供可以为经帧间预测块245或经帧内预测块255的预测块265。
模式选择单元262可以用于选择预测模式(例如帧内或帧间预测模式)和/或对应的用作预测块265的预测块245或255，以计算残差块205和重构经重构块215。
模式选择单元262的实施例可以用于选择预测模式(例如，从预测处理单元260所支持的那些预测模式中选择)，所述预测模式提供最佳匹配或者说最小残差(最小残差意味着传输或存储中更好的压缩)，或提供最小信令开销(最小信令开销意味着传输或存储中更好的压缩)，或同时考虑或平衡以上两者。模式选择单元262可以用于基于码率失真优化(rate distortion optimization，RDO)确定预测模式，即选择提供最小码率失真优化的预测模式，或选择相关码率失真至少满足预测模式选择标准的预测模式。
下文将详细解释编码器20的实例(例如，通过预测处理单元260)执行的预测处理和(例如，通过模式选择单元262)执行的模式选择。
如上文所述，编码器20用于从(预先确定的)预测模式集合中确定或选择最好或最优的预测模式。预测模式集合可以包括例如帧内预测模式和/或帧间预测模式。
帧内预测模式集合可以包括35种不同的帧内预测模式，例如，如DC(或均值)模式和平面模式的非方向性模式，或如H.265中定义的方向性模式，或者可以包括67种不同的帧内预测模式，例如，如DC(或均值)模式和平面模式的非方向性模式，或如正在发展中的H.266中定义的方向性模式。
(可能的)帧间预测模式集合取决于可用参考图片(即，例如前述存储在DBP 230中的至少部分经解码图片)和其它帧间预测参数，例如取决于是否使用整个参考图片或只使用参考图片的一部分，例如围绕当前块的区域的搜索窗区域，来搜索最佳匹配参考块，和/或例如取决于是否应用如半像素和/或四分之一像素内插的像素内插。
除了以上预测模式，也可以应用跳过模式和/或直接模式。
预测处理单元260可以进一步用于将块203分割成较小的块分区或子块，例如，通过迭代使用四叉树(quad-tree，QT)分割、二叉树(binary-tree，BT)分割或三叉树(triple-tree or ternary-tree，TT)分割，或其任何组合，以及用于例如为块分区或子块中的每一个执行预测，其中模式选择包括选择分割的块203的树结构和选择应用于块分区或子块中的每一个的预测模式。
帧间预测单元244可以包含运动估计(motion estimation，ME)单元(图2中未示出)和运动补偿(motion compensation，MC)单元(图2中未示出)。运动估计单元用于接收或获取图片块203(当前图片201的当前图片块203)和经解码图片231，或至少一个或多个先前经重构块，例如，一个或多个其它/不同先前经解码图片231的经重构块，来进行运动估计。例如，视频序列可以包括当前图片和先前经解码图片31，或换句话说，当前图片和先前经解码图片31可以是形成视频序列的图片序列的一部分，或者形成该图片序列。
例如，编码器20可以用于从多个其它图片中的同一或不同图片的多个参考块中选择参考块，并向运动估计单元(图2中未示出)提供参考图片(或参考图片索引)和/或提供参考块的位置(X、Y坐标)与当前块的位置之间的偏移(空间偏移)作为帧间预测参数。该偏移也称为运动向量(motion vector，MV)。
运动补偿单元用于获取，例如接收帧间预测参数，并基于或使用帧间预测参数执行帧间预测来获取帧间预测块245。由运动补偿单元(图2中未示出)执行的运动补偿可以包含基于通过运动估计(可能执行对子像素精确度的内插)确定的运动/块向量取出或生成预测块。内插滤波可从已知像素样本产生额外像素样本，从而潜在地增加可用于编码图片块的候选预测块的数目。一旦接收到用于当前图片块的PU的运动向量，运动补偿单元246可以在一个参考图片列表中定位运动向量指向的预测块。运动补偿单元246还可以生成与块和视频条带相关联的语法元素，以供视频解码器30在解码视频条带的图片块时使用。
帧内预测单元254用于获取，例如接收同一图片的图片块203(当前图片块)和一个或多个先前经重构块，例如经重构相邻块，以进行帧内估计。例如，编码器20可以用于从多个(预定)帧内预测模式中选择帧内预测模式。
编码器20的实施例可以用于基于优化标准选择帧内预测模式，例如基于最小残差(例如，提供最类似于当前图片块203的预测块255的帧内预测模式)或最小码率失真。
帧内预测单元254进一步用于基于如所选择的帧内预测模式的帧内预测参数确定帧内预测块255。在任何情况下，在选择用于块的帧内预测模式之后，帧内预测单元254还用于向熵编码单元270提供帧内预测参数，即提供指示所选择的用于块的帧内预测模式的信息。在一个实例中，帧内预测单元254可以用于执行下文描述的帧内预测技术的任意组合。
熵编码单元270用于将熵编码算法或方案(例如，可变长度编码(variable length coding，VLC)方案、上下文自适应VLC(context adaptive VLC，CAVLC)方案、算术编码方案、上下文自适应二进制算术编码(context adaptive binary arithmetic coding，CABAC)、基于语法的上下文自适应二进制算术编码(syntax-based context-adaptive binary arithmetic coding，SBAC)、概率区间分割熵(probability interval partitioning entropy，PIPE)编码或其它熵编码方法或技术)应用于经量化残差系数209、帧间预测参数、帧内预测参数和/或环路滤波器参数中的单个或所有上(或不应用)，以获得可以通过输出272以例如经编码比特流21的形式输出的经编码图片数据21。可以将经编码比特流传输到视频解码器30，或将其存档稍后由视频解码器30传输或检索。熵编码单元270还可用于熵编码正被编码的当前视频条带的其它语法元素。
视频编码器20的其它结构变型可用于编码视频流。例如，基于非变换的编码器20可以在没有针对某些块或帧的变换处理单元206的情况下直接量化残差信号。在另一实施方式中，编码器20可具有组合成单个单元的量化单元208和逆量化单元210。
图3示出示例性视频解码器30，用于实现本申请的技术。视频解码器30用于接收例如由编码器20编码的经编码图片数据(例如，经编码比特流)21，以获得经解码图片231。在解码过程期间，视频解码器30从视频编码器20接收视频数据，例如表示经编码视频条带的图片块的经编码视频比特流及相关联的语法元素。
在图3的实例中，解码器30包括熵解码单元304、逆量化单元310、逆变换处理单元312、重构单元314(例如求和器314)、缓冲器316、环路滤波器320、经解码图片缓冲器330以及预测处理单元360。预测处理单元360可以包含帧间预测单元344、帧内预测单元354和模式选择单元362。在一些实例中，视频解码器30可执行大体上与参照图2的视频编码器20描述的编码遍次互逆的解码遍次。
熵解码单元304用于对经编码图片数据21执行熵解码，以获得例如经量化系数309和/或经解码的编码参数(图3中未示出)，例如，帧间预测、帧内预测参数、环路滤波器参数和/或其它语法元素中(经解码)的任意一个或全部。熵解码单元304进一步用于将帧间预测参数、帧内预测参数和/或其它语法元素转发至预测处理单元360。视频解码器30可接收视频条带层级和/或视频块层级的语法元素。
逆量化单元310功能上可与逆量化单元110相同，逆变换处理单元312功能上可与逆变换处理单元212相同，重构单元314功能上可与重构单元214相同，缓冲器316功能上可与缓冲器216相同，环路滤波器320功能上可与环路滤波器220相同，经解码图片缓冲器330功能上可与经解码图片缓冲器230相同。
预测处理单元360可以包括帧间预测单元344和帧内预测单元354，其中帧间预测单元344功能上可以类似于帧间预测单元244，帧内预测单元354功能上可以类似于帧内预测单元254。预测处理单元360通常用于执行块预测和/或从经编码数据21获取预测块365，以及从例如熵解码单元304(显式地或隐式地)接收或获取预测相关参数和/或关于所选择的预测模式的信息。
当视频条带经编码为经帧内编码(I)条带时，预测处理单元360的帧内预测单元354用于基于信号表示的帧内预测模式及来自当前帧或图片的先前经解码块的数据来产生用于当前视频条带的图片块的预测块365。当视频帧经编码为经帧间编码(即B或P)条带时，预测处理单元360的帧间预测单元344(例如，运动补偿单元)用于基于运动向量及从熵解码单元304接收的其它语法元素生成用于当前视频条带的视频块的预测块365。对于帧间预测，可从一个参考图片列表内的一个参考图片中产生预测块。视频解码器30可基于存储于DPB 330中的参考图片，使用默认建构技术来建构参考帧列表：列表0和列表1。
预测处理单元360用于通过解析运动向量和其它语法元素，确定用于当前视频条带的视频块的预测信息，并使用预测信息产生用于正经解码的当前视频块的预测块。例如，预测处理单元360使用接收到的一些语法元素确定用于编码视频条带的视频块的预测模式 (例如，帧内或帧间预测)、帧间预测条带类型(例如，B条带、P条带或GPB条带)、用于条带的参考图片列表中的一个或多个的建构信息、用于条带的每个经帧间编码视频块的运动向量、条带的每个经帧间编码视频块的帧间预测状态以及其它信息，以解码当前视频条带的视频块。
逆量化单元310可用于逆量化(即，反量化)在比特流中提供且由熵解码单元304解码的经量化变换系数。逆量化过程可包含使用由视频编码器20针对视频条带中的每一视频块所计算的量化参数来确定应该应用的量化程度并同样确定应该应用的逆量化程度。
逆变换处理单元312用于将逆变换(例如，逆DCT、逆整数变换或概念上类似的逆变换过程)应用于变换系数，以便在像素域中产生残差块。
重构单元314(例如，求和器314)用于将逆变换块313(即经重构残差块313)添加到预测块365，以在样本域中获取经重构块315，例如通过将经重构残差块313的样本值与预测块365的样本值相加。
环路滤波器单元320(在编码循环期间或在编码循环之后)用于对经重构块315进行滤波以获得经滤波块321，从而顺利进行像素转变或提高视频质量。在一个实例中，环路滤波器单元320可以用于执行下文描述的滤波技术的任意组合。环路滤波器单元320旨在表示一个或多个环路滤波器，例如去块滤波器、样本自适应偏移(sample-adaptive offset，SAO)滤波器或其它滤波器，例如双边滤波器、自适应环路滤波器(adaptive loop filter，ALF)，或锐化或平滑滤波器，或协同滤波器。尽管环路滤波器单元320在图3中示出为环内滤波器，但在其它配置中，环路滤波器单元320可实施为环后滤波器。
随后将给定帧或图片中的经解码视频块321存储在存储用于后续运动补偿的参考图片的经解码图片缓冲器330中。
解码器30用于例如，藉由输出332输出经解码图片31，以向用户呈现或供用户查看。
视频解码器30的其它变型可用于对压缩的比特流进行解码。例如，解码器30可以在没有环路滤波器单元320的情况下生成输出视频流。例如，基于非变换的解码器30可以在没有针对某些块或帧的逆变换处理单元312的情况下直接逆量化残差信号。在另一实施方式中，视频解码器30可以具有组合成单个单元的逆量化单元310和逆变换处理单元312。
图4是根据一示例性实施例的包含图2的编码器20和/或图3的解码器30的视频编码系统40的实例的说明图。系统40可以实现本申请的各种技术的组合。在所说明的实施方式中，视频编码系统40可以包含成像设备41、视频编码器20、视频解码器30(和/或藉由处理单元46的逻辑电路47实施的视频编码器)、天线42、一个或多个处理器43、一个或多个存储器44和/或显示设备45。
如图所示，成像设备41、天线42、处理单元46、逻辑电路47、视频编码器20、视频解码器30、处理器43、存储器44和/或显示设备45能够互相通信。如所论述，虽然用视频编码器20和视频解码器30绘示视频编码系统40，但在不同实例中，视频编码系统40可以只包含视频编码器20或只包含视频解码器30。
在一些实例中，如图所示，视频编码系统40可以包含天线42。例如，天线42可以用 于传输或接收视频数据的经编码比特流。另外，在一些实例中，视频编码系统40可以包含显示设备45。显示设备45可以用于呈现视频数据。在一些实例中，如图所示，逻辑电路47可以通过处理单元46实施。处理单元46可以包含专用集成电路(application-specific integrated circuit，ASIC)逻辑、图形处理器、通用处理器等。视频编码系统40也可以包含可选处理器43，该可选处理器43类似地可以包含专用集成电路(application-specific integrated circuit，ASIC)逻辑、图形处理器、通用处理器等。在一些实例中，逻辑电路47可以通过硬件实施，如视频编码专用硬件等，处理器43可以通过通用软件、操作系统等实施。另外，存储器44可以是任何类型的存储器，例如易失性存储器(例如，静态随机存取存储器(Static Random Access Memory，SRAM)、动态随机存储器(Dynamic Random Access Memory，DRAM)等)或非易失性存储器(例如，闪存等)等。在非限制性实例中，存储器44可以由超速缓存内存实施。在一些实例中，逻辑电路47可以访问存储器44(例如用于实施图像缓冲器)。在其它实例中，逻辑电路47和/或处理单元46可以包含存储器(例如，缓存等)用于实施图像缓冲器等。
在一些实例中，通过逻辑电路实施的视频编码器20可以包含(例如，通过处理单元46或存储器44实施的)图像缓冲器和(例如，通过处理单元46实施的)图形处理单元。图形处理单元可以通信耦合至图像缓冲器。图形处理单元可以包含通过逻辑电路47实施的视频编码器20，以实施参照图2和/或本文中所描述的任何其它编码器系统或子系统所论述的各种模块。逻辑电路可以用于执行本文所论述的各种操作。
视频解码器30可以以类似方式通过逻辑电路47实施，以实施参照图3的解码器30和/或本文中所描述的任何其它解码器系统或子系统所论述的各种模块。在一些实例中，逻辑电路实施的视频解码器30可以包含(通过处理单元2820或存储器44实施的)图像缓冲器和(例如，通过处理单元46实施的)图形处理单元。图形处理单元可以通信耦合至图像缓冲器。图形处理单元可以包含通过逻辑电路47实施的视频解码器30，以实施参照图3和/或本文中所描述的任何其它解码器系统或子系统所论述的各种模块。
在一些实例中，视频编码系统40的天线42可以用于接收视频数据的经编码比特流。如所论述，经编码比特流可以包含本文所论述的与编码视频帧相关的数据、指示符、索引值、模式选择数据等，例如与编码分割相关的数据(例如，变换系数或经量化变换系数，(如所论述的)可选指示符，和/或定义编码分割的数据)。视频编码系统40还可包含耦合至天线42并用于解码经编码比特流的视频解码器30。显示设备45用于呈现视频帧。
图5是根据一示例性实施例的可用作图1中的源设备12和目的地设备14中的任一个或两个的装置500的简化框图。装置500可以实现本申请的技术，装置500可以采用包含多个计算设备的计算系统的形式，或采用例如移动电话、平板计算机、膝上型计算机、笔记本电脑、台式计算机等单个计算设备的形式。
装置500中的处理器502可以为中央处理器。或者，处理器502可以为现有的或今后将研发出的能够操控或处理信息的任何其它类型的设备或多个设备。如图所示，虽然可以使用例如处理器502的单个处理器实践所揭示的实施方式，但是使用一个以上处理器可以实现速度和效率方面的优势。
在一实施方式中，装置500中的存储器504可以为只读存储器(Read Only Memory，ROM)设备或随机存取存储器(random access memory，RAM)设备。任何其他合适类型的存储设备都可以用作存储器504。存储器504可以包括代码和由处理器502使用总线512访问的数据506。存储器504可进一步包括操作系统508和应用程序510，应用程序510包含至少一个准许处理器502执行本文所描述的方法的程序。例如，应用程序510可以包括应用1到N，应用1到N进一步包括执行本文所描述的方法的视频编码应用。装置500还可包含采用从存储器514形式的附加存储器，该从存储器514例如可以为与移动计算设备一起使用的存储卡。因为视频通信会话可能含有大量信息，这些信息可以整体或部分存储在从存储器514中，并按需要加载到存储器504用于处理。
装置500还可包含一或多个输出设备，例如显示器518。在一个实例中，显示器518可以为将显示器和可操作以感测触摸输入的触敏元件组合的触敏显示器。显示器518可以通过总线512耦合于处理器502。除了显示器518还可以提供其它准许用户对装置500编程或以其它方式使用装置500的输出设备，或提供其它输出设备作为显示器518的替代方案。当输出设备是显示器或包含显示器时，显示器可以以不同方式实现，包含通过液晶显示器(liquid crystal display，LCD)、阴极射线管(cathode-ray tube，CRT)显示器、等离子显示器或发光二极管(light emitting diode，LED)显示器，如有机LED(organic LED，OLED)显示器。
装置500还可包含图像感测设备520或与其连通，图像感测设备520例如为相机或为现有的或今后将研发出的可以感测图像的任何其它图像感测设备520，所述图像例如为运行装置500的用户的图像。图像感测设备520可以放置为直接面向运行装置500的用户。在一实例中，可以配置图像感测设备520的位置和光轴以使其视野包含紧邻显示器518的区域且从该区域可见显示器518。
装置500还可包含声音感测设备522或与其连通，声音感测设备522例如为麦克风或为现有的或今后将研发出的可以感测装置500附近的声音的任何其它声音感测设备。声音感测设备522可以放置为直接面向运行装置500的用户，并可以用于接收用户在运行装置500时发出的声音，例如语音或其它发声。
虽然图5中将装置500的处理器502和存储器504绘示为集成在单个单元中，但是还可以使用其它配置。处理器502的运行可以分布在多个可直接耦合的机器中(每个机器具有一个或多个处理器)，或分布在本地区域或其它网络中。存储器504可以分布在多个机器中，例如基于网络的存储器或多个运行装置500的机器中的存储器。虽然此处只绘示单个总线，但装置500的总线512可以由多个总线形成。进一步地，从存储器514可以直接耦合至装置500的其它组件或可以通过网络访问，并且可包括单个集成单元，例如一个存储卡，或多个单元，例如多个存储卡。因此，可以以多种配置实施装置500。
在通用视频编码(VVC：versatile video coding)标准草案2.0中，除了传统的离散余弦变换2(DCT2：Discrete Cosine Transform 2)变换核外，还引入了两种新的变换核，即DCT8和离散正弦变换7(DST7：Discrete Sine Transform)。如表1所示，为这些变换核对应的基函数，他们呈现不同的分布特性。
表1 DCT和DST变换基函数
Figure PCTCN2019106383-appb-000008
对于预测残差，由于不同的预测模式具有不同的残差特性，因此，采用多核变换技术多核变换选择(MTS：multiple transform selection)可以充分利用不同变换矩阵的特性来较好适应这些残差特性，从而实现提升编码压缩性能的目的。
在确定了变换核后，可以根据变换核对应的基函数获取对应的变换矩阵，例如DCT2矩阵，DST7矩阵，DCT8矩阵等等。
在VVC标准草案测试模型(VTM2.0)JVET-K1002中的MTS方案如表2所示：
表2一种MTS方案
Figure PCTCN2019106383-appb-000009
表中A、B表示变换矩阵，A＝DST7矩阵；B＝DCT8矩阵。变换尺寸(变换矩阵大小)包括：4x4,8x8,16x16,32x32。水平方向/垂直方向的变换矩阵可以组合出4种变换矩阵对，分别对应不同的编号index。这些index写入码流，告知解码器采用哪组变换矩阵对。
以表2所示的MTS方案为例，在编码端进行变换处理时，遍历表2中的4组变换矩阵对，利用每组变换矩阵对对预测残差块进行水平和垂直变换，挑选rate-distortion cost最小的变换 矩阵对，并将该变换矩阵对的index写入码流。其中，在确定了对应的变换矩阵对后(假设为index 1对应的变换矩阵对)，利用变换矩阵AH和B对预测残差块R进行变换(即矩阵相乘)得到变换系数块F。
F＝B*R*A’
然后将系数块F进行熵编码写入码流。
在解码端进行反变换处理时，解码获得变换矩阵对的index确定需要采用的变换矩阵对，并利用该变换矩阵对对解码获得的系数块进行垂直和水平方向的反变换，得到预测残差块(重建残差块)。具体地，利用A矩阵和B矩阵对解码获得的变换系数块F进行反变换(即矩阵相乘)得到残差块R。
R＝B’*F*A
其中，A’表示A矩阵的转置矩阵，B’表示B矩阵的转置矩阵，由于A矩阵和B矩阵都为正交矩阵，转置相当于求逆矩阵。
其中，矩阵乘法在电路实现时，一般采用蝶形快速算法(partial butterfly)，从而可以利用矩阵系数的对称性，减少所需乘法的次数。但是DST7和DCT8变换，并不存在类似DCT2变换的蝶形快速算法(partial butterfly)；因此只能用矩阵乘法，计算复杂度(如乘法次数)高。同时，DST7和DCT8的变换矩阵的系数需要存储，考虑到不同尺寸，需要存储的系数数量高达2*(4x4+8x8+16x16+32x32)＝2720。
需要指出的是，除了上述变换矩阵A,B外，VVC标准草案还利用了DCT2矩阵作为变换矩阵，尺寸大小包括4x4～128x128。
在另一种实现方式中，提出了一种MTS的简化方案，如表3所示：
表3另一种MTS方案
Figure PCTCN2019106383-appb-000010
其中，C＝DST4矩阵；D＝DCT4矩阵，即利用DST4矩阵和DCT4矩阵替换现有技术2中的DST7矩阵和DCT8矩阵。DST4和DCT4具有相近的变换核基函数特性，具体的变换基函数如表4。
表4 DCT4和DST4变换基函数
Figure PCTCN2019106383-appb-000011
在确定了变换核为DST4和DCT4后，可以根据变换核对应的基函数获取对应的变换矩阵，即DST4矩阵和DCT4矩阵。
基于表1和表4的基函数，可以获得如下的变换矩阵示例：
表5 8x8 DCT2变换矩阵示例
Figure PCTCN2019106383-appb-000012
表6 4x4 DCT2变换矩阵示例
Figure PCTCN2019106383-appb-000013
表7 4x4 DCT4变换矩阵示例
Figure PCTCN2019106383-appb-000014
表8 4x4 DST4变换矩阵示例
Figure PCTCN2019106383-appb-000015
从上面各个变换矩阵可以看出来，8X8 DCT2矩阵的系数中包含了4X4 DCT2矩阵(如表5中加粗斜体部分系数与表6系数相同)和4X4 DCT4矩阵(如表5中加下划线部分系数与表7系数相同)的所有系数。再由表7和表8可以看出，DST4矩阵可用通过对DCT4矩阵进行镜像(FLIP)和符号变换获得。
为了验证表3描述的MTS算法与表2描述的MTS算法之间的效果，在VVC参考软件VTM-2.0平台上对表3描述的MTS算法进行了性能测试，对比表2描述的MTS算法获得的测试数据如表9和表10所示。
表9表3描述的MTS算法在AI测试条件下的数据
Figure PCTCN2019106383-appb-000016
表10表3描述的MTS算法在RA测试条件下的数据
Figure PCTCN2019106383-appb-000017
表中数值表示在相同视频图像质量下编码比特的增加的百分比。Class X(A1,A2,B,C,或者E)表示测试视频序列，Y，U/V分别表示视频图像的亮度和色度分量，EncT和DecT分别表示编码和解码时间。测试条件AI表示All Intra，测试条件RA表示random access。
图6描述了HEVC中16×16 DCT2矩阵的蝶形快速算法电路实现，从图6可以看出，16×16 DCT2矩阵的蝶形快速算法电路中包括了4×4 DCT2矩阵，8×8 DCT2矩阵，4×4 DCT4矩阵以及8×8 DCT4矩阵的实现电路，也就是说，在实现4×4 DCT2矩阵，8×8 DCT2矩阵，4×4 DCT4矩阵以及8×8 DCT4矩阵的变换时可以直接复用16×16 DCT2矩阵的电路实现；但是只有4×4 DCT2矩阵和8×8 DCT2矩阵可以复用蝶形快速算法电路，而4×4 DCT4矩阵以及8×8 DCT4矩阵的实现虽然能够复用16×16 DCT2矩阵的实现电路，但是并没有使用蝶形快速算法。
为了进一步降低MTS的实现复杂度，同时减少性能损失，本发明一个实施例提供的一 种MTS的实现方案如表11所示。
表11一种MTS实现方案
Figure PCTCN2019106383-appb-000018
其中，C＝DST4矩阵,E＝DCT2’矩阵，DCT2’矩阵即DCT2矩阵的转置矩阵，符号“’”表示转置。实际上，DCT2矩阵的转置矩阵与DCT3矩阵一致。
其中，4×4 DST4矩阵的一种实现示例如表8所示。4×4 DCT2’矩阵的一种实现示例如表12所示。
表12 4×4 DCT2’变换矩阵示例
Figure PCTCN2019106383-appb-000019
对比表11和表3可以看出，表9利用DCT2’矩阵替换了表3中的DCT4矩阵。考虑到为DCT2’矩阵的变换/反变换实现时存在蝶形快速算法，因此可以进一步简化变换/反变换的实现。同时，在电路实现上仍可以复用DCT2矩阵对应的变换/反变换实现电路。而对于DST4矩阵的实现，如前面所示，DST4矩阵经过FLIP、符号变换等操作即可复用2Nx2N DCT2矩阵变换/反变换实现电路。
为了验证表11的MTS方案的效果，发明人在VVC参考软件VTM-2.0.1平台上对表11的技术方案进行了性能测试，相对于表2的MTS方案的编解码压缩性能如表13和表14所示。
表13
Figure PCTCN2019106383-appb-000020
表14
Figure PCTCN2019106383-appb-000021
从表13和表14可以看出，相比于表2描述的MTS方案，表11描述的MTS方案的平均编码比特率增加的微乎其微(在Y下，AI测试条件下编码比特增加0.01％，RA测试条件下编码比特增加0.02％)，也就是说对编码压缩性能的影响几乎可以忽略，但是该方案利用了蝶形快速算法，能够简化变换/反变换的实现，如表中数据显示，编码时间有2％-4％的节省，解码时间也有一定的节省。同时，所使用的变换矩阵的系数可以简便地从2Nx2N DCT2矩阵中导出，不需要额外的存储空间；并且，所使用的变换矩阵的实现电路可以复用2Nx2N DCT2矩阵对应的变换/反变换实现电路，能够简化编解码器的实现电路的设计。
其中，为了明确本发明实施例中的变换矩阵的实现电路可以可以复用2Nx2N DCT2矩阵对应的变换/反变换实现电路，如下对电路复用进行具体的描述。例如，文献Core Transform Design in the High Efficiency Video Coding(HEVC)Standard所揭示的反变换电路的partial butterfly快速实现方法。DCT2矩阵反变换的实现，可以分解成EVEN、ODD和ADDSUB三个模块，其中EVEN表示利用由DCT2矩阵奇数行系数组成的矩阵进行列变换，ODD表示利用由DCT2矩阵偶数行系数组成的矩阵进行列变换，ADDSUB表示加减模块。
例如，图7描述了32×32的反变换实现电路，其中，Even4模块,Odd4模块以及Addsub4模块组成了4×4矩阵的反变换实现电路701；4×4矩阵的反变换实现电路701，Odd8模块以及Addsub8模块组成了8×8矩阵的反变换实现电路702；8×8矩阵的反变换实现电路702，Odd16模块以及Addsub16模块组成了16×16矩阵的反变换实现电路703；16×16矩阵的反变换电路实现703，Odd16模块以及Addsub16模块组成了32×32矩阵的反变换实现电路704。
图8描述了一种实现电路，如图8所示，Even4模块和Odd4模块的矩阵乘法电路可以被变换电路和反变换电路共享。
图9描述了8x8 DCT2矩阵的反变换架构，其中d n表示32x32 DCT2矩阵中的第n-th行第0列的系数，图9具体描述了EVEN模块实现和ODD模块实现矩阵乘法运算的内部结构。其中EVEN8和ODD8矩阵可以从2Nx2N DCT2矩阵获得。
具体地，8x8 DCT2矩阵如表15所示：
表15 8x8 DCT2矩阵
Figure PCTCN2019106383-appb-000022
Figure PCTCN2019106383-appb-000023
其中，4x4 EVEN8变换矩阵可以按照如下步骤获取：
获取从表15所示的8x8 DCT2矩阵的左半部分抽取奇数列系数(如表15中框起来的系数)，组成如表16所示的4x4矩阵:
表16 4x4矩阵
Figure PCTCN2019106383-appb-000024
再对表16的矩阵进行转置，即可获得如表17所示的4x4变换矩阵EVEN8。其中，EVEN8矩阵实际上是DCT2’矩阵。
表17 4x4 EVEN8变换矩阵
Figure PCTCN2019106383-appb-000025
其中，4x4 ODD8变换矩阵可以按照如下步骤获取：
获取从表15所示的8x8 DCT2矩阵的右半部分抽取偶数列系数(如表15中加下划线的系数)，组成如表18所示的4x4矩阵:
表18 4x4矩阵
Figure PCTCN2019106383-appb-000026
再对表18的矩阵进行转置或符号变换处理，即可获得如表19所示的4x4变换矩阵ODD8。其中，ODD8矩阵实际上DST4矩阵变形，例如可以对DST4矩阵进行符号变换，具体是对DST4矩阵的奇数列系数的负号进行取反即可获得ODD8矩阵。
表19 4x4 ODD8变换矩阵
Figure PCTCN2019106383-appb-000027
Figure PCTCN2019106383-appb-000028
从上面的描述可以看出，对于NxN的变换矩阵，可以从2Nx2N的DCT2矩阵中推导获得。因此只需要存储一个64x64的DCT2矩阵系数，即可推导获得32x32,16x16,8x8,4x4,2x2的矩阵系数。因此，并不需要额外的存储空间来存储32x32,16x16,8x8,4x4,2x2的矩阵系数。
通过比较表12和表16可知，表12和表16是一样的，也就是说4×4 DCT2’变换矩阵可以直接从8x8 DCT2矩阵推导出来，因此4×4 DCT2’变换矩阵的实现电路也包含在了2Nx2N DCT2的变换/反变换实现电路中，因此4×4 DCT2’变换矩阵的实现可以直接复用2Nx2N DCT2的实现电路。
再比较表8和表19可知，只需要对表8描述的矩阵进行符号变换(奇数列系数符号取反)即可获得表19所示的变换矩阵，即4x4 DST4矩阵可以直接从8x8 DCT2矩阵推导出来，因此4×4 DST4矩阵的实现电路也包含在了2Nx2N DCT2矩阵的变换/反变换实现电路中，因此4×4 DST4矩阵的实现可以直接复用2Nx2N DCT2的实现电路。
为了进一步降低MTS的实现复杂度，同时减少性能损失，本发明一个实施例提供的一种MTS的实现方案如表20所示。
表20一种MTS实现方案
Figure PCTCN2019106383-appb-000029
其中，C＝DST4矩阵,E＝DCT2’矩阵。其中，上面的变形可以是对矩阵按行或列进行符号变换(例如取反操作)。
针对不同的2Nx2N DCT2矩阵的电路实现，为达到复用电路的目的，对C矩阵和E矩阵的变形要求会有所不同。例如，在表3描述的MTS方案中提到，DST4矩阵要通过FLIP和符号变换处理(变成DCT4矩阵)来复用2Nx2N DCT2矩阵的实现电路；而在表11描述的MTS方案中提到，2Nx2N DCT2矩阵的实现电路实际上包含有0DD8矩阵，而DST4矩阵只需经过符号变换即可变成ODD8矩阵以实现复用。多种C矩阵和E矩阵的变形，可以更好适配不同的2Nx2N DCT2矩阵的实现电路，从而简化电路复用。
此外，某些C矩阵和E矩阵的变形，可以直接从2Nx2N DCT2矩阵中推导出，从而可以简化C矩阵和E矩阵的系数的导出过程。
作为一个例子，C矩阵的一种变形可以是对C矩阵的奇数行进行取反，得到如表21所示的：
表21 C矩阵的变形矩阵系数示例
Figure PCTCN2019106383-appb-000030
Figure PCTCN2019106383-appb-000031
通过比较表21和表19可知，表21和表19是一样的，可以直接从8x8 DCT2矩阵的系数中导出，无需任何附加操作，因此可以进一步简化C的变形矩阵的导出过程。同时，由于C的变形矩阵可以直接从2Nx2N DCT2矩阵中推导出，因此可以适配不同的2Nx2N DCT2矩阵的电路以实现简化电路复用，同时确保对编码压缩性能影响小。
为了验证表20的MTS方案的效果，发明人在VVC参考软件VTM-2.0.1平台上对表20的技术方案进行了性能测试，相对于表2的MTS方案的编解码压缩性能如表22和表23所示。
表22
Figure PCTCN2019106383-appb-000032
表23
Figure PCTCN2019106383-appb-000033
从表13和表14可以看出，相比于表2描述的MTS方案，表11描述的MTS方案的平均编码比特率增加的微乎其微(在Y下，AI测试条件下编码比特增加0.06％，RA测试条件下编码比特增加0.08％)，也就是说对编码压缩性能的影响几乎可以忽略，但是该方案利用了蝶形快速算法，能够简化变换/反变换的实现。同时，所使用的变换矩阵的矩阵系数可以直接地从2Nx2N DCT2矩阵中导出，不需要额外的存储空间；并且，所使用的变换矩阵的实现电路可以直接复用2Nx2N DCT2矩阵对应的变换/反变换实现电路，能够简化编解码器的实现电路的设计。
本发明另一个实施例提供的一种MTS的实现方案如表24所示。
表24一种MTS实现方案
Figure PCTCN2019106383-appb-000034
其中，C＝DST4矩阵,E＝DCT2’矩阵。其中，上面的变形可以是对矩阵按行或列进行符号变换(例如取反操作)。
本发明另一个实施例提供的一种MTS的实现方案如表25所示。
表25一种MTS实现方案
Figure PCTCN2019106383-appb-000035
其中，C＝DST4矩阵,E＝DCT2’矩阵。其中，上面的变形可以是对矩阵按行或列进行符号变换(例如取反操作)。
本发明另一个实施例提供的一种MTS的实现方案如表26所示。
表26一种MTS实现方案
Figure PCTCN2019106383-appb-000036
其中，C＝DST4矩阵,E＝DCT2’矩阵。
本发明另一个实施例提供的一种MTS的实现方案如表27所示。
表27一种MTS实现方案
Figure PCTCN2019106383-appb-000037
其中，C＝DST4矩阵,E＝DCT2’矩阵。
本发明另一个实施例提供的一种MTS的实现方案如表28所示。
表28一种MTS实现方案
Figure PCTCN2019106383-appb-000038
Figure PCTCN2019106383-appb-000039
其中，C＝DST4矩阵,E＝DCT2’矩阵。
本发明另一个实施例提供的一种MTS的实现方案如表29所示。
表29一种MTS实现方案
Figure PCTCN2019106383-appb-000040
其中，C＝DST4矩阵,E＝DCT2’矩阵。
本发明另一个实施例提供的一种MTS的实现方案如表30所示。
表30一种MTS实现方案
Figure PCTCN2019106383-appb-000041
其中，C＝DST4矩阵,E＝DCT2’矩阵。
本发明另一个实施例提供的一种MTS的实现方案如表31所示。
表31一种MTS实现方案
Figure PCTCN2019106383-appb-000042
其中，C＝DST4矩阵,E＝DCT2’矩阵。
本发明另一个实施例提供的一种MTS的实现方案如表32所示。
表32一种MTS实现方案
Figure PCTCN2019106383-appb-000043
其中，C＝DST4矩阵,E＝DCT2’矩阵。
本发明另一个实施例提供的一种MTS的实现方案如表33所示。
表33一种MTS实现方案
Figure PCTCN2019106383-appb-000044
Figure PCTCN2019106383-appb-000045
其中，C＝DST4矩阵,E＝DCT2’矩阵。
从上可知，在一种实施方式中，上述的DST4矩阵，DCT2’矩阵，DST4矩阵的变形或DCT2’矩阵的变形中的至少一个除了可以从8×8的DCT2矩阵中获得。由于编码器或解码器会保存8×8的DCT2矩阵，因此从8×8的DCT2矩阵中获得上述的DST4矩阵，DCT2’矩阵，DST4矩阵的变形或DCT2’矩阵的变形中的至少一个可以减少编码器或解码器需要存储的变换矩阵的数量，因此可以减少变换矩阵对编码器或解码器的存储空间的占用。
在另一种实施方式中，上述的DST4矩阵，DCT2’矩阵，DST4矩阵的变形或DCT2’矩阵的变形中的至少一个还可以可以直接从64×64的DCT2矩阵中获得。由于编码器或解码器会保存64×64的DCT2矩阵，因此从64×64的DCT2矩阵中获得上述的DST4矩阵，DCT2’矩阵，DST4矩阵的变形或DCT2’矩阵的变形中的至少一个可以减少编码器或解码器需要存储的变换矩阵的数量，因此可以减少变换矩阵对编码器或解码器的存储空间的占用。
在一种实施方式中，上述的64×64的DCT2矩阵可以如表34和表35所示(由于64×64 DCT2矩阵比较大，因此用两个表来表示，其中表34描述的是该矩阵的第0～15列(记为transMatrixCol0to15)，表35描述的是该矩阵的第16～31列(记为transMatrixCol16to31))。
表34 64×64 DCT2矩阵的0～15列
{256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256}
{362 361 359 357 353 349 344 338 331 323 315 306 296 285 274 262}
{362 358 351 341 327 311 291 268 243 216 186 155 122 88 53 18}
{361 353 338 315 285 250 208 163 114 62 9 -44 -97 -147 -194 -236}
{360 346 319 280 230 171 105 35 -35 -105 -171 -230 -280 -319 -346 -360}
{359 338 296 236 163 79 -9 -97 -178 -250 -306 -344 -361 -357 -331 -285}
{358 327 268 186 88 -18 -122 -216 -291 -341 -362 -351 -311 -243 -155 -53}
{357 315 236 130 9 -114 -223 -306 -353 -359 -323 -250 -147 -27 97 208}
{355 301 201 71 -71 -201 -301 -355 -355 -301 -201 -71 71 201 301 355}
{353 285 163 9 -147 -274 -349 -357 -296 -178 -27 130 262 344 359 306}
{351 268 122 -53 -216 -327 -362 -311 -186 -18 155 291 358 341  243 88}
{349 250 79 -114 -274 -357 -338 -223 -44 147 296 361 323 194 9 -178}
{346 230 35 -171 -319 -360 -280 -105 105 280 360 319 171 -35 -230 -346}
{344 208 -9 -223 -349 -338 -194 27 236 353 331 178 -44 -250 -357 -323}
{341 186 -53 -268 -362 -291 -88 155 327 351 216 -18 -243 -358 -311 -122}
{338 163 -97 -306 -357 -223 27 262 362 274 44 -208 -353 -315 -114 147}
{334 139 -139 -334 -334 -139 139 334 334 139 -139 -334 -334 -139 139 334}
{331 114 -178 -353 -296 -44 236 362 250 -27 -285 -357 -194 97 323 338}
{327 88 -216 -362 -243 53 311 341 122 -186 -358 -268 18 291 351 155}
{323 62 -250 -359 -178 147 353 274 -27 -306 -338 -97 223 362 208 -114}
{319 35 -280 -346 -105 230 360 171 -171 -360 -230 105 346 280 -35 -319}
{315 9 -306 -323 -27 296 331 44 -285 -338 -62 274 344 79 -262 -349}
{311 -18 -327 -291 53 341 268 -88 -351 -243 122 358 216 -155 -362 -186}
{306 -44 -344 -250 130 361 178 -208 -357 -97 274 331 9 -323 -285 79}
{301 -71 -355 -201 201 355 71 -301 -301 71 355 201 -201 -355 -71 301}
{296 -97 -361 -147 262 323 -44 -353 -194 223 344 9 -338 -236 178 357}
{291 -122 -362 -88 311 268 -155 -358 -53 327 243 -186 -351 -18 341 216}
{285 -147 -357 -27 344 194 -250 -315 97 362 79 -323 -236 208 338 -44}
{280 -171 -346 35 360 105 -319 -230 230 319 -105 -360 -35 346 171 -280}
{274 -194 -331 97 359 9 -357 -114 323 208 -262 -285 178 338 -79 -361}
{268 -216 -311 155 341 -88 -358 18 362 53 -351 -122 327 186 -291 -243}
{262 -236 -285 208 306 -178 -323 147 338 -114 -349 79 357 -44 -361 9}
{256 -256 -256 256 256 -256 -256 256 256 -256 -256 256 256 -256 -256 256}
{250 -274 -223 296 194 -315 -163 331 130 -344 -97 353 62 -359 -27 362}
{243 -291 -186 327 122 -351 -53 362 -18 -358 88 341 -155 -311 216 268}
{236 -306 -147 349 44 -362 62 344 -163 -296 250 223 -315 -130 353 27}
{230 -319 -105 360 -35 -346 171 280 -280 -171 346 35 -360 105 319 -230}
{223 -331 -62 361 -114 -306 262 178 -349 -9 353 -163 -274 296 130 -359}
{216 -341 -18 351 -186 -243 327 53 -358 155 268 -311 -88 362 -122 -291}
{208 -349 27 331 -250 -163 359 -79 -306 285 114 -362 130 274 -315 -62}
{201 -355 71 301 -301 -71 355 -201 -201 355 -71 -301 301 71 -355 201}
{194 -359 114 262 -338 27 315 -296 -62 349 -236 -147 362 -163 -223 353}
{186 -362 155 216 -358 122 243 -351 88 268 -341 53 291 -327 18 311}
{178 -362 194 163 -361 208 147 -359 223 130 -357 236 114 -353 250 97}
{171 -360 230 105 -346 280 35 -319 319 -35 -280 346 -105 -230 360 -171}
{163 -357 262 44 -315 331 -79 -236 361 -194 -130 349 -285 -9 296 -344}
{155 -351 291 -18 -268 358 -186 -122 341 -311 53 243 -362 216 88 -327}
{147 -344 315 -79 -208 359 -274 9 262 -361 223 62 -306 349 -163 -130}
{139 -334 334 -139 -139 334 -334 139 139 -334 334 -139 -139 334 -334 139}
{130 -323 349 -194 -62 285 -361 250 -9 -236 359 -296 79 178 -344 331}
{122 -311 358 -243 18 216 -351 327 -155 -88 291 -362 268 -53 -186 341}
{114 -296 362 -285 97 130 -306 361 -274 79 147 -315 359 -262 62 163}
{105 -280 360 -319 171 35 -230 346 -346 230 -35 -171 319 -360 280 -105}
{97 -262 353 -344 236 -62 -130 285 -359 331 -208 27 163 -306  362 -315}
{88 -243 341 -358 291 -155 -18 186 -311 362 -327 216 -53 -122 268 -351}
{79 -223 323 -362 331 -236 97 62 -208 315 -361 338 -250 114 44 -194}
{71 -201 301 -355 355 -301 201 -71 -71 201 -301 355 -355 301 -201 71}
{62 -178 274 -338 362 -344 285 -194 79 44 -163 262 -331 361 -349 296}
{53 -155 243 -311 351 -362 341 -291 216 -122 18 88 -186 268 -327 358}
{44 -130 208 -274 323 -353 362 -349 315 -262 194 -114 27 62 -147 223}
{35 -105 171 -230 280 -319 346 -360 360 -346 319 -280 230 -171 105 -35}
{27 -79 130 -178 223 -262 296 -323 344 -357 362 -359 349 -331 306 -274}
{18 -53 88 -122 155 -186 216 -243 268 -291 311 -327 341 -351 358 -362}
{9 -27 44 -62 79 -97 114 -130 147 -163 178 -194 208 -223 236 -250}
表35 64×64 DCT2矩阵的16～31列
{256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256}
{250 236 223 208 194 178 163 147 130 114 97 79 62 44 27 9}
{-18 -53 -88 -122 -155 -186 -216 -243 -268 -291 -311 -327 -341 -351 -358 -362}
{-274 -306 -331 -349 -359 -362 -357 -344 -323 -296 -262 -223 -178 -130 -79 -27}
{-360 -346 -319 -280 -230 -171 -105 -35 35 105 171 230 280 319 346 360}
{-223 -147 -62 27 114 194 262 315 349 362 353 323 274 208 130 44}
{53 155 243 311 351 362 341 291 216 122 18 -88 -186 -268 -327 -358}
{296 349 361 331 262 163 44 -79 -194 -285 -344 -362 -338 -274 -178 -62}
{355 301 201 71 -71 -201 -301 -355 -355 -301 -201 -71 71 201 301 355}
{194 44 -114 -250 -338 -361 -315 -208 -62 97 236 331 362 323  223 79}
{-88 -243 -341 -358 -291 -155 18 186 311 362 327 216 53 -122 -268 -351}
{-315 -362 -306 -163 27 208 331 359 285 130 -62 -236 -344 -353 -262 -97}
{-346 -230 -35 171 319 360 280 105 -105 -280 -360 -319 -171 35 230 346}
{-163 62 262 359 315 147 -79 -274 -361 -306 -130 97 285 362 296 114}
{122 311 358 243 18 -216 -351 -327 -155 88 291 362 268 53 -186 -341}
{331 344 178 -79 -296 -359 -236 9 250 361 285 62 -194 -349 -323 -130}
{334 139 -139 -334 -334 -139 139 334 334 139 -139 -334 -334 -139 139 334}
{130 -163 -349 -306 -62 223 361 262 -9 -274 -359 -208 79 315 344 147}
{-155 -351 -291 -18 268 358 186 -122 -341 -311 -53 243 362 216 -88 -327}
{-344 -296 -9 285 349 130 -194 -361 -236 79 331 315 44 -262 -357 -163}
{-319 -35 280 346 105 -230 -360 -171 171 360 230 -105 -346 -280 35 319}
{-97 250 353 114 -236 -357 -130 223 359 147 -208 -361 -163 194 362 178}
{186 362 155 -216 -358 -122 243 351 88 -268 -341 -53 291 327 18 -311}
{353 223 -163 -362 -147 236 349 62 -296 -315 27 338 262 -114 -359 -194}
{301 -71 -355 -201 201 355 71 -301 -301 71 355 201 -201 -355 -71 301}
{62 -315 -274 130 362 114 -285 -306 79 359 163 -250 -331 27 349 208}
{-216 -341 18 351 186 -243 -327 53 358 155 -268 -311 88 362 122 -291}
{-359 -130 296 274 -163 -353 -9 349 178 -262 -306 114 361 62 -331 -223}
{-280 171 346 -35 -360 -105 319 230 -230 -319 105 360 35 -346 -171 280}
{-27 353 130 -315 -223 250 296 -163 -344 62 362 44 -349 -147 306 236}
{243 291 -186 -327 122 351 -53 -362 -18 358 88 -341 -155 311 216 -268}
{362 27 -359 -62 353 97 -344 -130 331 163 -315 -194 296 223 -274 -250}
{256 -256 -256 256 256 -256 -256 256 256 -256 -256 256 256 -256 -256 256}
{-9 -361 44 357 -79 -349 114 338 -147 -323 178 306 -208 -285 236 262}
{-268 -216 311 155 -341 -88 358 18 -362 53 351 -122 -327 186 291 -243}
{-361 79 338 -178 -285 262 208 -323 -114 357 9 -359 97 331 -194 -274}
{-230 319 105 -360 35 346 -171 -280 280 171 -346 -35 360 -105 -319 230}
{44 338 -208 -236 323 79 -362 97 315 -250 -194 344 27 -357 147 285}
{291 122 -362 88 311 -268 -155 358 -53 -327 243 186 -351 18 341 -216}
{357 -178 -236 338 9 -344 223 194 -353 44 323 -262 -147 361 -97 -296}
{201 -355 71 301 -301 -71 355 -201 -201 355 -71 -301 301 71 -355 201}
{-79 -285 323 9 -331 274 97 -357 208 178 -361 130 250 -344 44 306}
{-311 -18 327 -291 -53 341 -268 -88 351 -243 -122 358 -216 -155 362 -186}
{-349 262 79 -344 274 62 -338 285 44 -331 296 27 -323 306 9-315}
{-171 360 -230 -105 346 -280 -35 319 -319 35 280 -346 105 230 -360 171}
{114 208 -362 223 97 -338 306 -27 -274 353 -147 -178 359 -250 -62 323}
{327 -88 -216 362 -243 -53 311 -341 122 186 -358 268 18 -291 351 -155}
{338 -323 97 194 -357 285 -27 -250 362 -236 -44 296 -353 178 114 -331}
{139 -334 334 -139 -139 334 -334 139 139 -334 334 -139 -139 334 -334 139}
{-147 -114 315 -353 208 44 -274 362 -262 27 223 -357 306 -97 -163 338}
{-341 186 53 -268 362 -291 88 155 -327 351 -216 -18 243 -358 311 -122}
{-323 357 -250 44 178 -331 353 -236 27 194 -338 349 -223 9 208 -344}
{-105 280 -360 319 -171 -35 230 -346 346 -230 35 171 -319  360 -280 105}
{178 9 -194 323 -361 296 -147 -44 223 -338 357 -274 114 79 -250 349}
{351 -268 122 53 -216 327 -362 311 -186 18 155 -291 358 -341 243 -88}
{306 -359 344 -262 130 27 -178 296 -357 349 -274 147 9 -163 285 -353}
{71 -201 301 -355 355 -301 201 -71 -71 201 -301 355 -355 301 -201 71}
{-208 97 27 -147 250 -323 359 -353 306 -223 114 9 -130 236 -315 357}
{-358 327 -268 186 -88 -18 122 -216 291 -341 362 -351 311 -243 155 -53}
{-285 331 -357 361 -344 306 -250 178 -97 9 79 -163 236 -296 338 -359}
{-35 105 -171 230 -280 319 -346 360 -360 346 -319 280 -230 171 -105 35}
{236 -194 147 -97 44 9 -62 114 -163 208 -250 285 -315 338 -353 361}
{362 -358 351 -341 327 -311 291 -268 243 -216 186 -155 122 -88 53 -18}
{262 -274 285 -296 306 -315 323 -331 338 -344 349 -353 357 -359 361 -362}
通过如下操作，即可通过表34和表35获得64x64的DCT2矩阵transMatrix。
transMatrix[m][n]＝transMatrixCol0to15[m][n]with m＝0..15,n＝0..63
transMatrix[m][n]＝transMatrixCol16to31[m-16][n]with m＝16..31,n＝0..63
transMatrix[m][n]＝(n&1？-1:1)*transMatrixCol16to31[47-m][n]
with m＝32..47,n＝0..63
transMatrix[m][n]＝(n&1？-1:1)*transMatrixCol0to15[63-m][n]
with m＝48..63,n＝0..63
在一种实施方式中，用trType来指示变换核，例如指示变换核为DST4矩阵/DST4矩阵的变形，还是DCT2’矩阵/DCT2’矩阵的变形。例如trType＝1时表示变换矩阵为DST4矩阵，trType＝2时表示变换矩阵为DCT2’矩阵；当然也可以反过来，即trType＝2时表示变换矩阵为DST4矩阵，trType＝1时表示变换矩阵为DCT2’矩阵。可以理解的是，trType还可以取别的值来指示DST4矩阵和DCT2’矩阵。本发明实施例对trType与变换矩阵之间的对应关系不做限定，只要trType的取值能够与变换矩阵一一对应就不会影响本发明实施例的实现。
例如，在变换矩阵为DST4矩阵，可以通过如下的公式(1)从64×64的DCT2矩阵推导出DST4矩阵：
Figure PCTCN2019106383-appb-000046
其中，transMatrix表示所述DCT2矩阵(64×64 DCT2矩阵)，nTbs表示变换矩阵的大小，0≤i≤nTbS–1，0≤j≤nTbS–1；偏移量64-nTbs表示列的偏移，即偏移到64x64矩阵的最后nTbs列；偏移量
Figure PCTCN2019106383-appb-000047
表示行的偏移；(-1) j表示进行符号变换。
其中，在本发明实施例中，i表示变换矩阵中系数的列坐标，j表示变换矩阵中系数的行坐标。
例如，当nTbs＝4，即DST4矩阵的大小为4×4时，根据公式(1)来推导得出4×4的DST4矩阵为：
Figure PCTCN2019106383-appb-000048
例如，当nTbs＝8，即DST4矩阵的大小为8×8时，根据公式(1)来推导得出8×8的DST4矩阵为：
Figure PCTCN2019106383-appb-000049
在DST4矩阵的大小为16或者32时，也可以采用公式(1)推导得出，不再赘述。
例如，在变换矩阵为DCT2’矩阵，可以通过如下的公式(2)从64×64的DCT2矩阵推导出DCT2’矩阵：
transMatrix[j][i×2 6-Log2(nTbs)]      (2)
其中，transMatrix表示所述DCT2矩阵(64×64 DCT2矩阵)，nTbs表示变换矩阵的大小，0≤i≤nTbS–1，0≤j≤nTbS–1。
例如，当nTbs＝4，即DCT2’矩阵的大小为4×4时，根据公式(2)来推导得出4×4的DCT2’矩阵为：
Figure PCTCN2019106383-appb-000050
例如，当nTbs＝8，即DCT2’矩阵的大小为8×8时，根据公式(2)来推导得出8×8的DCT2’矩阵为：
Figure PCTCN2019106383-appb-000051
在DCT2’矩阵的大小为16或者32时，也可以采用公式(2)推导得出，不再赘述。
其中，在一种实施方式中，编码器或解码器还可以从存储的大尺寸的DCT2矩阵推导出小尺寸的DCT2矩阵。例如，在所述大尺寸的DCT2矩阵的尺寸为64，即64×64时，可以根据如下公式(3)推导出尺寸小于64的DCT2矩阵。
transMatrix[i][j×2 6-Log2(nTbs)]     (3)
其中，transMatrix表示所述DCT2矩阵(64×64 DCT2矩阵)，nTbs表示变换矩阵的大小，0≤i≤nTbS–1，0≤j≤nTbS–1。
对比公式(2)和(3)可以看出，其区别在于i和j的位置变化，表示通过公式(2)和(3)获得的矩阵互为转置。
图10描述了本发明一个实施例提供的视频解码方法的流程，该方法例如可以由图3所示的视频解码器来执行，该方法包括：
1001、解析接收的码流，以获得当前块进行逆变换处理的变换矩阵对的指示信息以及所述当前块的量化系数，所述变换矩阵对包括水平方向变换矩阵和垂直方向变换矩阵。
1002、对所述当前块的量化系数进行逆量化处理以获得所述当前块的反量化系数。
1003、根据所述指示信息从候选变换矩阵对中确定所述当前块进行逆变换处理的变换矩阵对；所述候选变换矩阵对所包括的水平方向变换矩阵和垂直方向变换矩阵均为预设的两个变换矩阵中的一个；所述两个变换矩阵中一个为DST4矩阵或DST4矩阵的变形，所述两个变换矩阵中的另一个为DCT2’矩阵或DCT2’矩阵的变形。
其中，候选变换矩阵对的数量可以为2个，3个或4个。
其中，任意一个所述候选变换矩阵对所包括的水平方向变换矩阵和垂直方向变换矩阵要么相同要么不同。
其中，在一种实施方式中，所述DST4矩阵的变形是通过对所述DST4矩阵中的至少一部分行或至少一部分列的系数进行符号变换获得，例如所述的符号变换可以是符号取反。
在一种实施方式中，所述DCT2’矩阵的变形是通过对所述DCT2’矩阵中的至少一部分行或至少一部分列的系数进行符号变换获得，例如所述的符号变换可以是符号取反。
例如，所述的候选变换矩阵对可以是如表11，表20，表24，表25，或表26-表33任一所描述的候选变换矩阵对。
其中，在一种实施方式中，所述候选变换矩阵对的数量为四个；当前块进行逆变换处理的变换矩阵对的指示信息即为表11，表20，表24或表25中的索引。以表11为例，若索引为0，则表示当前块进行逆变换处理的变换矩阵对中的垂直方向变换矩阵为DST4矩阵，数值变换矩阵为DST4矩阵；若索引为1，则表示当前块进行逆变换处理的变换矩阵对中的垂直方向变换矩阵为DST4矩阵，数值变换矩阵为DCT2’矩阵；若索引为2，则表示当前块进行逆变换处理的变换矩阵对中的垂直方向变换矩阵为DCT2’矩阵，数值变换矩阵为DST4矩阵；若索引为3，则表示当前块进行逆变换处理的变换矩阵对中的垂直方向变换矩阵为DCT2’矩阵，数值变换矩阵为DCT2’矩阵。表20，和表24-表33的索引的处理与表11类似，不再赘述。
在另一种实施方式中，当前块进行逆变换处理的变换矩阵对的指示信息包括用于指示所述当前块进行逆变换处理的变换矩阵对中的垂直方向变换矩阵的标识，以及用于指示所述当前块进行逆变换处理的变换矩阵对中的水平方向变换矩阵的标识。例如，用一个比特位作为垂直方向变换矩阵的标识，用另一个比特位作为水平方向变换矩阵的标识。
以表11为例，若垂直方向变换矩阵的比特位的值为0，则表示垂直方向变换矩阵为DST4矩阵，反之则表示垂直方向变换矩阵为DCT2’矩阵；若水平方向变换矩阵的比特位的值为0，则表示水平方向变换矩阵为DST4矩阵，反之则表示水平方向变换矩阵为DCT2’矩阵。
以表20为例，若垂直方向变换矩阵的比特位的值为0，则表示垂直方向变换矩阵为DST4矩阵的变形，反之则表示垂直方向变换矩阵为DCT2’矩阵的变形；若水平方向变换矩阵的比特位的值为0，则表示水平方向变换矩阵为DST4矩阵的变形，反之则表示水平方向变换矩阵为DCT2’矩阵的变形。
以表24为例，若垂直方向变换矩阵的比特位的值为0，则表示垂直方向变换矩阵为DST4矩阵的变形，反之则表示垂直方向变换矩阵为DCT2’矩阵；若水平方向变换矩阵的比特位的值为0，则表示水平方向变换矩阵为DST4矩阵的变形，反之则表示水平方向变换矩阵为DCT2’矩阵。
以表25为例，若垂直方向变换矩阵的比特位的值为0，则表示垂直方向变换矩阵为DST4矩阵，反之则表示垂直方向变换矩阵为DCT2’矩阵的变形；若水平方向变换矩阵的比特位的值为0，则表示水平方向变换矩阵为DST4矩阵，反之则表示水平方向变换矩阵为DCT2’矩阵的变形。
1004、根据所述当前块进行逆变换处理的变换矩阵对对所述当前块的反量化系数进行逆变换处理，以得到所述当前块的重建残差块。
1005、根据所述当前块的重建残差块获得所述当前块的重构块。
可见，由于DCT2’矩阵或DCT2’矩阵的变形在变换/反变换时存在蝶形快速算法，因此可以简化变换/反变换的实现。同时，DCT2’矩阵或DCT2’矩阵的变形以及DST4矩阵或DST4矩阵的变形均可以直接复用DCT2矩阵对应的变换/反变换实现电路，因此在变换/反变换模块在通过电路实现时可以简化变换/反变换模块的实现电路的设计。
在一种实施方式中，在步骤1004前，所述方法还可以包括：根据预设算法从DCT2矩阵推导出所述当前块进行逆变换处理的变换矩阵对所包括的变换矩阵。
例如，在所述当前块进行逆变换处理的变换矩阵对包括DST4矩阵，所述DCT2矩阵的大小为64时，所述根据预设算法从DCT2矩阵推导出所述当前块进行逆变换处理的变换矩阵对所包括的变换矩阵可以包括：根据前述的公式(1)推导出所述DST4矩阵。
例如，在所述当前块进行逆变换处理的变换矩阵对包括DCT2’矩阵，所述DCT2矩阵的大小为64时，所述根据预设算法从DCT2矩阵推导出所述当前块进行逆变换处理的变换矩阵对所包括的变换矩阵可以包括：根据前述的公式(2)推导出所述DCT2’矩阵。
可见，解码器只需要存储DCT2矩阵就可以推导获得变换矩阵对所包括的矩阵，因此可以减少解码器需要存储的变换矩阵的数量，从而减少变换矩阵对解码器的存储空间的占用。
图11描述了本发明一个实施例提供的视频编码方法的流程，该方法例如可以由图2所示的视频编码器来执行，该方法包括：
1101、确定用于对当前残差块进行变换处理的变换矩阵对的指示信息，所述变换矩阵对包括水平方向变换矩阵和垂直方向变换矩阵；所述变换矩阵对是候选变换矩阵对中的一个，所述候选变换矩阵对所包括的水平方向变换矩阵和垂直方向变换矩阵均为预设的两个变换矩阵中的一个；所述两个变换矩阵中一个为DST4矩阵或DST4矩阵的变形，所述两个变换矩阵中的另一个为DCT2’矩阵或DCT2’矩阵的变形。
其中，任意一个所述候选变换矩阵对所包括的水平方向变换矩阵和垂直方向变换矩阵要么相同要么不同。
其中，候选变换矩阵对的数量可以为2个，3个或4个。
其中，在一种实施方式中，所述DST4矩阵的变形是通过对所述DST4矩阵中的至少一部分行或至少一部分列的系数进行符号变换获得，例如所述的负号变换可以是符号取反。
在一种实施方式中，所述DCT2’矩阵的变形是通过对所述DCT2’矩阵中的至少一部分行或至少一部分列的系数进行符号变换获得，例如所述的符号变换可以是符号取反。
例如，所述的候选变换矩阵对可以是如表11，表20，表24，表25，或表26-表33任一所描述的候选变换矩阵对。
具体地，编码器可以利用所述四个候选变换矩阵对对残差块进行水平方向变换和垂直方向变换，从而挑选出率失真代价(rate-distortion cost)最小的变换矩阵对作为当前残差块进行变换处理的变换矩阵对，再从表11，表20，或表24-表33中任一确定当前残差块进行变换处理的变换矩阵对的指示信息。
1102、对通过所述变换矩阵对对所述当前残差块进行变换处理获得的变换系数进行量化处理，以获得所述当前残差块的量化系数。
1103、对所述当前残差块的量化系数和所述指示信息进行熵编码处理。
1104、将熵编码处理后的所述变换矩阵对的指示信息和熵编码处理后的所述当前残差块的量化系数写入码流。
可见，由于DCT2’矩阵或DCT2’矩阵的变形在变换/反变换时存在蝶形快速算法，因此可以简化变换/反变换的实现。同时，DCT2’矩阵或DCT2’矩阵的变形以及DST4矩阵或DST4矩阵的变形均可以直接复用DCT2矩阵对应的变换/反变换实现电路，因此在变换/反变换模块在通过电路实现时可以简化变换/反变换模块的实现电路的设计。
其中，在一种实施方式中，所述编码方法还包括：根据预设算法从DCT2矩阵推导出所述变换矩阵对所包括的变换矩阵。
例如，在所述变换矩阵对所包括的变换矩阵包括DST4矩阵，所述DCT2矩阵的大小为64时；所述根据预设算法从DCT2矩阵推导出所述变换矩阵对所包括的变换矩阵包括：根据上述的公式(1)推导出所述DST4矩阵。
例如，在所述变换矩阵对所包括的变换矩阵包括DCT2’矩阵，所述DCT2矩阵的大小为64时；所述根据预设算法从DCT2矩阵推导出所述变换矩阵对所包括的变换矩阵包括：根据上述的公式(1)推导出所述DCT2’矩阵。
可见，编码器只需要存储DCT2矩阵就可以推导获得变换矩阵对所包括的矩阵，因此可以减少编码器需要存储的变换矩阵的数量，从而减少变换矩阵对编码器的存储空间的占用。
本发明一个实施例提供的视频解码器30的结构如图3所示，包括：
熵解码单元304，用于解析接收的码流，以获得当前块进行逆变换处理的变换矩阵对 的指示信息以及所述当前块的量化系数309，所述变换矩阵对包括水平方向变换矩阵和垂直方向变换矩阵。
逆量化单元310，用于对所述当前块的量化系数309进行逆量化处理以获得所述当前块的反量化系数311。
逆变换处理单元312，用于根据所述指示信息从候选变换矩阵对中确定所述当前块进行逆变换处理的变换矩阵对；所述候选变换矩阵对所包括的水平方向变换矩阵和垂直方向变换矩阵均为预设的两个变换矩阵中的一个；所述两个变换矩阵中一个为DST4矩阵或DST4矩阵的变形，所述两个变换矩阵中的另一个为DCT2’矩阵或DCT2’矩阵的变形；根据所述当前块进行逆变换处理的变换矩阵对对所述当前块的反量化系数进行逆变换处理，以得到所述当前块的重建残差块313。
具体处理可以参考步骤1003的处理。
重构单元314，用于基于所述当前块的重建残差块获得所述当前块的重构块315。
其中，在一种实施方式中，所述逆变换处理单元312还可以用于：根据预设算法从DCT2矩阵推导出所述当前块进行逆变换处理的变换矩阵对所包括的变换矩阵。
例如，在所述当前块进行逆变换处理的变换矩阵对包括DST4矩阵，所述DCT2矩阵的大小为64时，所述逆变换处理单元312可以具体用于根据上述公式(1)推导出所述DST4矩阵。
例如，在所述当前块进行逆变换处理的变换矩阵对包括DCT2’矩阵，所述DCT2矩阵的大小为64时，所述逆变换处理单元312可以具体用于根据上述公式(2)推导出所述DCT2’矩阵。
本发明一个实施例提供的视频编码器20的结构如图2所示，包括：
变换处理单元206，用于确定用于对当前残差块205进行变换处理的变换矩阵对的指示信息，所述变换矩阵对包括水平方向变换矩阵和垂直方向变换矩阵；所述变换矩阵对是候选变换矩阵对中的一个，所述候选变换矩阵对所包括的水平方向变换矩阵和垂直方向变换矩阵均为预设的两个变换矩阵中的一个；所述两个变换矩阵中一个为DST4矩阵或DST4矩阵的变形，所述两个变换矩阵中的另一个为DCT2’矩阵或DCT2’矩阵的变形。
具体实现可以参考1101的处理。
量化单元207，对通过所述变换矩阵对对所述当前残差块进行变换处理获得的变换系数207进行量化处理，以获得所述当前残差块的量化系数。
其中，变换系数207具体可以通过变换处理单元206获得。
熵编码单元270，用于对所述当前残差块的量化系数和所述指示信息进行熵编码处理；
输出272，用于将熵编码处理后的所述变换矩阵对的指示信息和熵编码处理后的所述当前残差块的量化系数写入码流。
在一种实施方式中，所述变换处理单元206还可以用于根据预设算法从DCT2矩阵推导出所述变换矩阵对所包括的变换矩阵。
例如，在所述变换矩阵对包括DST4矩阵，所述DCT2矩阵的大小为64时，所述变换处理单元206具体可以用于根据上述公式(1)推导出所述DST4矩阵。
例如，在所述变换矩阵对包括DCT2’矩阵，所述DCT2矩阵的大小为64时，所述变换处理单元206具体可以用于根据上述公式(2)推导出所述DCT2’矩阵。
本发明实施例还提供了一种视频解码器，包括用于执行上述任一所述的视频解码方法的执行电路。
本发明实施例还提供了一种视频解码器，包括：至少一个处理器；和与所述至少一个处理器耦合的非易失性计算机可读存储介质，所述非易失性计算机可读存储介质存储有可被所述至少一个处理器执行的计算机程序，当所述计算机程序被所述至少一个处理器执行时，使得所述视频解码器用于执行上一任一所述的视频解码方法。
本发明实施例还提供了一种视频编码器，包括用于执行上述任一所述的视频编码方法的执行电路。
本发明实施例还提供了一种视频编码器，包括：至少一个处理器；和与所述至少一个处理器耦合的非易失性计算机可读存储介质，所述非易失性计算机可读存储介质存储有可被所述至少一个处理器执行的计算机程序，当所述计算机程序被所述至少一个处理器执行时，使得所述视频解码器用于执行上一任一所述的视频编码方法。
本发明实施例还提供了一种计算机可读存储介质，用于存储可被处理器执行的计算机程序，当所述计算机程序被所述至少一个处理器执行时，执行上述任一所述的方法。
本发明实施例还提供了一种计算机程序，当所述计算机程序被执行时，执行上述任一所述的方法。
在一个或一个以上实例中，所描述功能可以硬件、软件、固件或其任何组合来实施。如果在软件中实施，那么所述功能可作为一或多个指令或代码在计算机可读介质上存储或传输，并且由基于硬件的处理单元执行。计算机可读介质可以包含计算机可读存储介质，其对应于例如数据存储介质或通信介质的有形介质，通信介质例如根据通信协议包含有助于将计算机程序从一处传送到另一处的任何介质。以此方式，计算机可读介质通常可对应于(1)非暂时性的有形计算机可读存储介质，或(2)通信介质，例如，信号或载波。数据存储介质可以是可由一或多个计算机或一或多个处理器存取以检索用于实施本发明中描述的技术的指令、代码和/或数据结构的任何可用介质。计算机程序产品可包含计算机可读介质。
借助于实例而非限制，此类计算机可读存储介质可包括RAM、ROM、EEPROM、CD-ROM或其它光盘存储器、磁盘存储器或其它磁性存储设备、闪存，或可用以存储呈指令或数据结构形式的所需程序代码且可由计算机存取的任何其它介质。并且，任何连接可适当地称为计算机可读介质。举例来说，如果使用同轴电缆、光纤缆线、双绞线、数字订户线(digital subscriber line，DSL)或例如红外线、无线电及微波等无线技术从网站、服务器或其它远程源传输指令，则同轴电缆、光纤缆线、双绞线、DSL或例如红外线、无线电及微波等无线技术包含在介质的定义中。但是，应理解，所述计算机可读存储介质及数据 存储介质并不包括连接、载波、信号或其它暂时性介质，而是实际上针对于非暂时性有形存储介质。如本文中所使用，磁盘和光盘包含压缩光盘(compact disc，CD)、激光光盘、光学光盘、数字多功能光盘(digital versatile disc，DVD)、软性磁盘及蓝光光盘，其中磁盘通常以磁性方式再现数据，而光盘用激光以光学方式再现数据。以上各项的组合也应包含于计算机可读介质的范围内。
指令可以由一或多个处理器执行，所述一或多个处理器例如是一或多个数字信号处理器(digital signal processor，DSP)、通用微处理器、专用集成电路(application specific integrated circuit，ASIC)、现场可编程逻辑阵列(field programmable logic arrays，FPGA)或其它等效的集成或离散逻辑电路。因此，如本文中所使用的术语“处理器”可指代上述结构或适用于实施本文中所描述的技术的任何其它结构中的任一者。另外，在一些方面中，本文中所描述的功能性可在用于编码和解码的专用硬件和/或软件模块内提供，或并入在合成编解码器中。并且，所述技术可完全实施于一或多个电路或逻辑元件中。
本公开的技术可以在包含无线手持机、集成电路(integrated circuit，IC)或IC集合(例如，芯片组)的多种设备或装置中实施。本公开描述各种组件、模块或单元是为了强调用于执行所揭示的技术的设备的功能方面，但未必需要通过不同硬件单元实现。确切地，如上文所描述，各种单元可结合合适的软件和/或固件组合在编解码器硬件单元中，或由互操作硬件单元的集合来提供，所述硬件单元包含如上文所描述的一或多个处理器。

Claims (27)

  1. 一种视频解码方法，其特征在于，包括：
    解析接收的码流，以获得当前块进行逆变换处理的变换矩阵对的指示信息以及所述当前块的量化系数，所述变换矩阵对包括水平方向变换矩阵和垂直方向变换矩阵；
    对所述当前块的量化系数进行逆量化处理以获得所述当前块的反量化系数；
    根据所述指示信息从候选变换矩阵对中确定所述当前块进行逆变换处理的变换矩阵对；所述候选变换矩阵对所包括的水平方向变换矩阵和垂直方向变换矩阵均为预设的两个变换矩阵中的一个；所述两个变换矩阵中一个为DST4矩阵或DST4矩阵的变形，所述两个变换矩阵中的另一个为DCT2’矩阵或DCT2’矩阵的变形，其中，DCT2’矩阵为DCT2矩阵的转置矩阵；
    根据所述当前块进行逆变换处理的变换矩阵对对所述当前块的反量化系数进行逆变换处理，以得到所述当前块的重建残差块；
    根据所述当前块的重建残差块获得所述当前块的重构块。
  2. 根据权利要求1所述的方法，其特征在于，所述DST4矩阵的变形是通过对所述DST4矩阵中的至少一部分行或至少一部分列的系数进行符号变换获得；或
    所述DCT2’矩阵的变形是通过对所述DCT2’矩阵中的至少一部分行或至少一部分列的系数进行符号变换获得。
  3. 根据权利要求1或2所述的方法，其特征在于，所述候选变换矩阵对的数量为四个；在所述两个变换矩阵中一个为DST4矩阵，另一个为DCT2’矩阵时，所述四个候选变换矩阵对中的第一个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵，所述第一个变换矩阵对包括的水平方向变换矩阵为DST4矩阵；
    所述四个候选变换矩阵对中的第二个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵，所述第二个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵；
    所述四个候选变换矩阵对中的第三个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵，所述第三个变换矩阵对包括的水平方向变换矩阵为DST4矩阵；
    所述四个候选变换矩阵对中的第四个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵，所述第四个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵。
  4. 根据权利要求1或2所述的方法，其特征在于，所述候选变换矩阵对的数量为四个；在所述两个变换矩阵中一个为DST4矩阵的变形，另一个为DCT2’矩阵的变形时，所述四个候选变换矩阵对中的第一个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵的变形，所述第一个变换矩阵对包括的水平方向变换矩阵为DST4矩阵的变形；
    所述四个候选变换矩阵对中的第二个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵的变形，所述第二个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵的变形；
    所述四个候选变换矩阵对中的第三个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵的变形，所述第三个变换矩阵对包括的水平方向变换矩阵为DST4矩阵的变形；
    所述四个候选变换矩阵对中的第四个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵的变形，所述第四个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵的变形。
  5. 根据权利要求1至4任一所述的方法，其特征在于，所述指示信息包括用于指示所述当前块进行逆变换处理的变换矩阵对中的垂直方向变换矩阵的标识，以及用于指示所述当前块进行逆变换处理的变换矩阵对中的水平方向变换矩阵的标识。
  6. 根据权利要求1至5任一所述的方法，其特征在于，所述根据所述当前块进行逆变换处理的变换矩阵对对所述当前块的反量化系数进行逆变换处理前，所述方法还包括：
    根据预设算法从DCT2矩阵推导出所述当前块进行逆变换处理的变换矩阵对所包括的变换矩阵。
  7. 根据权利要求6所述的方法，其特征在于，所述当前块进行逆变换处理的变换矩阵对包括DST4矩阵；所述DCT2矩阵的大小为64；
    所述根据预设算法从DCT2矩阵推导出所述当前块进行逆变换处理的变换矩阵对所包括的变换矩阵包括：
    根据如下公式从所述DCT2矩阵推导出所述DST4矩阵：
    Figure PCTCN2019106383-appb-100001
    其中，transMatrix表示所述DCT2矩阵，nTbs表示所述DST4矩阵的大小，0≤i≤nTbS–1，0≤j≤nTbS–1；偏移量64-nTbs表示列的偏移；偏移量
    Figure PCTCN2019106383-appb-100002
    表示行的偏移；(-1) j表示进行符号变换。
  8. 根据权利要求6或7所述的方法，其特征在于，所述当前块进行逆变换处理的变换矩阵对包括DCT2’矩阵；所述DCT2矩阵的大小为64；
    所述根据预设算法从DCT2矩阵推导出所述当前块进行逆变换处理的变换矩阵对所包括的变换矩阵包括：
    根据如下公式从所述DCT2矩阵推导出所述DCT2’矩阵：
    transMatrix[j][i×2 6-Log2(nTbs)]；
    其中，transMatrix表示所述DCT2矩阵，nTbs表示所述DCT2’的大小，0≤i≤nTbS–1，0≤j≤nTbS–1。
  9. 一种编码方法，其特征在于，包括：
    确定用于对当前残差块进行变换处理的变换矩阵对的指示信息，所述变换矩阵对包括水平方向变换矩阵和垂直方向变换矩阵；所述变换矩阵对是候选变换矩阵对中的一个，所述候选变换矩阵对所包括的水平方向变换矩阵和垂直方向变换矩阵均为预设的两个变换矩阵中的一个；所述两个变换矩阵中一个为DST4矩阵或DST4矩阵的变形，所述两个变换矩阵中的另一个为DCT2’矩阵或DCT2’矩阵的变形，其中，DCT2’矩阵为DCT2矩阵的转置矩阵；
    对通过所述变换矩阵对对所述当前残差块进行变换处理获得的变换系数进行量化处 理，以获得所述当前残差块的量化系数；
    对所述当前残差块的量化系数和所述指示信息进行熵编码处理；
    将熵编码处理后的所述变换矩阵对的指示信息和熵编码处理后的所述当前残差块的量化系数写入码流。
  10. 根据权利要求9所述的方法，其特征在于，所述DST4矩阵的变形是通过对所述DST4矩阵中的至少一部分行或至少一部分列的系数进行符号变换获得；或
    所述DCT2’矩阵的变形是通过对所述DCT2’矩阵中的至少一部分行或至少一部分列的系数进行符号变换获得。
  11. 根据权利要求9或10所述的方法，其特征在于，所述候选变换矩阵对的数量为四个；在所述两个变换矩阵中一个为DST4矩阵，另一个为DCT2’矩阵时，所述四个候选变换矩阵对中的第一个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵，所述第一个变换矩阵对包括的水平方向变换矩阵为DST4矩阵；
    所述四个候选变换矩阵对中的第二个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵，所述第二个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵；
    所述四个候选变换矩阵对中的第三个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵，所述第三个变换矩阵对包括的水平方向变换矩阵为DST4矩阵；
    所述四个候选变换矩阵对中的第四个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵，所述第四个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵。
  12. 根据权利要求9或10所述的方法，其特征在于，所述候选变换矩阵对的数量为四个；在所述两个变换矩阵中一个为DST4矩阵的变形，另一个为DCT2’矩阵的变形时，所述四个候选变换矩阵对中的第一个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵的变形，所述第一个变换矩阵对包括的水平方向变换矩阵为DST4矩阵的变形；
    所述四个候选变换矩阵对中的第二个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵的变形，所述第二个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵的变形；
    所述四个候选变换矩阵对中的第三个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵的变形，所述第三个变换矩阵对包括的水平方向变换矩阵为DST4矩阵的变形；
    所述四个候选变换矩阵对中的第四个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵的变形，所述第四个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵的变形。
  13. 一种视频解码器，其特征在于，包括：
    熵解码单元，用于解析接收的码流，以获得当前块进行逆变换处理的变换矩阵对的指示信息以及所述当前块的量化系数，所述变换矩阵对包括水平方向变换矩阵和垂直方向变换矩阵；
    逆量化单元，用于对所述当前块的量化系数进行逆量化处理以获得所述当前块的反量化系数；
    逆变换处理单元，用于根据所述指示信息从候选变换矩阵对中确定所述当前块进行逆 变换处理的变换矩阵对；所述候选变换矩阵对所包括的水平方向变换矩阵和垂直方向变换矩阵均为预设的两个变换矩阵中的一个；所述两个变换矩阵中一个为DST4矩阵或DST4矩阵的变形，所述两个变换矩阵中的另一个为DCT2’矩阵或DCT2’矩阵的变形，其中，DCT2’矩阵为DCT2矩阵的转置矩阵；根据所述当前块进行逆变换处理的变换矩阵对对所述当前块的反量化系数进行逆变换处理，以得到所述当前块的重建残差块；
    重构单元，用于基于所述当前块的重建残差块获得所述当前块的重构块。
  14. 根据权利要求13所述的视频解码器，其特征在于，所述DST4矩阵的变形是通过对所述DST4矩阵对应的矩阵中的至少一部分行或至少一部分列的系数进行符号变换获得；或
    所述DCT2’矩阵的变形是通过对所述DCT2’矩阵中的至少一部分行或至少一部分列的系数进行符号变换获得。
  15. 根据权利要求13或14所述的视频解码器，其特征在于，所述候选变换矩阵对的数量为四个；在所述两个变换矩阵中一个为DST4矩阵，另一个为DCT2’矩阵时，所述四个候选变换矩阵对中的第一个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵，所述第一个变换矩阵对包括的水平方向变换矩阵为DST4矩阵；
    所述四个候选变换矩阵对中的第二个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵，所述第二个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵；
    所述四个候选变换矩阵对中的第三个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵，所述第三个变换矩阵对包括的水平方向变换矩阵为DST4矩阵；
    所述四个候选变换矩阵对中的第四个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵，所述第四个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵。
  16. 根据权利要求13或14所述的视频解码器，其特征在于，所述候选变换矩阵对的数量为四个；在所述两个变换矩阵中一个为DST4矩阵的变形，另一个为DCT2’矩阵的变形时，所述四个候选变换矩阵对中的第一个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵的变形，所述第一个变换矩阵对包括的水平方向变换矩阵为DST4矩阵的变形；
    所述四个候选变换矩阵对中的第二个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵的变形，所述第二个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵的变形；
    所述四个候选变换矩阵对中的第三个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵的变形，所述第三个变换矩阵对包括的水平方向变换矩阵为DST4矩阵的变形；
    所述四个候选变换矩阵对中的第四个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵的变形，所述第四个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵的变形。
  17. 根据权利要求13至16任一所述的视频解码器，其特征在于，所述指示信息包括用于指示所述当前块进行逆变换处理的变换矩阵对中的垂直方向变换矩阵的标识，以及用于指示所述当前块进行逆变换处理的变换矩阵对中的水平方向变换矩阵的标识。
  18. 根据权利要求13至17任一所述的视频解码器，其特征在于，所述逆变换处理单 元还用于：根据预设算法从DCT2矩阵推导出所述当前块进行逆变换处理的变换矩阵对所包括的变换矩阵。
  19. 根据权利要求18所述的视频解码器，其特征在于，所述当前块进行逆变换处理的变换矩阵对包括DST4矩阵；所述DCT2矩阵的大小为64；
    所述逆变换处理单元具体用于：
    根据如下公式从所述DCT2矩阵推导出所述DST4矩阵：
    Figure PCTCN2019106383-appb-100003
    其中，transMatrix表示所述DCT2矩阵，nTbs表示所述DST4矩阵的大小，0≤i≤nTbS–1，0≤j≤nTbS–1；偏移量64-nTbs表示列的偏移；偏移量
    Figure PCTCN2019106383-appb-100004
    表示行的偏移；(-1) j表示进行符号变换。
  20. 根据权利要求18或19所述的视频解码器，其特征在于，所述当前块进行逆变换处理的变换矩阵对包括DCT2’矩阵；所述DCT2矩阵的大小为64；
    所述逆变换处理单元具体用于：
    根据如下公式从所述DCT2矩阵推导出所述DCT2’矩阵：
    transMatrix[j][i×2 6-Log2(nTbs)]；
    其中，transMatrix表示所述DCT2矩阵，nTbs表示所述DCT2’的大小，0≤i≤nTbS–1，0≤j≤nTbS–1。
  21. 一种视频编码器，其特征在于，包括：
    变换处理单元，用于确定用于对当前残差块进行变换处理的变换矩阵对的指示信息，所述变换矩阵对包括水平方向变换矩阵和垂直方向变换矩阵；所述变换矩阵对是候选变换矩阵对中的一个，所述候选变换矩阵对所包括的水平方向变换矩阵和垂直方向变换矩阵均为预设的两个变换矩阵中的一个；所述两个变换矩阵中一个为DST4矩阵或DST4矩阵的变形，所述两个变换矩阵中的另一个为DCT2’矩阵或DCT2’矩阵的变形，其中，DCT2’矩阵为DCT2矩阵的转置矩阵；
    量化单元，对通过所述变换矩阵对对所述当前残差块进行变换处理获得的变换系数进行量化处理，以获得所述当前残差块的量化系数；
    熵编码单元，用于对所述当前残差块的量化系数和所述指示信息进行熵编码处理；
    输出，用于将熵编码处理后的所述变换矩阵对的指示信息和熵编码处理后的所述当前残差块的量化系数写入码流。
  22. 根据权利要求21所述的视频编码器，其特征在于，所述DST4矩阵的变形是通过对所述DST4矩阵对应的矩阵中的至少一部分行或至少一部分列的系数进行符号变换获得；或
    所述DCT2’矩阵的变形是通过对所述DCT2’矩阵对应的矩阵中的至少一部分行或至 少一部分列的系数进行符号变换获得。
  23. 根据权利要求21或22所述的视频编码器，其特征在于，所述候选变换矩阵对的数量为四个；在所述两个变换矩阵中一个为DST4矩阵，另一个为DCT2’矩阵时，所述四个候选变换矩阵对中的第一个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵，所述第一个变换矩阵对包括的水平方向变换矩阵为DST4矩阵；
    所述四个候选变换矩阵对中的第二个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵，所述第二个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵；
    所述四个候选变换矩阵对中的第三个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵，所述第三个变换矩阵对包括的水平方向变换矩阵为DST4矩阵；
    所述四个候选变换矩阵对中的第四个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵，所述第四个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵。
  24. 根据权利要求21或22所述的视频编码器，其特征在于，所述候选变换矩阵对的数量为四个；在所述两个变换矩阵中一个为DST4矩阵的变形，另一个为DCT2’矩阵的变形时，所述四个候选变换矩阵对中的第一个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵的变形，所述第一个变换矩阵对包括的水平方向变换矩阵为DST4矩阵的变形；
    所述四个候选变换矩阵对中的第二个变换矩阵对包括的垂直方向变换矩阵为DST4矩阵的变形，所述第二个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵的变形；
    所述四个候选变换矩阵对中的第三个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵的变形，所述第三个变换矩阵对包括的水平方向变换矩阵为DST4矩阵的变形；
    所述四个候选变换矩阵对中的第四个变换矩阵对包括的垂直方向变换矩阵为DCT2’矩阵的变形，所述第四个变换矩阵对包括的水平方向变换矩阵为DCT2’矩阵的变形。
  25. 一种视频解码器，其特征在于，包括用于执行如权利要求1至8任一所述的方法的执行电路。
  26. 一种视频解码器，其特征在于，包括：
    至少一个处理器；和
    与所述至少一个处理器耦合的非易失性计算机可读存储介质，所述非易失性计算机可读存储介质存储有可被所述至少一个处理器执行的计算机程序，当所述计算机程序被所述至少一个处理器执行时，使得所述视频解码器用于执行如权利要求1至8任一所述的方法。
  27. 一种计算机可读存储介质，用于存储可被处理器执行的计算机程序，当所述计算机程序被所述至少一个处理器执行时，执行如权利要求1至12任一所述的方法。
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