WO2020097932A1 - 一种阻抗调整电路、芯片及参考电压产生电路 - Google Patents

一种阻抗调整电路、芯片及参考电压产生电路 Download PDF

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Publication number
WO2020097932A1
WO2020097932A1 PCT/CN2018/115998 CN2018115998W WO2020097932A1 WO 2020097932 A1 WO2020097932 A1 WO 2020097932A1 CN 2018115998 W CN2018115998 W CN 2018115998W WO 2020097932 A1 WO2020097932 A1 WO 2020097932A1
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Prior art keywords
circuit
clock
reference voltage
transistor
operational amplifier
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PCT/CN2018/115998
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English (en)
French (fr)
Inventor
黄慕理
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2018/115998 priority Critical patent/WO2020097932A1/zh
Priority to CN201880002327.9A priority patent/CN109643139B/zh
Publication of WO2020097932A1 publication Critical patent/WO2020097932A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors

Definitions

  • the present application relates to a semiconductor circuit, in particular to an impedance adjustment circuit, a chip and a reference voltage generating circuit.
  • Termination resistors are set at the receiving end of many communication systems.
  • the current practice is to set the termination resistor in the chip to reduce the interference of the parasitic inductance effect on the received signal.
  • the internal termination resistance of the chip is often due to the deviation of the manufacturing process
  • the error of its resistance value for example, the resistance value of the polysilicon resistor (polyresistor) can be as high as about ⁇ 20%.
  • the resistance value error of the receiving terminal resistance will directly affect the signal-to-noise ratio (SNR) of the received signal It is necessary to improve the accuracy of the terminal resistance of the receiving end.
  • SNR signal-to-noise ratio
  • an innovative termination resistance correction method is needed to improve the accuracy of the termination resistance at the receiving end and avoid the use of additional pins and external precision reference resistors.
  • One of the purposes of the present application is to disclose an impedance adjustment circuit, a chip and a reference voltage generating circuit to solve the above problems.
  • An embodiment of the present application discloses an impedance adjustment circuit for determining the resistance value of a terminal resistance unit.
  • the terminal resistance unit includes a plurality of resistors.
  • the impedance adjustment circuit includes: a current mirror to provide a first reference Current and a second reference current, wherein the current mirror uses the first reference current mirror to emit the second reference current; a reference voltage generating circuit based at least on the first reference current, the first clock, and the second clock, Generating a reference voltage; a switch group including a plurality of switches, the on and off of the plurality of switches are used to change an equivalent resistance value of the terminal resistance unit, the second reference current flows through the terminal resistance unit, and
  • the termination resistance unit has a termination resistance voltage corresponding to the equivalent resistance value in response to the second reference current; and a comparator that generates a comparison result based on the reference voltage and the termination resistance voltage; the control unit based on The comparison result controls the on and off of multiple switches in the switch group.
  • An embodiment of the present application discloses a chip including a terminal resistance unit and the impedance adjustment circuit.
  • the impedance adjustment circuit is used to adjust an equivalent resistance value of the terminal resistance unit.
  • An embodiment of the present application discloses a reference voltage generating circuit that generates a reference voltage according to a reference current, a first clock, and a second clock, including: a first circuit for accumulating the reference current The provided positive charge; a second circuit for storing the positive charge accumulated in the first circuit to form the reference voltage; and an operational amplifier, the negative input terminal of the operational amplifier is coupled to the first circuit And the second circuit, the positive input terminal of the operational amplifier is coupled to a ground voltage, and the output terminal of the operational amplifier generates the reference voltage; the first clock and the second clock are generated from the same clock source , The same frequency, and the first clock is used to start the first circuit, the second clock is used to start the second circuit, the first clock and the second clock will not start the The first circuit and the second circuit.
  • FIG. 1 is a schematic diagram of an embodiment of an impedance adjustment circuit for adjusting the terminal resistance value of the present disclosure.
  • FIG. 2 is a schematic diagram of an embodiment of a terminal resistance unit and a switch group of the impedance adjustment circuit shown in FIG. 1.
  • FIG. 3 is a schematic diagram of the impedance adjustment circuit shown in FIG. 1 configured to perform a signal receiving mode.
  • 4 to 6 are schematic diagrams of the process of adjusting the termination resistance unit by the impedance adjustment circuit shown in FIG. 1.
  • FIG. 7 is a waveform diagram of a process of adjusting the termination resistance unit by the impedance adjustment circuit shown in FIG. 1. Among them, the reference signs are described as follows:
  • Termination resistance unit
  • first and second features are in direct contact with each other; and may also include additional components are formed between the first and second features, so that the first and second features may not have direct contact.
  • present disclosure may reuse component symbols and / or reference numerals in various embodiments. Such repeated use is based on the purpose of brevity and clarity, and does not itself represent the relationship between the different embodiments and / or configurations discussed.
  • spatially relative terms here such as “below”, “below”, “below”, “above”, “above”, and similar ones, may be for the convenience of illustration The relationship between a component or feature shown relative to another component or feature.
  • the meaning of these spatially relative words also covers a variety of different orientations in which the device is used or operated. The device may be placed in other orientations (eg, rotated 90 degrees or in other orientations), and these spatially relative description words should be interpreted accordingly.
  • LVDS Low-Voltage Differential Signaling
  • MIPI Mobile Industry Processor Interface
  • FIG. 1 is a schematic diagram of an embodiment of an impedance adjustment circuit for adjusting the resistance value of a terminating resistor.
  • the circuit 100 can be installed in a communication system to adjust the terminal resistance value of the receiving end, for example, the receiving end of a low voltage differential signal standard.
  • the circuit 100 is arranged in the chip as a whole, without the need for additional components outside the chip, the purpose of adjusting the terminal resistance value of the receiving end can be achieved, so that the system does not need to additionally set an accurate reference resistance outside the chip, and avoid Increase the pin of the chip to use the precision reference resistor outside the chip to correct the terminal resistance value of the receiving end.
  • the circuit 100 includes a comparator CP.
  • Reference voltage generating circuit includes a first circuit 104, second circuit 106 and the OP an operational amplifier, a reference voltage generating circuit 110 may be used to provide a stable reference voltage V out.
  • the circuit 100 adjusts the equivalent resistance value R terminal of the terminal resistance unit 108 according to the reference voltage V out .
  • circuit 100 may be according to the reference voltage V out terminal resistance correcting unit 108, so that the resistance value of the terminal resistor R terminal unit equivalent resistance value of the terminal as much as possible close to the pre-108.
  • the switches S R1 and S R2 When the communication system set in the circuit 100 is in the initial state after power-on or reset, the switches S R1 and S R2 will be turned on, as shown in FIGS. 1 and 4 to 6, the circuit 100 is in the correction state to correct the terminal Resistance unit 108; After the circuit 100 corrects the termination resistance unit 108, the switches S R1 and S R2 will stop conducting. As shown in FIG. 3, the receiving end of the communication system provided by the circuit 100 can start signal reception.
  • the reference voltage generating circuit 110 is coupled to the first clock CLK 1 and the second clock CLK 2 , and the first circuit 104 and the second circuit 106 are turned on or off according to the first clock CLK 1 and the second clock CLK 2 respectively .
  • the first clock CLK 1 and the second clock CLK 2 are generated from the same clock source with the same frequency, and the first clock CLK 1 and the second clock CLK 2 will not be simultaneously raised to the high bit of logic 1 status.
  • the horizontal axis is time T
  • the first clock CLK 1 and the second clock CLK 2 have the same frequency
  • the duty cycle is 50%, that is, the phase difference is exactly 90 degrees.
  • the duty ratio of the first clock CLK 1 and the second clock CLK 2 can be freely adjusted according to the required working time of the first circuit 104 and the second circuit 106, for example, the first clock CLK 1 and The duty ratio of the second clock CLK 2 may be 40% and 60%, respectively, or the duty ratio of the first clock CLK 1 and the second clock CLK 2 may be 45% and 45%, respectively.
  • the first circuit 104 When the first circuit 104 is activated, the first circuit 104 continuously accumulates the positive charge provided by the current I REF .
  • the second circuit 106 starts and stores the positive charge collected by the first circuit 104 to form the reference voltage V out .
  • the circuit 100 will correct the terminal resistance unit 108 according to the reference voltage V out so that the equivalent value R terminal of the terminal resistance unit 108 is as close as possible to the preset terminal resistance value. The detailed operations of the first circuit 104 and the second circuit 106 will be described below.
  • the current mirror 102 in FIG. 1 includes a first transistor T 1 and a second transistor T 2.
  • the first transistor T 1 and the second transistor T 2 are both P-type transistors.
  • One end of the current mirror 102 is coupled to the voltage source V REF , and provides the reference current I REF to the reference voltage generating circuit 110, and provides the reference current M * I REF to the termination resistance unit 108 by adjusting the first transistor T 1 and the first
  • the size of the two transistors T 2 can be adjusted to the size of M. In general applications, M is greater than 1, but this disclosure is not limited to this.
  • the current mirror 102 utilizes the first reference current I REF A reference current I REF has a multiple relationship of the second reference current M * I REF .
  • the reference current I REF causes the reference voltage generating circuit 110 to generate the reference voltage V out to the negative input terminal of the comparator CP, and the reference current M * I REF flowing through the terminal resistance unit 108 generates the terminal resistance voltage V R to the comparator CP
  • the terminal resistance unit 108 has a terminal resistance voltage V R in response to the reference current M * I REF
  • the comparator CP generates a comparison result based on the difference between the reference voltage V out and the terminal resistance voltage V R Therefore , the equivalent resistance value R terminal of the terminal resistance unit 108 will change according to the comparison result, so that the reference voltage V out and the terminal resistance voltage V R are equal.
  • control unit 112 can be used to convert the reference voltage V out into an N-bit digital signal to control the switch 109, thereby adjusting the terminal resistance unit 108, where N is a positive integer greater than or equal to 1, and the control unit 112 can include an analog The digital converter and / or other encoding units correspondingly control the terminating resistance unit 108.
  • the termination resistance unit 108 may be formed by a plurality of resistors R 1 ⁇ R N (for example, polysilicon resistors) connected in parallel, and the plurality of resistors are controlled by switches 109 respectively, and the switches 109 may include a plurality of switches S 1 ⁇ S N , a plurality of switches S The on-off of 1 ⁇ S N is used to change the equivalent resistance value R terminal of the terminal resistance unit 108, and the second reference current M * I REF flows through the terminal resistance unit 108 so that the terminal resistance unit 108 has the corresponding equivalent resistance value R terminal the terminal voltage V R of the resistor in response to a second reference current M * I REF, S N, and a plurality of parallel resistors R N 1 R & lt plurality of switches S 1 in FIG.
  • resistors R 1 ⁇ R N for example, polysilicon resistors
  • the terminating resistance unit 108 can also be configured as shown in FIG. 2, that is, multiple switches S 1 ⁇ S N and multiple resistors R, respectively 1 ⁇ RN in series.
  • the circuit other than the terminal resistance unit 108 in the circuit 100 is an impedance adjustment circuit for adjusting the terminal resistance unit 108.
  • the impedance adjustment circuit includes a current mirror 102, a reference voltage generation circuit 110, a comparator CP Control unit 112.
  • the first transistor T 1 and the second transistor T 2 output the reference currents I REF and M * I REF to the reference voltage generating circuit 110 and the terminal resistance unit 108, respectively, since the reference currents I REF and M * I REF remain fixed to each other M times the ratio between, so long as the constant M, the reference current I REF error itself does not affect the result of the comparator CP is adjusted according to the resistance unit terminal V out and the reference voltage difference between the terminal voltage V R of the resistor 108. That is to say, the accuracy of the reference current I REF itself does not affect the accuracy of the correction terminal resistance unit 108, so there is no need to spend extra cost to generate an accurate reference current I REF .
  • the equivalent resistance R EQ of the reference voltage generating circuit 110 will be the corrected terminal resistance unit 108
  • the equivalent resistance value is about M times of R terminal . Please note that, depending on the number of adjustable segments of the terminal resistance unit 108, it may not necessarily be completely equal to M times.
  • the present disclosure uses capacitors and transistors to provide the equivalent resistance R EQ of the reference voltage generating circuit 110.
  • the first circuit 104 of the reference voltage generating circuit 110 includes an N-type third transistor T 3 and an N-type fourth transistor T 4 And the first capacitor C 1 , wherein the third transistor T 3 and the first capacitor C 1 are connected in series between the transistor T 2 and the negative input terminal of the operational amplifier OP in sequence.
  • the fourth transistor T 4 is connected across the negative input terminal and the output terminal of the operational amplifier OP, and the gates of the third transistor T 3 and the fourth transistor T 4 are coupled to the first clock CLK 1 .
  • the second circuit 106 of the reference voltage generating circuit 110 includes an N-type fifth transistor T 5 and a second capacitor C 2 , wherein one end of the fifth transistor T 5 is coupled to the third transistor T 3 and the first capacitor of the first circuit 104 Between C 1 , the other end of the fifth transistor T 5 is coupled to the ground voltage GND.
  • the second capacitor C 2 is connected in parallel with the fourth transistor T 4 , that is, like the fourth transistor T 4 , it is connected between the negative input terminal and the output terminal of the operational amplifier OP.
  • the gate of the fifth transistor T 5 is coupled to the second clock CLK 2 .
  • the positive input terminal of the operational amplifier OP is coupled to the ground voltage GND.
  • the operational amplifier OP forms a negative feedback
  • the right side P 2 of the first capacitor C 1 is a virtual ground and is equivalent to a passive capacitor charged by the current I REF , because the fourth transistor T 4 is turned on
  • the two ends of the second capacitor C 2 are short-circuited and will not be charged.
  • the left side P 1 of the first capacitor C 1 will continue to accumulate the positive charge provided by the current I REF in a substantially linear manner, and the right side P 2 of the first capacitor C 1 will correspondingly accumulate negative charges until The first clock CLK 1 drops to logic 0, the third transistor T 3 and the fourth transistor T 4 are not turned on, and the current I REF stops charging the first capacitor C 1 . It can be seen from the voltage V in in FIG. 7 that the voltage of the left side P 1 of the first capacitor C 1 rises when the first clock CLK 1 is logic 1, and the reference voltage V out is fixed at 0 at this time.
  • the second clock CLK 2 is logic 1
  • the second circuit of the fifth transistor T 5 is turned 106
  • the first capacitor C 1 P 1 momentarily left the ground to become a ground voltage
  • a first capacitor C 1 P 1 left positive charges are collected and disappearing moment
  • the first capacitor C 1 and P 2 on the right side will be accumulated negative charge to the second capacitor C 3 accumulation of P 2 on the left side
  • the second capacitor C 2 P 4 on the right will gradually generate a positive charge accordingly.
  • the amount of positive charge generated on the right side P 4 of the second capacitor C 2 is stabilized, and the reference voltage V out is formed. It can be seen from the reference voltage V out of FIG.
  • the comparator CP can be based on the difference voltage V out and the reference voltage V R of the terminal resistor to adjust the resistance of the terminal unit 108.
  • the loop bandwidth of the operational amplifier OP should be greater than or equal to the frequency F of the first clock CLK 1 and the second clock CLK 2 , in other words, the frequency of the first clock CLK 1 does not exceed the loop bandwidth range of the operational amplifier OP, so In order to ensure a stable reference voltage V out before the second clock CLK 2 transitions from logic 1 to logic 0.
  • the equivalent resistance R EQ of the reference voltage generating circuit 110 when the second clock CLK 2 is logic 1 can be expressed as:
  • C 1 and C 2 are the values of the first capacitor C 1 and the second capacitor C 2
  • F is the frequency of the first clock CLK 1 and the second clock CLK 2
  • duty_cycle (CLK 1 ) is the proportion of the first clock CLK 1 Air ratio.
  • the accuracy of the equivalent resistance R EQ is mainly occupied by the frequency F of the first capacitor C 1 , the second capacitor C 2 , the frequency F of the first clock CLK 1 and the second clock CLK 2 and the first clock CLK 1 Duty cycle (CLK 1 ) affects.
  • the error value of the capacitance in the chip will be much smaller than the error value of the resistance in the chip.
  • the first capacitor C 1 and the second capacitor C 2 in the chip are metal-insulator-metal type (Metal -Insulator-Metal (MIM) capacitors, the error is about ⁇ 2 to ⁇ 5%, more than ⁇ 20% of the crystalline silicon resistance is much smaller, and the error of the frequency F and duty cycle (CLK 1 ) is only about ⁇ 2%. It can be seen that the error value of the equivalent resistance R EQ generated by the reference voltage generating circuit 110 is much smaller than the error value of the on-chip resistance.
  • MIM Metal -Insulator-Metal
  • the circuit 100 will repeatedly operate in FIGS. 4-6 until the termination resistance unit 108 is adjusted.
  • the disclosed circuit 100 is entirely located in the chip, that is to say, the method of the impedance adjustment circuit of the present disclosure does not need to use an additional reference resistor outside the chip to help calibrate the terminal resistance in the chip, eliminating at least one pin and external Accurately reference the cost of the resistor, while maintaining the accuracy of the terminating resistor.
  • the present application also provides a chip including the circuit 100.
  • the circuit 100 can be used in a fingerprint recognition chip.
  • the circuit 100 can be used in a large-screen optical fingerprint recognition chip, since the large-screen optical fingerprint recognition chip has multiple sensors, each of which At least one accurate termination resistor is needed to avoid signal reflection during data transmission.
  • the use of external termination resistors will have packaging and cost considerations, and the use of the on-chip circuit 100 can save additional pins and external accurate reference Resistance, the cost is relatively advantageous.
  • the calibration can be turned on according to the need, the relevant circuit can be closed after the calibration. It is not executed in the background at any time, and the power consumption of the system is almost negligible.

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Abstract

本申请公开了一种阻抗调整电路，用来决定终端电阻单元的电阻值，所述终端电阻单元包括多个电阻，所述阻抗调整电路包括：电流镜，用以提供第一参考电流和第二参考电流，其中所述电流镜利用所述第一参考电流镜射出所述第二参考电流；参考电压产生电路，至少依据所述第一参考电流、第一时钟以及第二时钟，产生参考电压；开关组，包括多个开关；以及比较器，依据所述参考电压和所述终端电阻电压来产生比较结果；控制单元，依据所述比较结果来控制所述开关组中多个开关的通断。

Description

一种阻抗调整电路、芯片及参考电压产生电路 技术领域
本申请涉及半导体电路，尤其涉及一种阻抗调整电路、芯片及参考电压产生电路。
背景技术
在许多通讯系统的接收端都设置有终端电阻，现有的作法多是将终端电阻设置在芯片内以降低寄生电感效应对接收讯号的干扰，然而，芯片内部的终端电阻往往因为制程的偏移造成其电阻值的误差，例如多晶硅电阻(poly resistor)的电阻值误差可高达约±20％，接收端终端电阻的电阻值误差会直接地影响接收讯号的信噪比(SNR)，换句话说，提升接收端终端电阻的精准度是必须的。
针对此一问题，常见的作法包括利用芯片外部的额外参考电阻来帮助校准芯片内的终端电阻，但此作法的缺点是需要额外增加一个引脚和外部的精准参考电阻。
因此，需要一种创新的终端电阻校正方法来提升接收端终端电阻的精准度且避免使用额外的引脚和外部精准参考电阻。
发明内容
本申请的目的之一在于公开一种阻抗调整电路、芯片及参考电压产生电路，来解决上述问题。
本申请的一实施例公开了一种阻抗调整电路，用来决定终端电阻单元的电阻值，所述终端电阻单元包括多个电阻，所述阻抗调整电路包括：电流镜，用以提供第一参考电流和第二参考电流，其中所述电流镜利用所述第一参考电流镜射出所述第二参考电流；参考电压产生电路，至少依据所述第一参考电流、 第一时钟以及第二时钟，产生参考电压；开关组，包括多个开关，所述多个开关的通断用来改变所述终端电阻单元的等效电阻值，所述第二参考电流流经所述终端电阻单元，并使所述终端电阻单元具有对应所述等效电阻值的终端电阻电压以响应所述第二参考电流；以及比较器，依据所述参考电压和所述终端电阻电压来产生比较结果；控制单元，依据所述比较结果来控制所述开关组中多个开关的通断。
本申请的一实施例公开了一种芯片，包括终端电阻单元以及所述的阻抗调整电路，所述阻抗调整电路用于调整所述终端电阻单元的等效电阻值。
本申请的一实施例公开了一种参考电压产生电路，所述参考电压产生电路依据参考电流、第一时钟以及第二时钟，产生参考电压，包括：第一电路，用来累积所述参考电流所提供的正电荷；第二电路，用来将所述第一电路累积的正电荷储存起来形成所述参考电压；以及运算放大器，所述运算放大器的负输入端耦接至所述第一电路和所述第二电路，所述运算放大器的正输入端耦接至地电压，所述运算放大器输出端产生所述参考电压；所述第一时钟和所述第二时钟产生自同一个时钟源，频率相同，且所述第一时钟用来启动所述第一电路，所述第二时钟用来启动所述第二电路，所述第一时钟和所述第二时钟不会同时启动所述第一电路和所述第二电路。
附图说明
图1是本揭露用来调整终端电阻值的阻抗调整电路的实施例的示意图。
图2是图1所示的阻抗调整电路的终端电阻单元以及开关组的实施例的示意图。
图3是图1所示的阻抗调整电路设置为进行讯号接收模式的示意图。
图4～图6是图1所示的阻抗调整电路调整终端电阻单元的过程示意图。
图7是图1所示的阻抗调整电路调整终端电阻单元的过程的波型图。其中，附图标记说明如下：
100                                     电路
102                                     电流镜
104                                     第一电路
106                                     第二电路
108                                     终端电阻单元
109                                     开关组
110                                     参考电压产生电路
T 1、T 2、T 3、T 4、T 5                      晶体管
C 1、C 2                                  电容
OP                                      运算放大器
CP                                      比较器
112                                     控制单元
S R1、S R2                                开关
R 1～R N                                  电阻
S 1～S N                                  开关
I REF                                    电流
V in                                     电压
V out                                    参考电压
CLK 1                                    第一时钟
CLK 2                                    第二时钟
V REF                                    电压源
V R                                      终端电阻电压
P 1                                      电容C 1左侧
P 2                                      电容C 1右侧
P 3                                      电容C 2左侧
P 4                                      电容C 2右侧
具体实施方式
以下揭示内容提供了多种实施方式或例示，其能用以实现本揭示内容的不同特征。下文所述之组件与配置的具体例子系用以简化本揭示内容。当可想见， 这些叙述仅为例示，其本意并非用于限制本揭示内容。举例来说，在下文的描述中，将一第一特征形成于一第二特征上或之上，可能包括某些实施例其中所述的第一与第二特征彼此直接接触；且也可能包括某些实施例其中还有额外的组件形成于上述第一与第二特征之间，而使得第一与第二特征可能没有直接接触。此外，本揭示内容可能会在多个实施例中重复使用组件符号和/或标号。此种重复使用乃是基于简洁与清楚的目的，且其本身不代表所讨论的不同实施例和/或组态之间的关系。
再者，在此处使用空间上相对的词汇，譬如「之下」、「下方」、「低于」、「之上」、「上方」及与其相似者，可能是为了方便说明图中所绘示的一组件或特征相对于另一或多个组件或特征之间的关系。这些空间上相对的词汇其本意除了图中所绘示的方位之外，还涵盖了装置在使用或操作中所处的多种不同方位。可能将所述设备放置于其他方位(如，旋转90度或处于其他方位)，而这些空间上相对的描述词汇就应该做相应的解释。
虽然用以界定本申请较广范围的数值范围与参数皆是约略的数值，此处已尽可能精确地呈现具体实施例中的相关数值。然而，任何数值本质上不可避免地含有因个别测试方法所致的标准偏差。在此处，「约」通常系指实际数值在一特定数值或范围的正负10％、5％、1％或0.5％之内。或者是，「约」一词代表实际数值落在平均值的可接受标准误差之内，视本申请所属技术领域中具有通常知识者的考虑而定。当可理解，除了实验例之外，或除非另有明确的说明，此处所用的所有范围、数量、数值与百分比(例如用以描述材料用量、时间长短、温度、操作条件、数量比例及其他相似者)均经过「约」的修饰。因此，除非另有相反的说明，本说明书与附随申请专利范围所揭示的数值参数皆为约略的数值，且可视需求而更动。至少应将这些数值参数理解为所指出的有效位数与套用一般进位法所得到的数值。在此处，将数值范围表示成由一端点至另一端点或介于二端点之间；除非另有说明，此处所述的数值范围皆包括端点。
许多通讯系统都需要在传输线的终端设置终端电阻，以避免形成反射波，干扰原信号，使信号到达传输线末端后不反射。例如低电压差分信号(Low-Voltage Differential Signaling,LVDS)标准规范了100欧姆的终端电阻、行动产业处理器接口(Mobile Industry Processor Interface,MIPI) 标准规范了50欧姆的终端电阻等等。
图1是本揭露用来调整终端电阻的电阻值的阻抗调整电路的实施例的示意图。电路100可设置于通讯系统中，用来调整接收端的终端电阻值，例如低电压差分信号标准的接收端。在本揭露中，电路100整体设置在芯片中，不需额外的芯片外的其他组件，即可达到调整接收端的终端电阻值的目的，使系统不需要额外设置芯片外部的精准参考电阻，也避免增加芯片引脚来使用芯片外部的精准参考电阻以校正接收端的终端电阻值。电路100包括比较器CP，比较器CP的一端，例如负输入端，耦接至参考电压产生电路110，比较器CP的另一端，例如正输入端，耦接至终端电阻单元108。参考电压产生电路包括第一电路104、第二电路106以及运算放大器OP，参考电压产生电路110可用来提供稳定的参考电压V out。电路100会依据参考电压V out来调整终端电阻单元108的等效电阻值R terminal。换句话说，电路100会依据参考电压V out来校正终端电阻单元108，使终端电阻单元108的等效电阻值R terminal尽量地接近预设的终端电阻值。
当电路100所设置的通讯系统在上电或重置后的初始状态时，开关S R1和S R2会导通，如图1和图4～6所示，使电路100处于校正状态以校正终端电阻单元108；电路100校正完终端电阻单元108后，开关S R1和S R2会停止导通，如图3所示，电路100所设置的通讯系统的接收端便可开始进行讯号的接收。
详细来看，参考电压产生电路110耦接至第一时钟CLK 1以及第二时钟CLK 2，第一电路104和第二电路106分别依据第一时钟CLK 1以及第二时钟CLK 2来启动或关闭，在本实施例中，第一时钟CLK 1和第二时钟CLK 2产生自同一个时钟源，频率相同，且第一时钟CLK 1和第二时钟CLK 2不会同时拉升为逻辑1的高位状态。参阅图7可以看到，横轴为时间T，第一时钟CLK 1和第二时钟CLK 2彼此频率相同，占空比(duty cycle)皆为50％，即相位差刚好为90度。简单来说，第一时钟CLK 1为逻辑1时，第一电路104会工作，第二电路106会停止工作；第二时钟CLK 2为逻辑1时，第一电路104会停止工作，第二电路106会工作。因此，在实际的应用中，第一时钟CLK 1和第二时钟CLK 2的占空比可依据第一电路104和第二电路106所需的工作时间自由地调整，例如第一时钟CLK 1和第二时钟CLK 2的占空比可以分别为40％和60％，或第一时钟CLK 1和第二时钟CLK 2的占空 比可以分别为45％和45％。
当第一电路104启动时，第一电路104会持续地累积电流I REF所提供的正电荷。当第一电路104停用后，第二电路106启动并且将第一电路104收集到的正电荷储存起来形成参考电压V out。如前所述，电路100会依据参考电压V out来校正终端电阻单元108，使终端电阻单元108的等效值R terminal尽量地接近预设的终端电阻值。以下将说明第一电路104和第二电路106的详细操作。
图1中的电流镜102包括第一晶体管T 1和第二晶体管T 2，在此实施例中，第一晶体管T 1和第二晶体管T 2均为P型晶体管。电流镜102的一端耦接至电压源V REF，并提供参考电流I REF给参考电压产生电路110，而且提供参考电流M*I REF给终端电阻单元108，藉由调整第一晶体管T 1和第二晶体管T 2的尺寸，可以调整M的大小，在一般的应用中，M大于1，但本揭露不以此为限，换句话说，电流镜102利用第一参考电流I REF镜射出和第一参考电流I REF具有倍数关系的第二参考电流M*I REF。参考电流I REF会使参考电压产生电路110产生参考电压V out至比较器CP的负输入端，而参考电流M*I REF流经终端电阻单元108则会产生终端电阻电压V R至比较器CP的正输入端，换句话说，终端电阻单元108具有终端电阻电压V R以响应参考电流M*I REF，比较器CP则会依据参考电压V out和终端电阻电压V R的差异来产生比较结果，终端电阻单元108的等效电阻值R terminal，则会依据所述比较结果而改变，使参考电压V out和终端电阻电压V R相等。
具体来说，可利用控制单元112来将参考电压V out转换为N位的数字讯号来控制开关109，进而调整终端电阻单元108，其中N为大于等于1的正整数，控制单元112可包括模拟数字转换器及/或其他的编码单元来相对应的控制终端电阻单元108。终端电阻单元108可以是多个电阻R 1～R N(例如多晶硅电阻)并联形成，所述多个电阻分别受到开关109控制，开关109可包括多个开关S 1～S N，多个开关S 1～S N的通断用来改变终端电阻单元108的等效电阻值R terminal，而第二参考电流M*I REF流经终端电阻单元108使终端电阻单元108具有对应等效电阻值R terminal的终端电阻电压V R以响应第二参考电流M*I REF，图1中的多个开关S 1～S N分别和多个电阻R 1～R N并联，且多个开关S 1～S N分别被N位的数字讯号控制。但本揭露对终端电阻单元108的架构并不多做限制，举例来说，亦可以如图2所示的方式配置终端电阻单元108，即多个开关S 1～S N分别和多个 电阻R 1～R N串联。
回到图1，电路100中除了终端电阻单元108以外的电路为阻抗调整电路，用以调整终端电阻单元108，例如所述阻抗调整电路包括电流镜102、参考电压产生电路110、比较器CP以及控制单元112。
第一晶体管T 1和第二晶体管T 2分别将参考电流I REF和M*I REF输出给参考电压产生电路110和终端电阻单元108，由于参考电流I REF和M*I REF彼此之间维持固定M倍的比例关系，因此只要M不变，参考电流I REF本身产生误差并不会影响比较器CP依据参考电压V out和终端电阻电压V R的差异来调整终端电阻单元108的结果。也就是说，参考电流I REF本身的精准度并不影响校正终端电阻单元108的精准度，因此并不需要花费额外的成本产生一个精准的参考电流I REF。由于比较器CP会驱使终端电阻电压V R往参考电压V out来靠拢，因此最终终端电阻电压V R会大约等于参考电压V out。又因为流经参考电压产生电路110和终端电阻单元108的电流分别为参考电流I REF和M*I REF，所以参考电压产生电路110的等效电阻R EQ会是校正完成的终端电阻单元108的等效电阻值R terminal的约M倍，请注意，视终端电阻单元108的可调段数而定，实际上不一定会完全等于M倍。
本揭露利用电容和晶体管来提供参考电压产生电路110的等效电阻R EQ，具体而言，参考电压产生电路110的第一电路104包括N型第三晶体管T 3、N型第四晶体管T 4和第一电容C 1，其中第三晶体管T 3和第一电容C 1依序串接于晶体管T 2和运算放大器OP的负输入端之间。第四晶体管T 4则跨接于运算放大器OP的负输入端和输出端之间，第三晶体管T 3和第四晶体管T 4的闸极耦接至第一时钟CLK 1。参考电压产生电路110的第二电路106包括N型第五晶体管T 5和第二电容C 2，其中第五晶体管T 5的一端耦接于第一电路104的第三晶体管T 3和第一电容C 1之间，第五晶体管T 5的另一端则耦接至地电压GND。第二电容C 2则并联第四晶体管T 4，即和第四晶体管T 4一样，跨接于运算放大器OP的负输入端和输出端之间。第五晶体管T 5的闸极耦接至第二时钟CLK 2。运算放大器OP的正输入端耦接至地电压GND。
请参阅图4，当第一时钟CLK 1为逻辑1时，第一电路104的第三晶体管T 3和第四晶体管T 4导通，第二电路106的第五晶体管T 5不导通，由于第四晶体管 T 4导通，运算放大器OP形成负回授，第一电容C 1的右侧P 2为虚拟接地而等效为一个被动电容被电流I REF充电，因为第四晶体管T 4导通，第二电容C 2的两端是短路状态，不会被充电。具体来说，第一电容C 1左侧P 1会持续地以实质线性的方式累积电流I REF所提供的正电荷，第一电容C 1右侧P 2则会相对应地聚集负电荷，直到第一时钟CLK 1降为逻辑0，第三晶体管T 3和第四晶体管T 4不导通，电流I REF停止对第一电容C 1充电。由图7的电压V in可见第一时钟CLK 1为逻辑1时第一电容C 1左侧P 1的电压上升情形，此时参考电压V out被固定在0。
请参阅图5，接着第二时钟CLK 2为逻辑1，第二电路106的第五晶体管T 5导通，因此第一电容C 1左侧P 1会瞬间成为接地为地电压，第一电容C 1左侧P 1收集到的正电荷被中和瞬间消失，而第一电容C 1右侧P 2聚集的负电荷会往第二电容C 2的左侧P 3聚集，因此第二电容C 2的右侧P 4会相对应地逐渐生成正电荷。如图6所示，最终第二电容C 2右侧P 4生成的正电荷数量达到稳定，并形成参考电压V out。由图7的参考电压V out可见第二时钟CLK 2为逻辑1时第二电容C 2右侧P 4的电压上升情形，电压V in被固定在0。有了稳定的参考电压V out，比较器CP便可依据参考电压V out和终端电阻电压V R的差异来调整终端电阻单元108。请注意，运算放大器OP的回路带宽应大于或等于第一时钟CLK 1和第二时钟CLK 2的频率F，换句话说，第一时钟CLK 1的频率不超过运算放大器OP的回路带宽范围，这样才能确保在第二时钟CLK 2从逻辑1转换到逻辑0之前得到稳定的参考电压V out。
参考电压产生电路110在第二时钟CLK 2为逻辑1的等效电阻R EQ可以表示为：
Figure PCTCN2018115998-appb-000001
其中C 1、C 2为第一电容C 1、第二电容C 2的值，F是第一时钟CLK 1和第二时钟CLK 2的频率，duty_cycle(CLK 1)为第一时钟CLK 1的占空比。
由以上数学式可知，等效电阻R EQ的准确度主要受到第一电容C 1、第二电容C 2、第一时钟CLK 1和第二时钟CLK 2的频率F和第一时钟CLK 1的占空比duty_cycle(CLK 1)影响。一般来说，芯片内的电容的误差值会远小于芯片内电阻的误差值，例如本实施例中，芯片内的第一电容C 1、第二电容C 2为金属-绝 缘体-金属型(Metal-Insulator-Metal，MIM)电容，误差约±2～±5％，较多晶硅电阻的±20％小的多，又频率F和占空比duty_cycle(CLK 1)的误差也仅约±2％。由此可知，参考电压产生电路110所产生的等效电阻R EQ的误差值远小于芯片内电阻的误差值。
电路100会重复地操作在图4～图6，直到终端电阻单元108调整好。本揭露的电路100整体位于芯片中，也就是说，本揭露的阻抗调整电路的作法不需利用芯片外部的额外参考电阻来帮助校准芯片内的终端电阻，省去了至少一个引脚和外部的精准参考电阻的成本，同时又保有终端电阻的精准度。
本申请还提供了一种芯片，其包括电路100。
在某些实施例中，电路100可应用在指纹辨识芯片内,举例来说，由于电路100可应用在大屏幕光学指纹辨识芯片，由于大屏幕光学指纹辨识芯片具有多个传感器,其中每一传感器至少需要一个准确的终端电阻以避免数据传输过程产生讯号反射,如前所述，使用外部终端电阻将有封装跟成本的考虑，而使用芯片内的电路100可以节省额外的引脚和外部精准参考电阻，成本相对有优势。且由于校准可视需要才开启,校准后可将相关电路关闭,并非随时地在背景执行,系统耗电几乎可忽略。
上文的叙述简要地提出了本申请某些实施例之特征，而使得本申请所属技术领域具有通常知识者能够更全面地理解本揭示内容的多种态样。本申请所属技术领域具有通常知识者当可明了，其可轻易地利用本揭示内容作为基础，来设计或更动其他制程与结构，以实现与此处所述之实施方式相同的目的和/或达到相同的优点。本申请所属技术领域具有通常知识者应当明白，这些均等的实施方式仍属于本揭示内容之精神与范围，且其可进行各种变更、替代与更动，而不会悖离本揭示内容之精神与范围。

Claims (20)

  1. 一种阻抗调整电路，用来决定终端电阻单元的等效电阻值，其特征在于，所述阻抗调整电路包括：
    电流镜，用以提供第一参考电流和第二参考电流，其中所述电流镜利用所述第一参考电流镜射出所述第二参考电流；
    参考电压产生电路，至少依据所述第一参考电流、第一时钟以及第二时钟，产生参考电压；
    开关组，包括多个开关，所述多个开关的通断用来改变所述终端电阻单元的等效电阻值，所述第二参考电流流经所述终端电阻单元，并使所述终端电阻单元具有对应所述等效电阻值的终端电阻电压以响应所述第二参考电流；以及比较器，依据所述参考电压和所述终端电阻电压来产生比较结果；
    控制单元，依据所述比较结果来控制所述开关组中多个开关的通断。
  2. 如权利要求1所述的阻抗调整电路，其特征在于，所述参考电压产生电路包括：
    第一电路，用来累积所述第一参考电流所提供的正电荷；以及
    第二电路，用来将所述第一电路累积的正电荷储存起来形成所述参考电压。
  3. 如权利要求2所述的阻抗调整电路，其特征在于，所述参考电压产生电路另包括运算放大器，所述运算放大器的负输入端耦接至所述第一电路和所述第二电路，所述运算放大器的正输入端耦接至地电压，所述运算放大器输出端产生所述参考电压。
  4. 如权利要求3所述的阻抗调整电路，其特征在于，所述第一电路包括：
    第一晶体管；
    第一电容，其中所述第一晶体管和所述第一电容依序串接于所述电流镜和所述运算放大器的负输入端之间；以及
    第二晶体管，跨接于所述运算放大器的负输入端和输出端之间。
  5. 如权利要求4所述的阻抗调整电路，其特征在于，所述第二电路包括：
    第三晶体管，所述第三晶体管的一端耦接于所述第一晶体管和所述第一电容之间，所述第三晶体管的另一端耦接于所述地电压；以及
    第二电容，跨接于所述运算放大器的负输入端和输出端之间。
  6. 如权利要求5所述的阻抗调整电路，其特征在于，所述第一晶体管、所述第二晶体管依据所述第一时钟决定导通与否，所述第三晶体管依据所述第二时钟决定导通与否。
  7. 如权利要求2-6任一项所述的阻抗调整电路，其特征在于，所述第一时钟为第一位准时，所述第一电路累积所述第一参考电流所提供的正电荷；所述第一时钟为相反于所述第一位准的第二位准时，所述第一电路累积的正电荷消失；所述第二时钟为所述第一位准时，所述第二电路将所述第一电路累积的正电荷储存起来形成所述参考电压；所述第二时钟为所述第二位准时，所述第二电路将所述参考电压固定为0。
  8. 如权利要求7所述的阻抗调整电路，其特征在于，所述第一时钟和所述第二时钟产生自同一个时钟源，频率相同，且所述第一时钟和所述第二时钟不会同时为所述第一位准。
  9. 如权利要求8所述的阻抗调整电路，其特征在于，所述参考电压的大 小是依据所述第一电容的大小、所述第二电容的大小以及所述第一时钟的频率来决定。
  10. 如权利要求9所述的阻抗调整电路，其特征在于，所述参考电压的大小另依据所述第一时钟的占空比来决定。
  11. 如权利要求3-6任一项所述的阻抗调整电路，其特征在于，所述运算放大器的回路带宽大于或等于所述第一时钟的频率。
  12. 如权利要求1-6任一项所述的阻抗调整电路，其特征在于，所述控制单元将所述比较结果转换为多个位的数字讯号来控制所述开关组。
  13. 如权利要求1-6任一项所述的阻抗调整电路，其特征在于，所述第二参考电流大于所述第一参考电流。
  14. 一种芯片，其特征在于，包括：
    终端电阻单元；以及
    权利要求1-13任意一项所述的阻抗调整电路，所述阻抗调整电路用于调整所述终端电阻单元的等效电阻值。
  15. 一种参考电压产生电路，其特征在于，所述参考电压产生电路依据参考电流、第一时钟以及第二时钟，产生参考电压，所述参考电压产生电路包括：
    第一电路，用来累积所述参考电流所提供的正电荷；
    第二电路，用来将所述第一电路累积的正电荷储存起来形成所述参考电压；以及
    运算放大器，所述运算放大器的负输入端耦接至所述第一电路和所述第二 电路，所述运算放大器的正输入端耦接至地，所述运算放大器输出端产生所述参考电压；
    所述第一时钟和所述第二时钟产生自同一个时钟源，频率相同，且所述第一时钟用来启动所述第一电路，所述第二时钟用来启动所述第二电路，所述第一时钟和所述第二时钟不会同时启动所述第一电路和所述第二电路。
  16. 如权利要求15所述的参考电压产生电路，其特征在于，所述第一电路启动时，所述第一电路累积所述参考电流所提供的正电荷；所述第一电路不启动时，所述第一电路累积的正电荷消失；所述第二电路启动时，所述第二电路将所述第一电路累积的正电荷储存起来形成所述参考电压；所述第二电路不启动时，所述第二电路将所述参考电压固定在重置电压。
  17. 如权利要求16所述的参考电压产生电路，其特征在于，所述第一电路包括：
    第一晶体管；
    第一电容，其中所述第一晶体管和所述第一电容依序串接于所述电流镜和所述运算放大器的负输入端之间；以及
    第二晶体管，跨接于所述运算放大器的负输入端和输出端之间。
  18. 如权利要求17所述的参考电压产生电路，其特征在于，所述第二电路包括：
    第三晶体管，所述第三晶体管的一端耦接于所述第一晶体管和所述第一电容之间，所述第三晶体管的另一端耦接于所述地电压；以及
    第二电容，跨接于所述运算放大器的负输入端和输出端之间。
  19. 如权利要求18所述的参考电压产生电路，其特征在于，所述第一晶 体管、所述第二晶体管依据所述第一时钟决定导通与否，所述第三晶体管依据所述第二时钟决定导通与否。
  20. 如权利要求15-19任一项所述的参考电压产生电路，其特征在于，所述第一时钟的频率不超过所述运算放大器的回路带宽范围。
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