WO2020093765A1 - 光模块 - Google Patents

光模块 Download PDF

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Publication number
WO2020093765A1
WO2020093765A1 PCT/CN2019/103025 CN2019103025W WO2020093765A1 WO 2020093765 A1 WO2020093765 A1 WO 2020093765A1 CN 2019103025 W CN2019103025 W CN 2019103025W WO 2020093765 A1 WO2020093765 A1 WO 2020093765A1
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WIPO (PCT)
Prior art keywords
circuit
transistor
terminal
mirror circuit
voltage
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PCT/CN2019/103025
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English (en)
French (fr)
Inventor
秦士萱
黄锐
薛登山
李明
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青岛海信宽带多媒体技术有限公司
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Application filed by 青岛海信宽带多媒体技术有限公司 filed Critical 青岛海信宽带多媒体技术有限公司
Priority to US16/585,787 priority Critical patent/US10784968B2/en
Publication of WO2020093765A1 publication Critical patent/WO2020093765A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters

Definitions

  • This application relates to the field of optical fiber communication technology, and in particular to an optical module.
  • Avalanche Photodiode is a commonly used light-receiving device in optical modules, which will form a photocurrent after absorbing the incident light. If the reverse bias voltage is increased, the photocurrent of the avalanche photodiode will increase exponentially, which can make the receiving sensitivity better.
  • An embodiment of the present application provides an optical module, including a circuit board, an avalanche photodiode, a processor, and a probe point provided on the circuit board.
  • the circuit board includes a boost circuit.
  • the processor is connected to the control terminal of the booster circuit to control the output voltage of the booster circuit.
  • the voltage output terminal of the booster circuit is connected to the avalanche photodiode and the probe point, respectively.
  • Figure 1 is a circuit diagram of a boost circuit in the related art
  • Fig. 2 is a block diagram of an optical module according to some exemplary embodiments
  • Fig. 3 is a block diagram of another optical module according to some exemplary embodiments.
  • Fig. 4 is a block diagram of yet another optical module according to some exemplary embodiments.
  • Fig. 5 is a block diagram of still another optical module according to some exemplary embodiments.
  • Fig. 6 is a block diagram of yet another optical module according to some exemplary embodiments.
  • Fig. 7 is a circuit diagram of a boost circuit according to some exemplary embodiments.
  • Avalanche Photodiode is a commonly used light-receiving device in optical modules, which will form a photocurrent after absorbing the incident light. If the reverse bias voltage is increased, the photocurrent of the avalanche photodiode will increase exponentially, which can make the receiving sensitivity better. Because the voltage of the power supply of the optical module is only 3.3V, the optical module is usually provided with a booster circuit to increase the voltage of the power supply from 3.3V to several tens of volts, which is then used as the reverse bias voltage of the APD.
  • optical modules are generally divided into the following categories: optical transmitting modules, optical receiving modules, and optical transceiver modules.
  • the optical transmitter module converts electrical signals into optical signals and transmits them through optical fibers.
  • the optical receiving module converts the received optical signal into an electrical signal.
  • the optical transceiver module can convert both electrical signals into optical signals and electrical signals into optical signals.
  • the optical module includes an avalanche photodiode and a circuit board.
  • the optical transceiver module includes an avalanche photodiode and a circuit board.
  • the light receiving module includes an avalanche photodiode and a circuit board.
  • Figure 1 is a circuit diagram of a boost circuit.
  • the working principle of the booster circuit is: when the control signal APD-PWM (Pulse-Width Modulation) is a low voltage, the switching MOS (Metal Oxide Semiconductor) tube T3 is turned off.
  • APD-PWM Pulse-Width Modulation
  • MOS Metal Oxide Semiconductor
  • the current flows from the power supply VCC, through the inductor L1, the diode D1 to the capacitor C1, so that the power supply VCC charges the capacitor C1, and the current also reaches the avalanche photodiode through the resistor R2 and the output terminal APD-OUT. That is, the capacitor C1 and the power supply VCC provide reverse bias for the avalanche photodiode.
  • the control signal APD-PWM is a high voltage
  • the switching MOS transistor T3 is turned on.
  • current flows from the power supply VCC, through the inductor L1, the switching MOS transistor T3 to the ground GND in sequence. Due to the unidirectional conduction characteristic of diode D1, capacitor C1 provides a reverse bias for the avalanche photodiode through resistor R2.
  • the optimal working voltage of the avalanche photodiode will be limited by the process, which is not fixed, it is necessary to detect the voltage of the voltage output terminal APD-OUT of the booster circuit to match it with the optimal operating voltage of the APD
  • the booster circuit is built by devices. Due to the differences between the devices, the output voltage of each booster circuit built is ultimately inconsistent, and the voltage of APD-OUT needs to be fine-tuned. However, technicians usually directly use a probe or a piece of wire to detect the voltage of the voltage output terminal APD-OUT.
  • the optical module 10 provided by the embodiment of the present application includes a circuit board 11 and an avalanche photodiode 12.
  • the surface of the circuit board 11 is provided with a processor 21, a probe point and a gold finger 23.
  • the circuit board 11 has a booster circuit 22.
  • the voltage input terminal of the booster circuit 22 is connected to the power supply pin of the golden finger 23.
  • the power supply pin is pluggably connected to the power supply VCC.
  • the processor 21 is connected to the control terminal of the booster circuit 22, so that the processor 21 can input the control signal APD-PWM to the control terminal of the booster circuit 22, thereby controlling the output voltage of the voltage output terminal of the booster circuit. That is, the processor can control the booster circuit to output an output voltage higher than the voltage provided by the power supply, and the output voltage is related to the control signal.
  • the voltage output terminal APD-OUT of the booster circuit 22 is connected to the avalanche photodiode 12 and the probe point, respectively.
  • the way of presenting the probe points on the circuit board 11 in this embodiment may include at least one of the following: a solder tab, a lead, and a gold finger. In this way, the technician can directly touch the probe to the probe point to obtain the voltage on the voltage output terminal APD-OUT.
  • FIG. 2 only shows the gold finger related to the power supply of the booster circuit 22, and the technician can also adjust the function and number of the gold finger according to the specific scenario, which is not limited herein.
  • a power management chip may be provided between the golden finger and the booster circuit 22. Referring to FIG. 3, the power management chip 24 can adjust the voltage and / or current input by the power supply VCC to meet the input voltage, current, and power requirements of the booster circuit 22. In addition, technicians can select the power management chip 24 according to specific scenarios, which is not limited herein.
  • the golden finger on the circuit board is connected to the power supply, and the voltage input terminal of the booster circuit is connected to the golden finger, so that the power supply can provide voltage to the booster circuit.
  • the processor on the circuit board is connected to the control terminal of the booster circuit.
  • the processor can control the booster circuit to output an output voltage higher than the voltage provided by the power supply by inputting a control signal to the control terminal.
  • the voltage output of the booster circuit is connected to the avalanche photodiode and the probe point, so the voltage on the probe point is the output voltage, so that the technician can easily detect the output voltage on the probe point, which can reduce the detection difficulty and improve the The voltage accuracy on the voltage output of the booster circuit is detected.
  • the voltage output terminal APU-OUT of the booster circuit 22 may be connected to the avalanche photodiode 12 and the probe point through two wires, respectively.
  • the voltage output terminal APU-OUT is connected to the probe point through the first wire 221 and connected to the avalanche photodiode 12 through the second wire 222.
  • the probe point is led through the wire, and the probe point can be set at an empty position of the circuit board 11 to facilitate user detection.
  • the voltage output terminal APU-OUT of the booster circuit 22 may be connected to the avalanche photodiode 12 and the probe point through a mirror circuit, respectively.
  • the mirror circuit 25 includes an input terminal and two output terminals, wherein the input terminal is connected to the voltage output terminal APD-OUT of the booster circuit 22, one output terminal is connected to the probe point, and the other output terminal is connected to the avalanche photodiode 12 connections.
  • the mirror circuit 25 includes at least a first transistor T1 and a second transistor T2.
  • the second terminal T12 of the first transistor T1 is connected to the voltage output terminal APD-OUT of the booster circuit 22, and the first terminal T11 and the third terminal T13 of the first transistor T1 are connected to the probe point.
  • the first terminal T21 of the second transistor T2 is connected to the first terminal T11, the third terminal T13 and the probe point of the first transistor T1, respectively.
  • the second terminal T22 of the second transistor T2 and the voltage output terminal APD- of the booster circuit 22 OUT is connected, and the third terminal T23 of the second transistor T2 is connected to the avalanche photodiode 12.
  • the first transistor T1 and the second transistor T2 need to be implemented with components of the same model or the same process, such as transistors or Field effect tube.
  • the first transistor T1 and the second transistor T2 use PNP transistors.
  • the voltage at the voltage output terminal APD-OUT of the booster circuit 22 may be a first voltage higher than the voltage provided by the power supply VCC or a second voltage lower than the voltage provided by the power supply VCC.
  • the first voltage matches the optimal operating voltage of the avalanche photodiode 12.
  • the optimal operating voltage refers to the reverse bias voltage corresponding to the highest sensitivity of the avalanche photodiode 12.
  • the voltage at the voltage output APD-OUT is equal to the optimal operating voltage of the avalanche photodiode.
  • the voltage at the voltage output terminal APD-OUT of the booster circuit 22 is the first voltage
  • the voltage at the second terminal T12 (ie, emitter) of the first transistor T1 is greater than the voltage at the first terminal T11 (ie, base), ie
  • the Vbe of the first transistor T1 is reverse-biased, so that the first transistor T1 is turned on, and the third terminal T13 (ie, collector) of the first transistor T1 outputs the voltage at the emitter T12.
  • the voltage at the second terminal T22 (i.e., emitter) of the second transistor T2 is greater than the voltage at the first terminal T21 (i.e., base), that is, the Vbe of the second transistor T2 is reverse biased, so that the second transistor T2 is turned on and the second transistor
  • the third terminal T23 (ie, collector) of T2 outputs the voltage at the emitter T22.
  • the emitter T12 of the first transistor T1 is connected to the voltage output terminal APD-OUT of the booster circuit 22, so the voltage at the probe point and the booster circuit 22
  • the first voltage provided by the voltage output terminal APD-OUT is similar, the difference is that the voltage occupied by the PN junction between the emitter T12 and the collector T13 (less than 1V, such as a germanium tube is 0.4V), when the voltage is tens of volts Next, the voltage occupied by the PN junction is negligible, that is, the voltage at the probe point and the first voltage provided by the voltage output terminal APD-OUT are considered to be the same.
  • the avalanche photodiode 12 Since the collector T23 of the second transistor T2 is connected to the input terminal of the avalanche photodiode 12, and the emitter T22 of the second transistor T2 is connected to the voltage output terminal APD-OUT of the booster circuit 22, the avalanche photodiode 12
  • the input voltage is similar to the first voltage provided by the voltage output terminal of the booster circuit 22, the difference is that the voltage occupied by the PN junction between the emitter T22 and the collector T23 (less than 1V, for example, the germanium tube is 0.4V), the voltage is several In the case of ten volts, the voltage occupied by the PN junction is negligible, that is, the input voltage of the avalanche photodiode 12 and the first voltage provided by the voltage output terminal APD-OUT are considered to be the same.
  • the voltage occupied by the PN junction is the same.
  • the voltage at the probe point is the same as the input voltage of the avalanche photodiode 12, that is, the voltage at the probe point can represent the input voltage of the avalanche photodiode 12 and the output voltage of the booster circuit 22.
  • the second transistor T2 when the second transistor T2 is turned on, if a probe is used to detect the voltage at the probe point, applying a voltage to the probe point will increase the voltage at the base T21 of the second transistor T2,
  • the voltage of the electrode T23 changes synchronously, that is, the probe voltage and the input voltage of the avalanche photodiode 12 change synchronously, so that the voltage at the voltage output terminal APD-OUT is not affected by the voltage fluctuation at the probe point.
  • the mirror circuit 25 may further include a first current limiting circuit and a second current limiting circuit.
  • the first current limiting circuit may be connected in series between the second terminal T12 of the first transistor T1 and the voltage output terminal APD-OUT (ie, the input terminal of the mirror circuit), and the second current limiting circuit may be connected in series to the second transistor T2 Between the second terminal T22 and the voltage output terminal APD-OUT. In this way, in this embodiment, the current of the branch where the first current limiting circuit and the second current limiting circuit can be adjusted respectively.
  • the first current limiting circuit and the second current limiting circuit respectively include at least one current limiting resistor. Referring to FIG. 5, the first current limiting circuit includes a current limiting resistor R1, and the second current limiting circuit includes a current limiting resistor R2.
  • the current limiting resistor R1 and the current limiting resistor R2 have the same resistance value.
  • the mirror circuit 25 may include a third current limiting circuit.
  • the third current limiting circuit may include at least one current limiting resistor R, which is connected in series between the voltage output terminal APD-OUT (ie, the input terminal of the mirror circuit) and the second terminal of the first transistor T1 Between T12 and the second terminal T22 of the second transistor T2 is used to adjust the current input to the mirror circuit.
  • the mirror circuit 25 may include a first current limiting circuit and a second current limiting circuit as shown in FIG. 5, and a third current limiting circuit as shown in FIG. 6. The current of the branch where it is located is adjusted by the first current limiting circuit and the second current limiting circuit respectively, and the current input to the mirror circuit is adjusted by the third current limiting circuit.
  • the booster circuit 22 may include: a first inductor L1, a first diode D1, a first capacitor C1, a third resistor R3, a fourth resistor R4, and a field effect transistor T3.
  • the first end of the first inductor L1 is connected to the power supply VCC. In some embodiments, the first end of the first inductor L1 is connected to the power supply VCC through the golden finger 23.
  • the second terminal of the first inductor L1 is connected to the anode of the first diode D1.
  • the cathode of the first diode D1 is connected to the first end of the fourth resistor R4.
  • the second terminal of the fourth resistor R4 is connected to the output terminal APD-OUT of the booster circuit 22.
  • the first end of the first capacitor C1 is connected to the cathode of the first diode D1, and the second end of the first capacitor C1 is grounded GND.
  • the first end of the third resistor R3 is connected to the signal output end of the processor, and the second end of the third resistor R3 is connected to the first end of the field effect transistor T3.
  • the second end of the field effect transistor T3 is connected to the second end of the first inductor L1, and the third end of the field effect transistor T3 is grounded.
  • the signal output terminal of the processor may output the control signal APD-PWM.
  • the APD-PWM may be a first voltage higher than the voltage provided by the power supply VCC or a second voltage lower than the voltage provided by the power supply VCC. Since the field effect transistor T3 is an N-type field effect transistor, the first end of the field effect transistor T3 is turned on when receiving the first voltage, and is turned off when receiving the second voltage.
  • the field effect transistor T3 When the APD-PWM is the second voltage, the field effect transistor T3 is turned off. During the turn-off of the field effect transistor T3, the current flows from the power supply VCC through the first inductor L1, the first diode D1 to the first capacitor C1, that is, the power supply VCC charges the first capacitor C1, and the current also passes through the fourth resistor R4 And the voltage output terminal APD-OUT reaches the avalanche photodiode 12.
  • the first capacitor C1, the first inductor L1, and the power supply VCC provide a voltage to the avalanche photodiode 12, whereby the voltage at the input of the avalanche photodiode 12 is the voltage of the first capacitor C1, the inductance of the first inductor L1, and The sum of the voltage of the power supply VCC.
  • the field effect transistor T3 When the APD-PWM is the first voltage, the field effect transistor T3 is turned on. During the conduction period of the field effect transistor T3, the current VCC flows from the power supply VCC, through the inductor L1, the field effect transistor T3 to the ground GND, that is, the power supply VCC does not charge the first capacitor C1. Due to the unidirectional conduction characteristic of the first diode D1, the first capacitor C1 provides a voltage to the avalanche photodiode 12 through the fourth resistor R4, and the voltage at the input end of the avalanche photodiode 12 is the voltage of the first capacitor C1.
  • the processor can adjust the voltage of the first capacitor C1 by adjusting the duty ratio of the output control signal APD-PWM, thereby adjusting the voltage of the voltage output terminal of the booster circuit 22.
  • the output voltage of the booster circuit 22 is equal to the optimal operating voltage of the avalanche photodiode.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
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  • Automation & Control Theory (AREA)
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Abstract

本公开提供一种光模块。在一些实施方式中，该光模块包括：雪崩光电二极管、电路板、处理器和在所述电路板上的探点。所述电路板包括升压电路。处理器与升压电路的控制端连接，以控制所述升压电路的输出电压。升压电路的输出端分别与所述雪崩光电二极管及所述探点连接。

Description

光模块
相关申请的交叉引用
本专利申请要求于2018年11月6日提交的、申请号为2018113141260的中国专利申请的优先权，该申请的全文以引用的方式并入本文中。
技术领域
本申请涉及光纤通信技术领域，尤其涉及一种光模块。
背景技术
雪崩光电二极管(Avalanche Photodiode，APD)是光模块中常用的光接收器件，在吸收射入的光后会形成光电流。若增加反向偏压，则雪崩光电二极管的光电流会成倍地激增，从而可以使接受灵敏度更好。
发明内容
本申请实施例提供了一种光模块，包括电路板、雪崩光电二极管、处理器和设在电路板上的探点。电路板包括升压电路。处理器与升压电路的控制端连接，以控制升压电路的输出电压。升压电路的电压输出端分别与所述雪崩光电二极管及所述探点连接。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本申请。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本申请的实施例，并与说明书一起用于解释本申请的原理。
图1是相关技术中一种升压电路的电路图；
图2是根据一些示例性实施例示出的一种光模块的框图；
图3是根据一些示例性实施例示出的另一种光模块的框图；
图4是根据一些示例性实施例示出的又一种光模块的框图；
图5是根据一些示例性实施例示出的又一种光模块的框图；
图6是根据一些示例性实施例示出的又一种光模块的框图；
图7是根据一些示例性实施例示出的一种升压电路的电路图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
雪崩光电二极管(Avalanche Photodiode，APD)是光模块中常用的光接收器件，在吸收射入的光后会形成光电流。若增加反向偏压，则雪崩光电二极管的光电流会成倍地激增，从而可以使接受灵敏度更好。由于光模块的供电电源的电压仅为3.3V，因此光模块中通常设置有升压电路，将电源的电压从3.3V升到几十伏，再作为APD的反向偏压。
通常，光模块通常分为以下几类：光发射模块、光接收模块和光收发模块。光发射模块将电信号转换为光信号，并通过光纤传送。光接收模块将接收到的光信号转换为电信号。光收发模块既能将电信号转换为光信号又能将电信号转换为光信号。在一些实施例中，光模块包括雪崩光电二极管和电路板。在另一些实施例中，光收发模块包括雪崩光电二极管和电路板。可选地，光接收模块包括雪崩光电二极管和电路板。下面以光模块包括雪崩光电二极管和电路板为例进行详细说明。图1是一种升压电路的电路图。参见图1，升压电路的工作原理为：在控制信号APD-PWM(Pulse-Width Modulation)为低电压时，开关MOS(Metal Oxide Semiconductor)管T3截止。在开关MOS管T3截止期间，电流从电源VCC，依次通过电感L1、二极管D1到达电容C1，从而实现电源VCC向电容C1充电，同时电流还通过电阻R2和输出端APD-OUT到达雪崩光电二极管，即电容C1和电源VCC为雪崩光电二极管提供反向偏压。在控制信号APD-PWM为高电压时，开关MOS管T3导通。在开关MOS管T3导通期间，电流从电源VCC，依次通过电感L1、开关MOS管T3流向地GND。由于二极管D1的单向导通特性，此时电容C1通过电阻R2为雪崩光电二极管提供反向偏压。
实际应用中，由于雪崩光电二极管的最优工作电压会受到工艺限制，导致其不固定，因此需要对升压电路电压输出端APD-OUT的电压进行检测，使之与APD的最优工作 电压匹配；此外，升压电路由器件搭建，由于器件之间存在差异性，最终每个搭建的升压电路的输出电压并不一致，也需要对APD-OUT的电压进行微调。然而，技术人员通常直接利用探针或者一段导线检测电压输出端APD-OUT的电压，在检测电压输出端APD-OUT的电压的过程中会对包括升压电路的线路施加一定的电压，从而产生一些电压冲击，使检测的电压值不准确，进而影响到电压输出端APD-OUT电压，以及影响到雪崩光电二极管的灵敏度。
为此，参见图2，本申请实施例提供的光模块10包括电路板11及雪崩光电二极管12。电路板11表面设置有处理器21、探点及金手指23。电路板11具有升压电路22。升压电路22的电压输入端与金手指23的供电引脚连接。供电引脚可插拔式地与电源VCC连接。
处理器21与升压电路22的控制端连接，这样处理器21可以向升压电路22的控制端输入控制信号APD-PWM，从而控制升压电路电压输出端的输出电压。即处理器可以控制升压电路输出一高于电源提供电压的输出电压，该输出电压与控制信号相关。
升压电路22的电压输出端APD-OUT分别与雪崩光电二极管12及探点连接。
本实施例中探点在电路板11上的呈现方式，可以包括以下至少一种：一个焊片、一根引线、一个金手指。这样，技术人员可以直接将探针接触到探点即可获得电压输出端APD-OUT上的电压。
图2仅示出了与升压电路22的供电电源相关的金手指，技术人员还可以根据具体场景，调整金手指的功能和数量，在此不作限定。在一些实施例中，在金手指与升压电路22之间还可以设置一电源管理芯片。参见图3，电源管理芯片24可以对电源VCC输入的电压和/或电流进行调整，从而满足升压电路22的输入电压、电流和功率的需求。另外，技术人员可以根据具体场景选择电源管理芯片24，在此不作限定。
至此，本实施例中电路板上金手指与电源连接，升压电路的电压输入端与金手指连接，这样电源可以为升压电路提供电压。电路板上的处理器与升压电路的控制端连接，处理器通过向控制端输入控制信号可以控制升压电路输出高于电源所提供电压的输出电压，其中该输出电压的大小与控制信号相关。并且，升压电路的电压输出端分别与雪崩光电二极管及探点连接，因此探点上电压为输出电压，这样技术人员可以方便地在探点上检测到输出电压，可以降低检测难度以及提高所检测到升压电路的电压输出端上电压准确度。
在一些实施例中，升压电路22的电压输出端APU-OUT可以通过两根导线分别与雪崩光电二极管12及探点连接。继续参见图2，电压输出端APU-OUT通过第一根导线221与探点连接，以及通过第二根导线222与雪崩光电二极管12连接。本实施例中通过导线引出探点，可以将探点设置在电路板11的空闲位置，方便用户检测。
在一些实施例中，升压电路22的电压输出端APU-OUT可以通过镜像电路分别与雪崩光电二极管12和探点连接。参见图4，镜像电路25包括一个输入端和两个输出端，其中输入端与升压电路22的电压输出端APD-OUT连接，一个输出端与探点连接，另一个输出端与雪崩光电二极管12连接。
继续参见图4，该镜像电路25至少包括第一晶体管T1和第二晶体管T2。其中，第一晶体管T1的第二端T12与升压电路22的电压输出端APD-OUT连接，第一晶体管T1的第一端T11与第三端T13连接于探点。第二晶体管T2的第一端T21分别与第一晶体管T1的第一端T11、第三端T13和探点连接，第二晶体管T2的第二端T22和升压电路22的电压输出端APD-OUT连接，第二晶体管T2的第三端T23与雪崩光电二极管12连接。
为保证第一晶体管T1的第三端和第二晶体管T2的第三端的电压相同，本实施例中第一晶体管T1和第二晶体管T2需要采用相同型号或者相同工艺的元器件实现，例如晶体管或者场效应管。在一些实施例中，第一晶体管T1和第二晶体管T2采用PNP型三极管。
继续参见图4，以第一晶体管T1和第二晶体管T2为PNP型三极管为例，且两者都工作在线性区域。镜像电路25的工作原理为：升压电路22的电压输出端APD-OUT处电压可以为高于电源VCC所提供电压的第一电压或者为低于电源VCC所提供电压的第二电压。第一电压与雪崩光电二极管12的最优工作电压相匹配。最优工作电压是指雪崩光电二极管12的灵敏度最高时对应的反偏电压。理想情况下，电压输出端APD-OUT处电压与雪崩光电二极管的最优工作电压相等。
当升压电路22的电压输出端APD-OUT处电压为第一电压时，第一晶体管T1的第二端T12(即发射极)处电压大于第一端T11(即基极)处电压，即第一晶体管T1的Vbe反偏，这样第一晶体管T1导通，第一晶体管T1的第三端T13(即集电极)输出发射极T12处的电压。
第二晶体管T2的第二端T22(即发射极)处电压大于第一端T21(即基极)处电压， 即第二晶体管T2的Vbe反偏，这样第二晶体管T2导通，第二晶体管T2的第三端T23(即集电极)输出发射极T22处的电压。
继续参见图4，由于第一晶体管T1集电极T13与探点连接，第一晶体管T1的发射极T12与升压电路22的电压输出端APD-OUT连接，因此探点上的电压和升压电路22电压输出端APD-OUT提供的第一电压相近，区别在于发射极T12和集电极T13之间PN结所占电压(小于1V，例如锗管为0.4V)，在电压为几十伏的情况下，PN结所占电压可忽略，即探点上的电压和电压输出端APD-OUT提供的第一电压认为相同。
继续参见图4，由于第二晶体管T2集电极T23与雪崩光电二极管12的输入端连接，第二晶体管T2的发射极T22与升压电路22的电压输出端APD-OUT连接，因此雪崩光电二极管12的输入电压和升压电路22电压输出端提供的第一电压相近，区别在于发射极T22和集电极T23之间PN结所占电压(小于1V，例如锗管为0.4V)，在电压为几十伏的情况下，PN结所占电压可忽略，即雪崩光电二极管12的输入电压和电压输出端APD-OUT提供的第一电压认为相同。
由于第一晶体管T1和第二晶体管T2为型号相同或者采用相同工艺制成的元器件，因此PN结所占电压相同。换言之，探点上的电压和雪崩光电二极管12的输入电压相同，即探点上的电压可以表征雪崩光电二极管12的输入电压以及升压电路22的输出电压。
本实施例中在第二晶体管T2导通的情况下，若使用探针检测探点的电压，向探点施加一电压会提高第二晶体管T2基极T21的电压，则第二晶体管T2的集电极T23的电压会同步变化，即探点电压和雪崩光电二极管12的输入电压同步变化，这样，电压输出端APD-OUT处的电压不受探点处电压波动的影响。
在一些实施例中，镜像电路25还可以包括第一限流电路和第二限流电路。第一限流电路可以串接在第一晶体管T1的第二端T12和电压输出端APD-OUT(即镜像电路的输入端)之间，而第二限流电路可以串接在第二晶体管T2的第二端T22和电压输出端APD-OUT之间。这样，本实施例中可以通过第一限流电路和第二限流电路分别调整其所在支路的电流。在一些实施例中，第一限流电路和第二限流电路中分别至少包括一限流电阻。参见图5，第一限流电路中包括限流电阻R1，第二限流电路中包括限流电阻R2。
在一个示例中，在镜像电路25中包括第一晶体管T1和第二晶体管T2的情况下，限流电阻R1和限流电阻R2阻值相同。
在另一实施例中，镜像电路25可包括第三限流电路。参见图6，该第三限流电路可以至少包括一个限流电阻R，该限流电阻R串接在电压输出端APD-OUT(即镜像电路的输入端)与第一晶体管T1的第二端T12和第二晶体管T2的第二端T22之间，用于调整输入到镜像电路中的电流。
在另一实施例中，镜像电路25可包括如图5所示的第一限流电路和第二限流电路，以及如图6所示的第三限流电路。通过第一限流电路和第二限流电路分别调整其所在支路的电流，通过第三限流电路调整输入到镜像电路中的电流。
在一些实施例中，参见图7，升压电路22可以包括：第一电感L1、第一二极管D1、第一电容C1、第三电阻R3、第四电阻R4和场效应管T3。
第一电感L1的第一端和电源VCC连接。在一些实施方式中，第一电感L1的第一端通过金手指23和电源VCC连接。第一电感L1的第二端和第一二极管D1的阳极连接。第一二极管D1的阴极和第四电阻R4的第一端连接。第四电阻R4的第二端与升压电路22的输出端APD-OUT连接。第一电容C1的第一端与第一二极管D1的阴极连接，第一电容C1的第二端接地GND。第三电阻R3的第一端与处理器的信号输出端连接，第三电阻R3的第二端与场效应管T3的第一端连接。场效应管T3的第二端与第一电感L1的第二端连接，场效应管T3的第三端接地。
继续参见图7，将讨论该升压电路22的工作原理。
处理器的信号输出端可以输出控制信号APD-PWM，例如APD-PWM可以为高于电源VCC所提供电压的第一电压或者低于电源VCC所提供电压的第二电压。由于场效应管T3为N型场效应管，因此该场效应管T3的第一端接收到第一电压时导通，接收到第二电压时关断。
在APD-PWM为第二电压时，场效应管T3关断。在场效应管T3关断期间，电流从电源VCC，依次通过第一电感L1、第一二极管D1到达第一电容C1，即电源VCC向第一电容C1充电，同时电流还通过第四电阻R4和电压输出端APD-OUT到达雪崩光电二极管12。这样，第一电容C1、第一电感L1和电源VCC为雪崩光电二极管12提供电压，由此，雪崩光电二极管12的输入端处电压为第一电容C1的电压、第一电感L1的感应电感和电源VCC的电压之和。
在APD-PWM为第一电压时，场效应管T3导通。在场效应管T3导通期间，电流VCC从电源VCC，依次通过电感L1、场效应管T3流向地GND，即电源VCC不给第 一电容C1充电。由于第一二极管D1的单向导通特性，此时第一电容C1通过第四电阻R4为雪崩光电二极管12提供电压，雪崩光电二极管12的输入端处电压为第一电容C1的电压。
本实施例中，处理器通过调整输出控制信号APD-PWM的占空比，可以调整第一电容C1的电压，从而达到调整升压电路22的电压输出端的电压。理想情况下，升压电路22的输出电压与雪崩光电二极管的最优工作电压相等。调整控制信号占空比的方式可以参考相关技术，在此不再赘述。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
以上仅为本申请的一些实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种光收发模块，包括：
    雪崩光电二极管，
    电路板，其包括升压电路；
    处理器，配置为控制所述升压电路的输出电压；和
    探点，配置为在所述电路板上；
    其中，所述升压电路的控制端与所述处理器连接，所述升压电路的输出端分别与所述雪崩光电二极管及所述探点连接。
  2. 根据权利要求1所述的光收发模块，其中，所述光收发模块还包括：
    设置于所述电路板上的镜像电路，所述镜像电路的输入端与所述升压电路的输出端连接，所述镜像电路的第一输出端与所述雪崩光电二极管的输入端连接，所述镜像电路的第二输出端与所述探点连接。
  3. 根据权利要求2所述的光收发模块，其中，所述镜像电路至少包括：
    第一晶体管，所述第一晶体管的第二端与所述升压电路的输出端连接，所述第一晶体管的第一端与第三端连接；和
    第二晶体管；所述第二晶体管的第一端分别与所述第一晶体管的第三端和所述探点连接，所述第二晶体管的第二端和所述升压电路的输出端连接，所述第二晶体管的第三端与所述雪崩光电二极管连接。
  4. 根据权利要求3所述的光收发模块，其中，
    所述第一晶体管为PNP型三极管；
    所述第二晶体管为PNP型三极管。
  5. 根据权利要求3所述的光收发模块，其中，所述镜像电路还包括：
    第一限流电路，串接在所述第一晶体管的第二端和所述镜像电路的输入端之间；和
    第二限流电路，串接在所述第二晶体管的第二端和所述镜像电路的输入端之间。
  6. 根据权利要求5所述的光收发模块，其中，
    所述第一限流电路至少包括第一限流电阻；
    所述第二限流电路至少包括第二限流电阻。
  7. 根据权利要求3所述的光收发模块，其中，所述镜像电路还包括：
    第三限流电路，串接在所述镜像电路的输入端与所述第一晶体管的第二端、所述第二晶体管的第二端之间。
  8. 根据权利要求7所述的光收发模块，其中，所述第三限流电路至少包括第三限流 电阻。
  9. 根据权利要求1所述的光收发模块，其中，所述光模块还包括金手指，所述金手指设置于所述电路板的表面，所述金手指的供电引脚与所述升压电路的输入端连接。
  10. 根据权利要求9所述的光收发模块，其中，所述光模块还包括电源管理芯片，所述升压电路的输入端通过所述电源管理芯片与所述金手指的供电引脚连接。
  11. 根据权利要求1所述的光收发模块，其中，所述升压电路包括：
    第一电阻，其第一端与所述处理器的输出端连接，其第二端与场效应管的第一端连接；
    所述场效应管，其第二端与第一电感的第二端连接，其第三端接地；
    所述第一电感，其第一端接收供电，其第二端和第一二极管的阳极连接；
    所述第一二极管，其阴极分别和第二电阻的第一端、第一电容的第一端连接；
    所述第二电阻，其第二端与所述升压电路的输出端连接；和
    所述第一电容，其第二端接地。
  12. 一种光接收模块，包括：
    雪崩光电二极管，
    电路板，其包括升压电路；
    处理器，配置为控制所述升压电路的输出电压；和
    探点，配置为在所述电路板上；
    其中，所述升压电路的控制端与所述处理器连接，所述升压电路的输出端分别与所述雪崩光电二极管及所述探点连接。
  13. 根据权利要求12所述的光接收模块，其中，所述光接收模块还包括：
    设置于所述电路板上的镜像电路，所述镜像电路的输入端与所述升压电路的输出端连接，所述镜像电路的第一输出端与所述雪崩光电二极管的输入端连接，所述镜像电路的第二输出端与所述探点连接。
  14. 根据权利要求13所述的光接收模块，其中，所述镜像电路至少包括：
    第一晶体管，所述第一晶体管的第二端与所述升压电路的输出端连接，所述第一晶体管的第一端与第三端连接；和
    第二晶体管；所述第二晶体管的第一端分别与所述第一晶体管的第三端和所述探点连接，所述第二晶体管的第二端和所述升压电路的输出端连接，所述第二晶体管的第三端与所述雪崩光电二极管连接。
  15. 根据权利要求14所述的光接收模块，其中，所述镜像电路还包括：
    第一限流电路，串接在所述第一晶体管的第二端和所述镜像电路的输入端之间；和
    第二限流电路，串接在所述第二晶体管的第二端和所述镜像电路的输入端之间。
  16. 根据权利要求14所述的光接收模块，其中，所述镜像电路还包括：
    第三限流电路，串接在所述镜像电路的输入端与所述第一晶体管的第二端、所述第二晶体管的第二端之间。
  17. 一种光模块，包括：
    雪崩光电二极管，
    电路板，其包括升压电路；
    处理器，配置为控制所述升压电路的输出电压；和
    探点，配置为在所述电路板上；
    其中，所述升压电路的控制端与所述处理器连接，所述升压电路的输出端分别与所述雪崩光电二极管及所述探点连接。
  18. 根据权利要求17所述的光模块，其中，所述光模块还包括：
    设置于所述电路板上的镜像电路，所述镜像电路的输入端与所述升压电路的输出端连接，所述镜像电路的第一输出端与所述雪崩光电二极管的输入端连接，所述镜像电路的第二输出端与所述探点连接。
  19. 根据权利要求18所述的光模块，其中，所述镜像电路至少包括：
    第一晶体管，所述第一晶体管的第二端与所述升压电路的输出端连接，所述第一晶体管的第一端与第三端连接；和
    第二晶体管；所述第二晶体管的第一端分别与所述第一晶体管的第三端和所述探点连接，所述第二晶体管的第二端和所述升压电路的输出端连接，所述第二晶体管的第三端与所述雪崩光电二极管连接。
  20. 根据权利要求19所述的光模块，其中，所述镜像电路还包括：
    第一限流电路，串接在所述第一晶体管的第二端和所述镜像电路的输入端之间；和
    第二限流电路，串接在所述第二晶体管的第二端和所述镜像电路的输入端之间。
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CN112925068B (zh) * 2019-12-06 2023-05-05 青岛海信宽带多媒体技术有限公司 一种光模块
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