WO2020093519A1 - 存储器件及其制造方法及包括该存储器件的电子设备 - Google Patents

存储器件及其制造方法及包括该存储器件的电子设备 Download PDF

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Publication number
WO2020093519A1
WO2020093519A1 PCT/CN2018/120889 CN2018120889W WO2020093519A1 WO 2020093519 A1 WO2020093519 A1 WO 2020093519A1 CN 2018120889 W CN2018120889 W CN 2018120889W WO 2020093519 A1 WO2020093519 A1 WO 2020093519A1
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layer
dielectric layer
gate dielectric
electrode
active region
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PCT/CN2018/120889
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English (en)
French (fr)
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朱慧珑
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中国科学院微电子研究所
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Priority to US17/309,222 priority Critical patent/US11895845B2/en
Publication of WO2020093519A1 publication Critical patent/WO2020093519A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40111—Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/50—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the boundary region between the core and peripheral circuit regions

Definitions

  • the present disclosure relates to the field of semiconductors, and in particular, to a storage device based on a vertical type device and a method of manufacturing the same, and an electronic device including such a storage device.
  • the source, gate, and drain are arranged in a direction substantially parallel to the surface of the substrate. Due to this arrangement, the horizontal type device is not easy to shrink further. Unlike this, in the vertical type device, the source, gate, and drain are arranged in a direction substantially perpendicular to the substrate surface. Therefore, the vertical type device is easier to shrink than the horizontal type device.
  • MOSFET metal oxide semiconductor field effect transistor
  • a three-dimensional (3D) memory device such as a flash memory (NAND type or NOR type) can be manufactured.
  • 3D memory device such as a flash memory (NAND type or NOR type)
  • NAND type or NOR type flash memory
  • it has become increasingly difficult to further increase their integration density.
  • it is difficult to reduce the source / drain resistance of the memory cell.
  • the source / drain resistances of the vertically stacked memory cells are connected in series, resulting in an increase in the total resistance and poor performance of the memory device.
  • an object of the present disclosure is, at least in part, to provide a memory device based on a vertical device with improved characteristics, a method of manufacturing the same, and an electronic apparatus including such a memory device.
  • a memory device including: a substrate; an electrode structure provided on the substrate, including a plurality of first electrode layers and a plurality of second electrode layers stacked alternately; a through electrode structure A plurality of vertical active regions; a first gate dielectric layer disposed between the vertical active region and each first electrode layer in the electrode structure and a second gate dielectric layer disposed between the vertical active region and the electrode structure A second gate dielectric layer between the electrode layers, wherein the first gate dielectric layer and the second gate dielectric layer respectively constitute a data storage structure.
  • the first effective work function of the combination of the first electrode layer and the first gate dielectric layer is different from the second effective work function of the combination of the second electrode layer and the second gate dielectric layer.
  • a method of manufacturing a memory device comprising: providing a stack of a plurality of first sacrificial layers and a plurality of second sacrificial layers alternately stacked on a substrate; forming a stack penetrating the stack A plurality of vertical holes of the layer; forming a first gate dielectric layer corresponding to the first sacrificial layer and a second gate dielectric layer corresponding to the second sacrificial layer on the side walls of the vertical hole; The hole is filled with semiconductor material to form an active region; the first sacrificial layer is replaced with a first electrode layer; and the second sacrificial layer is replaced with a second electrode layer.
  • the first effective work function of the combination of the first electrode layer and the first gate dielectric layer is different from the second effective work function of the combination of the second electrode layer and the second gate dielectric layer.
  • an electronic device including the above storage device.
  • even source / drain regions in a memory cell can be controlled by corresponding electrode layers.
  • the number of stacked memory cells can be increased, and thus the integration density can be increased.
  • a portion of the active region corresponding to each electrode layer can be used as a source / drain region on the one hand, and can be used as a channel region on the other hand.
  • the integration density can be increased compared to the technology of providing a channel region and a source / drain region separately in conventional devices.
  • FIG. 1 to 12 are schematic diagrams showing some stages in the process of manufacturing a memory device according to an embodiment of the present disclosure
  • 15 (a) and 15 (b) are schematic diagrams showing different configurations of the gate dielectric layer according to an embodiment of the present disclosure.
  • a layer / element when a layer / element is referred to as being “on” another layer / element, the layer / element may be directly on the other layer / element, or there may be a middle layer / between element.
  • the layer / element may be "below” the other layer / element.
  • the memory device is based on a vertical type device, and thus may include a plurality of vertical active regions formed on the substrate and extending vertically upward (eg, substantially perpendicular to the substrate surface) from the substrate.
  • the active region may be solid or hollow (where dielectric may be filled).
  • gate stacks can be formed around their outer periphery to form vertical devices.
  • the upper and lower sides of the channel region in the active region are source / drain regions, respectively, and a gate stack is formed around the outer periphery of the channel region, and a dielectric layer is usually formed around the outer periphery of the source / drain region. That is, the channel region is controlled by the gate stack (especially the gate electrode therein), and the source / drain region has no corresponding electrode to control it.
  • a control electrode corresponding to the source / drain region may also be provided.
  • the gate electrode for controlling the source / drain region may also be provided in the form of a gate stack like the gate electrode for controlling the channel region, that is, there is a gate dielectric layer between the gate electrode and the active region to be controlled .
  • the gate stack may be a memory gate stack in order to realize the storage function. More specifically, the gate dielectric layer may constitute a data storage structure.
  • the gate stack may include a gate dielectric layer formed on at least a portion of the sidewall of the active region and a gate electrode layer facing the active region through the gate dielectric layer.
  • the gate electrode layer may extend in a direction that intersects the extending direction of the vertical active region (e.g., substantially parallel to the surface of the substrate) so as to intersect the vertical active region.
  • each gate stack it can define a channel region in the vertical active region, and correspondingly define source / drain regions, that is, portions of the active region on opposite sides of the channel region. That is to say, the part of the vertical active region corresponding to each gate stack can be used as a channel region of a certain device or as a source / drain region of another device.
  • a plurality of gate electrode layers arranged in order from bottom to top may be provided, so that a plurality of channel regions (and thus a plurality of memory cells are defined in each vertical active region, and each memory cell includes a corresponding channel region And source / drain regions on opposite sides of the channel region).
  • the channel region of each memory cell may constitute the source / drain region of the memory cell adjacent thereto.
  • the storage unit may be a flash memory unit.
  • An insulating layer for electrical isolation may be provided between adjacent gate electrode layers.
  • the electrical isolation between adjacent gate electrode layers can also be provided by the gate dielectric layer or a part thereof.
  • the memory cells are more densely arranged, so that the integration density can be improved.
  • the gate stack for the channel region and the gate stack for the source / drain region may have different effective work functions.
  • the effective work function of one of the gate stack for the channel region and the gate stack for the source / drain region can be close to the conduction band of the semiconductor material in the active region, and the other can be close to the active region The valence band of semiconductor materials. Due to this difference in effective work function, a desired carrier (electron or hole) distribution can be formed in the semiconductor material of the active region.
  • the memory device may include an electrode structure formed by alternately stacking two types of electrode layers having different work functions, especially if the gate dielectric layers are the same.
  • the vertical active regions may be arranged in an array (for example, usually a two-dimensional array arranged in rows and columns).
  • the memory device can be a three-dimensional (3D) array. In this 3D array, each vertical active area defines a string of memory cells.
  • the "gate dielectric layer constituting the data storage structure” refers to a portion of the gate stack between the gate electrode layer and the active region (or channel region).
  • the gate dielectric layer may be a stacked structure, which exhibits dielectric characteristics as a whole, that is, the gate electrode layer and the channel region are not directly electrically connected, which is called “dielectric", but this does not exclude that it may contain one or more layers Layer conductive layer.
  • the gate dielectric layer may include a charge trapping layer or a ferroelectric material, etc., in order to realize a storage function.
  • the gate dielectric layer may include a first dielectric layer, a charge trapping layer, and a second dielectric layer stacked in sequence, or may be a dielectric layer including a ferroelectric material, for example, an oxide of Hf or Zr.
  • a ferroelectric material for example, an oxide of Hf or Zr.
  • Such a memory device can be manufactured as follows, for example. Specifically, a stack layer in which the first sacrificial layer and the second sacrificial layer are alternately stacked may be provided on the substrate. To facilitate subsequent replacement processing of the sacrificial layer, an etch stop layer may be provided between adjacent sacrificial layers. Then, several vertical holes can be formed in the stack. Subsequently, an active region will be formed in these holes (corresponding to the shape of the hole, so it may be "pillared", including but not limited to cylindrical). These holes may extend along the stacking direction (vertical direction) of the laminate, and may penetrate the laminate.
  • a gate dielectric layer may be formed on the sidewall of the hole at least corresponding to each sacrificial layer. For example, a first gate dielectric layer corresponding to the first sacrificial layer and a second gate dielectric layer corresponding to the second sacrificial layer may be formed separately.
  • the gate dielectric layer thus formed together with the subsequently formed gate electrode layer constitutes a gate stack.
  • the semiconductor material may be filled (doped) in the hole to form an active region.
  • the semiconductor material can completely fill the hole to form a solid active region, or be formed only along the inner wall of the hole to form a hollow active region (the inside can be further filled with a dielectric layer).
  • the active area cooperates with each gate stack to form a memory cell.
  • the gate dielectric layer may be formed by depositing a corresponding material layer on the sidewall of the hole before filling the semiconductor material, or may be formed on the sidewall of the hole after filling the semiconductor layer (more specifically, in the hole).
  • the surface of the filled semiconductor layer is deposited by depositing a corresponding material layer, or a part of the gate stack may be formed before the semiconductor material is filled, and the remaining part may be formed after the semiconductor material is filled.
  • Vertical processing channels can be formed in the stack to expose the sacrificial layers.
  • the sacrificial layer can be removed by selective etching and replaced with a corresponding electrode layer.
  • the first sacrificial layer can be replaced with the first electrode layer
  • the second sacrificial layer can be replaced with the second electrode layer.
  • the combined effective work function of the first electrode layer and the corresponding gate dielectric layer may be different from the combined effective work function of the second electrode layer and the corresponding gate dielectric layer.
  • the work function of the first electrode layer may be different from the work function of the second electrode layer, especially if the gate dielectric layer is the same.
  • FIG. 1 to 12 are schematic diagrams showing some stages in the process of manufacturing a memory device according to an embodiment of the present disclosure.
  • the substrate 1001 may be various forms of substrates, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • SOI semiconductor-on-insulator
  • SiGe substrates SiGe substrates
  • a bulk Si substrate is taken as an example for description.
  • a well region 1001w is formed by ion implantation, for example.
  • the well region 1001w can then serve as a common source / drain connection layer (eg, a common ground potential surface) of the memory device, and the source / drain regions under each of the lowermost memory cells in the memory device can be connected to the common source / drain connection layer .
  • the well region 1001w may be doped to be n-type; if the memory cell is a p-type device, the well region 1001w may be doped to be p-type.
  • first sacrificial layers 1003, 1007 and the second sacrificial layers 1005, 1009 may be sequentially formed by, for example, deposition.
  • the first sacrificial layer 1003, 1007 and the second sacrificial layer 1005, 1009 may include materials having etch selectivity with respect to each other.
  • the first sacrificial layers 1003 and 1007 may include polycrystalline silicon with a thickness of about 10-100 nm;
  • the second sacrificial layers 1005 and 1009 may include polycrystalline SiGe (the atomic percentage of Ge is, for example, about 15-50%) with a thickness of about 10 -100nm.
  • the first sacrificial layer 1003, 1007 and the second sacrificial layer 1005, 1009 can determine the thickness or gate length of the corresponding gate-controlled source / drain, so to ensure the consistency of device performance, the first sacrificial layer 1003, 1007 and the second sacrificial layer Each of the layers 1005, 1009 may have substantially the same thickness. The steps of forming the first sacrificial layer and the second sacrificial layer may be repeated until the desired number of layers.
  • an etch stop layer 1011 may be provided between adjacent layers in the first sacrificial layer 1003, 1007 and the second sacrificial layer 1005, 1009. In addition, an etch stop layer 1011 may be provided between the lowermost first sacrificial layer 1003 and the substrate 1001.
  • the etch stop layer 1011 may include a material having etch selectivity with respect to the first sacrificial layer 1003, 1007 and the second sacrificial layer 1005, 1009 (and the substrate 1001).
  • the etch stop layer 1011 may be a dielectric material so as to be used for electrical isolation between adjacent gate electrode layers later.
  • the etch stop layer 1011 may include SiC with a thickness of about 1-5 nm.
  • the hard mask layer may include an oxide (eg, silicon oxide) layer 1013 with a thickness of, for example, about 2-10 nm and a nitride (eg, silicon nitride) layer 1015 with a thickness of, for example, about 10-100 nm.
  • oxide eg, silicon oxide
  • nitride eg, silicon nitride
  • the substrate may include a memory cell area and a contact area, a memory cell may be formed in the memory cell area, and various electrical contacts may be formed in the contact area.
  • the substrate may also include other areas, such as a circuit area for forming related circuits.
  • a photoresist 1017 may be formed on the structure shown in FIG. 1. By photolithography (exposure and development), the photoresist 1017 is patterned to have an opening at the position of the active region to expose the underlying nitride layer 1015.
  • the layout of the openings depends on the layout of the memory cells. For example, the openings can be arranged in a two-dimensional array in rows and columns.
  • a hole can be opened downward through the photoresist 1017.
  • the hard mask layer nitride layer 1015 and oxide layer 1013
  • RIE reactive ion etching
  • the above-mentioned alternately stacked first sacrificial layer, etch stop layer and second sacrificial layer can be selectively etched in sequence Layer to form holes.
  • RIE reactive ion etching
  • the photoresist 1017 may be removed.
  • the hole may penetrate the stack of the first sacrificial layer and the second sacrificial layer, and expose the well region 1001w at the bottom.
  • the hole is shown as a circle, but the present disclosure is not limited thereto.
  • the hole can be of any shape suitable for machining.
  • a gate dielectric layer may be formed along the sidewall of the hole.
  • a spacer formation process may be used to form a gate dielectric layer in the form of a sidewall on the sidewall of the hole.
  • the gate dielectric layer may constitute a data storage structure.
  • the gate dielectric layer may include a first dielectric layer 1019 (for example, oxide or high-K dielectric such as HfO 2 with a thickness of about 1-10 nm) and a charge trapping layer 1021 (for example, nitride with a thickness of about 1-20 nm) and a second dielectric layer 1023 (for example, an oxide or high-K dielectric with a thickness of about 1-10 nm), as shown in FIG. 4.
  • a first dielectric layer 1019 for example, oxide or high-K dielectric such as HfO 2 with a thickness of about 1-10 nm
  • a charge trapping layer 1021 for example, nitride with a thickness of about 1-20 nm
  • the gate dielectric layer of such a stacked configuration can be deposited on the structure shown in FIG. 3 in a substantially conformal manner in order to deposit a first dielectric layer 1019, a charge trapping layer 1021, and a second dielectric layer 1023 in a vertical direction (For example, a direction substantially perpendicular to the surface of the substrate) They are formed by RIE. In this way, a gate dielectric layer extending continuously along the sidewall of the hole can be formed.
  • a semiconductor material for example, polysilicon
  • the filled semiconductor material 1025 may extend approximately conformally along the side wall and bottom wall of the hole, with a thickness of, for example, about 4-20 nm, thereby forming a tubular structure with a closed bottom end.
  • the semiconductor material 1025 may be undoped or unintentionally doped.
  • the semiconductor material 1025 may be moderately doped (for example, the doping concentration is about 1E17-1E19cm -3 , and the doping type may depend on the specific device requirements) to adjust the device threshold voltage, reduce the device resistance, and so on.
  • the hole can be filled with semiconductor material 1025 by deposition, and in-situ doping can be performed at the same time as the deposition.
  • the filled semiconductor material 1025 may be relatively thin, and therefore the hole is not completely filled.
  • the filled semiconductor material 1025 can also completely fill the hole.
  • a dielectric material 1027 such as oxide may be further filled in the hole.
  • the semiconductor material 1025 (and the dielectric material 1027) may be subjected to a planarization process such as CMP to remove its portion outside the hole.
  • the planarization process may stop at the hard mask layer (the nitride 1015 therein).
  • the semiconductor material 1025 may also be etched back so that its top surface is lower than the top surface of the hard mask layer (but preferably higher than the top surface of the uppermost sacrificial layer). Then, a dielectric material (which may include the same material as the dielectric material 1027, shown here as 1027 in one piece) is further formed to fill the space in the hole due to the etchback of the semiconductor material 1025. The further formed dielectric material may exceed the top surface of the hard mask layer, and may be subjected to a planarization process such as CMP to have a relatively flat top surface.
  • a planarization process such as CMP
  • a doped region 1025d may also be formed at the bottom end (portion on the bottom wall of the hole) of the semiconductor material 1025 by, for example, ion implantation .
  • the doped region 1025d may be doped to the same type as the well region 1001w, and thus may have a reduced contact resistance with the well region 1001w (common source / drain connection layer), and thus may be used as an active region and The contact area between the source / drain connection layer.
  • the doped region 1025d can overlap the lowermost sacrificial layer in the lateral direction (horizontal direction in the figure), as shown by the dotted circle in FIG. 4, which helps reduce the resistance between the channel and the source / drain connection layer .
  • the semiconductor material 1025 forms a (pillar) active region.
  • the active region is filled in the hole and extends vertically on the substrate like the hole.
  • the semiconductor material 1025 in the active region is substantially homogeneous, and a contact region 1025d can be formed at the bottom end.
  • a replacement gate process may be performed to replace the first sacrificial layer and the second sacrificial layer with the final gate electrode layer.
  • a processing channel can be formed in the stack to expose each sacrificial layer.
  • a photoresist 1029 may be formed on the structure shown in FIG. 4, and the photoresist 1029 may be patterned by photolithography (exposure and development) to have openings where processing channels need to be formed.
  • the opening may be elongated in a direction extending from the memory cell area toward the contact area (horizontal direction in the figure). This is because the subsequently formed gate electrode layer needs to extend from the memory cell region to the contact region (in order to connect to the interconnection structure in the contact region to form the desired electrical connection). The above opening does not destroy the continuity of the gate electrode layer in this direction.
  • an opening extending in the row direction may be formed every several rows of active regions (here, the active regions arranged in the horizontal direction are referred to as one row).
  • FIGS. 6 (a) and 6 (b) are top views
  • FIG. 6 (b) is a cross-sectional view taken along line BB ′ in FIG. 6 (a)
  • pass the photoresist 1029. Slot down.
  • the selective etching such as RIE hard mask layer (nitride layer 1015 and oxide layer 1013) and the above-mentioned alternately stacked first sacrificial layer, etch stop layer and second sacrificial layer can be sequentially formed to form a processing channel .
  • RIE can be performed in a direction substantially perpendicular to the substrate surface, thereby obtaining a processing channel extending in a direction substantially perpendicular to the substrate surface.
  • RIE can stop at the lowermost etch stop layer 1011.
  • the photoresist 1029 may be removed.
  • the sacrificial layers 1003, 1005, 1007, and 1009 are exposed through the processing channel. Specifically, the side walls of the sacrificial layer 1003, 1005, 1007, 1009 are exposed in the processing channel.
  • the first sacrificial layer 1003, 1007 (here, Polycrystalline Si) and the etch stop layer 1011 (here, SiC)
  • the second sacrificial layers 1005, 1009 (here, polycrystalline SiGe) are removed.
  • the second sacrificial layers 1005, 1009 include polycrystalline SiGe as described above, for example, it can be removed by HCl (for example, gaseous HCl). In this way, space is left where the second sacrificial layers 1005, 1009 are located.
  • the second gate electrode layer 1031 may be formed in this space via a processing channel, for example, by deposition and then RIE in the vertical direction.
  • the second gate electrode layer 1031 may have a certain work function.
  • the second gate electrode layer 1031 may include a metal, for example, an n-type metal such as TiN, TaN, TiCAl, TiAl, TiNAl, TaC x .
  • the first sacrificial layers 1003, 1007 can be similarly replaced with the first gate electrode layer.
  • a protective layer 1033 may be formed at the sidewall of the second gate electrode layer 1031.
  • the second gate electrode layer 1031 may be etched back through the processing channel, so that the side wall of the second gate electrode layer 1031 is relatively recessed. Then, for example, by depositing and then performing RIE in the vertical direction, the protective layer 1033 is filled in this recess.
  • the protective layer 1033 thus formed may be self-aligned to the second gate electrode layer 1033.
  • the protective layer 1033 may include a material having a desired etching selectivity, such as nitride.
  • FIGS. 9 (a) and 9 (b) cross-sectional views along the line AA ′ and BB ′, respectively
  • the etch stop layer 1011 (here, SiC) is selectively etched to remove the first sacrificial layers 1003 and 1007 (here, polycrystalline Si).
  • the first sacrificial layer 1003, 1007 includes polysilicon as described above, it can be removed by a TMAH solution, for example. In this way, space is left where each first sacrificial layer 1003, 1007 is located.
  • the first gate electrode layer 1035 may be formed in the space via a processing channel, for example, by deposition and then RIE in the vertical direction.
  • the first gate electrode layer 1035 may have a work function different from that of the second gate electrode layer 1031.
  • the first gate electrode layer 1035 may include a metal, for example, a p-type metal such as TiN, TaAl.
  • Each gate electrode layer 1031, 1035 may define a channel region in the active region. Therefore, in the memory cell region, a vertical string of memory cells is formed, and each memory cell includes a corresponding channel region and source / drain regions located on both sides of the channel region.
  • An example of memory cells in the upper and lower layers is shown by a dotted circle in FIG. 9 (a).
  • the lower memory cell includes a channel region corresponding to the second gate electrode layer 1031 and source / drain regions on the upper and lower sides of the channel region. The source / drain regions are affected by the first gate electrode layer 1035 control.
  • the upper memory cell includes a channel region corresponding to the first gate electrode layer 1035 and source / drain regions on the upper and lower sides of the channel region. The source / drain regions are controlled by the second gate electrode layer 1031.
  • the etch stop layer is relatively thin, excluding here), namely the first sacrificial layer-second sacrificial layer-first sacrificial layer-second sacrificial layer .
  • the two-layer memory cell configuration can be realized. Therefore, the integration density can be improved.
  • the second sacrificial layer is replaced first, and then the first sacrificial layer is replaced.
  • the present disclosure is not limited to this.
  • the first sacrificial layer can be replaced first, and then the second sacrificial layer can be replaced.
  • the first gate electrode layer includes p-type metal
  • the second gate electrode layer includes n-type metal.
  • the present disclosure is not limited to this.
  • the first gate electrode layer may include n-type metal
  • the first gate electrode layer may include p-type metal.
  • the electrode structure in the contact region may be patterned in a stepped shape so as to form electrical contacts to the gate electrode layers.
  • a dielectric material may be further filled in the processing channel to shield the formed electrode structure ( The first gate electrode layer and the second gate electrode layer).
  • the filled dielectric material may be the same as the dielectric material 1027 described above.
  • the dielectric material may be subjected to planarization CMP, and CMP may be stopped at the hard mask layer (the nitride layer 1015 therein) to obtain a dielectric layer 1027 '.
  • the electrode structure can be etched by trimming the photoresist and using the photoresist as an etching mask.
  • the electrode structure is patterned in steps.
  • a dielectric (which may be the same as the material of the dielectric material 1027) may be further filled to obtain a dielectric layer 1027 ".
  • a common source / drain connection layer 1001w (and thus to The source / drain regions of all the lowermost memory cells), the electrical contacts to each gate electrode layer, and the electrical contacts 1037 to the source / drain regions of each uppermost memory cell.
  • Such electrical contacts may It is made by forming a contact hole in the dielectric layer and filling it with a conductive material such as tungsten (W).
  • a diffusion barrier layer such as TiN may be formed on the sidewall of the contact hole.
  • the memory device may include a plurality of memory cell layers (in this example, only two layers are shown), and each memory cell layer includes an array of memory cells.
  • Each memory cell includes a channel region opposite to the corresponding gate electrode layer and source / drain regions on both sides of the channel region. The source / drain regions are also controlled by the corresponding gate electrode layer.
  • the memory cells in the same active area extending in the vertical direction are connected in a string in the vertical direction, connected to corresponding electrical contacts at the upper end, and connected to the common source / drain connection layer at the lower end.
  • the memory cells in each layer share the same gate electrode layer.
  • a certain memory cell layer can be selected.
  • a certain memory cell string can be selected.
  • electrical contacts are formed for the source / drain regions of each memory cell in the uppermost layer. Since the density of memory cells is large, the density of such source / drain contacts is large.
  • electrodes arranged in rows (or columns) that are electrically connected to the source / drain regions of the lowermost memory cell may be formed, and columns that are electrically connected to the source / drain regions of the uppermost memory cell may be formed (Or row) arranged electrodes. In this way, through the upper electrode and the lower electrode (crossing each other to form an array corresponding to the memory cell array), the corresponding memory cell string can be selected.
  • a selection transistor may also be added to the uppermost end and / or the lowermost end of the active region, which will not be repeated here.
  • Such a selection transistor may also be a vertical device.
  • Figure 13 shows the effect of gate stacks with different effective work functions on semiconductor materials.
  • the first electrode layer Ma and the second electrode layer Mb are provided on the semiconductor material 2001 (for example, Si). Between the first electrode layer Ma, the second electrode layer Mb and the semiconductor material 2001, a (gate) dielectric layer 2100 is provided.
  • the first electrode layer Ma and the gate dielectric layer 2100 constitute a first gate stack
  • the second electrode layer Mb and the gate dielectric layer 2100 constitute a second gate stack.
  • the first gate stack and the second gate stack have different effective work functions.
  • the first electrode layer Ma and the second electrode layer Mb may have different work functions so that the first gate stack and the second gate stack The two-gate stack provides different effective work functions.
  • the effective work function of the first gate stack is closer to the conductive energy level of the semiconductor material 2001, and the effective work function of the second gate stack is closer to the valence band level of the semiconductor material 2001, then it can be obtained as shown in FIG. 13
  • the electron potential of, that is, the electron concentration in the portion of the semiconductor material 2001 corresponding to the first gate stack may be higher than the electron concentration in the portion of the semiconductor material 2001 corresponding to the second gate stack.
  • the portion of the semiconductor material 2001 corresponding to the first gate stack may appear as an n-type semiconductor
  • the portion of the semiconductor material 2001 corresponding to the second gate stack may appear as a p-type semiconductor.
  • 14 (a) and 14 (b) respectively show configurations of an n-type device and a p-type device according to an embodiment of the present disclosure.
  • a first electrode layer Ma, a second electrode layer Mb, and a first electrode layer Ma that are adjacently formed are formed on the gate dielectric layer 2100 formed on the surface of the semiconductor material 2001. Since the first electrode layer Ma and the second electrode layer Mb have different work functions, they are combined with the gate dielectric layer 2100 to provide different effective work functions. Thus, as described above, the electron potential as shown in the figure can be established in the semiconductor material 2001. In other words, a structure in which n-type semiconductors, p-type semiconductors, and n-type semiconductors are adjacently formed in the semiconductor material 2001 is a characteristic of n-type devices.
  • the electron potential as shown in the figure can be established in the semiconductor material 2001.
  • a structure in which a p-type semiconductor, an n-type semiconductor, and a p-type semiconductor are adjacently formed in the semiconductor material 2001 is a characteristic of a p-type device.
  • the memory cell string described in the above embodiments may be a p-type device or an n-type device connected in series, which is a typical NAND structure.
  • the read and write operations of this storage device can be the same as conventional 3D NAND flash memory. The only difference is that a voltage needs to be applied to the first gate electrode layer and the second gate electrode layer, so that a p-type device or an n-type device is formed at least when the state of storing 0 or the absolute value of the threshold voltage is at least in the memory cell string
  • the series structure of the device, that is, the corresponding memory cell is in the off state.
  • a voltage can be applied to all second gate electrode layers so that the active regions under its control become n-type semiconductors Or a p-type semiconductor, a voltage is applied to all the first gate electrode layers at the same time, so that the active region under its control becomes a p-type semiconductor or an n-type semiconductor when the state where 0 is stored or the absolute value of the threshold voltage is maximized.
  • the first gate electrode layer is used as a gate to perform read and write operations, and reading and writing can be completed.
  • similar read and write operations can be performed on the second gate electrode.
  • the gate dielectric layer is first formed along the sidewall of the hole, and then the semiconductor material is filled in the hole to form an active region.
  • the present disclosure is not limited to this.
  • a part of the gate dielectric layer may be formed along the sidewall of the hole, and then other parts of the gate dielectric layer may be formed when forming the gate electrode layer.
  • a charge trapping layer 1021 and a second dielectric layer 1023 may be formed along the sidewall of the hole, and then after removing the sacrificial layer and before filling the gate electrode layer, the first dielectric layer 1019 is formed .
  • the gate dielectric layer may not be formed before filling the semiconductor material, and then the gate dielectric layer may be formed when the gate electrode layer is formed.
  • the gate dielectric layer may be formed when the gate electrode layer is formed. For example, as shown in FIG. 15 (b), after the sacrificial layer is removed and before the gate electrode layer is filled, a stack of the second dielectric layer 1023, the charge trapping layer 1021, and the first dielectric layer 1019 may be formed.
  • the gate dielectric layer may be different. As long as the gate electrode layer and the gate dielectric layer can provide different effective work functions.
  • the gate electrode layer is not limited to a single-layer structure, and may include a stacked-layer structure.
  • the memory device can be applied to various electronic devices.
  • the storage device may store various programs, applications, and data necessary for the operation of the electronic equipment.
  • the electronic device may also include a processor cooperating with the storage device.
  • the processor may operate the electronic device by allowing the program stored in the storage device.
  • Such electronic devices are, for example, smart phones, computers, tablet computers (PCs), wearable smart devices, mobile power supplies, robots, smart chips, and so on.

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Abstract

一种存储器件及其制造方法及包括该存储器件的电子设备，该存储器件可以包括：衬底（1001）；设置在衬底（1001）上的电极结构，包括交替堆叠的多个第一电极层和多个第二电极层；穿透电极结构的多个竖直有源区；设置在竖直有源区与电极结构中的各第一电极层之间的第一栅介质层以及设置在竖直有源区与电极结构中的各第二电极层之间的第二栅介质层，其中，第一栅介质层和第二栅介质层分别构成数据存储结构。第一电极层与第一栅介质层的组合的第一有效功函数不同于第二电极层与第二栅介质层的组合的第二有效功函数。

Description

存储器件及其制造方法及包括该存储器件的电子设备
相关申请的引用
本申请要求于2018年11月9日递交的题为“存储器件及其制造方法及包括该存储器件的电子设备”的中国专利申请201811336212.1的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，具体地，涉及基于竖直型器件的存储器件及其制造方法以及包括这种存储器件的电子设备。
背景技术
在水平型器件如金属氧化物半导体场效应晶体管(MOSFET)中，源极、栅极和漏极沿大致平行于衬底表面的方向布置。由于这种布置，水平型器件不易进一步缩小。与此不同，在竖直型器件中，源极、栅极和漏极沿大致垂直于衬底表面的方向布置。因此，相对于水平型器件，竖直型器件更容易缩小。
基于竖直型器件，可以制作三维(3D)存储器件，如闪存(NAND型或NOR型)。目前，随着3D存储器件中层数的增加，已经越来越难以进一步增加其集成密度。另外，难以降低存储单元的源/漏电阻。于是，竖直叠置的存储单元的源/漏电阻串联在一起，导致总电阻增大，存储器件性能变差。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种具有改进特性的基于竖直型器件的存储器件及其制造方法以及包括这种存储器件的电子设备。
根据本公开的一个方面，提供了一种存储器件，包括：衬底；设置在衬底上的电极结构，包括交替堆叠的多个第一电极层和多个第二电极层；穿透电极结构的多个竖直有源区；设置在竖直有源区与电极结构中的各第一电极层之间的第一栅介质层以及设置在竖直有源区与电极结构中的各第二电极层之间的第二栅介质层，其中，第一栅介质层和第二栅介质层分别构成数据存储结构。 第一电极层与第一栅介质层的组合的第一有效功函数不同于第二电极层与第二栅介质层的组合的第二有效功函数。
根据本公开的另一方面，提供了一种制造存储器件的方法，包括：在衬底上设置多个第一牺牲层和多个第二牺牲层交替堆叠的叠层；形成穿透所述叠层的多个竖直孔；在所述竖直孔的侧壁上形成与第一牺牲层相对应的第一栅介质层以及与第二牺牲层相对应的第二栅介质层；在竖直孔中填充半导体材料，以形成有源区；将第一牺牲层替换为第一电极层；以及将第二牺牲层替换为第二电极层。第一电极层与第一栅介质层的组合的第一有效功函数不同于第二电极层与第二栅介质层的组合的第二有效功函数。
根据本公开的另一方面，提供了一种电子设备，包括上述存储器件。
根据本公开的实施例，即便是存储单元中的源/漏区也可以受相应电极层控制。于是，可以降低源/漏电阻，并因此降低叠置的存储单元的总串联电阻。于是，叠置的存储单元数目可以增大，并因此可以增加集成密度。
根据本公开的实施例，有源区中与各电极层相对应的部分一方面可以用作源/漏区，另一方面可以用作沟道区。与常规器件中分别地提供沟道区和源/漏区的技术相比，可以增加集成密度。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1至12(b)示出了根据本公开实施例的制造存储器件的流程中部分阶段的示意图；
图13、14(a)和14(b)示出了根据本公开实施例的存储器件的工作原理的示意图；
图15(a)和15(b)示出了根据本公开实施例的栅介质层的不同配置的示意图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是 示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开实施例的存储器件基于竖直型器件，因此可以包括在衬底上形成的从衬底向上竖直(例如，大致垂直于衬底表面)延伸的多个竖直有源区。有源区可以是实心的，也可以是空心的(其中可以填充电介质)。基于这些竖直有源区，可以绕它们外周形成栅堆叠，以形成竖直器件。
在常规的竖直器件中，有源区中沟道区的上下两侧分别是源/漏区，且绕沟道区的外周形成栅堆叠，而绕源/漏区的外周通常形成电介质层。也即，沟道区受栅堆叠(尤其是其中的栅电极)的控制，而源/漏区并无相应的电极来进行控制。
与上述常规竖直器件不同，根据本公开的实施例，还可以设置与源/漏区相对应的控制电极(在此，也可以称为“栅电极”)。用于控制源/漏区的栅电极也可以如同用于控制沟道区的栅电极一样以栅堆叠的形式来设置，也即，在栅电极与要控制的有源区之间存在栅介质层。通过这种栅电极来控制源/漏区，可以降低源/漏电阻。
栅堆叠可以是存储栅堆叠，以便实现存储功能。更具体地，栅介质层可以构成数据存储结构。例如，栅堆叠可以包括在有源区的至少一部分侧壁上形成的栅介质层以及介由栅介质层面对有源区的栅电极层。栅电极层可以沿与竖直有源区的延伸方向相交的方向(例如，大致平行于衬底表面)延伸，从而与竖 直有源区相交。
对于每一栅堆叠，其可以在竖直有源区中限定沟道区，且相应地限定了源/漏区，即有源区中位于沟道区相对两侧的部分。也就是说，竖直有源区中与各栅堆叠相对应的部分，既可以用作某一器件的沟道区，也可以用作另一器件的源/漏区。
可以设置从下向上依次排列的多层栅电极层，从而在各竖直有源区中相应地限定多个沟道区(并因此限定多个存储单元，每个存储单元包括相应的沟道区以及该沟道区相对两侧的源/漏区)。每一存储单元的沟道区可以构成与之相邻的存储单元的源/漏区。在此，存储单元可以是闪存(flash)单元。相邻的栅电极层之间可以设置有用于电隔离的绝缘层。当然，相邻栅电极层之间的电隔离也可以由栅介质层或其一部分来提供。相比于常规技术，存储单元更为密集地布置，从而可以提高集成密度。
对于这样的配置，为了使各存储单元能够更好地工作，针对沟道区的栅堆叠与针对源/漏区的栅堆叠可以具有不同的有效功函数。例如，针对沟道区的栅堆叠与针对源/漏区的栅堆叠中一种的有效功函数可以接近有源区中半导体材料的导带，而另一种的有效功函数可以接近有源区中半导体材料的价带。由于这种有效功函数的差异，可以在有源区的半导体材料中形成所需的载流子(电子或空穴)分布。于是，存储器件可以包括由具有不同功函数的两种电极层交替堆叠而形成的电极结构，特别是在栅介质层相同的情况下。
竖直有源区可以排列为阵列(例如，通常是按行和列排列的二维阵列)。另外，由于它们如上所述在衬底上竖直延伸且通过多层的栅电极层分别限定出多层存储单元，从而该存储器件可以是三维(3D)阵列。在该3D阵列中，各竖直有源区限定了存储单元的串。
在本文中，所谓“构成数据存储结构的栅介质层”是指栅堆叠中处于栅电极层和有源区(或者说沟道区)之间的部分。栅介质层可以是叠层结构，整体上呈现电介质特性，即，使得栅电极层与沟道区并不直接电连接，从而称作“介质”，但是这并不排除其中可能包含一层或多层导电层。栅介质层可以包括电荷俘获层或者铁电材料等，以便实现存储功能。例如，栅介质层可以包括依次叠置的第一介质层、电荷俘获层和第二介质层，或者可以为包括铁电材料的介 质层，例如，Hf或Zr的氧化物。本领域存在各种能够实现存储功能的存储栅堆叠配置，在此不再赘述。
这种存储器件例如可以如下制造。具体地，可以在衬底上设置第一牺牲层和第二牺牲层交替堆叠的叠层。为便于后继对牺牲层的替换处理，在相邻的牺牲层之间可以设置刻蚀停止层。然后，可以在叠层中形成若干竖直孔。随后，将在这些孔中形成有源区(与孔的形状相对应，因此可以是“柱状”，包括但不限于圆柱状)。这些孔可以沿着叠层的堆叠方向(竖直方向)延伸，并可以贯穿叠层。
可以在孔的侧壁上至少与各牺牲层相对应之处，形成栅介质层。例如，可以分别形成与第一牺牲层相对应的第一栅介质层以及与第二牺牲层相对应的第二栅介质层。如此形成的栅介质层与随后形成的栅电极层一起，构成栅堆叠。可以在孔中填充(掺杂的)半导体材料，以形成有源区。半导体材料可以完全填满孔从而形成实心的有源区，或者仅沿孔的内壁形成从而形成空心的有源区(内侧可以进一步填充电介质层)。有源区与各栅堆叠相配合，形成存储单元。
栅介质层可以是在填充半导体材料之前通过在孔的侧壁上淀积相应的材料层而形成，也可以是在填充半导体层之后通过在孔的侧壁上(更具体地，在孔中所填充的半导体层的表面上)淀积相应的材料层而形成，或者栅堆叠的一部分可以在填充半导体材料之前形成，而其余部分可以在填充半导体材料之后形成。
可以在叠层中形成竖直的加工通道，以露出各牺牲层。可以通过选择性刻蚀，去除牺牲层，并代之以相应的电极层。如上所述，可以将第一牺牲层替换为第一电极层，并可以将第二牺牲层替换为第二电极层。第一电极层与相应栅介质层的组合的有效功函数可以不同于第二电极层与相应栅介质层的组合的有效功函数。第一电极层的功函数可以不同于第二电极层的功函数，特别是在栅介质层相同的情况下。
本公开可以各种形式呈现，以下将描述其中一些示例。
图1至12(b)示出了根据本公开实施例的制造存储器件的流程中部分阶段的示意图。
如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括 但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
在衬底1001中，例如通过离子注入，形成阱区1001w。该阱区1001w随后可以充当存储器件的公共源/漏连接层(例如，公共地电势面)，存储器件中最下层存储单元各自下层的源/漏区均可以连接到该公共源/漏连接层。如果最下层的存储单元是n型器件，则阱区1001w可以掺杂为n型；如果存储单元是p型器件，则阱区1001w可以掺杂为p型。
在衬底1001上，可以通过例如淀积，依次形成第一牺牲层1003、1007和第二牺牲层1005、1009的交替堆叠。第一牺牲层1003、1007和第二牺牲层1005、1009可以包括相对于彼此具有刻蚀选择性的材料。例如，第一牺牲层1003、1007可以包括多晶硅，厚度为约10-100nm；第二牺牲层1005、1009可以包括多晶SiGe(Ge的原子百分比例如为约15-50％)，厚度为约10-100nm。第一牺牲层1003、1007和第二牺牲层1005、1009可以确定相应的栅控源/漏的厚度或者栅长，因此为确保器件性能的一致性，第一牺牲层1003、1007和第二牺牲层1005、1009中的每一层可以具有实质上相同的厚度。可以重复形成第一牺牲层和第二牺牲层的步骤，直至所需的层数。
另外，为了更好地控制刻蚀，在第一牺牲层1003、1007和第二牺牲层1005、1009中相邻的层之间，可以设置刻蚀停止层1011。另外，在最下层的第一牺牲层1003与衬底1001之间，也可以设置刻蚀停止层1011。刻蚀停止层1011可以包括相对于第一牺牲层1003、1007和第二牺牲层1005、1009(以及衬底1001)具有刻蚀选择性的材料。另外，刻蚀停止层1011可以是电介质材料，以便随后还可以用于相邻栅电极层之间的电隔离。例如，刻蚀停止层1011可以包括SiC，厚度为约1-5nm。
另外，为了后继处理中构图的方便以及提供适当的停止层等目的，在所生长的这些层之上，还可以形成硬掩模层。例如，硬掩模层可以包括厚度例如为约2-10nm的氧化物(例如，氧化硅)层1013以及厚度例如为约10-100nm的氮化物(例如，氮化硅)层1015。
随后，可以限定有源区的位置。如图2的俯视图所示，衬底可以包括存储 单元区和接触区，在存储单元区中可以形成存储单元，而在接触区中可以形成各种电接触部。当然，衬底还可以包括其他区域，例如用于形成相关电路的电路区等。在存储单元区中，可以在图1所示的结构上形成光刻胶1017。通过光刻(曝光和显影)，将光刻胶1017构图为在有源区的位置处具有开口，以露出之下的氮化物层1015。开口的布局根据存储单元的布局而定，例如各开口可以按行和列排列为二维阵列。
接着，如图3(沿图2中AA′线的截面图)所示，可以通过光刻胶1017，向下开孔。具体地，可以依次选择性刻蚀例如反应离子刻蚀(RIE)硬掩模层(氮化物层1015和氧化物层1013)以及上述交替堆叠的第一牺牲层、刻蚀停止层和第二牺牲层，以形成孔。例如，RIE可以沿大致垂直于衬底表面的方向进行，从而得到沿大致垂直于衬底表面的方向延伸的孔。之后，可以去除光刻胶1017。在该示例中，孔可以贯穿第一牺牲层和第二牺牲层的叠层，并在底部露出阱区1001w。
在此，将孔示出为圆形，但是本公开不限于此。孔可以是适于加工的任何形状。
可以沿孔的侧壁形成栅介质层。例如，可以按侧墙(spacer)形成工艺，来在孔的侧壁上形成侧墙形式的栅介质层。根据本公开的实施例，栅介质层可以构成数据存储结构。例如，栅介质层可以包括依次叠置的第一介质层1019(例如，氧化物或高K介质如HfO 2，厚度为约1-10nm)、电荷俘获层1021(例如，氮化物，厚度为约1-20nm)和第二介质层1023(例如，氧化物或高K介质，厚度为约1-10nm)，如图4所示。这种叠层配置的栅介质层可以通过在图3所示的结构上以大致共形的方式依次淀积第一介质层1019、电荷俘获层1021和第二介质层1023，并沿竖直方向(例如，大致垂直于衬底表面的方向)对它们进行RIE来形成。这样，可以形成沿孔的侧壁连续延伸的栅介质层。
然后，可以在侧壁上形成有栅介质层的孔中填充半导体材料(例如，多晶硅)，以形成有源区。如图4所示，所填充的半导体材料1025可以沿着孔的侧壁和底壁大致共形延伸，厚度例如为约4-20nm，从而形成底端封闭的管状结构。在此，半导体材料1025可以未掺杂或未有意掺杂。备选地，半导体材料1025可以中等掺杂(例如，掺杂浓度为约1E17-1E19cm -3，掺杂类型可以视具 体器件要求而定)以调节器件阈值电压、减低器件电阻等。
例如，可以通过淀积向孔中填充半导体材料1025，在淀积同时可以进行原位掺杂。在该示例中，所填充的半导体材料1025可以相对较薄，且因此没有完全填满孔。当然，所填充的半导体材料1025也可以完全填满孔。在未完全填满孔的情况下，还可以进一步在孔中填充电介质材料1027如氧化物。可以对半导体材料1025(和电介质材料1027)进行平坦化处理如CMP，以去除其位于孔之外的部分。例如，平坦化处理可以停止于硬掩模层(其中的氮化物1015)。根据本公开的实施例，还可以对半导体材料1025进行回蚀，以使其顶面低于硬掩模层的顶面(但优选地高于最上面的牺牲层的顶面)。然后，进一步形成电介质材料(可以与电介质材料1027包括相同的材料，在此一体示出为1027)，以填满由于半导体材料1025的回蚀而在孔中导致的空间。进一步形成的电介质材料可以超出硬掩模层的顶面，并且可以进行平坦化处理如CMP，以具有相对平坦的顶面。
根据本公开的实施例，在填充半导体材料1025之后且在填充电介质材料1027之前，还可以通过例如离子注入，在半导体材料1025的底端(在孔的底壁上的部分)形成掺杂区1025d。该掺杂区1025d可以被掺杂为与阱区1001w相同的类型，从而与阱区1001w(公共源/漏连接层)之间可以具有减小的接触电阻，并因此可以用作有源区与源/漏连接层之间的接触区。掺杂区1025d在横向(图中水平方向)上可以与最下方的牺牲层相交迭，如图4中的虚线圈所示，这有助于降低沟道与源/漏连接层之间的电阻。
这样，半导体材料1025形成了(柱状)有源区。有源区填充在孔内，同孔一样在衬底上竖直延伸。有源区中半导体材料1025基本是匀质的，且在底端可以形成接触区1025d。
接下来，可以进行替代栅工艺，以将第一牺牲层和第二牺牲层替换为最终的栅电极层。为了方便替换牺牲层，可以在叠层中形成加工通道，以露出各牺牲层。
为此，如图5所示，可以在图4所示的结构上形成光刻胶1029，并通过光刻(曝光和显影)将光刻胶1029构图为在需要形成加工通道之处具有开口。在此，开口可以是沿着从存储单元区指向接触区的方向(图中水平方向)延伸 的长条状。这是因为随后形成的栅电极层需要从存储单元区延伸到接触区(以便在接触区中连接到互连结构，从而形成所需的电连接)。上述开口不会破坏栅电极层在该方向上的连续性。在光刻胶1029中，可以每隔若干行的有源区(在此，将沿水平方向排列的有源区称为一行)形成一个沿行方向延伸的开口。
然后，如图6(a)和6(b)(图6(a)是俯视图，图6(b)是沿图6(a)中BB′线的截面图)所示，通过光刻胶1029，向下开槽。具体地，可以依次选择性刻蚀如RIE硬掩模层(氮化物层1015和氧化物层1013)以及上述交替堆叠的第一牺牲层、刻蚀停止层和第二牺牲层，以形成加工通道。例如，RIE可以沿大致垂直于衬底表面的方向进行，从而得到沿大致垂直于衬底表面的方向延伸的加工通道。RIE可以停止于最下方的刻蚀停止层1011。之后，可以去除光刻胶1029。如图6(b)所示，通过加工通道，露出各牺牲层1003、1005、1007、1009。具体地，牺牲层1003、1005、1007、1009的侧壁在加工通道中露出。
接下来，如图7(a)和7(b)(分别是沿AA′线和BB′线的截面图)所示，可以经由加工通道，相对于第一牺牲层1003、1007(在此，多晶Si)和刻蚀停止层1011(在此，SiC)，通过选择性刻蚀，去除第二牺牲层1005、1009(在此，多晶SiGe)。在第二牺牲层1005、1009如上所述包括多晶SiGe的情况下，例如可以通过HCl(例如，气态HCl)来去除。这样，在各第二牺牲层1005、1009所在的位置处，留下了空间。之后，可以经由加工通道，例如通过淀积然后沿竖直方向进行RIE，在该空间中形成第二栅电极层1031。第二栅电极层1031可以具有一定的功函数。例如，第二栅电极层1031可以包括金属，例如n型金属如TiN、TaN、TiCAl、TiAl、TiNAl、TaC x。
可以类似地将第一牺牲层1003、1007替换为第一栅电极层。为了在替换过程中保护第二栅电极层1031，如图8(沿BB′线的截面图)所示，可以在第二栅电极层1031的侧壁处形成保护层1033。例如，可以通过加工通道，对第二栅电极层1031进行回蚀，使得第二栅电极层1031的侧壁相对凹入。然后，例如通过淀积然后沿竖直方向进行RIE，在这种凹入中填充保护层1033。如此形成的保护层1033可以自对准于第二栅电极层1033。保护层1033可以包括具有所需刻蚀选择性的材料，例如氮化物。
然后，如图9(a)和9(b)(分别是沿AA′线和BB′线的截面图)所示，可以 经由加工通道，相对于保护层1033(在此，氮化物)和刻蚀停止层1011(在此，SiC)，通过选择性刻蚀，去除第一牺牲层1003、1007(在此，多晶Si)。在第一牺牲层1003、1007如上所述包括多晶硅的情况下，例如可以通过TMAH溶液来去除。这样，在各第一牺牲层1003、1007所在的位置处，留下了空间。之后，可以经由加工通道，例如通过淀积然后沿竖直方向进行RIE，在该空间中形成第一栅电极层1035。第一栅电极层1035可以具有不同于第二栅电极层1031的功函数。例如，第一栅电极层1035可以包括金属，例如p型金属如TiN、TaAl。
各栅电极层1031、1035可以在有源区中限定沟道区。因此，在存储单元区中，形成了存储单元的竖直串，每一存储单元包括相应的沟道区以及位于沟道区上下两侧的源/漏区。图9(a)中以虚线圈示出了上下两层存储单元的示例。如图9(a)所示，下层的存储单元包括与第二栅电极层1031相对应的沟道区以及沟道区上下两侧的源/漏区，源/漏区受第一栅电极层1035的控制。类似地，上层的存储单元包括与第一栅电极层1035对应的沟道区以及沟道区上下两侧的源/漏区，源/漏区受第二栅电极层1031的控制。
根据本公开的实施例，通过衬底上的四层堆叠结构(刻蚀停止层相对较薄，在此不计)，即第一牺牲层-第二牺牲层-第一牺牲层-第二牺牲层，就可以实现两层存储单元配置。而在常规技术中，需要衬底上的至少五层堆叠结构，即绝缘层(对应于源/漏区)-牺牲层(随后替换为栅电极层)-绝缘层(对应于源/漏区)-牺牲层(随后替换为栅电极层)-绝缘层(对应于源/漏区)，才可实现两层存储单元配置。因此，可以提高集成密度。
在以上实施例中，先替换第二牺牲层，然后替换第一牺牲层。但是，本公开不限于此。例如，可以先替换第一牺牲层，然后替换第二牺牲层。另外，在以上实施例中，第一栅电极层包括p型金属，且第二栅电极层包括n型金属。但是，本公开不限于此。例如，第一栅电极层可以包括n型金属，且第一栅电极层可以包括p型金属。
随后，可以制造各种电接触部以实现所需的电连接。对于三维阵列，本领域存在多种方式来制作互连。例如，可以将接触区中的电极结构构图为阶梯状，以便形成到各层栅电极层的电接触部。
为此，如图10(a)和10(b)(分别是沿AA′线和BB′线的截面图)所示，可以在加工通道中进一步填充电介质材料，以遮蔽所形成的电极结构(第一栅电极层和第二栅电极层)。例如，填充的电介质材料可以与上述电介质材料1027相同。可以对电介质材料进行平坦化处理CMP，CMP可以停止于硬掩模层(其中的氮化物层1015)，得到电介质层1027′。
然后，如图11(沿AA′线线的截面图)所示，可以通过光刻胶的修整(trimming)并以光刻胶为刻蚀掩模对电极结构进行刻蚀，在接触区中将电极结构构图为阶梯状。在电极结构由于被构图为阶梯状而导致的空隙中，可以进一步填充电介质(可以与电介质材料1027的材料相同)，从而得到电介质层1027″。
如图12(a)和12(b)(分别是沿AA′线和BB′线的截面图)所示，在电介质层1027″中，可以形成到公共源/漏连接层1001w(且因此到所有的最下层存储单元的源/漏区)的电接触部、到各栅电极层的电接触部以及到各最上层存储单元的源/漏区的电接触部1037。这种电接触部可以通过在电介质层中形成接触孔、并在其中填充导电材料如钨(W)来制作。另外，在填充导电材料之前，可以在接触孔的侧壁上形成扩散阻挡层如TiN。
于是，得到了根据该实施例的存储器件。如图12(a)和12(b)所示，该存储器件可以包括多个存储单元层(在该示例中，仅示出了两层)，每个存储单元层包括存储单元的阵列。每一存储单元包括与相应栅电极层相对的沟道区以及位于沟道区两侧的源/漏区。源/漏区也受相应栅电极层的控制。沿竖直方向延伸的同一有源区中各存储单元在竖直方向上连接成串，在上端连接到相应的电接触部，在下端连接到公共源/漏连接层。每一层中的存储单元共享相同的栅电极层。
通过到栅电极层的电接触部，可以选择某一存储单元层。另外，通过源/漏接触部，可以选择某一存储单元串。
在该示例中，针对最上层的每个存储单元的源/漏区，均形成电接触部。由于存储单元的密度较大，故而这种源/漏接触部的密度较大。根据另一实施例，可以形成与最下层的存储单元的源/漏区电连接的按行(或列)排列的电极，且形成与最上层的存储单元的源/漏区电连接的按列(或行)排列的电极。 这样，通过上侧的电极和下侧的电极(彼此交叉形成与存储单元阵列相对应的阵列)，可以选择相应的存储单元串。
另外，根据本公开的实施例，还可以在有源区的最上端和/或最下端增加选择晶体管，在此不再赘述。这种选择晶体管也可以是竖直型器件。
以下，将结合图13、14(a)和14(b)解释根据本公开实施例的存储器件的工作原理。
图13示出了具有不同有效功函数的栅堆叠对于半导体材料的影响。
如图13所示，在半导体材料2001(例如，Si)上设置第一电极层Ma和第二电极层Mb。在第一电极层Ma、第二电极层Mb与半导体材料2001之间，设置有(栅)介质层2100。第一电极层Ma与栅介质层2100构成了第一栅堆叠，第二电极层Mb与栅介质层2100构成了第二栅堆叠。第一栅堆叠和第二栅堆叠具有不同的有效功函数。在该示例中，由于第一栅堆叠和第二栅堆叠具有相同的栅介质层2100，因此第一电极层Ma和第二电极层Mb可以具有不同的功函数，以便为第一栅堆叠和第二栅堆叠提供不同的有效功函数。由于不同的有效功函数，可以在半导体材料2001中导致不同的电场，并因此可以导致相应的(电子或空穴)载流子分布。在此，假设第一栅堆叠的有效功函数更接近半导体材料2001的导电能级，而第二栅堆叠的有效功函数更接近半导体材料2001的价带能级，则可以得到如图13所示的电子电势，即半导体材料2001中与第一栅堆叠相对应的部分中的电子浓度可以高于半导体材料2001中与第二栅堆叠相对应的部分中的电子浓度。于是，半导体材料2001中与第一栅堆叠相对应的部分可以呈现为n型半导体，而半导体材料2001中与第二栅堆叠相对应的部分可以呈现为p型半导体。
图14(a)和14(b)分别示出了根据本公开实施例的n型器件和p型器件的配置。
如图14(a)所示，在半导体材料2001的表面上形成的栅介质层2100上形成相邻设置的第一电极层Ma、第二电极层Mb和第一电极层Ma。由于第一电极层Ma和第二电极层Mb具有不同的功函数，它们分别与栅介质层2100相结合而提供了不同的有效功函数。于是，如上所述可以在半导体材料2001中建立了如图所示的电子电势。换言之，在半导体材料2001中形成了n型半导 体、p型半导体和n型半导体相邻设置的结构，这是n型器件的特性。
类似地，如图14(b)所示，通过依次设置的第二电极层Mb、第一电极层Ma和第二电极层Mb，可以在半导体材料2001中建立如图所示的电子电势。换言之，在半导体材料2001中形成了p型半导体、n型半导体和p型半导体相邻设置的结构，这是p型器件的特性。
于是，以上实施例中描述的存储单元串可以是p型器件或n型器件的串联连接，这是典型的NAND结构。这种存储器件的读写操作可以与常规3D NAND闪存一样。不同之处仅在于需要向第一栅电极层和第二栅电极层施加电压，使得在存储单元串中至少在存储0的状态或阈值电压的绝对值最大的状态时形成p型器件或n型器件的串联结构，也即相应的存储单元处于关断状态。例如，要读出与第一栅电极层相对应的栅介质层中存储的电荷信息时，可以向所有第二栅电极层施加电压，使得在其控制下的有源区都变为n型半导体或p型半导体，同时向所有第一栅电极层施加电压，使在其控制下的有源区在存储0的状态或阈值电压的绝对值最大的状态时变为p型半导体或n型半导体。在所有第二栅电极层的电压不变(或维持其控制区为n型半导体或p型半导体)的情况下，把第一栅电极层作为栅极进行读写操作，即可完成读写。同理，可以对第二栅电极进行类似的读写操作。
在以上实施例中，先沿孔的侧壁形成栅介质层，然后在孔中填充半导体材料以形成有源区。但是，本公开不限于此。例如，可以先沿孔的侧壁形成部分栅介质层，随后在形成栅电极层时形成栅介质层的其他部分。例如，如图15(a)所示，可以沿孔的侧壁形成电荷俘获层1021和第二介质层1023，随后在去除牺牲层之后且在填充栅电极层之前，先形成第一介质层1019。或者，可以在填充半导体材料之前并不形成栅介质层，随后在形成栅电极层时形成栅介质层。例如，如图15(b)所示，可以在去除牺牲层之后且在填充栅电极层之前，先形成第二介质层1023、电荷俘获层1021和第一介质层1019的叠层。
在以上示例中，说明了栅介质层相同而栅电极层具有不同功函数的情况。但是，本公开不限于此。例如，栅介质层可以不同。只要栅电极层和栅介质层可以提供不同的有效功函数即可。另外，栅电极层不限于单层结构，也可以包括叠层结构。
根据本公开实施例的存储器件可以应用于各种电子设备。例如，存储器件可以存储电子设备操作所需的各种程序、应用和数据。电子设备还可以包括与存储器件相配合的处理器。例如，处理器可以通过允许存储器件中存储的程序来操作电子设备。这种电子设备例如智能电话、计算机、平板电脑(PC)、可穿戴智能设备、移动电源、机器人、智能芯片等。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (25)

  1. 一种存储器件，包括：
    衬底；
    设置在衬底上的电极结构，包括交替堆叠的多个第一电极层和多个第二电极层；
    穿透电极结构的多个竖直有源区；
    设置在竖直有源区与电极结构中的各第一电极层之间的第一栅介质层以及设置在竖直有源区与电极结构中的各第二电极层之间的第二栅介质层，其中，第一栅介质层和第二栅介质层分别构成数据存储结构，
    其中，第一电极层与第一栅介质层的组合的第一有效功函数不同于第二电极层与第二栅介质层的组合的第二有效功函数。
  2. 根据权利要求1所述的存储器件，其中，
    第一有效功函数接近竖直有源区中半导体材料的导带，而第二有效功函数接近竖直有源区中半导体材料的价带；或者
    第一有效功函数接近竖直有源区中半导体材料的价带，而第二有效功函数接近竖直有源区中半导体材料的导带。
  3. 根据权利要求1所述的存储器件，还包括所述第一电极层与所述第二电极层之间的绝缘层。
  4. 根据权利要求1所述的存储器件，其中，第一栅介质层和第二栅介质层分别包括第一介质层-电荷俘获层-第二介质层的叠层结构。
  5. 根据权利要求4所述的存储器件，其中，第一栅介质层和第二栅介质层由相同的第一介质层-电荷俘获层-第二介质层的叠层结构构成，第一介质层、电荷俘获层和第二介质层均沿竖直有源区的侧壁连续延伸。
  6. 根据权利要求4所述的存储器件，其中，叠层结构中的第一介质层靠近竖直有源区，第二介质层靠近电极结构，第一栅介质层的叠层结构中第一介质层和电荷俘获层分别与第二栅介质层的叠层结构中第一电介质层和电荷俘获层由相同的层构成，第一介质层和电荷俘获层均沿竖直有源区的侧壁连续延伸，而各栅介质层的叠层结构中的第二介质层分别沿着相应电极层的侧壁和上、 下表面延伸。
  7. 根据权利要求4所述的存储器件，其中，第一栅介质层沿着各第一电极层的侧壁和上、下表面延伸，第二栅介质层沿着各第二电极层的侧壁和上、下表面延伸。
  8. 根据权利要求1所述的存储器件，还包括：
    形成在衬底中与各竖直有源区的底端相接触的接触区。
  9. 根据权利要求8所述的存储器件，其中，竖直有源区中的半导体材料至少在底端被掺杂为与接触区相同的导电类型，被掺杂的部分在横向上与第一电极层和第二电极层中最下方的电极层相交迭。
  10. 根据权利要求1所述的存储器件，其中，竖直有源区中的半导体材料呈底端封闭的管状。
  11. 根据权利要求1所述的存储器件，其中，竖直有源区中与各第一电极层及其上、下方的相邻第二电极层相对应的部分分别构成同一器件的沟道区和源/漏区，竖直有源区中与各第二电极层及其上、下方的相邻第一电极层相对应的部分分别构成同一器件的沟道区和源/漏区。
  12. 根据权利要求1所述的存储器件，其中，第一栅介质层和第二栅介质层分别为包括铁电材料的介质层。
  13. 一种制造存储器件的方法，包括：
    在衬底上设置多个第一牺牲层和多个第二牺牲层交替堆叠的叠层；
    形成穿透所述叠层的多个竖直孔；
    在所述竖直孔的侧壁上形成与第一牺牲层相对应的第一栅介质层以及与第二牺牲层相对应的第二栅介质层；
    在竖直孔中填充半导体材料，以形成有源区；
    将第一牺牲层替换为第一电极层；以及
    将第二牺牲层替换为第二电极层，
    其中，第一电极层与第一栅介质层的组合的第一有效功函数不同于第二电极层与第二栅介质层的组合的第二有效功函数。
  14. 根据权利要求13所述的方法，其中，
    第一有效功函数接近有源区中半导体材料的导带，而第二有效功函数接近 有源区中半导体材料的价带；或者
    第一有效功函数接近有源区中半导体材料的价带，而第二有效功函数接近有源区中半导体材料的导带。
  15. 根据权利要求13所述的方法，其中，设置叠层还包括：
    在相邻的第一牺牲层与第二牺牲层之间设置电介质的刻蚀停止层。
  16. 根据权利要求13所述的方法，其中，形成第一栅介质层和第二栅介质层包括：
    形成第一介质层-电荷俘获层-第二介质层的叠层结构。
  17. 根据权利要求16所述的方法，其中，第一栅介质层和第二栅介质层由相同的第一介质层-电荷俘获层-第二介质层的叠层结构构成，形成第一栅介质层和第二栅介质层包括：
    在填充半导体材料之前，沿着竖直孔的侧壁形成连续延伸的所述叠层结构。
  18. 根据权利要求16所述的方法，其中，叠层结构中的第一介质层靠近有源区，第二介质层靠近电极结构，第一栅介质层的叠层结构中第一介质层和电荷俘获层分别与第二栅介质层的叠层结构中第一电介质层和电荷俘获层由相同的层构成，形成第一栅介质层和第二栅介质层包括：
    在填充半导体材料之前，沿着竖直孔的侧壁形成连续延伸的电荷俘获层和第一介质层；
    在替换第一牺牲层时，在竖直孔的侧壁上形成的电荷俘获层的侧壁上形成用于第一栅介质层的第二介质层；以及
    在替换第二牺牲层时，在竖直孔的侧壁上形成的电荷俘获层的侧壁上形成用于第二栅介质层的第二介质层。
  19. 根据权利要求16所述的方法，其中，形成第一栅介质层和第二栅介质层包括：
    在替换第一牺牲层时，在竖直孔中填充的半导体材料的侧壁上形成用于第一栅介质层的叠层结构；以及
    在替换第二牺牲层时，在竖直孔中填充的半导体材料的侧壁上形成用于第二栅介质层的叠层结构。
  20. 根据权利要求13所述的方法，其中，形成第一栅介质层和第二栅介 质层包括：
    形成包括铁电材料的介质层。
  21. 根据权利要求13所述的方法，还包括：在形成所述叠层之前，在衬底中形成阱区，以用作与各竖直有源区的底端相接触的接触区。
  22. 根据权利要求21所述的方法，还包括：
    至少将竖直有源区中的半导体材料的底端掺杂为与接触区相同的导电类型，被掺杂的部分在横向上与第一电极层和第二电极层中最下方的电极层相交迭。
  23. 根据权利要求13所述的方法，其中，竖直有源区中的半导体材料呈底端封闭的管状。
  24. 一种电子设备，包括如权利要求1至12中任一项所述的存储器件。
  25. 根据权利要求24所述的电子设备，该电子设备包括智能电话、计算机、平板电脑、可穿戴智能设备、移动电源、机器人、智能芯片。
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