WO2020087401A1 - 程序烧写设备、系统及方法 - Google Patents

程序烧写设备、系统及方法 Download PDF

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Publication number
WO2020087401A1
WO2020087401A1 PCT/CN2018/113188 CN2018113188W WO2020087401A1 WO 2020087401 A1 WO2020087401 A1 WO 2020087401A1 CN 2018113188 W CN2018113188 W CN 2018113188W WO 2020087401 A1 WO2020087401 A1 WO 2020087401A1
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Prior art keywords
programming
program
flash memory
programmed
address
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PCT/CN2018/113188
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English (en)
French (fr)
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刘鹏
刘松
杨顺
陈浩
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华北电力大学扬中智能电气研究中心
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Priority to PCT/CN2018/113188 priority Critical patent/WO2020087401A1/zh
Publication of WO2020087401A1 publication Critical patent/WO2020087401A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating

Definitions

  • This application relates to the field of communication technology, and in particular to a program programming device, system, and method.
  • each Flash chip needs to be programmed before it can be used.
  • the traditional programming method is to write the program into the Flash chip through an emulator or serial port tool. As shown in Figure 1, one end of the J-Link emulator is connected to the PC through the USB interface or serial port, and the other end of the J-Link emulator is connected to the Flash chip through the JTAG interface. The data to be downloaded on the PC (or " The program to be downloaded ”) is written into the Flash chip through the emulator.
  • the embodiments of the present application provide a program programming device, system and method, which solve the above problems of the prior art and improve the program programming efficiency.
  • a program programming device may include:
  • Memory for storing programs to be downloaded
  • the controller connected to the memory is used to receive the user's programming instructions, and start the pre-stored programming steps according to the programming instructions; according to the programming steps, read the program to be downloaded, and read the program to be downloaded and
  • the pre-stored combination information of each address code in the address codes of the at least two flash memories to be programmed is output to the FPGA chip to program the program to be downloaded to the at least two flash memories to be programmed through the FPGA chip;
  • the FPGA chip connected to the controller is used to receive the combined information of each address code and the program to be downloaded; according to the address code, a preset decoding operation is used to obtain the address of the flash memory to be written, and the The flash memory corresponding to the obtained address is programmed with the program to be downloaded, and the packaging format of the memory and the flash memory to be programmed is the same;
  • the flash memory base connected to the FPGA chip is used to carry the flash memory to be programmed, and the model of the memory base is the same as the model of the memory to be programmed.
  • the controller is also used to update the programming step according to user needs.
  • the controller is also used to obtain the programming status of the flash memory that has been programmed and output the address and corresponding programming status of the flash memory that has been programmed to the FPGA chip;
  • the FPGA chip is also used to receive the programming status of the flash memory that has been programmed and to display the programming status of at least two flash memories that have been programmed.
  • the programming status includes programming success and programming failure.
  • the FPGA chip may include: a decoder, an SPI expansion module, and a programming status indication module;
  • the decoder is used to receive the address code in the combined information, and use the preset decoding operation according to the address code to obtain the address of the flash memory to be programmed;
  • SPI extension module used to receive the address of the flash memory to be downloaded and the decoded flash memory in the combined information, and to be written to the address of the flash memory to be written after decoding Flash memory to write the program to be downloaded;
  • the programming status indication module is used to receive the address and corresponding programming status of the flash memory after programming and display the programming status corresponding to the flash memory after programming.
  • a program programming system may include: the program programming device of the first aspect, a communication interface, a memory for storing computer programs, and a communication bus, wherein the program programming device and the communication interface , System memory completes communication with each other through the communication bus.
  • a method for programming a program may include:
  • the method before receiving the programming request, the method further includes:
  • the method further includes:
  • the programming status includes programming success and programming failure.
  • a computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method steps described in any one of the above first aspects are implemented.
  • the program programming device includes: a memory for storing a program to be downloaded; a controller connected to the memory, for receiving a user's programming instruction, and starting a pre-stored programming step according to the programming instruction ; According to the programming steps, read the program to be downloaded, and output the combined information of the read program to be downloaded and each of the at least two address codes stored in advance to the FPGA chip to write to the chip to be programmed through the FPGA chip
  • the flash memory is programmed with the program to be downloaded; the FPGA chip connected to the controller is used to receive the combined information of each address code and the program to be downloaded; according to the address code, the preset decoding operation is used to obtain the fast programming to be written The address of the flash memory, and write the program to be downloaded to the flash memory corresponding to the decoded address.
  • the memory has the same packaging format as at least two flash memories to be written; they are the same as the memory, the controller, and the FPGA chip.
  • the connected power supply, the flash memory base connected to the FPGA chip, used to carry the flash memory to be programmed, the model of the memory base The same type of memory to be written.
  • the device expands at least two ports connected to the flash memory to be programmed by using FPGA, so as to realize programming of multiple flash memory chips, and improves the programming efficiency of the program.
  • FIG. 1 is a schematic structural diagram of a program programming system in the prior art
  • FIG. 2 is a schematic structural diagram of a program programming system provided by an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a program programming device according to an embodiment of the present invention.
  • FIG. 4A is a schematic structural diagram of an FPGA chip in FIG. 3;
  • FIG. 4B is a schematic structural diagram of another FPGA chip in FIG. 3;
  • FIG. 5 is a schematic flowchart of a program programming method provided by an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a program programming system provided by an embodiment of the present invention. As shown in FIG. 2, the system may include: a program programming device 200 and a flash memory group 210 to be programmed.
  • the program programming device 200 and the flash memory group 210 to be programmed are connected through a serial peripheral interface (Serial Peripheral Interface, SPI).
  • SPI Serial Peripheral Interface
  • the program programming device 200 is used to receive a user's programming instruction; according to the programming instruction, obtain the addresses of at least two flash memories to be programmed, and add the addresses to the flash memory group 210 corresponding to the addresses Flash memory to program stored programs to be downloaded, such as programs.
  • the flash memory group 210 to be programmed includes at least two flash memories to be programmed, that is, at least two empty Flash chips, such as flash memory 1 to flash memory N, where N is an integer not less than 2.
  • the program programming device 200 may also receive the programming status of the flash memory in the flash memory group 210 to be programmed.
  • the program programming device 200 may be connected to the terminal to receive the download data to be stored sent by the terminal, and the program programming device 200 uses the download data to be stored as the program to be downloaded;
  • the terminal may be a personal computer (personal computer) computer (PC), notebook computer, personal digital assistant (PDA), tablet computer (PAD) and other user equipment (User Equipment, UE).
  • PC personal computer
  • PDA personal digital assistant
  • PAD tablet computer
  • UE User Equipment
  • the program programming device in the above program programming system can be detached from the terminal and execute the program programming independently, or can be connected to the terminal to receive and store the program to be downloaded.
  • the program programming device can program the stored program to be downloaded into at least two flash memories.
  • the above program programming in the embodiment of the present invention The system realizes the simultaneous programming of multiple flash memories, which improves the efficiency of programming.
  • the program programming device 200 may include:
  • the memory 300 for storing the program to be downloaded.
  • the controller 310 connected to the memory 300 is used to receive a user's programming instruction and start a pre-stored programming procedure according to the programming instruction; according to the programming procedure, the program to be downloaded is read, and the The combined information of the download program and the pre-stored at least two address codes of each address code is output to a field programmable gate array (Field-Programmable Gate Array, FPGA) 320 to be burned into the flash memory to be written through the FPGA chip Write the program to be downloaded.
  • FPGA Field-Programmable Gate Array
  • the memory 300 is connected to the SPI1 port of the controller 310.
  • the programming process of the program to be downloaded is performed through the programming step stored in the controller 310, it can be based on the user's programming requirements or the packaging format of the flash memory to be programmed or to be programmed Factors such as the type of flash memory update the programming steps, such as adding, deleting, and / or modifying programming steps, and adjusting the hardware configuration of the controller 310 to make the programming method more in line with user needs, while improving programming Efficiency and operational flexibility.
  • the controller 310 can also receive the download data to be stored sent by the PC, and upload the download data to be stored to the memory 300, and the memory 300 uses the download data to be stored as the program to be downloaded.
  • controller 310 may also be used to obtain the programming status of at least two flash memories to be programmed in the flash memory group 210 that has been programmed and completed by the FPGA chip 320, and output at least two to the FPGA chip 320 The programming status of the flash memory to be programmed.
  • the programming status includes programming success and programming failure.
  • the FPGA chip 320 connected to the controller 310 is used to receive the combined information of the address code of each flash memory and the program to be downloaded; according to the address code, a preset decoding operation is used to obtain the flash memory group 210 to be programmed Address of at least two flash memories to be programmed, and program the program to be downloaded to the flash memory corresponding to the decoded address.
  • the FPGA chip 320 is connected to the SPI2 port of the controller 310.
  • the SPI2 port of the controller is connected to the FPGA chip 320, and the FPGA chip 320 decodes the address code output by the controller through a preset decoding operation to obtain an address corresponding to the flash memory, and then passes A chip selection signal is used to decide whether to program the flash memory corresponding to the address, thereby downloading multiple flash memories and improving download efficiency.
  • the FPGA chip 320 is further used to receive the programming status of at least two flash memories completed by the programming controller 310 and to display the programming status of at least two flash memories completed by programming In order to intuitively understand the flash memory programming status.
  • the FPGA chip 320 may include a decoder 321, an SPI expansion module 322, and a programming status indication module 323;
  • the decoder 321 is configured to receive the address code in the combined information, and use a preset decoding operation according to the address code to obtain the address of the flash memory to be programmed.
  • the address code can be a 5-bit binary code, such as 00001-01111 and 10000-10100, the preset decoding operation is adopted for 00001-01111 and 10000-10100 respectively to obtain the decoded 1-20 address number, so it can be Program 20 programs to be downloaded to 20 flash memories to be programmed.
  • the decoder 321 may be composed of two 74HC154 decoders, each 74HC154 including A pin, B pin, C pin, and D pin.
  • the decoder input is invalid, that is, when the G1N pin or G2N pin input is high, the decoder does not work.
  • the decoder on the left works normally, and the decoder on the right does not work.
  • the flash memory address ADDR1 is valid.
  • A4 input is 1, the decoder on the right works, and the one on the left does not work.
  • Output 0 channel is valid, the channel is the flash memory programming address ADDR16, so the flash memory programming address ADDR16 is valid at the same time.
  • the SPI extension module 322 is used to receive the program to be downloaded in the combined information and the address obtained after decoding, and write the program to be downloaded into the flash memory to be written corresponding to the address obtained after decoding; wherein, the SPI extension The module 322 also needs to receive a control signal sent by the controller to control whether the SPI expansion module writes the program to be downloaded into the flash memory to be written corresponding to the address obtained after decoding.
  • the programming status indication module 323 is used to receive the address and corresponding programming status of the flash memory that has been programmed and display the programming status corresponding to the flash memory that has been programmed.
  • a power supply 330 connected to the memory 300, the controller 310, and the FPGA chip 320, respectively.
  • the power supply 330 can reduce the output voltage of the external power supply to provide power to the memory 300, the controller 310, and the FPGA chip 320.
  • the power supply 300 can reduce the 12V DC voltage output by the external power supply to 3.3V DC voltage.
  • a memory base 340 connected to the FPGA chip 320 and each of the at least two flash memories to be programmed is used to carry the flash memory to be programmed;
  • the model of the memory base 340 is the same as the model of the flash memory to be programmed.
  • the address code is 10000
  • the memory to be programmed is an empty Flash chip
  • the memory is a Flash mother chip that stores a program to be downloaded.
  • the controller receives the programming command input by the user, starts the pre-stored programming step, reads the program to be downloaded from the flash master according to the programming step, and reads the read program to be downloaded and at least two pre-stored programs
  • the combined information of each address code in the address code is output to the FPGA chip; the FPGA chip encodes the address 10000 and uses the preset decoding operation to obtain the address of the empty Flash chip with the write address of 16.
  • the controller then writes the program to be downloaded to the empty Flash chip corresponding to the address through the FPGA chip.
  • the program programming device includes: a memory for storing a program to be downloaded; a controller connected to the memory, for receiving a user's programming instruction, and starting a pre-stored programming step according to the programming instruction ; According to the programming steps, read the program to be downloaded, and output the combined information of the read program to be downloaded and each of the at least two address codes stored in advance to the FPGA chip to write to the chip to be programmed through the FPGA chip
  • the flash memory is programmed with the program to be downloaded; the FPGA chip connected to the controller is used to receive the combined information of each address code and the program to be downloaded; according to the programming address code, the preset decoding operation is used to obtain the program to be written Address of the flash memory, and write the program to be downloaded to the flash memory corresponding to the decoded address.
  • the memory has the same packaging format as at least two flash memories to be written;
  • the power supply connected to the FPGA chip, the flash memory base connected to the FPGA chip, used to carry the flash memory to be written, and the memory base And model number to be written in the same memory.
  • the device expands at least two ports connected to the flash memory to be programmed by using FPGA, so as to realize programming of multiple flash memory chips, and improves the programming efficiency of the program.
  • an embodiment of the present invention also provides a program programming method. As shown in FIG. 5, the method may include:
  • Step 510 Receive a programming instruction
  • Step 520 Read the stored program to be downloaded according to the programming instruction and the pre-stored programming procedure
  • Step 530 Encode the addresses of at least two flash memories to be programmed, and use preset decoding operations to obtain addresses of at least two flash memories to be programmed.
  • Step 540 Program the program to be downloaded into the flash memory to be programmed corresponding to the address obtained after decoding.
  • the method before receiving the programming request, the method further includes:
  • the method further includes:
  • the programming status includes programming success and programming failure.
  • the above embodiment of the present invention receives the programming instruction; reads the stored program to be downloaded according to the programming instruction and the pre-stored programming procedure; adopts a preset for the address coding of the stored at least two flash memories to be programmed Decoding the operation to obtain the addresses of at least two flash memories to be programmed; programming the program to be downloaded to the flash memory to be programmed corresponding to the address obtained after the decoding. It can be seen that the above method uses FPGA technology to expand the SPI port, realizes the download of multiple flash memories to be written, and improves the download efficiency.
  • An embodiment of the present invention also provides an electronic device.
  • the electronic device 610 includes a communication interface 620, a memory 630, and a communication bus 640. Complete communication with each other.
  • the memory 630 is used to store a computer program, address codes of at least two flash memories to be programmed and programs to be downloaded, and the computer program includes a programming step;
  • preset decoding operations are used to obtain addresses of at least two flash memories to be programmed.
  • the programming step before receiving the programming request, the programming step is updated according to user requirements.
  • the address and corresponding programming status of the flash memory to which the programming is completed are obtained;
  • the programming status includes programming success and programming failure.
  • the communication bus mentioned above may be a peripheral component interconnection standard (Peripheral Component Interconnect, PCI) bus or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, etc.
  • PCI peripheral component interconnection standard
  • EISA Extended Industry Standard Architecture
  • the communication bus can be divided into an address bus, a data bus, and a control bus. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.
  • the communication interface is used for communication between the above electronic device and other devices.
  • the memory may include random access memory (Random Access Memory, RAM), or non-volatile memory (Non-Volatile Memory, NVM), for example, at least one disk memory.
  • RAM Random Access Memory
  • NVM Non-Volatile Memory
  • the memory may also be at least one storage device located away from the foregoing processor.
  • the foregoing processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (Network), NP, etc .; or a digital signal processor (DSP).
  • CPU central processing unit
  • Network network processor
  • NP network processor
  • DSP digital signal processor
  • a computer-readable storage medium stores instructions, which when executed on a computer, causes the computer to execute any of the above embodiments The program burning method.
  • a computer program product containing instructions is also provided, which, when it runs on a computer, causes the computer to execute the program burning method described in any of the above embodiments.
  • the embodiments in the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the embodiments of the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present application may take the form of computer program products implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code .
  • computer usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions can be provided to the processor of a general-purpose computer, special-purpose computer, embedded processing machine, or other programmable data processing device to produce a machine that enables the generation of instructions executed by the processor of the computer or other programmable data processing device
  • These computer program instructions may also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, the instructions The device implements the functions specified in one block or multiple blocks of the flowchart one flow or multiple flows and / or block diagrams.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operating steps are performed on the computer or other programmable device to produce computer-implemented processing, which is executed on the computer or other programmable device
  • the instructions provide steps for implementing the functions specified in one block or multiple blocks of the flowchart one flow or multiple flows and / or block diagrams.

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Abstract

一种程序烧写设备、系统及方法，所述烧写设备包括用于存储待下载程序的存储器；与所述存储器连接的控制器，用于接收用户的烧写指令，并根据烧写指令，启动预先存储的烧写步骤，根据烧写步骤，读取待下载程序，并将读取的待下载程序和预先存储的至少两个待烧写的快闪存储器的地址编码中每个地址编码的组合信息输出至FPGA芯片；与控制器连接的FPGA芯片，用于根据地址编码，采用预设译码运算，得到待烧写的快闪存储器的地址，并向译码后得到的地址对应的快闪存储器烧写待下载程序；与FPGA芯片相连的快闪存储器底座，以及为上述各器件供电的供电电源。该设备实现了对多个快闪存储器的程序烧写，提高了程序烧写效率。

Description

程序烧写设备、系统及方法 技术领域
本申请涉及通信技术领域，尤其涉及一种程序烧写设备、系统及方法。
背景技术
由于生产线上生产出的Flash芯片内没有应用程序，每个Flash芯片都需要烧录程序后才能使用。传统的程序烧写方法是通过仿真器或串口工具将程序烧写入Flash芯片。如图1所示，J-Link仿真器的一端通过USB接口或串口与PC端相连，J-Link仿真器的另一端通过JTAG接口与Flash芯片相连，PC端上的待下载数据(或称“待下载程序”)通过仿真器烧写入到Flash芯片中。
然而，发明人发现上述程序烧写方法每次只能实现一个Flash芯片的程序烧写，故当需要烧写程序的Flash芯片数量较多时，烧写效率会明显降低，难以满足实际的需要。
发明内容
本申请实施例提供一种程序烧写设备、系统及方法，解决了现有技术的上述问题，提高了程序的烧写效率。
第一方面，提供了一种程序烧写设备，该设备可以包括：
用于存储待下载程序的存储器；
与存储器连接的控制器，用于接收用户的烧写指令，并根据烧写指令，启动预先存储的烧写步骤；根据烧写步骤，读取待下载程序，并将读取的待下载程序和预先存储的至少两个待烧写的快闪存储器的地址编码中每个地址编码的组合信息输出至FPGA芯片，以通过FPGA芯片向至少两个待烧写的快闪存储器烧写待下载程序；
与控制器连接的FPGA芯片，用于接收每个地址编码和待下载程序的组合信息；根据地址编码，采用预设译码运算，得到待烧写的快闪存储器的地 址，并向译码后得到的地址对应的快闪存储器烧写待下载程序，存储器与待烧写的快闪存储器的封装格式相同；
分别与存储器、控制器和FPGA芯片连接的供电电源；
与FPGA芯片相连的快闪存储器底座，用于承载待烧写的快闪存储器，存储器底座的型号与待烧写存储器的型号相同。
在一个可选的实现中，控制器，还用于根据用户需求，更新所述烧写步骤。
在一个可选的实现中，控制器，还用于获取烧写完成的快闪存储器的烧写状态，并向FPGA芯片输出烧写完成的快闪存储器的地址和相应烧写状态；
FPGA芯片，还用于接收烧写完成的快闪存储器的烧写状态，以及展示至少两个烧写完成的快闪存储器的烧写状态，烧写状态包括烧写成功和烧写失败。
在一个可选的实现中，FPGA芯片，可以包括：译码器、SPI扩展模块和烧写状态指示模块；
译码器，用于接收组合信息中的地址编码，并根据地址编码，采用预设译码运算，得到待烧写的快闪存储器的地址；
SPI扩展模块，用于接收组合信息中的待下载程序和译码后的待烧写的快闪存储器的地址，以及向译码后得到的待烧写的快闪存储器的地址对应的待烧写的快闪存储器烧写待下载程序；
烧写状态指示模块，用于接收烧写完成的快闪存储器的地址和相应烧写状态，以及展示烧写完成的快闪存储器对应的烧写状态。
第二方面，提供了一种程序烧写系统，该系统可以包括：第一方面的程序烧写设备、通信接口、用于存放计算机程序的存储器和通信总线，其中，程序烧写设备，通信接口，系统存储器通过通信总线完成相互间的通信。
第三方面，提供了一种程序烧写方法，该方法可以包括：
接收烧写指令；
根据烧写指令和预先存储的烧写步骤，读取存储的待下载程序；
对至少两个待烧写的快闪存储器的地址编码，采用预设译码运算，得到至少两个待烧写的快闪存储器的地址；
向译码后得到的地址对应的待烧写的快闪存储器烧写待下载程序。
在一个可选的实现中，接收烧写请求之前，该方法还包括：
根据用户需求，更新所述烧写步骤。
在一个可选的实现中，向译码后得到的地址对应的待烧写的快闪存储器烧写待下载程序之后，该方法还包括：
获取烧写完成的快闪存储器的地址和相应烧写状态；
展示烧写完成的快闪存储器对应的烧写状态，烧写状态包括烧写成功和烧写失败。
第四方面，提供了一种计算机可读存储介质，该计算机可读存储介质内存储有计算机程序，所述计算机程序被处理器执行时实现上述第一方面中任一所述的方法步骤。
本发明实施例提供的程序烧写设备包括：用于存储待下载程序的存储器；与存储器连接的控制器，用于接收用户的烧写指令，并根据烧写指令，启动预先存储的烧写步骤；根据烧写步骤，读取待下载程序，并将读取的待下载程序和预先存储的至少两个地址编码中每个地址编码的组合信息输出至FPGA芯片，以通过FPGA芯片向待烧写的快闪存储器烧写待下载程序；与控制器连接的FPGA芯片，用于接收每个地址编码和待下载程序的组合信息；根据地址编码，采用预设译码运算，得到待烧写的快闪存储器的地址，并向译码后得到的地址对应的快闪存储器烧写待下载程序，存储器与至少两个待烧写的快闪存储器的封装格式相同；分别与存储器、控制器和FPGA芯片连接的供电电源，与FPGA芯片相连的快闪存储器底座，用于承载待烧写的快闪存储器，存储器底座的型号与待烧写存储器的型号相同。该设备通过采用FPGA扩展出至少两个与待烧写的快闪存储器连接的端口，实现对多个快闪存储器片烧写，提高了程序烧写效率。
附图说明
图1为现有技术的一种程序烧写系统的结构示意图；
图2为本发明实施例提供的一种程序烧写系统的结构示意图；
图3为本发明实施例提供的一种程序烧写设备的结构示意图；
图4A为图3中的一种FPGA芯片的结构示意图；
图4B为图3中的另一种FPGA芯片的结构示意图；
图5为本发明实施例提供的一种程序烧写方法的流程示意图；
图6为本发明实施例提供的一种电子设备的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请一部分实施例，并不是全部的实施例。基于本申请实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
图2为本发明实施例提供的一种程序烧写系统的结构示意图。如图2所示，该系统可以包括：程序烧写设备200和待烧写的快闪存储器组210。
程序烧写设备200与待烧写的快闪存储器组210通过串行外设接口(Serial Peripheral Interface，SPI)连接。
程序烧写设备200，用于接收用户的烧写指令；根据烧写指令，获取至少两个待烧写的快闪存储器的地址，并向该地址对应的待烧写的快闪存储器组210中的快闪存储器烧写存储的待下载程序，如程序。
待烧写的快闪存储器组210包括至少两个待烧写的快闪存储器，即至少两个空Flash芯片，如快闪存储器1至快闪存储器N，N为不小于2的整数。
可选地，程序烧写设备200还可以接收待烧写的快闪存储器组210中快闪存储器的烧写状态。
可选地，程序烧写设备200可以与终端连接，以接收终端发送的待存储的下载数据，程序烧写设备200将待存储的下载数据作为待下载程序；其中， 终端可以是个人计算机(personal computer，PC)、笔记本电脑、个人数字助理(PDA)、平板电脑(PAD)等用户设备(User Equipment，UE)。
可见，上述程序烧写系统中的程序烧写设备可以脱离终端，单独执行程序烧写，也可以与终端连接，以接收并存储待下载程序。同时程序烧写设备可以将存储的待下载程序烧写入至少两个快闪存储器，与现有技术一次只能完成对一个快闪存储器的烧写相比，本发明实施例的上述程序烧写系统实现了对多个快闪存储器的同时烧写，提高了烧写效率。
其中，如图3所示，程序烧写设备200可以包括：
用于存储待下载程序的存储器300。
其中，为了实现存储器300与至少两个待烧写的快闪存储器的兼容性，需要保证存储器300与至少两个待烧写的快闪存储器的封装格式相同。
与存储器300连接的控制器310，用于接收用户的烧写指令，并根据烧写指令，启动预先存储的烧写步骤；根据该烧写步骤，读取待下载程序，并将读取的待下载程序和预先存储的至少两个地址编码中每个地址编码的组合信息输出至现场可编程门阵列(Field-Programmable Gate Array，FPGA)320，以通过FPGA芯片向待烧写的快闪存储器烧写待下载程序。
存储器300与控制器310的SPI1口连接。
可选地，由于待下载程序的烧写过程是通过控制器310中存储的烧写步骤进行的，故可以根据用户的烧写需求或待烧写的快闪存储器的封装格式或待烧写的快闪存储器的类型等因素更新所述烧写步骤，如增加、删减和/或修改烧写步骤，以及调整控制器310的硬件配置，使烧写方式更加符合用户需求，同时提高了烧录效率和操作的灵活性。
可选地，控制器310还可以接收PC端发送的待存储的下载数据，并将该待存储的下载数据上传至存储器300，存储器300将待存储的下载数据作为待下载程序。
进一步的，控制器310，还可以用于通过FPGA芯片320获取烧写完成的快闪存储器组210中至少两个待烧写的快闪存储器的烧写状态，并向FPGA 芯片320输出至少两个待烧写的快闪存储器的烧写状态，烧写状态包括烧写成功和烧写失败。
与控制器310连接的FPGA芯片320，用于接收每个快闪存储器的地址编码和待下载程序的组合信息；根据地址编码，采用预设译码运算，得到待烧写的快闪存储器组210中至少两个待烧写的快闪存储器的地址，并向译码后得到的地址对应的快闪存储器烧写待下载程序。
FPGA芯片320与控制器310的SPI2口连接。本发明上述实施例中控制器的SPI2口与FPGA芯片320相连，且FPGA芯片320通过预设译码运算将控制器输出的地址编码进行译码，得到与快闪存储器相对应的地址，然后通过片选信号来决定是否向该地址对应的快闪存储器烧写程序，从而实现了对多个快闪存储器的下载，提高了下载效率。
可选地，FPGA芯片320，还用于接收烧写控制器310输出的至少两个烧写完成的快闪存储器的烧写状态，以及展示至少两个烧写完成的快闪存储器的烧写状态，从而直观的了解快闪存储器的烧写状态。
如图4A所示，FPGA芯片320可以包括译码器321、SPI扩展模块322、烧写状态指示模块323；
译码器321，用于接收组合信息中的地址编码，并根据地址编码，采用预设译码运算，得到待烧写的快闪存储器的地址。
该地址编码可以是5位的二进制编码，如00001-01111和10000-10100，将00001-01111和10000-10100分别采用预设译码运算，得到译码后的1-20的地址编号，故可以向20个待烧写的快闪存储器烧写待下载程序。
在一种可实现的方式中，如图4B所示，译码器321可以由两个74HC154译码器组成，每个74HC154包括A引脚、B引脚、C引脚和D引脚共4个二进制编码输入、G1N引脚和G2N引脚共两个使能引脚，以及第一片译码器中1-15的输出引脚和第二片译码器中0-4的输出引脚。
当G1N引脚或G2N引脚为高电平时，译码器输入无效，即G1N引脚或G2N引脚输入为高电平时，译码器不工作。当A4引脚输入为0时，左边的 译码器正常工作，右边的译码器不工作。
例如，当输入A4A3A2A1A0＝00001时，快闪存储器的烧写地址ADDR1有效，当A4输入为1时，右边的译码器工作，左边的不工作，所以当输入A4A3A2A1A0＝10000时，译码器的输出0通道有效，该通道为快闪存储器的烧写地址ADDR16，所以此时快闪存储器的烧写地址ADDR16有效，同理，当A4A3A2A1A0＝10001时，快闪存储器的烧写地址ADDR17有效。SPI扩展模块322，用于接收组合信息中的待下载程序和译码后得到的地址，以及向译码后得到的地址对应的待烧写的快闪存储器烧写待下载程序；其中，SPI扩展模块322还需要接收控制器发送的控制信号，以控制SPI扩展模块是否向译码后得到的地址对应的待烧写的快闪存储器烧写待下载程序。
烧写状态指示模块323，用于接收烧写完成的快闪存储器的地址和相应烧写状态，以及展示烧写完成的快闪存储器对应的烧写状态。
分别与存储器300、控制器310和FPGA芯片320连接的供电电源330。
其中，供电电源330可以将外接电源的输出电压降低，来为存储器300、控制器310和FPGA芯片320提供电能，如供电电源300可以将外接电源输出的12V直流电压降低至3.3V直流电压。
与FPGA芯片320和至少两个待烧写的快闪存储器中每个待烧写的快闪存储器相连的存储器底座340，用于承载待烧写的快闪存储器；
该存储器底座340的型号与待烧写的快闪存储器的型号相同。
当需要烧写不同型号的快闪存储器时，只需要根据快闪存储器的型号，对存储器底座进行更新即可，不需要重新设计整个快闪存储器的下载电路，进一步提高了烧写效率和操作的灵活性。
在一个例子中，地址编码为10000，待烧写存储器为空Flash芯片，存储器为存储待下载程序的Flash母片。
控制器接收用户输入的烧写指令，启动预先存储的烧写步骤，根据该烧写步骤，从Flash母片中读取待下载程序，并将读取的待下载程序和预先存储的至少两个地址编码中每个地址编码的组合信息输出至FPGA芯片；FPGA芯 片将地址编码10000，采用预设译码运算，得到烧写地址为16的空Flash芯片的地址。之后控制器通过FPGA芯片向该地址对应的空Flash芯片烧写待下载程序。
本发明实施例提供的程序烧写设备包括：用于存储待下载程序的存储器；与存储器连接的控制器，用于接收用户的烧写指令，并根据烧写指令，启动预先存储的烧写步骤；根据烧写步骤，读取待下载程序，并将读取的待下载程序和预先存储的至少两个地址编码中每个地址编码的组合信息输出至FPGA芯片，以通过FPGA芯片向待烧写的快闪存储器烧写待下载程序；与控制器连接的FPGA芯片，用于接收每个地址编码和待下载程序的组合信息；根据烧写地址编码，采用预设译码运算，得到待烧写的快闪存储器的地址，并向译码后得到的地址对应的快闪存储器烧写待下载程序，存储器与至少两个待烧写的快闪存储器的封装格式相同；分别与存储器、控制器和FPGA芯片连接的供电电源，与FPGA芯片相连的快闪存储器底座，用于承载待烧写的快闪存储器，存储器底座的型号与待烧写存储器的型号相同。该设备通过采用FPGA扩展出至少两个与待烧写的快闪存储器连接的端口，实现对多个快闪存储器片烧写，提高了程序烧写效率。
与上述设备对应的，本发明实施例还提供一种程序烧写方法，如图5所示，该方法可以包括：
步骤510、接收烧写指令；
步骤520、根据烧写指令和预先存储的烧写步骤，读取存储的待下载程序；
步骤530、对至少两个待烧写的快闪存储器的地址编码，采用预设译码运算，得到至少两个待烧写的快闪存储器的地址。
步骤540、向译码后得到的地址对应的待烧写的快闪存储器烧写待下载程序。
可选地，接收烧写请求之前，该方法还包括：
根据用户需求，更新烧写步骤。
可选地，向译码后得到的地址对应的待烧写的快闪存储器烧写待下载程序之后，该方法还包括：
获取烧写完成的快闪存储器的地址和相应烧写状态；
展示烧写完成的快闪存储器的烧写状态，该烧写状态包括烧写成功和烧写失败。
本发明上述实施例接收烧写指令；根据烧写指令和预先存储的烧写步骤，读取存储的待下载程序；对存储的至少两个待烧写的快闪存储器的地址编码，采用预设译码运算，得到至少两个待烧写的快闪存储器的地址；向译码后得到的地址对应的待烧写的快闪存储器烧写待下载程序。可见，上述方法采用FPGA技术，对SPI端口进行了扩展，实现了对多个待烧写的快闪存储器的下载，提高了下载效率。
本发明实施例还提供了一种电子设备，如图6所示，包括电子设备610、通信接口620、存储器630和通信总线640，其中，处理器610，通信接口620，存储器630通过通信总线640完成相互间的通信。
存储器630，用于存放计算机程序、至少两个待烧写的快闪存储器的地址编码和待下载程序，所述计算机程序包括烧写步骤；
处理器610，用于执行存储器630上所存放的程序时，实现如下步骤：
接收烧写指令；
根据烧写指令和预先存储的烧写步骤，读取存储的待下载程序；
对至少两个待烧写的快闪存储器的地址编码，采用预设译码运算，得到至少两个待烧写的快闪存储器的地址。
向译码后得到的地址对应的待烧写的快闪存储器烧写所述待下载程序。
在一个可选的实现中，接收烧写请求之前，根据用户需求，更新烧写步骤。
在一个可选的实现中，向译码后得到的地址对应的待烧写的快闪存储器烧写待下载程序之后，获取烧写完成的快闪存储器的地址和相应烧写状态；
展示烧写完成的快闪存储器的烧写状态，该烧写状态包括烧写成功和烧写失败。
上述提到的通信总线可以是外设部件互连标准(Peripheral Component Interconnect，PCI)总线或扩展工业标准结构(Extended Industry Standard Architecture，EISA)总线等。该通信总线可以分为地址总线、数据总线、控制总线等。为便于表示，图中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
通信接口用于上述电子设备与其他设备之间的通信。
存储器可以包括随机存取存储器(Random Access Memory，RAM)，也可以包括非易失性存储器(Non-Volatile Memory，NVM)，例如至少一个磁盘存储器。可选的，存储器还可以是至少一个位于远离前述处理器的存储装置。
上述的处理器可以是通用处理器，包括中央处理器(Central Processing Unit，CPU)、网络处理器(Network Processor，NP)等；还可以是数字信号处理器(Digital Signal Processing，DSP)。
由于上述实施例中电子设备的各器件解决问题的实施方式以及有益效果可以参见图5所示的实施例中的各步骤来实现，因此，本发明实施例提供的电子设备的具体工作过程和有益效果，在此不复赘述。
在本发明提供的又一实施例中，还提供了一种计算机可读存储介质，该计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述实施例中任一所述的程序烧写方法。
在本发明提供的又一实施例中，还提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述实施例中任一所述的程序烧写方法。
本领域内的技术人员应明白，本申请实施例中的实施例可提供为方法、系统、或计算机程序产品。因此，本申请实施例中可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请实施例中可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存 储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请实施例中是参照根据本申请实施例中实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本申请实施例中的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请实施例中范围的所有变更和修改。
显然，本领域的技术人员可以对本申请实施例中实施例进行各种改动和变型而不脱离本申请实施例中实施例的精神和范围。这样，倘若本申请实施例中实施例的这些修改和变型属于本申请实施例中权利要求及其等同技术的范围之内，则本申请实施例中也意图包含这些改动和变型在内。

Claims (9)

  1. 一种程序烧写设备，其特征在于，所述设备包括：
    用于存储待下载程序的存储器；
    与所述存储器连接的控制器，用于接收用户烧写指令，并根据所述烧写指令，启动预先存储的烧写步骤；根据所述烧写步骤，读取所述待下载程序，并将读取的所述待下载程序和预先存储的至少两个待烧写的快闪存储器的地址编码中每个待烧写的快闪存储器的地址编码的组合信息输出至现场可编程门阵列FPGA芯片，以通过所述FPGA芯片向所述至少两个待烧写的快闪存储器烧写待下载程序；
    与所述控制器连接的FPGA芯片，用于接收所述每个地址编码和所述待下载程序的组合信息；根据所述地址编码，采用预设译码运算，得到所述待烧写的快闪存储器的地址，并向译码后得到的地址对应的快闪存储器烧写所述待下载程序，所述存储器与待烧写的快闪存储器的封装格式相同；
    分别与所述存储器、所述控制器和所述FPGA芯片连接的供电电源；
    与所述FPGA芯片相连的快闪存储器底座，用于承载待烧写的快闪存储器，所述存储器底座的型号与所述待烧写存储器的型号相同。
  2. 如权利要求1所述的设备，其特征在于，所述控制器，还用于根据用户需求，更新所述烧写步骤。
  3. 如权利要求1所述的设备，其特征在于，
    所述控制器，还用于获取烧写完成的快闪存储器的地址和相应烧写状态，并向所述FPGA芯片输出所述烧写完成的快闪存储器的地址和相应烧写状态；
    所述FPGA芯片，还用于接收所述烧写完成的快闪存储器的地址和相应烧写状态，以及展示所述烧写完成的快闪存储器的对应的烧写状态，所述烧写状态包括烧写成功和烧写失败。
  4. 如权利要求3所述的设备，其特征在于，所述FPGA芯片，包括：译码器、串行外设接口SPI扩展模块和烧写状态指示模块；
    所述译码器，用于接收所述组合信息中的每个地址编码，并根据所述地址编码，采用预设译码运算，得到待烧写的快闪存储器的地址；
    所述SPI扩展模块，用于接收所述组合信息中的待下载程序和所述译码得到的待烧写的快闪存储器的地址，以及向所述译码得到的待烧写的快闪存储器的地址对应的待烧写的快闪存储器烧写所述待下载程序；
    所述烧写状态指示模块，用于接收烧写完成的快闪存储器的地址和相应烧写状态，以及展示所述烧写完成的快闪存储器对应的烧写状态。
  5. 一种程序烧写系统，其特征在于，所述系统包括：权利要求1-4所述的程序烧写设备、通信接口、用于存放计算机程序的存储器和通信总线，其中，程序烧写设备，通信接口，系统存储器通过通信总线完成相互间的通信。
  6. 一种程序烧写方法，其特征在于，所述方法包括：
    接收烧写指令；
    根据所述烧写指令和预先存储的烧写步骤，读取存储的待下载程序；
    对所述至少两个待烧写的快闪存储器的地址编码，采用预设译码运算，得到至少两个待烧写的快闪存储器的地址；
    向译码后得到的地址对应的待烧写的快闪存储器烧写所述待下载程序。
  7. 如权利要求6所述的方法，其特征在于，接收烧写请求之前，所述方法还包括：
    根据用户需求，更新所述烧写步骤。
  8. 如权利要求6所述的方法，其特征在于，向译码后得到的地址对应的待烧写的快闪存储器烧写待下载程序之后，所述方法还包括：
    获取烧写完成的快闪存储器的地址和相应烧写状态；
    展示烧写完成的快闪存储器对应的烧写状态，所述烧写状态包括烧写成功和烧写失败。
  9. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质内存储有计算机程序，所述计算机程序被处理器执行时实现权利要求5-9任一所述的方法步骤。
PCT/CN2018/113188 2018-10-31 2018-10-31 程序烧写设备、系统及方法 WO2020087401A1 (zh)

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CN102736938A (zh) * 2012-06-18 2012-10-17 中国电子科技集团公司第十研究所 Fpga配置程序的烧写方法
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US20180203681A1 (en) * 2017-01-17 2018-07-19 Oracle International Corporation Private computer network installations
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CN102736938A (zh) * 2012-06-18 2012-10-17 中国电子科技集团公司第十研究所 Fpga配置程序的烧写方法
CN104200843A (zh) * 2014-09-13 2014-12-10 无锡中星微电子有限公司 闪存烧入器、烧入系统及烧入方法
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