WO2024087607A1 - 闪存管理算法调试方法、系统、设备和可读存储介质 - Google Patents

闪存管理算法调试方法、系统、设备和可读存储介质 Download PDF

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Publication number
WO2024087607A1
WO2024087607A1 PCT/CN2023/096119 CN2023096119W WO2024087607A1 WO 2024087607 A1 WO2024087607 A1 WO 2024087607A1 CN 2023096119 W CN2023096119 W CN 2023096119W WO 2024087607 A1 WO2024087607 A1 WO 2024087607A1
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Prior art keywords
flash memory
memory management
control unit
management algorithm
test stimulus
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PCT/CN2023/096119
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English (en)
French (fr)
Inventor
林寅
吴大畏
李晓强
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深圳市硅格半导体有限公司
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Publication of WO2024087607A1 publication Critical patent/WO2024087607A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements

Definitions

  • the present application relates to the field of fast storage technology, and in particular to a flash memory management algorithm debugging method, a flash memory management algorithm debugging system, a flash memory management algorithm debugging device, and a computer-readable storage medium.
  • SSD Solid State Drive
  • NAND Flash storage media.
  • the storage method of NAND Flash depends on its physical properties. Existing file systems cannot directly access or operate SSDs. In order for the file system to access SSDs like accessing mechanical hard drives, it is necessary to add a software layer FTL (Flash Translation Layer) between NAND Flash and the file system.
  • FTL Flash Translation Layer
  • FTL runs in the microcontroller unit of the solid-state drive, and the processor frequency of the microcontroller unit is relatively low, so it takes a lot of time to debug FTL.
  • the embodiments of the present application solve the technical problem of high time cost for debugging the main control and FTL of the solid-state hard disk in the related technology by providing a flash memory management algorithm debugging method, a flash memory management algorithm debugging system, a flash memory management algorithm debugging device and a computer-readable storage medium, and achieve the technical effect of quickly completing the debugging of the main control and FTL of the solid-state hard disk.
  • the present invention provides a flash memory management algorithm debugging method, the flash memory management algorithm debugging method comprising:
  • the processing result of the virtual micro control unit on the test stimulus is obtained, and the processing result is sent to the storage module to control the storage module to complete the storage action.
  • generating the test stimulus based on a preset stimulus generation method includes:
  • the virtual host Upon receiving the test instruction, the virtual host determines the business process corresponding to the test instruction;
  • the starting up the virtual micro control unit and sending the test stimulus to the virtual micro control unit, wherein after starting up the virtual micro control unit, the virtual micro control unit runs the flash memory management algorithm to be debugged so that the virtual micro control unit can process the test stimulus includes:
  • the virtual micro control unit After receiving the test stimulus, the virtual micro control unit determines a processor associated with the virtual micro control unit and sends the test stimulus to the processor;
  • the processor After receiving the test stimulus, the processor runs the flash memory management algorithm to process the test stimulus.
  • the flash memory management algorithm is run, and processing the test stimulus includes:
  • the processor After the processor receives the test stimulus, determining a logical address corresponding to the test stimulus;
  • the logical address is associated with the physical address of the storage module and stored in a logical mapping table.
  • the method before associating the logical address with the physical address of the storage module and storing it in the logical mapping table based on a preset mapping relationship, the method further includes:
  • the physical address of the flash memory block to be executed is determined.
  • the obtaining of the processing result of the virtual micro control unit on the test stimulus and sending the processing result to the storage module to control the storage module to complete the storage action includes:
  • the storage module After receiving the processing result, the storage module determines the data to be stored corresponding to the processing result;
  • the method of starting the virtual micro control unit and sending the test stimulus to the virtual micro control unit, wherein the virtual micro control unit runs the flash memory management algorithm to be debugged after starting so that the virtual micro control unit can process the test stimulus further comprises:
  • the storage module After the storage module receives the processing result, determining the physical address of the to-be-read data corresponding to the processing result;
  • the physical address is read based on the logical mapping table included in the processing result.
  • the present application also proposes a flash memory management algorithm debugging system
  • the flash memory management algorithm debugging system includes a virtual host, after receiving a test instruction, the virtual host generates a test stimulus corresponding to the test instruction, and sends the test stimulus to a virtual micro control unit;
  • a virtual micro control unit which, after receiving the test stimulus, sends the test stimulus to the processor, so that the processor is called to run a flash memory management algorithm to process the test stimulus;
  • a storage module which, after receiving the processing result sent by the virtual micro control unit, executes a storage action corresponding to the processing result
  • a processor after receiving the test stimulus sent by the virtual micro control unit, runs a flash memory management algorithm to process the test stimulus.
  • the present application also proposes a flash memory management algorithm debugging device, which includes a memory, a processor, and a flash memory management algorithm debugging program stored in the memory and executable on the processor, and the processor implements the steps of the flash memory management algorithm debugging method as described above when executing the flash memory management algorithm debugging program.
  • the present application also proposes a computer-readable storage medium, on which a flash memory management algorithm debugging program is stored.
  • a flash memory management algorithm debugging program is executed by a processor, the steps of the flash memory management algorithm debugging method described above are implemented.
  • a test stimulus is generated based on a preset stimulus generation method; a virtual micro control unit is started, and the test stimulus is sent to the virtual micro control unit, wherein, after the virtual micro control unit is started, the flash memory management algorithm to be debugged is run, so that the virtual micro control unit can process the test stimulus; the processing result of the virtual micro control unit on the test stimulus is obtained, and the processing result is sent to the storage module to control the storage module to complete the storage action. Therefore, the technical problem of high time cost for debugging the main control and FTL of the solid-state hard disk in the related technology is effectively solved, thereby realizing the rapid completion of the debugging of the main control and FTL of the solid-state hard disk.
  • the test stimulus is sent to the processor associated with the virtual micro control unit, and the computing power of the processor is called to run the flash memory management algorithm so that the test stimulus is processed by the processor. Therefore, the technical problem of high time cost for debugging the main control and FTL of the solid-state hard disk in the related technology is effectively solved, thereby realizing the rapid completion of the debugging of the main control and FTL of the solid-state hard disk.
  • the logic address corresponding to the test stimulus is determined, and based on a preset mapping relationship, the logic address is associated with the physical address of the flash memory particle in the storage module and stored in the logic mapping table; at the same time, based on a preset wear leveling function, the flash memory block to be executed in the storage module is determined, and the physical address of the flash memory block to be executed is used as the physical address associated with the logical address. Therefore, the technical problem of high time cost for debugging the main control and FTL of the solid-state hard disk in the related technology is effectively solved, thereby realizing the rapid completion of the debugging of the main control and FTL of the solid-state hard disk.
  • the storage module After the storage module receives the processing result of the test stimulus, the data to be stored corresponding to the processing result is determined, the logical address of the data to be stored is determined, and the logical address is stored in the physical address associated with the logical address; the physical address of the data to be read corresponding to the processing result is determined, and the logical address associated with the physical address is read. Therefore, the technical problem of high time cost for debugging the main control and FTL of the solid-state hard disk in the related technology is effectively solved, thereby realizing the rapid completion of the debugging of the main control and FTL of the solid-state hard disk.
  • FIG1 is a flow chart of a first embodiment of a flash memory management algorithm debugging method of the present application
  • FIG2 is a schematic diagram of a detailed flow chart of step S20 of the first embodiment of the flash memory management algorithm debugging method of the present application;
  • FIG3 is a flow chart of a second embodiment of the flash memory management algorithm debugging method of the present application.
  • FIG4 is a flow chart of a third embodiment of the flash memory management algorithm debugging method of the present application.
  • FIG5 is a schematic diagram of the hardware structure involved in the flash memory management algorithm debugging device embodiment of the present application.
  • the solid-state drive manufacturer needs to develop a new master control and flash memory management algorithm for the new flash memory particles; however, the solid-state drive manufacturer cannot get the new flash memory particles in the first place, and the processing frequency of the solid-state drive master control is low, resulting in the time cost of the solid-state drive master control development process and the flash memory management algorithm debugging process being too high.
  • the main technical solution adopted in the embodiment of the present application is: when the virtual host receives the test instruction, it generates a test stimulus based on a preset method; sends the test stimulus to the virtual micro-control unit to control the virtual micro-control unit to call the computing power of the processor and run the flash memory management algorithm; sends the processing result of the test stimulus to the storage module to control the storage module to complete the corresponding storage action.
  • the solid-state drive master control and FTL debugging are quickly completed.
  • Embodiment 1 of the present application discloses a flash memory management algorithm debugging method.
  • the flash memory management algorithm debugging method includes:
  • Step S10 upon receiving a test instruction, generating a test stimulus based on a preset stimulus generation method
  • the test instruction can be regarded as an instruction to start the test, and the test instruction can also include data to be read or written, and can also include the terminal model to be simulated by the test stimulus.
  • the virtual host receives the test instruction, it generates the corresponding test stimulus based on the preset stimulus generation method.
  • step S10 includes:
  • Step S11 upon receiving the test instruction, the virtual host determines the business process corresponding to the test instruction;
  • Step S12 running the virtual driver corresponding to the test instruction, and generating the test stimulus according to the business process.
  • the virtual host when it receives a test instruction, it determines the business process corresponding to the test instruction and the terminal model to be simulated; calls the corresponding script in a pre-stored script library according to the terminal model, and determines the virtual driver associated with the script; runs the virtual driver to generate the test stimulus corresponding to the business process.
  • Step S20 starting the virtual micro control unit and sending the test stimulus to the virtual micro control unit, wherein after starting, the virtual micro control unit runs the flash memory management algorithm to be debugged, so that the virtual micro control unit can process the test stimulus;
  • the virtual micro control unit processes the received test stimulus by running the flash memory management algorithm, and sends the processing result to the storage module to control the storage module to perform the corresponding read and write operations.
  • the virtual micro control unit is associated with the processor, that is, the computing power of the processor can be called to perform the above operations.
  • the processor can be the processor of the terminal where the virtual micro control unit is located, or it can be a processor that has established a wired or wireless connection with the terminal, so that the terminal can call the processor of other terminals connected to it. Multiple processors can also be called at the same time, which is not specifically limited here.
  • step S20 includes:
  • Step S21 after receiving the test stimulus, the virtual micro control unit determines a processor associated with the virtual micro control unit and sends the test stimulus to the processor;
  • Step S22 After the processor receives the test stimulus, the processor runs the flash memory management algorithm to process the test stimulus.
  • the virtual micro control unit determines the processor associated with the virtual micro control unit and sends the test stimulus to the processor.
  • the processor runs the flash memory management algorithm to be debugged so that the processor can process the test stimulus and generate a processing result of the test stimulus.
  • the processor associated with the virtual micro control unit is a processor of a terminal on which the virtual micro control unit runs.
  • the processor associated with the virtual micro control unit is a processor of a terminal connected to the terminal on which the virtual micro control unit is running.
  • Step S30 obtaining the processing result of the virtual micro control unit on the test stimulus, and sending the processing result to the storage module to control the storage module to complete the storage action.
  • the virtual micro control unit After the virtual micro control unit processes the test stimulus, it sends the corresponding processing result to the storage module to control the storage module to perform a read operation or a write operation corresponding to the test stimulus.
  • the storage module may be a virtual flash memory particle or a physical flash memory particle.
  • the interface between the virtual microcontroller unit and the storage module is called, and the corresponding processing result is sent to the storage module through the interface.
  • the storage module After receiving the processing result, the storage module performs a corresponding read operation or write operation according to the processing result, and after the above operation is completed, sends execution completion information to the virtual microcontroller unit.
  • the method Since the method generates a test stimulus based on a preset stimulus generation method when a test instruction is received; starts a virtual micro control unit and sends the test stimulus to the virtual micro control unit, wherein the virtual micro control unit runs the flash memory management algorithm to be debugged after startup, so that the virtual micro control unit can process the test stimulus; obtains the processing result of the virtual micro control unit on the test stimulus, and sends the processing result to the storage module to control the storage module to complete the storage action, the technical problem of high time cost for debugging the main control and FTL of the solid-state hard disk in the related technology is effectively solved, thereby realizing the rapid completion of the debugging of the main control and FTL of the solid-state hard disk.
  • test stimulus is sent to the processor associated with the virtual microcontroller unit after starting the virtual microcontroller unit, and the computing power of the processor is called to run the flash memory management algorithm so that the test stimulus is processed by the processor, the technical problem of high time cost for debugging the main control and FTL of the solid-state hard disk in the related technology is effectively solved, thereby realizing the rapid completion of the debugging of the main control and FTL of the solid-state hard disk.
  • step S22 includes:
  • Step S210 after the processor receives the test stimulus, determining a logical address corresponding to the test stimulus;
  • Step S220 Based on a preset mapping relationship, the logical address is associated with the physical address of the storage module and stored in a logical mapping table.
  • the functions that can be achieved by running the flash memory management algorithm include associating and storing the logical address corresponding to the test stimulus with the physical address of the storage module, and establishing a logical mapping table, wherein the logical mapping table contains the association relationship between the logical address and the physical address.
  • the storage module performs read and write operations, the corresponding data can be read or written according to the logical mapping table.
  • the processor determines a logical address corresponding to the test stimulus; determines a physical address of data to be read in a storage module; and associates the logical address with the physical address and saves them in a logical mapping table.
  • the processor determines the logical address corresponding to the test stimulus; determines the physical address of the flash memory block to be executed in the storage module, and associates the logical address with the physical address and saves it in a logical mapping table.
  • the method before step S220, the method further includes:
  • Step S230 determining a flash memory block to be executed in the storage module based on a preset wear leveling function
  • Step S240 determining the physical address of the flash memory block to be executed.
  • the functions that can be realized by running the flash memory management algorithm include the balanced management of the service life of the flash memory particles in the storage module, and the wear leveling function can be obtained from the parameter manual of the flash memory particles.
  • the processor runs a flash memory management algorithm, determines some flash memory particles in the storage module based on a preset wear leveling function, marks the flash memory particles as flash memory blocks to be executed, and determines the physical addresses of the flash memory blocks to be executed, so that the service life of the flash memory particles in the storage module is balanced as a whole.
  • step S20 further includes:
  • Step S250 after the processor receives the test stimulus, determining the business process corresponding to the test stimulus;
  • Step S260 when the business process is to store data, determining the data to be stored corresponding to the test stimulus, and determining redundant data of the data to be stored based on a preset error correction algorithm;
  • Step S270 when the business process is to read data, determine the data to be read corresponding to the test stimulus, check the data to be read based on a preset error correction algorithm, and determine redundant data corresponding to the data to be read;
  • the virtual micro control unit when the virtual micro control unit controls the storage module to store data, it runs a flash memory management algorithm, calculates redundant data based on the data to be stored, and stores the data to be stored and the redundant data to the storage module at the same time.
  • the virtual micro control unit when controlling the storage module to read data, runs a flash memory management algorithm to check the data to be read, and updates the data to be read based on redundant data corresponding to the data to be read.
  • an error occurs in the data to be read relative to the original data
  • a flash memory management algorithm is run to correct the error based on redundant data corresponding to the data to be read to obtain the original data
  • the logic address corresponding to the test stimulus is determined, and based on a preset mapping relationship, the logic address is associated with the physical address of the flash memory particle in the storage module and stored in a logic mapping table; at the same time, based on a preset wear leveling function, the flash memory block to be executed in the storage module is determined, and the physical address of the flash memory block to be executed is used as the physical address associated with the logical address. Therefore, the technical problem of high time cost for debugging the main control and FTL of the solid-state hard disk in the related technology is effectively solved, thereby realizing the rapid completion of the debugging of the main control and FTL of the solid-state hard disk.
  • step S30 includes:
  • Step S310 after receiving the processing result, the storage module determines the data to be stored corresponding to the processing result;
  • Step S320 determining the logical address of the data to be stored, and storing the logical address.
  • the processing result includes a logic mapping table, so that the virtual micro control unit can determine the corresponding physical address in the storage module according to the logic address corresponding to the test stimulus.
  • the storage module determines the data to be stored corresponding to the processing result, and determines the logical address corresponding to the data to be stored; based on the logical mapping table included in the processing result, the flash memory particles to be stored in the storage module are determined, and the logical address is stored in the storage module based on the physical address of the flash memory particles.
  • the storage module when the storage module is a virtual flash memory particle, determine the first logical address of the data to be stored, determine the second logical address of the virtual flash memory particle based on the logical mapping table included in the processing result, and store the first logical address in the virtual flash memory particle; then, based on a preset mapping relationship, determine the physical address of the physical memory corresponding to the second logical address, and store the first logical address in the physical memory.
  • the logic mapping table when the storage module is a virtual flash memory particle, stores an association relationship between a first logic address corresponding to a test stimulus and a second logic address corresponding to the virtual flash memory particle.
  • step S20 the method further includes:
  • Step S330 obtaining the processing result of the virtual micro control unit on the test stimulus, and sending the processing result to the storage module;
  • Step S340 after the storage module receives the processing result, determining the physical address of the to-be-read data corresponding to the processing result;
  • Step S350 reading the physical address based on the logical mapping table included in the processing result.
  • the virtual microcontroller After the virtual microcontroller completes processing the test stimulus, it sends the corresponding processing result to the storage module, and after the storage module receives the processing result, it determines the data to be read corresponding to the processing result, determines the physical address of the data to be read in the storage module, and reads the physical address based on the logical mapping table included in the processing result. That is, the physical address is used as the data to be read during reading.
  • the storage module Since, after the storage module receives the processing result of the test stimulus, the data to be stored corresponding to the processing result is determined, the logical address of the data to be stored is determined, and the logical address is stored in the physical address associated with the logical address; the physical address of the data to be read corresponding to the processing result is determined, and the logical address associated with the physical address is read, the technical problem of high time cost for debugging the main control and FTL of the solid-state hard disk in the related technology is effectively solved, thereby realizing the rapid completion of the debugging of the main control and FTL of the solid-state hard disk.
  • the present application also proposes a flash memory management algorithm debugging device, referring to FIG5 , which is a schematic diagram of the structure of the flash memory management algorithm debugging device in the hardware operating environment involved in the embodiment of the present application.
  • the flash memory management algorithm debugging device may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005.
  • the communication bus 1002 is used to realize the connection and communication between these components.
  • the user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and the user interface 1003 may also include a standard wired interface and a wireless interface.
  • the network interface 1004 may include a standard wired interface and a wireless interface (such as a wireless fidelity (Wireless-Fidelity, WI-FI) interface).
  • the memory 1005 may be a high-speed random access memory (Random Access Memory, RAM) memory, or a stable non-volatile memory (Non-Volatile Memory, NVM), such as a disk memory.
  • RAM Random Access Memory
  • NVM Non-Volatile Memory
  • the memory 1005 may also be a storage device independent of the aforementioned processor 1001.
  • FIG. 5 does not constitute a limitation on the flash management algorithm debugging device, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.
  • the memory 1005 is electrically connected to the processor 1001 , and the processor 1001 can be used to control the operation of the memory 1005 and can also read the data in the memory 1005 to implement flash memory management algorithm debugging.
  • the memory 1005 as a storage medium may include an operating system, a data storage module, a network communication module, a user interface module, and a flash memory management algorithm debugging program.
  • the network interface 1004 is mainly used for data communication with other devices; the user interface 1003 is mainly used for data interaction with the user; the processor 1001 and memory 1005 in the flash memory management algorithm debugging device of the present application can be set in the flash memory management algorithm debugging device.
  • the flash memory management algorithm debugging device calls the flash memory management algorithm debugging program stored in the memory 1005 through the processor 1001, and performs the relevant steps of the flash memory management algorithm debugging method provided in the embodiment of the present application:
  • the processing result of the virtual micro control unit on the test stimulus is obtained, and the processing result is sent to the storage module to control the storage module to complete the storage action.
  • the processor 1001 may call the flash memory management algorithm debugging program stored in the memory 1005, and further perform the following operations:
  • the virtual host Upon receiving the test instruction, the virtual host determines the business process corresponding to the test instruction;
  • the processor 1001 may call the flash memory management algorithm debugging program stored in the memory 1005, and further perform the following operations:
  • the virtual micro control unit After receiving the test stimulus, the virtual micro control unit determines a processor associated with the virtual micro control unit and sends the test stimulus to the processor;
  • the processor After receiving the test stimulus, the processor runs the flash memory management algorithm to process the test stimulus.
  • the processor 1001 may call the flash memory management algorithm debugging program stored in the memory 1005, and further perform the following operations:
  • the processor After the processor receives the test stimulus, determining a logical address corresponding to the test stimulus;
  • the logical address is associated with the physical address of the storage module and stored in a logical mapping table.
  • the processor 1001 may call the flash memory management algorithm debugging program stored in the memory 1005, and further perform the following operations:
  • the physical address of the flash memory block to be executed is determined.
  • the processor 1001 may call the flash memory management algorithm debugging program stored in the memory 1005, and further perform the following operations:
  • the storage module After receiving the processing result, the storage module determines the data to be stored corresponding to the processing result;
  • the processor 1001 may call the flash memory management algorithm debugging program stored in the memory 1005, and further perform the following operations:
  • the storage module After the storage module receives the processing result, determining the physical address of the to-be-read data corresponding to the processing result;
  • the physical address is read based on the logical mapping table included in the processing result.
  • the present application also proposes a flash memory management algorithm debugging system, the flash memory management algorithm debugging system comprising:
  • a virtual host after receiving the test instruction, generates a test stimulus corresponding to the test instruction, and sends the test stimulus to the virtual micro control unit;
  • a virtual micro control unit which, after receiving the test stimulus, sends the test stimulus to the processor, so that the processor is called to run a flash memory management algorithm to process the test stimulus;
  • a storage module which, after receiving the processing result sent by the virtual micro control unit, executes a storage action corresponding to the processing result
  • a processor after receiving the test stimulus sent by the virtual micro control unit, runs a flash memory management algorithm to process the test stimulus.
  • an embodiment of the present application also proposes a computer-readable storage medium, on which a flash memory management algorithm debugging program is stored.
  • a flash memory management algorithm debugging program is executed by a processor, the relevant steps of any embodiment of the flash memory management algorithm debugging method described above are implemented.
  • the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
  • a computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.
  • These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.
  • any reference signs placed between brackets shall not be construed as limiting the claims.
  • the word “comprising” does not exclude the presence of components or steps not listed in the claims.
  • the word “a” or “an” preceding a component does not exclude the presence of a plurality of such components.
  • the present application may be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware.
  • the use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

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Abstract

本申请公开了一种闪存管理算法调试方法、系统、设备和可读存储介质，该方法包括：在接收到测试指令时，基于预置的激励生成方式生成测试激励；启动虚拟微控制单元，并将所述测试激励发送至所述虚拟微控制单元，其中，所述虚拟微控制单元在启动后，运行待调试的闪存管理算法，使得所述虚拟微控制单元能处理所述测试激励；获取所述虚拟微控制单元对所述测试激励的处理结果，并将所述处理结果发送至存储模块。

Description

闪存管理算法调试方法、系统、设备和可读存储介质
本申请要求于2022年10月25日提交中国专利局、申请号为202211312389.4、发明名称为“闪存管理算法调试方法、系统、设备和可读存储介质”的中国专利申请的优先权，其全部内容通过引用结合在申请中。
技术领域
本申请涉及快速存储技术领域，尤其涉及一种闪存管理算法调试方法、闪存管理算法调试系统、闪存管理算法调试设备和计算机可读存储介质。
 背景技术
固态硬盘(Solid State Driver，SSD)采用半导体作为存储介质。其无需依赖任何机械装置、不需要寻道，从而降低了I/O请求访问延迟，同时以功耗低、抗震防摔、体积小等优点逐渐取代机械硬盘。
SSD大多将闪存(NAND Flash)作为存储媒介，NAND Flash的存储方式依赖其物理特性，现有文件系统不能直接访问或操作SSD，为了文件系统能够像访问机械硬盘一样来访问SSD，需要在NAND Flash和文件系统之间增加一层软件层FTL(Flash Translation Layer，闪存转换层)。
 技术问题
FTL运行在固态硬盘的微控制单元中，而微控制单元的处理器频率较低，在调试FTL时需要花费较多时间。
 技术解决方案
本申请实施例通过提供一种闪存管理算法调试方法、闪存管理算法调试系统、闪存管理算法调试设备和计算机可读存储介质，解决了相关技术中调试固态硬盘的主控及FTL的时间成本高的技术问题，实现了快速完成固态硬盘主控及FTL调试的技术效果。
本申请实施例提供了一种闪存管理算法调试方法，所述闪存管理算法调试方法包括：
在接收到测试指令时，基于预置的激励生成方式生成测试激励；
启动虚拟微控制单元，并将所述测试激励发送至所述虚拟微控制单元，其中，所述虚拟微控制单元在启动后，运行待调试的闪存管理算法，使得所述虚拟微控制单元能处理所述测试激励；
获取所述虚拟微控制单元对所述测试激励的处理结果，并将所述处理结果发送至存储模块，以控制所述存储模块完成存储动作。
在一实施例中，所述在接收到测试指令时，基于预置的激励生成方式生成测试激励包括：
在接收到所述测试指令时，虚拟主机确定所述测试指令对应的业务流程；
运行所述测试指令对应的虚拟驱动，根据所述业务流程生成所述测试激励。
在一实施例中，所述启动虚拟微控制单元，并将所述测试激励发送至所述虚拟微控制单元，其中，所述虚拟微控制单元在启动后，运行待调试的闪存管理算法，使得所述虚拟微控制单元能处理所述测试激励包括：
所述虚拟微控制单元在接收到所述测试激励后，确定与所述虚拟微控制单元关联的处理器，发送所述测试激励至所述处理器；
在所述处理器接收到所述测试激励后，运行所述闪存管理算法，处理所述测试激励。
在一实施例中，所述在所述处理器接收到所述测试激励后，运行所述闪存管理算法，处理所述测试激励包括：
在所述处理器接收到所述测试激励后，确定所述测试激励对应的逻辑地址；
基于预设的映射关系，将所述逻辑地址与存储模块的物理地址关联存储在逻辑映射表。
在一实施例中，所述基于预设的映射关系，将所述逻辑地址与存储模块的物理地址关联存储在逻辑映射表之前，还包括：
基于预设的磨损均衡函数，确定所述存储模块中待执行闪存块；
确定所述待执行闪存块的所述物理地址。
在一实施例中，所述获取所述虚拟微控制单元对所述测试激励的处理结果，并将所述处理结果发送至存储模块，以控制所述存储模块完成存储动作包括：
所述存储模块在接收到所述处理结果后，确定所述处理结果对应的待存储数据；
确定所述待存储数据的逻辑地址，存储所述逻辑地址。
在一实施例中，所述启动虚拟微控制单元，并将所述测试激励发送至所述虚拟微控制单元，其中，所述虚拟微控制单元在启动后，运行待调试的闪存管理算法，使得所述虚拟微控制单元能处理所述测试激励之后，还包括：
获取所述虚拟微控制单元对所述测试激励的处理结果，并将所述处理结果发送至存储模块；
在所述存储模块接收到所述处理结果后，确定所述处理结果对应的待读取数据的物理地址；
基于所述处理结果包括的逻辑映射表，读取所述物理地址。
此外，本申请还提出一种闪存管理算法调试系统，所述闪存管理算法调试系统包括虚拟主机，所述虚拟主机在接收到测试指令后，生成所述测试指令对应的测试激励，发送所述测试激励给虚拟微控制单元；
虚拟微控制单元，所述虚拟微控制单元在接收到测试激励后，发送所述测试激励给处理器，以使得调用所述处理器运行闪存管理算法，处理所述测试激励；
存储模块，所述存储模块在接收到虚拟微控制单元发送的处理结果后，执行所述处理结果对应存储动作；
处理器，所述处理器在接受到虚拟微控制单元发送的测试激励后，运行闪存管理算法处理所述测试激励。
此外，本申请还提出一种闪存管理算法调试设备，所述闪存管理算法调试设备包括存储器、处理器及存储在存储器上并可在处理器上运行的闪存管理算法调试程序，所述处理器执行所述闪存管理算法调试程序时实现如上所述的闪存管理算法调试方法的步骤。
此外，本申请还提出一种计算机可读存储介质，所述计算机可读存储介质上存储有闪存管理算法调试程序，所述闪存管理算法调试程序被处理器执行时实现如上所述的闪存管理算法调试方法的步骤。
 有益效果
本申请实施例中提供的一个或多个技术方案，至少具有如下技术效果或优点：
1、由于采用了在接收到测试指令时，基于预置的激励生成方式生成测试激励；启动虚拟微控制单元，并将所述测试激励发送至所述虚拟微控制单元，其中，所述虚拟微控制单元在启动后，运行待调试的闪存管理算法，使得所述虚拟微控制单元能处理所述测试激励；获取所述虚拟微控制单元对所述测试激励的处理结果，并将所述处理结果发送至存储模块，以控制所述存储模块完成存储动作，所以，有效解决了相关技术中调试固态硬盘的主控及FTL的时间成本高的技术问题，进而实现了快速完成固态硬盘主控及FTL调试。
2、由于采用了启动虚拟微控制单元后，发送所述测试激励给所述虚拟微控制单元关联的处理器，调用所述处理器的算力来运行闪存管理算法，以使得通过所述处理器处理所述测试激励，所以，有效解决了相关技术中调试固态硬盘的主控及FTL的时间成本高的技术问题，进而实现了快速完成固态硬盘主控及FTL调试。
3、由于采用了在所述处理器接收到所述测试激励后，确定所述测试激励对应的逻辑地址，基于预设的映射关系，将所述逻辑地址与存储模块中闪存颗粒的物理地址关联存储在逻辑映射表中；同时，基于预设的磨损均衡函数，确定所述存储模块中待执行闪存块，将所述待执行闪存块的物理地址作为与所述逻辑地址关联的所述物理地址。所以，有效解决了相关技术中调试固态硬盘的主控及FTL的时间成本高的技术问题，进而实现了快速完成固态硬盘主控及FTL调试。
4、由于采用了在存储模块接收到测试激励的处理结果后，确定所述处理结果对应的待存储数据，确定所述待存储数据的逻辑地址，将所述逻辑地址存储进所述逻辑地址关联的物理地址中；确定所述处理结果对应的待读取数据的物理地址，读取所述物理地址关联的逻辑地址，所以，有效解决了相关技术中调试固态硬盘的主控及FTL的时间成本高的技术问题，进而实现了快速完成固态硬盘主控及FTL调试。
 附图说明
图1为本申请闪存管理算法调试方法实施例一的流程示意图；
图2为本申请闪存管理算法调试方法实施例一步骤S20细化的流程示意图；
图3为本申请闪存管理算法调试方法实施例二的流程示意图；
图4为本申请闪存管理算法调试方法实施例三的流程示意图；
图5为本申请闪存管理算法调试设备实施例涉及的硬件结构示意图。
 本发明的实施方式
在相关技术中，闪存颗粒厂商发布新的闪存颗粒后，固态硬盘厂商需要针对新的闪存颗粒开发新的主控以及闪存管理算法；但是固态硬盘厂商不能第一时间拿到新的闪存颗粒，同时固态硬盘主控的处理频率较低，导致固态硬盘主控开发过程以及闪存管理算法调试过程的时间成本过高。本申请实施例采用的主要技术方案是：虚拟主机在接收到测试指令时，基于预设的方式生成测试激励；将所述测试激励发送给虚拟微控制单元，以控制所述虚拟微控制单元调用处理器的算力，运行闪存管理算法；将所述测试激励的处理结果发送给存储模块，以控制所述存储模块完成对应的存储动作。从而实现了快速完成固态硬盘主控及FTL调试。
为了更好的理解上述技术方案，下面将参照附图更详细地描述本申请的示例性实施例。虽然附图中显示了本申请的示例性实施例，然而应当理解，可以以各种形式实现本申请而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本申请，并且能够将本申请的范围完整的传达给本领域的技术人员。
实施例一
本申请实施例一公开了一种闪存管理算法调试方法，参照图1，所述闪存管理算法调试方法包括：
步骤S10，在接收到测试指令时，基于预置的激励生成方式生成测试激励；
在本实施例中，测试指令可以视为测试开始的指令，所述测试指令也可以包含待读取或待写入的数据，也可以包含所述测试激励要模拟的终端型号。虚拟主机在接收到测试指令是，基于预置的激励生成方式生成对应的测试激励。
在一实施例中，步骤S10包括：
步骤S11，在接收到所述测试指令时，虚拟主机确定所述测试指令对应的业务流程；
步骤S12，运行所述测试指令对应的虚拟驱动，根据所述业务流程生成所述测试激励。
作为一种可选实施方式，虚拟主机在接收到测试指令时，确定所述测试指令对应的业务流程以及待模拟的终端型号；根据所述终端型号在预存脚本库中调用对应的脚本，确定与所述脚本关联的虚拟驱动；运行所述虚拟驱动，生成与所述业务流程对应的所述测试激励。
步骤S20，启动虚拟微控制单元，并将所述测试激励发送至所述虚拟微控制单元，其中，所述虚拟微控制单元在启动后，运行待调试的闪存管理算法，使得所述虚拟微控制单元能处理所述测试激励；
在本实施例中，虚拟微控制单元通过运行闪存管理算法，处理接收到的测试激励，并发送处理结果给存储模块，以控制存储模块执行对应的读写操作。其中，虚拟微控制单元与处理器关联，即可调用所述处理器的算力，来执行上述操作。所述处理器可以是虚拟微控制单元所在终端的处理器，也可以是与所述终端建立了有线或无线连接，使得所述终端可以调用与之连接的其他终端的处理器。也可以同时调用多个处理器，这里不作具体限定。
在一实施例中，参照图2，步骤S20包括：
步骤S21，所述虚拟微控制单元在接收到所述测试激励后，确定与所述虚拟微控制单元关联的处理器，发送所述测试激励至所述处理器；
步骤S22，在所述处理器接收到所述测试激励后，运行所述闪存管理算法，处理所述测试激励。
作为一种可选实施方式，虚拟微控制单元在接收到测试激励后，确定与所述虚拟微控制单元关联的处理器，发送所述测试激励给所述处理器，所述处理器在接收到所述测试激励后，运行待调试的闪存管理算法，以使得所述处理器可以处理所述测试激励，并生成所述测试激励的处理结果。
在一实施例中，与虚拟微控制单元关联的处理器，是所述虚拟微控制单元所运行的终端的处理器。
在一实施例中，与虚拟微控制单元关联的处理器，是与所述虚拟微控制单元所运行的终端相连接的终端的处理器。
步骤S30，获取所述虚拟微控制单元对所述测试激励的处理结果，并将所述处理结果发送至存储模块，以控制所述存储模块完成存储动作。
在本实施例中，虚拟微控制单元处理完所述测试激励后，将对应的处理结果发送给存储模块，以控制存储模块执行所述测试激励对应的读取操作或写入操作。
在一实施例中，所述存储模块可以是虚拟闪存颗粒，也可以是实体闪存颗粒。
作为一种可选实施方式，在虚拟微控制单元处理完所述测试激励后，调用虚拟微控制单元与存储模块间的接口，将对应的处理结果通过所述接口发送至存储模块，存储模块在接收到所述处理结果后，根据所述处理结果执行对应的读取操作或写入操作，并在上述操作执行完毕后，发送执行完成信息给所述虚拟微控制单元。
上述本申请实施例中的技术方案，至少具有如下的技术效果或优点：
由于采用了在接收到测试指令时，基于预置的激励生成方式生成测试激励；启动虚拟微控制单元，并将所述测试激励发送至所述虚拟微控制单元，其中，所述虚拟微控制单元在启动后，运行待调试的闪存管理算法，使得所述虚拟微控制单元能处理所述测试激励；获取所述虚拟微控制单元对所述测试激励的处理结果，并将所述处理结果发送至存储模块，以控制所述存储模块完成存储动作，所以，有效解决了相关技术中调试固态硬盘的主控及FTL的时间成本高的技术问题，进而实现了快速完成固态硬盘主控及FTL调试。
由于采用了启动虚拟微控制单元后，发送所述测试激励给所述虚拟微控制单元关联的处理器，调用所述处理器的算力来运行闪存管理算法，以使得通过所述处理器处理所述测试激励，所以，有效解决了相关技术中调试固态硬盘的主控及FTL的时间成本高的技术问题，进而实现了快速完成固态硬盘主控及FTL调试。
实施例二
基于实施例一，本申请实施例二公开一种闪存管理算法调试方法，参照图3，步骤S22包括：
步骤S210，在所述处理器接收到所述测试激励后，确定所述测试激励对应的逻辑地址；
步骤S220，基于预设的映射关系，将所述逻辑地址与存储模块的物理地址关联存储在逻辑映射表。
在本实施例中，运行闪存管理算法能实现的功能包括将测试激励对应的逻辑地址与存储模块的物理地址关联存储，并建立逻辑映射表，其中所述逻辑映射表包含了逻辑地址与物理地址的关联关系，在存储模块执行读写操作时，可以根据所述逻辑映射表读取或写入对应的数据。
作为一种可选实施方式，处理器在接收到测试激励后，当所述测试激励为读取测试时，确定所述测试激励对应的逻辑地址；确定存储模块中待读取数据的物理地址；将所述逻辑地址与所述物理地址关联保存在逻辑映射表中。
作为另一种可选实施方式，处理器在接收到测试激励后，当所述测试激励为写入测试时，确定所述测试激励对应的逻辑地址；确定存储模块中待执行闪存块的物理地址，将所述逻辑地址与所述物理地址关联保存在逻辑映射表中。
在一实施例中，步骤S220之前，还包括：
步骤S230，基于预设的磨损均衡函数，确定所述存储模块中待执行闪存块；
步骤S240，确定所述待执行闪存块的所述物理地址。
在本实施例中，运行闪存管理算法能实现的功能包括对存储模块中闪存颗粒使用寿命的均衡性管理，所述磨损均衡函数可以从所述闪存颗粒的参数手册中获取。
作为一种可选实施方式，处理器运行闪存管理算法，基于预设的磨损均衡函数，确定存储模块中的部分闪存颗粒，将所述闪存颗粒标记为待执行闪存块，确定所述待执行闪存块的物理地址，使得所述存储模块中的闪存颗粒的使用寿命整体均衡。
在一实施例中，步骤S20还包括：
步骤S250，在所述处理器接收到所述测试激励后，确定所述测试激励对应的业务流程；
步骤S260，当所述业务流程为存储数据时，确定所述测试激励对应的待存储数据，基于预设的纠错算法，确定所述待存储数据的冗余数据；
基于所述待存储数据以及所述冗余数据更新所述待存储数据；
步骤S270，当所述业务流程为读取数据时，确定所述测试激励对应的待读取数据，基于预设的纠错算法，检查所述待读取数据并确定所述待读取数据对应的冗余数据；
根据所述冗余数据更新所述待读取数据；
作为一种可选实施方式，虚拟微控制单元控制存储模块存储数据时，运行闪存管理算法，基于待存储数据计算出冗余数据，并将所述待存储数据以及所述冗余数据同时存储至所述存储模块。
作为另一种可选实施方式，虚拟微控制单元在控制存储模块读取数据时，运行闪存管理算法，检查待读取的数据，并基于所述待读取数据对应的冗余数据，更新所述待读取数据。
在一实施例中，所述待读取数据相对于原始数据发生了错误，运行闪存管理算法，基于所述待读取数据对应的冗余数据，纠正所述错误，获取所述原始数据。
上述本申请实施例中的技术方案，至少具有如下的技术效果或优点：
由于采用了在所述处理器接收到所述测试激励后，确定所述测试激励对应的逻辑地址，基于预设的映射关系，将所述逻辑地址与存储模块中闪存颗粒的物理地址关联存储在逻辑映射表中；同时，基于预设的磨损均衡函数，确定所述存储模块中待执行闪存块，将所述待执行闪存块的物理地址作为与所述逻辑地址关联的所述物理地址。所以，有效解决了相关技术中调试固态硬盘的主控及FTL的时间成本高的技术问题，进而实现了快速完成固态硬盘主控及FTL调试。
实施例三
基于实施例一，本申请实施例三公开一种闪存管理算法调试方法，参照图4，步骤S30包括：
步骤S310，所述存储模块在接收到所述处理结果后，确定所述处理结果对应的待存储数据；
步骤S320，确定所述待存储数据的逻辑地址，存储所述逻辑地址。
在本实施例中，所述处理结果包括的逻辑映射表，以供所述虚拟微控制单元根据测试激励对应的逻辑地址确定存储模块中对应的物理地址。
作为一种可选实施方式，存储模块在接收到虚拟微控制单元发送地处理结果后，确定所述处理结果对应的待存储数据，确定所述待存储数据对应的逻辑地址；基于所述处理结果包括的逻辑映射表，确定存储模块中待存储的闪存颗粒，将所述逻辑地址基于所述闪存颗粒的物理地址，存储至存储模块中。
作为另一种可选实施方式，当所述存储模块为虚拟闪存颗粒时，确定待存储数据的第一逻辑地址，基于处理结果包括的逻辑映射表，确定所述虚拟闪存颗粒的第二逻辑地址，将所述第一逻辑地址存储至所述虚拟闪存颗粒中；再基于预设的映射关系，确定与所述第二逻辑地址对应的实体存储器的物理地址，将所述第一逻辑地址存储至所述实体存储器中。
在一实施例中，当所述存储模块为虚拟闪存颗粒时，所述逻辑映射表存储有测试激励对应的第一逻辑地址与虚拟闪存颗粒对应的第二逻辑地址的关联关系。
在一实施例中，步骤S20之后，还包括：
步骤S330，获取所述虚拟微控制单元对所述测试激励的处理结果，并将所述处理结果发送至存储模块；
步骤S340，在所述存储模块接收到所述处理结果后，确定所述处理结果对应的待读取数据的物理地址；
步骤S350，基于所述处理结果包括的逻辑映射表，读取所述物理地址。
在本实施例中，不管是执行读取操作还是存储操作，都只读取或存储待执行数据的逻辑地址，以达到加快调试进度，节约时间成本的效果。
作为一种可选实施方式，虚拟微控制单元在处理完成所述测试激励后，将对应的处理结果发送至存储模块，在所述存储模块接收到所述处理结果后，确定所述处理结果对应的待读取数据，确定所述待读取数据在所述存储模块中的物理地址；基于所述处理结果包括的逻辑映射表，读取所述物理地址。即读取时将所述物理地址作为待读取数据。
上述本申请实施例中的技术方案，至少具有如下的技术效果或优点：
由于采用了在存储模块接收到测试激励的处理结果后，确定所述处理结果对应的待存储数据，确定所述待存储数据的逻辑地址，将所述逻辑地址存储进所述逻辑地址关联的物理地址中；确定所述处理结果对应的待读取数据的物理地址，读取所述物理地址关联的逻辑地址，所以，有效解决了相关技术中调试固态硬盘的主控及FTL的时间成本高的技术问题，进而实现了快速完成固态硬盘主控及FTL调试。
本申请还提出一种闪存管理算法调试设备，参照图5，图5为本申请实施例方案涉及的硬件运行环境的闪存管理算法调试设备结构示意图。
如图5所示，该闪存管理算法调试设备可以包括：处理器1001，例如中央处理器（Central Processing Unit，CPU），通信总线1002、用户接口1003，网络接口1004，存储器1005。其中，通信总线1002用于实现这些组件之间的连接通信。用户接口1003可以包括显示屏（Display）、输入单元比如键盘（Keyboard），用户接口1003还可以包括标准的有线接口、无线接口。网络接口1004可以包括标准的有线接口、无线接口（如无线保真（Wireless-Fidelity，WI-FI）接口）。存储器1005可以是高速的随机存取存储器（Random Access Memory，RAM）存储器，也可以是稳定的非易失性存储器（Non-Volatile Memory，NVM），例如磁盘存储器。存储器1005还可以是独立于前述处理器1001的存储装置。
本领域技术人员可以理解，图5中示出的结构并不构成对闪存管理算法调试设备的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
在一实施例中，存储器1005与处理器1001电性连接，处理器1001可用于控制存储器1005的运行，还可以读取存储器1005中的数据以实现闪存管理算法调试。
在一实施例中，如图5所示，作为一种存储介质的存储器1005中可以包括操作系统、数据存储模块、网络通信模块、用户接口模块以及闪存管理算法调试程序。
在一实施例中，在图5所示的闪存管理算法调试设备中，网络接口1004主要用于与其他设备进行数据通信；用户接口1003主要用于与用户进行数据交互；本申请闪存管理算法调试设备中的处理器1001、存储器1005可以设置在闪存管理算法调试设备中。
如图5所示，所述闪存管理算法调试设备通过处理器1001调用存储器1005中存储的闪存管理算法调试程序，并执行本申请实施例提供的闪存管理算法调试方法的相关步骤操作：
在接收到测试指令时，基于预置的激励生成方式生成测试激励；
启动虚拟微控制单元，并将所述测试激励发送至所述虚拟微控制单元，其中，所述虚拟微控制单元在启动后，运行待调试的闪存管理算法，使得所述虚拟微控制单元能处理所述测试激励；
获取所述虚拟微控制单元对所述测试激励的处理结果，并将所述处理结果发送至存储模块，以控制所述存储模块完成存储动作。
在一实施例中，处理器1001可以调用存储器1005中存储的闪存管理算法调试程序，还执行以下操作：
在接收到所述测试指令时，虚拟主机确定所述测试指令对应的业务流程；
运行所述测试指令对应的虚拟驱动，根据所述业务流程生成所述测试激励。
在一实施例中，处理器1001可以调用存储器1005中存储的闪存管理算法调试程序，还执行以下操作：
所述虚拟微控制单元在接收到所述测试激励后，确定与所述虚拟微控制单元关联的处理器，发送所述测试激励至所述处理器；
在所述处理器接收到所述测试激励后，运行所述闪存管理算法，处理所述测试激励。
在一实施例中，处理器1001可以调用存储器1005中存储的闪存管理算法调试程序，还执行以下操作：
在所述处理器接收到所述测试激励后，确定所述测试激励对应的逻辑地址；
基于预设的映射关系，将所述逻辑地址与存储模块的物理地址关联存储在逻辑映射表。
在一实施例中，处理器1001可以调用存储器1005中存储的闪存管理算法调试程序，还执行以下操作：
基于预设的磨损均衡函数，确定所述存储模块中待执行闪存块；
确定所述待执行闪存块的所述物理地址。
在一实施例中，处理器1001可以调用存储器1005中存储的闪存管理算法调试程序，还执行以下操作：
所述存储模块在接收到所述处理结果后，确定所述处理结果对应的待存储数据；
确定所述待存储数据的逻辑地址，存储所述逻辑地址。
在一实施例中，处理器1001可以调用存储器1005中存储的闪存管理算法调试程序，还执行以下操作：
获取所述虚拟微控制单元对所述测试激励的处理结果，并将所述处理结果发送至存储模块；
在所述存储模块接收到所述处理结果后，确定所述处理结果对应的待读取数据的物理地址；
基于所述处理结果包括的逻辑映射表，读取所述物理地址。
此外，本申请还提出一种闪存管理算法调试系统，所述闪存管理算法调试系统包括：
虚拟主机，所述虚拟主机在接收到测试指令后，生成所述测试指令对应的测试激励，发送所述测试激励给虚拟微控制单元；
虚拟微控制单元，所述虚拟微控制单元在接收到测试激励后，发送所述测试激励给处理器，以使得调用所述处理器运行闪存管理算法，处理所述测试激励；
存储模块，所述存储模块在接收到虚拟微控制单元发送的处理结果后，执行所述处理结果对应存储动作；
处理器，所述处理器在接受到虚拟微控制单元发送的测试激励后，运行闪存管理算法处理所述测试激励。
此外，本申请实施例还提出一种计算机可读存储介质，所述计算机可读存储介质上存储有闪存管理算法调试程序，所述闪存管理算法调试程序被处理器执行时实现如上所述闪存管理算法调试方法任一实施例的相关步骤。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质（包括但不限于磁盘存储器、CD-ROM、光学存储器等）上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备（系统）、和计算机程序产品的流程图和／或方框图来描述的。应理解可由计算机程序指令实现流程图和／或方框图中的每一流程和／或方框、以及流程图和／或方框图中的流程和／或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和／或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和／或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和／或方框图一个方框或多个方框中指定的功能的步骤。
应当注意的是，在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的部件或步骤。位于部件之前的单词“一”或“一个”不排除存在多个这样的部件。本申请可以借助于包括有若干不同部件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (10)

  1. 一种闪存管理算法调试方法，其中，所述闪存管理算法调试方法包括：
    在接收到测试指令时，基于预置的激励生成方式生成测试激励；
    启动虚拟微控制单元，并将所述测试激励发送至所述虚拟微控制单元，其中，所述虚拟微控制单元在启动后，运行待调试的闪存管理算法，使得所述虚拟微控制单元能处理所述测试激励；
    获取所述虚拟微控制单元对所述测试激励的处理结果，并将所述处理结果发送至存储模块，以控制所述存储模块完成存储动作。
  2. 如权利要求1所述的闪存管理算法调试方法，其中，所述在接收到测试指令时，基于预置的激励生成方式生成测试激励包括：
    在接收到所述测试指令时，虚拟主机确定所述测试指令对应的业务流程；
    运行所述测试指令对应的虚拟驱动，根据所述业务流程生成所述测试激励。
  3. 如权利要求1所述的闪存管理算法调试方法，其中，所述启动虚拟微控制单元，并将所述测试激励发送至所述虚拟微控制单元，其中，所述虚拟微控制单元在启动后，运行待调试的闪存管理算法，使得所述虚拟微控制单元能处理所述测试激励包括：
    所述虚拟微控制单元在接收到所述测试激励后，确定与所述虚拟微控制单元关联的处理器，发送所述测试激励至所述处理器；
    在所述处理器接收到所述测试激励后，运行所述闪存管理算法，处理所述测试激励。
  4. 如权利要求3所述的闪存管理算法调试方法，其中，所述在所述处理器接收到所述测试激励后，运行所述闪存管理算法，处理所述测试激励包括：
    在所述处理器接收到所述测试激励后，确定所述测试激励对应的逻辑地址；
    基于预设的映射关系，将所述逻辑地址与存储模块的物理地址关联存储在逻辑映射表。
  5. 如权利要求4所述的闪存管理算法调试方法，其中，所述基于预设的映射关系，将所述逻辑地址与存储模块的物理地址关联存储在逻辑映射表之前，还包括：
    基于预设的磨损均衡函数，确定所述存储模块中待执行闪存块；
    确定所述待执行闪存块的所述物理地址。
  6. 如权利要求1所述的闪存管理算法调试方法，其中，所述获取所述虚拟微控制单元对所述测试激励的处理结果，并将所述处理结果发送至存储模块，以控制所述存储模块完成存储动作包括：
    所述存储模块在接收到所述处理结果后，确定所述处理结果对应的待存储数据；
    确定所述待存储数据的逻辑地址，存储所述逻辑地址。
  7. 如权利要求1所述的闪存管理算法调试方法，其中，所述启动虚拟微控制单元，并将所述测试激励发送至所述虚拟微控制单元，其中，所述虚拟微控制单元在启动后，运行待调试的闪存管理算法，使得所述虚拟微控制单元能处理所述测试激励之后，还包括：
    获取所述虚拟微控制单元对所述测试激励的处理结果，并将所述处理结果发送至存储模块；
    在所述存储模块接收到所述处理结果后，确定所述处理结果对应的待读取数据的物理地址；
    基于所述处理结果包括的逻辑映射表，读取所述物理地址。
  8. 一种闪存管理算法调试系统，其中，所述闪存管理算法调试系统包括：
    虚拟主机，所述虚拟主机在接收到测试指令后，生成所述测试指令对应的测试激励，发送所述测试激励给虚拟微控制单元；
    虚拟微控制单元，所述虚拟微控制单元在接收到测试激励后，发送所述测试激励给处理器，以使得调用所述处理器运行闪存管理算法，处理所述测试激励；
    存储模块，所述存储模块在接收到虚拟微控制单元发送的处理结果后，执行所述处理结果对应存储动作；
    处理器，所述处理器在接受到虚拟微控制单元发送的测试激励后，运行闪存管理算法处理所述测试激励。
  9. 一种闪存管理算法调试设备，其中，所述闪存管理算法调试设备包括存储器、处理器及存储在存储器上并可在处理器上运行的闪存管理算法调试程序，所述处理器执行所述闪存管理算法调试程序时实现如权利要求1至7任一项所述的闪存管理算法调试方法的步骤。
  10. 一种计算机可读存储介质，其中，所述计算机可读存储介质上存储有闪存管理算法调试程序，所述闪存管理算法调试程序被处理器执行时实现如权利要求1至7任一项所述的闪存管理算法调试方法的步骤。
PCT/CN2023/096119 2022-10-25 2023-05-24 闪存管理算法调试方法、系统、设备和可读存储介质 WO2024087607A1 (zh)

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CN115576766A (zh) * 2022-10-25 2023-01-06 深圳市硅格半导体有限公司 闪存管理算法调试方法、系统、设备和可读存储介质

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